1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82 static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 static void pci_cfg_restore(device_t, struct pci_devinfo *); 95 static void pci_cfg_save(device_t, struct pci_devinfo *, int); 96 97 static device_method_t pci_methods[] = { 98 /* Device interface */ 99 DEVMETHOD(device_probe, pci_probe), 100 DEVMETHOD(device_attach, pci_attach), 101 DEVMETHOD(device_shutdown, bus_generic_shutdown), 102 DEVMETHOD(device_suspend, pci_suspend), 103 DEVMETHOD(device_resume, pci_resume), 104 105 /* Bus interface */ 106 DEVMETHOD(bus_print_child, pci_print_child), 107 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 108 DEVMETHOD(bus_read_ivar, pci_read_ivar), 109 DEVMETHOD(bus_write_ivar, pci_write_ivar), 110 DEVMETHOD(bus_driver_added, pci_driver_added), 111 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 112 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 113 114 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 115 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 116 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 117 DEVMETHOD(bus_delete_resource, pci_delete_resource), 118 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 119 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 120 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 121 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 122 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 123 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 124 125 /* PCI interface */ 126 DEVMETHOD(pci_read_config, pci_read_config_method), 127 DEVMETHOD(pci_write_config, pci_write_config_method), 128 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 129 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 130 DEVMETHOD(pci_enable_io, pci_enable_io_method), 131 DEVMETHOD(pci_disable_io, pci_disable_io_method), 132 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 133 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 134 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 135 136 { 0, 0 } 137 }; 138 139 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 140 141 devclass_t pci_devclass; 142 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 143 MODULE_VERSION(pci, 1); 144 145 static char *pci_vendordata; 146 static size_t pci_vendordata_size; 147 148 149 struct pci_quirk { 150 uint32_t devid; /* Vendor/device of the card */ 151 int type; 152 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 153 int arg1; 154 int arg2; 155 }; 156 157 struct pci_quirk pci_quirks[] = { 158 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 159 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 162 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 163 164 { 0 } 165 }; 166 167 /* map register information */ 168 #define PCI_MAPMEM 0x01 /* memory map */ 169 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 170 #define PCI_MAPPORT 0x04 /* port map */ 171 172 struct devlist pci_devq; 173 uint32_t pci_generation; 174 uint32_t pci_numdevs = 0; 175 176 /* sysctl vars */ 177 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 178 179 static int pci_enable_io_modes = 1; 180 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 181 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 182 &pci_enable_io_modes, 1, 183 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 184 enable these bits correctly. We'd like to do this all the time, but there\n\ 185 are some peripherals that this causes problems with."); 186 187 static int pci_do_powerstate = 1; 188 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 189 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 190 &pci_do_powerstate, 1, 191 "Power down devices into D3 state when no driver attaches to them.\n\ 192 Otherwise, leave the device in D0 state when no driver attaches."); 193 194 /* Find a device_t by bus/slot/function */ 195 196 device_t 197 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 198 { 199 struct pci_devinfo *dinfo; 200 201 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 202 if ((dinfo->cfg.bus == bus) && 203 (dinfo->cfg.slot == slot) && 204 (dinfo->cfg.func == func)) { 205 return (dinfo->cfg.dev); 206 } 207 } 208 209 return (NULL); 210 } 211 212 /* Find a device_t by vendor/device ID */ 213 214 device_t 215 pci_find_device(uint16_t vendor, uint16_t device) 216 { 217 struct pci_devinfo *dinfo; 218 219 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 220 if ((dinfo->cfg.vendor == vendor) && 221 (dinfo->cfg.device == device)) { 222 return (dinfo->cfg.dev); 223 } 224 } 225 226 return (NULL); 227 } 228 229 /* return base address of memory or port map */ 230 231 static uint32_t 232 pci_mapbase(unsigned mapreg) 233 { 234 int mask = 0x03; 235 if ((mapreg & 0x01) == 0) 236 mask = 0x0f; 237 return (mapreg & ~mask); 238 } 239 240 /* return map type of memory or port map */ 241 242 static int 243 pci_maptype(unsigned mapreg) 244 { 245 static uint8_t maptype[0x10] = { 246 PCI_MAPMEM, PCI_MAPPORT, 247 PCI_MAPMEM, 0, 248 PCI_MAPMEM, PCI_MAPPORT, 249 0, 0, 250 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 251 PCI_MAPMEM|PCI_MAPMEMP, 0, 252 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 253 0, 0, 254 }; 255 256 return maptype[mapreg & 0x0f]; 257 } 258 259 /* return log2 of map size decoded for memory or port map */ 260 261 static int 262 pci_mapsize(unsigned testval) 263 { 264 int ln2size; 265 266 testval = pci_mapbase(testval); 267 ln2size = 0; 268 if (testval != 0) { 269 while ((testval & 1) == 0) 270 { 271 ln2size++; 272 testval >>= 1; 273 } 274 } 275 return (ln2size); 276 } 277 278 /* return log2 of address range supported by map register */ 279 280 static int 281 pci_maprange(unsigned mapreg) 282 { 283 int ln2range = 0; 284 switch (mapreg & 0x07) { 285 case 0x00: 286 case 0x01: 287 case 0x05: 288 ln2range = 32; 289 break; 290 case 0x02: 291 ln2range = 20; 292 break; 293 case 0x04: 294 ln2range = 64; 295 break; 296 } 297 return (ln2range); 298 } 299 300 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 301 302 static void 303 pci_fixancient(pcicfgregs *cfg) 304 { 305 if (cfg->hdrtype != 0) 306 return; 307 308 /* PCI to PCI bridges use header type 1 */ 309 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 310 cfg->hdrtype = 1; 311 } 312 313 /* extract header type specific config data */ 314 315 static void 316 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 317 { 318 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 319 switch (cfg->hdrtype) { 320 case 0: 321 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 322 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 323 cfg->nummaps = PCI_MAXMAPS_0; 324 break; 325 case 1: 326 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 327 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 328 cfg->nummaps = PCI_MAXMAPS_1; 329 break; 330 case 2: 331 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 332 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 333 cfg->nummaps = PCI_MAXMAPS_2; 334 break; 335 } 336 #undef REG 337 } 338 339 /* read configuration header into pcicfgregs structure */ 340 341 struct pci_devinfo * 342 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 343 { 344 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 345 pcicfgregs *cfg = NULL; 346 struct pci_devinfo *devlist_entry; 347 struct devlist *devlist_head; 348 349 devlist_head = &pci_devq; 350 351 devlist_entry = NULL; 352 353 if (REG(PCIR_DEVVENDOR, 4) != -1) { 354 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 355 if (devlist_entry == NULL) 356 return (NULL); 357 358 cfg = &devlist_entry->cfg; 359 360 cfg->bus = b; 361 cfg->slot = s; 362 cfg->func = f; 363 cfg->vendor = REG(PCIR_VENDOR, 2); 364 cfg->device = REG(PCIR_DEVICE, 2); 365 cfg->cmdreg = REG(PCIR_COMMAND, 2); 366 cfg->statreg = REG(PCIR_STATUS, 2); 367 cfg->baseclass = REG(PCIR_CLASS, 1); 368 cfg->subclass = REG(PCIR_SUBCLASS, 1); 369 cfg->progif = REG(PCIR_PROGIF, 1); 370 cfg->revid = REG(PCIR_REVID, 1); 371 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 372 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 373 cfg->lattimer = REG(PCIR_LATTIMER, 1); 374 cfg->intpin = REG(PCIR_INTPIN, 1); 375 cfg->intline = REG(PCIR_INTLINE, 1); 376 377 cfg->mingnt = REG(PCIR_MINGNT, 1); 378 cfg->maxlat = REG(PCIR_MAXLAT, 1); 379 380 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 381 cfg->hdrtype &= ~PCIM_MFDEV; 382 383 pci_fixancient(cfg); 384 pci_hdrtypedata(pcib, b, s, f, cfg); 385 386 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 387 pci_read_extcap(pcib, cfg); 388 389 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 390 391 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 392 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 393 devlist_entry->conf.pc_sel.pc_func = cfg->func; 394 devlist_entry->conf.pc_hdr = cfg->hdrtype; 395 396 devlist_entry->conf.pc_subvendor = cfg->subvendor; 397 devlist_entry->conf.pc_subdevice = cfg->subdevice; 398 devlist_entry->conf.pc_vendor = cfg->vendor; 399 devlist_entry->conf.pc_device = cfg->device; 400 401 devlist_entry->conf.pc_class = cfg->baseclass; 402 devlist_entry->conf.pc_subclass = cfg->subclass; 403 devlist_entry->conf.pc_progif = cfg->progif; 404 devlist_entry->conf.pc_revid = cfg->revid; 405 406 pci_numdevs++; 407 pci_generation++; 408 } 409 return (devlist_entry); 410 #undef REG 411 } 412 413 static void 414 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 415 { 416 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 417 int ptr, nextptr, ptrptr; 418 419 switch (cfg->hdrtype & PCIM_HDRTYPE) { 420 case 0: 421 ptrptr = PCIR_CAP_PTR; 422 break; 423 case 2: 424 ptrptr = 0x14; 425 break; 426 default: 427 return; /* no extended capabilities support */ 428 } 429 nextptr = REG(ptrptr, 1); /* sanity check? */ 430 431 /* 432 * Read capability entries. 433 */ 434 while (nextptr != 0) { 435 /* Sanity check */ 436 if (nextptr > 255) { 437 printf("illegal PCI extended capability offset %d\n", 438 nextptr); 439 return; 440 } 441 /* Find the next entry */ 442 ptr = nextptr; 443 nextptr = REG(ptr + 1, 1); 444 445 /* Process this entry */ 446 switch (REG(ptr, 1)) { 447 case PCIY_PMG: /* PCI power management */ 448 if (cfg->pp.pp_cap == 0) { 449 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 450 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 451 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 452 if ((nextptr - ptr) > PCIR_POWER_DATA) 453 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 454 } 455 break; 456 case PCIY_MSI: /* PCI MSI */ 457 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 458 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 459 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 460 else 461 cfg->msi.msi_data = PCIR_MSI_DATA; 462 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 463 PCIM_MSICTRL_MMC_MASK)>>1); 464 default: 465 break; 466 } 467 } 468 #undef REG 469 } 470 471 /* free pcicfgregs structure and all depending data structures */ 472 473 int 474 pci_freecfg(struct pci_devinfo *dinfo) 475 { 476 struct devlist *devlist_head; 477 478 devlist_head = &pci_devq; 479 480 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 481 free(dinfo, M_DEVBUF); 482 483 /* increment the generation count */ 484 pci_generation++; 485 486 /* we're losing one device */ 487 pci_numdevs--; 488 return (0); 489 } 490 491 /* 492 * PCI power manangement 493 */ 494 int 495 pci_set_powerstate_method(device_t dev, device_t child, int state) 496 { 497 struct pci_devinfo *dinfo = device_get_ivars(child); 498 pcicfgregs *cfg = &dinfo->cfg; 499 uint16_t status; 500 int result, oldstate, highest, delay; 501 502 if (cfg->pp.pp_cap == 0) 503 return (EOPNOTSUPP); 504 505 /* 506 * Optimize a no state change request away. While it would be OK to 507 * write to the hardware in theory, some devices have shown odd 508 * behavior when going from D3 -> D3. 509 */ 510 oldstate = pci_get_powerstate(child); 511 if (oldstate == state) 512 return (0); 513 514 /* 515 * The PCI power management specification states that after a state 516 * transition between PCI power states, system software must 517 * guarantee a minimal delay before the function accesses the device. 518 * Compute the worst case delay that we need to guarantee before we 519 * access the device. Many devices will be responsive much more 520 * quickly than this delay, but there are some that don't respond 521 * instantly to state changes. Transitions to/from D3 state require 522 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 523 * is done below with DELAY rather than a sleeper function because 524 * this function can be called from contexts where we cannot sleep. 525 */ 526 highest = (oldstate > state) ? oldstate : state; 527 if (highest == PCI_POWERSTATE_D3) 528 delay = 10000; 529 else if (highest == PCI_POWERSTATE_D2) 530 delay = 200; 531 else 532 delay = 0; 533 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 534 & ~PCIM_PSTAT_DMASK; 535 result = 0; 536 switch (state) { 537 case PCI_POWERSTATE_D0: 538 status |= PCIM_PSTAT_D0; 539 break; 540 case PCI_POWERSTATE_D1: 541 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 542 return (EOPNOTSUPP); 543 status |= PCIM_PSTAT_D1; 544 break; 545 case PCI_POWERSTATE_D2: 546 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 547 return (EOPNOTSUPP); 548 status |= PCIM_PSTAT_D2; 549 break; 550 case PCI_POWERSTATE_D3: 551 status |= PCIM_PSTAT_D3; 552 break; 553 default: 554 return (EINVAL); 555 } 556 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 557 if (delay) 558 DELAY(delay); 559 return (0); 560 } 561 562 int 563 pci_get_powerstate_method(device_t dev, device_t child) 564 { 565 struct pci_devinfo *dinfo = device_get_ivars(child); 566 pcicfgregs *cfg = &dinfo->cfg; 567 uint16_t status; 568 int result; 569 570 if (cfg->pp.pp_cap != 0) { 571 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 572 switch (status & PCIM_PSTAT_DMASK) { 573 case PCIM_PSTAT_D0: 574 result = PCI_POWERSTATE_D0; 575 break; 576 case PCIM_PSTAT_D1: 577 result = PCI_POWERSTATE_D1; 578 break; 579 case PCIM_PSTAT_D2: 580 result = PCI_POWERSTATE_D2; 581 break; 582 case PCIM_PSTAT_D3: 583 result = PCI_POWERSTATE_D3; 584 break; 585 default: 586 result = PCI_POWERSTATE_UNKNOWN; 587 break; 588 } 589 } else { 590 /* No support, device is always at D0 */ 591 result = PCI_POWERSTATE_D0; 592 } 593 return (result); 594 } 595 596 /* 597 * Some convenience functions for PCI device drivers. 598 */ 599 600 static __inline void 601 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 602 { 603 uint16_t command; 604 605 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 606 command |= bit; 607 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 608 } 609 610 static __inline void 611 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 612 { 613 uint16_t command; 614 615 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 616 command &= ~bit; 617 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 618 } 619 620 int 621 pci_enable_busmaster_method(device_t dev, device_t child) 622 { 623 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 624 return (0); 625 } 626 627 int 628 pci_disable_busmaster_method(device_t dev, device_t child) 629 { 630 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 631 return (0); 632 } 633 634 int 635 pci_enable_io_method(device_t dev, device_t child, int space) 636 { 637 uint16_t command; 638 uint16_t bit; 639 char *error; 640 641 bit = 0; 642 error = NULL; 643 644 switch(space) { 645 case SYS_RES_IOPORT: 646 bit = PCIM_CMD_PORTEN; 647 error = "port"; 648 break; 649 case SYS_RES_MEMORY: 650 bit = PCIM_CMD_MEMEN; 651 error = "memory"; 652 break; 653 default: 654 return (EINVAL); 655 } 656 pci_set_command_bit(dev, child, bit); 657 /* Some devices seem to need a brief stall here, what do to? */ 658 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 659 if (command & bit) 660 return (0); 661 device_printf(child, "failed to enable %s mapping!\n", error); 662 return (ENXIO); 663 } 664 665 int 666 pci_disable_io_method(device_t dev, device_t child, int space) 667 { 668 uint16_t command; 669 uint16_t bit; 670 char *error; 671 672 bit = 0; 673 error = NULL; 674 675 switch(space) { 676 case SYS_RES_IOPORT: 677 bit = PCIM_CMD_PORTEN; 678 error = "port"; 679 break; 680 case SYS_RES_MEMORY: 681 bit = PCIM_CMD_MEMEN; 682 error = "memory"; 683 break; 684 default: 685 return (EINVAL); 686 } 687 pci_clear_command_bit(dev, child, bit); 688 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 689 if (command & bit) { 690 device_printf(child, "failed to disable %s mapping!\n", error); 691 return (ENXIO); 692 } 693 return (0); 694 } 695 696 /* 697 * New style pci driver. Parent device is either a pci-host-bridge or a 698 * pci-pci-bridge. Both kinds are represented by instances of pcib. 699 */ 700 701 void 702 pci_print_verbose(struct pci_devinfo *dinfo) 703 { 704 if (bootverbose) { 705 pcicfgregs *cfg = &dinfo->cfg; 706 707 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 708 cfg->vendor, cfg->device, cfg->revid); 709 printf("\tbus=%d, slot=%d, func=%d\n", 710 cfg->bus, cfg->slot, cfg->func); 711 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 712 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 713 cfg->mfdev); 714 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 715 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 716 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 717 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 718 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 719 if (cfg->intpin > 0) 720 printf("\tintpin=%c, irq=%d\n", 721 cfg->intpin +'a' -1, cfg->intline); 722 if (cfg->pp.pp_cap) { 723 uint16_t status; 724 725 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 726 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 727 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 728 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 729 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 730 status & PCIM_PSTAT_DMASK); 731 } 732 if (cfg->msi.msi_data) { 733 int ctrl; 734 735 ctrl = cfg->msi.msi_ctrl; 736 printf("\tMSI supports %d message%s%s%s\n", 737 cfg->msi.msi_msgnum, 738 (cfg->msi.msi_msgnum == 1) ? "" : "s", 739 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 740 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 741 } 742 } 743 } 744 745 static int 746 pci_porten(device_t pcib, int b, int s, int f) 747 { 748 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 749 & PCIM_CMD_PORTEN) != 0; 750 } 751 752 static int 753 pci_memen(device_t pcib, int b, int s, int f) 754 { 755 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 756 & PCIM_CMD_MEMEN) != 0; 757 } 758 759 /* 760 * Add a resource based on a pci map register. Return 1 if the map 761 * register is a 32bit map register or 2 if it is a 64bit register. 762 */ 763 static int 764 pci_add_map(device_t pcib, device_t bus, device_t dev, 765 int b, int s, int f, int reg, struct resource_list *rl) 766 { 767 uint32_t map; 768 uint64_t base; 769 uint64_t start, end, count; 770 uint8_t ln2size; 771 uint8_t ln2range; 772 uint32_t testval; 773 uint16_t cmd; 774 int type; 775 776 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 777 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 778 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 779 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 780 781 if (pci_maptype(map) & PCI_MAPMEM) 782 type = SYS_RES_MEMORY; 783 else 784 type = SYS_RES_IOPORT; 785 ln2size = pci_mapsize(testval); 786 ln2range = pci_maprange(testval); 787 base = pci_mapbase(map); 788 789 /* 790 * For I/O registers, if bottom bit is set, and the next bit up 791 * isn't clear, we know we have a BAR that doesn't conform to the 792 * spec, so ignore it. Also, sanity check the size of the data 793 * areas to the type of memory involved. Memory must be at least 794 * 32 bytes in size, while I/O ranges must be at least 4. 795 */ 796 if ((testval & 0x1) == 0x1 && 797 (testval & 0x2) != 0) 798 return (1); 799 if ((type == SYS_RES_MEMORY && ln2size < 5) || 800 (type == SYS_RES_IOPORT && ln2size < 2)) 801 return (1); 802 803 if (ln2range == 64) 804 /* Read the other half of a 64bit map register */ 805 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 806 807 if (bootverbose) { 808 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 809 reg, pci_maptype(map), ln2range, 810 (unsigned int) base, ln2size); 811 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 812 printf(", port disabled\n"); 813 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 814 printf(", memory disabled\n"); 815 else 816 printf(", enabled\n"); 817 } 818 819 /* 820 * This code theoretically does the right thing, but has 821 * undesirable side effects in some cases where peripherals 822 * respond oddly to having these bits enabled. Let the user 823 * be able to turn them off (since pci_enable_io_modes is 1 by 824 * default). 825 */ 826 if (pci_enable_io_modes) { 827 /* Turn on resources that have been left off by a lazy BIOS */ 828 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 829 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 830 cmd |= PCIM_CMD_PORTEN; 831 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 832 } 833 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 834 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 835 cmd |= PCIM_CMD_MEMEN; 836 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 837 } 838 } else { 839 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 840 return (1); 841 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 842 return (1); 843 } 844 /* 845 * If base is 0, then we have problems. It is best to ignore 846 * such entires for the moment. These will be allocated later if 847 * the driver specifically requests them. 848 */ 849 if (base == 0) 850 return 1; 851 852 start = base; 853 end = base + (1 << ln2size) - 1; 854 count = 1 << ln2size; 855 resource_list_add(rl, type, reg, start, end, count); 856 857 /* 858 * Not quite sure what to do on failure of allocating the resource 859 * since I can postulate several right answers. 860 */ 861 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 862 return ((ln2range == 64) ? 2 : 1); 863 } 864 865 /* 866 * For ATA devices we need to decide early what addressing mode to use. 867 * Legacy demands that the primary and secondary ATA ports sits on the 868 * same addresses that old ISA hardware did. This dictates that we use 869 * those addresses and ignore the BAR's if we cannot set PCI native 870 * addressing mode. 871 */ 872 static void 873 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 874 int s, int f, struct resource_list *rl) 875 { 876 int rid, type, progif; 877 #if 0 878 /* if this device supports PCI native addressing use it */ 879 progif = pci_read_config(dev, PCIR_PROGIF, 1); 880 if ((progif & 0x8a) == 0x8a) { 881 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 882 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 883 printf("Trying ATA native PCI addressing mode\n"); 884 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 885 } 886 } 887 #endif 888 progif = pci_read_config(dev, PCIR_PROGIF, 1); 889 type = SYS_RES_IOPORT; 890 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 891 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 892 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 893 } 894 else { 895 rid = PCIR_BAR(0); 896 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 897 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 898 rid = PCIR_BAR(1); 899 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 900 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 901 } 902 if (progif & PCIP_STORAGE_IDE_MODESEC) { 903 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 904 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 905 } 906 else { 907 rid = PCIR_BAR(2); 908 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 909 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 910 rid = PCIR_BAR(3); 911 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 912 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 913 } 914 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 915 } 916 917 static void 918 pci_add_resources(device_t pcib, device_t bus, device_t dev) 919 { 920 struct pci_devinfo *dinfo = device_get_ivars(dev); 921 pcicfgregs *cfg = &dinfo->cfg; 922 struct resource_list *rl = &dinfo->resources; 923 struct pci_quirk *q; 924 int b, i, irq, f, s; 925 926 b = cfg->bus; 927 s = cfg->slot; 928 f = cfg->func; 929 930 /* ATA devices needs special map treatment */ 931 if ((pci_get_class(dev) == PCIC_STORAGE) && 932 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 933 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 934 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 935 else 936 for (i = 0; i < cfg->nummaps;) 937 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 938 rl); 939 940 for (q = &pci_quirks[0]; q->devid; q++) { 941 if (q->devid == ((cfg->device << 16) | cfg->vendor) 942 && q->type == PCI_QUIRK_MAP_REG) 943 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 944 } 945 946 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 947 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 948 defined(__arm__) || defined(__alpha__) 949 /* 950 * Try to re-route interrupts. Sometimes the BIOS or 951 * firmware may leave bogus values in these registers. 952 * If the re-route fails, then just stick with what we 953 * have. 954 */ 955 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 956 if (PCI_INTERRUPT_VALID(irq)) { 957 pci_write_config(dev, PCIR_INTLINE, irq, 1); 958 cfg->intline = irq; 959 } else 960 #endif 961 irq = cfg->intline; 962 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 963 } 964 } 965 966 void 967 pci_add_children(device_t dev, int busno, size_t dinfo_size) 968 { 969 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 970 device_t pcib = device_get_parent(dev); 971 struct pci_devinfo *dinfo; 972 int maxslots; 973 int s, f, pcifunchigh; 974 uint8_t hdrtype; 975 976 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 977 ("dinfo_size too small")); 978 maxslots = PCIB_MAXSLOTS(pcib); 979 for (s = 0; s <= maxslots; s++) { 980 pcifunchigh = 0; 981 f = 0; 982 hdrtype = REG(PCIR_HDRTYPE, 1); 983 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 984 continue; 985 if (hdrtype & PCIM_MFDEV) 986 pcifunchigh = PCI_FUNCMAX; 987 for (f = 0; f <= pcifunchigh; f++) { 988 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 989 if (dinfo != NULL) { 990 pci_add_child(dev, dinfo); 991 } 992 } 993 } 994 #undef REG 995 } 996 997 void 998 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 999 { 1000 device_t pcib; 1001 1002 pcib = device_get_parent(bus); 1003 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1004 device_set_ivars(dinfo->cfg.dev, dinfo); 1005 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1006 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1007 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1008 pci_print_verbose(dinfo); 1009 } 1010 1011 static int 1012 pci_probe(device_t dev) 1013 { 1014 1015 device_set_desc(dev, "PCI bus"); 1016 1017 /* Allow other subclasses to override this driver. */ 1018 return (-1000); 1019 } 1020 1021 static int 1022 pci_attach(device_t dev) 1023 { 1024 int busno; 1025 1026 /* 1027 * Since there can be multiple independantly numbered PCI 1028 * busses on some large alpha systems, we can't use the unit 1029 * number to decide what bus we are probing. We ask the parent 1030 * pcib what our bus number is. 1031 */ 1032 busno = pcib_get_bus(dev); 1033 if (bootverbose) 1034 device_printf(dev, "physical bus=%d\n", busno); 1035 1036 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1037 1038 return (bus_generic_attach(dev)); 1039 } 1040 1041 int 1042 pci_suspend(device_t dev) 1043 { 1044 int dstate, error, i, numdevs; 1045 device_t acpi_dev, child, *devlist; 1046 struct pci_devinfo *dinfo; 1047 1048 /* 1049 * Save the PCI configuration space for each child and set the 1050 * device in the appropriate power state for this sleep state. 1051 */ 1052 acpi_dev = NULL; 1053 if (pci_do_powerstate) 1054 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1055 device_get_children(dev, &devlist, &numdevs); 1056 for (i = 0; i < numdevs; i++) { 1057 child = devlist[i]; 1058 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1059 pci_cfg_save(child, dinfo, 0); 1060 } 1061 1062 /* Suspend devices before potentially powering them down. */ 1063 error = bus_generic_suspend(dev); 1064 if (error) 1065 return (error); 1066 1067 /* 1068 * Always set the device to D3. If ACPI suggests a different 1069 * power state, use it instead. If ACPI is not present, the 1070 * firmware is responsible for managing device power. Skip 1071 * children who aren't attached since they are powered down 1072 * separately. Only manage type 0 devices for now. 1073 */ 1074 for (i = 0; acpi_dev && i < numdevs; i++) { 1075 child = devlist[i]; 1076 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1077 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1078 dstate = PCI_POWERSTATE_D3; 1079 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1080 pci_set_powerstate(child, dstate); 1081 } 1082 } 1083 free(devlist, M_TEMP); 1084 return (0); 1085 } 1086 1087 int 1088 pci_resume(device_t dev) 1089 { 1090 int i, numdevs; 1091 device_t acpi_dev, child, *devlist; 1092 struct pci_devinfo *dinfo; 1093 1094 /* 1095 * Set each child to D0 and restore its PCI configuration space. 1096 */ 1097 acpi_dev = NULL; 1098 if (pci_do_powerstate) 1099 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1100 device_get_children(dev, &devlist, &numdevs); 1101 for (i = 0; i < numdevs; i++) { 1102 /* 1103 * Notify ACPI we're going to D0 but ignore the result. If 1104 * ACPI is not present, the firmware is responsible for 1105 * managing device power. Only manage type 0 devices for now. 1106 */ 1107 child = devlist[i]; 1108 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1109 if (acpi_dev && device_is_attached(child) && 1110 dinfo->cfg.hdrtype == 0) { 1111 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1112 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1113 } 1114 1115 /* Now the device is powered up, restore its config space. */ 1116 pci_cfg_restore(child, dinfo); 1117 } 1118 free(devlist, M_TEMP); 1119 return (bus_generic_resume(dev)); 1120 } 1121 1122 static void 1123 pci_load_vendor_data(void) 1124 { 1125 caddr_t vendordata, info; 1126 1127 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1128 info = preload_search_info(vendordata, MODINFO_ADDR); 1129 pci_vendordata = *(char **)info; 1130 info = preload_search_info(vendordata, MODINFO_SIZE); 1131 pci_vendordata_size = *(size_t *)info; 1132 /* terminate the database */ 1133 pci_vendordata[pci_vendordata_size] = '\n'; 1134 } 1135 } 1136 1137 void 1138 pci_driver_added(device_t dev, driver_t *driver) 1139 { 1140 int numdevs; 1141 device_t *devlist; 1142 device_t child; 1143 struct pci_devinfo *dinfo; 1144 int i; 1145 1146 if (bootverbose) 1147 device_printf(dev, "driver added\n"); 1148 DEVICE_IDENTIFY(driver, dev); 1149 device_get_children(dev, &devlist, &numdevs); 1150 for (i = 0; i < numdevs; i++) { 1151 child = devlist[i]; 1152 if (device_get_state(child) != DS_NOTPRESENT) 1153 continue; 1154 dinfo = device_get_ivars(child); 1155 pci_print_verbose(dinfo); 1156 /*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1157 if (bootverbose) 1158 printf("pci%d:%d:%d: reprobing on driver added\n", 1159 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1160 pci_cfg_restore(child, dinfo); 1161 if (device_probe_and_attach(child) != 0) 1162 pci_cfg_save(child, dinfo, 1); 1163 } 1164 free(devlist, M_TEMP); 1165 } 1166 1167 int 1168 pci_print_child(device_t dev, device_t child) 1169 { 1170 struct pci_devinfo *dinfo; 1171 struct resource_list *rl; 1172 int retval = 0; 1173 1174 dinfo = device_get_ivars(child); 1175 rl = &dinfo->resources; 1176 1177 retval += bus_print_child_header(dev, child); 1178 1179 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1180 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1181 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1182 if (device_get_flags(dev)) 1183 retval += printf(" flags %#x", device_get_flags(dev)); 1184 1185 retval += printf(" at device %d.%d", pci_get_slot(child), 1186 pci_get_function(child)); 1187 1188 retval += bus_print_child_footer(dev, child); 1189 1190 return (retval); 1191 } 1192 1193 static struct 1194 { 1195 int class; 1196 int subclass; 1197 char *desc; 1198 } pci_nomatch_tab[] = { 1199 {PCIC_OLD, -1, "old"}, 1200 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1201 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1202 {PCIC_STORAGE, -1, "mass storage"}, 1203 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1204 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1205 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1206 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1207 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1208 {PCIC_NETWORK, -1, "network"}, 1209 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1210 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1211 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1212 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1213 {PCIC_DISPLAY, -1, "display"}, 1214 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1215 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1216 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1217 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1218 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1219 {PCIC_MEMORY, -1, "memory"}, 1220 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1221 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1222 {PCIC_BRIDGE, -1, "bridge"}, 1223 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1224 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1225 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1226 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1227 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1228 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1229 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1230 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1231 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1232 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1233 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1234 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1235 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1236 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1237 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1238 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1239 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1240 {PCIC_INPUTDEV, -1, "input device"}, 1241 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1242 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1243 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1244 {PCIC_DOCKING, -1, "docking station"}, 1245 {PCIC_PROCESSOR, -1, "processor"}, 1246 {PCIC_SERIALBUS, -1, "serial bus"}, 1247 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1248 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1249 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1250 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1251 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1252 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1253 {0, 0, NULL} 1254 }; 1255 1256 void 1257 pci_probe_nomatch(device_t dev, device_t child) 1258 { 1259 int i; 1260 char *cp, *scp, *device; 1261 1262 /* 1263 * Look for a listing for this device in a loaded device database. 1264 */ 1265 if ((device = pci_describe_device(child)) != NULL) { 1266 device_printf(dev, "<%s>", device); 1267 free(device, M_DEVBUF); 1268 } else { 1269 /* 1270 * Scan the class/subclass descriptions for a general 1271 * description. 1272 */ 1273 cp = "unknown"; 1274 scp = NULL; 1275 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1276 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1277 if (pci_nomatch_tab[i].subclass == -1) { 1278 cp = pci_nomatch_tab[i].desc; 1279 } else if (pci_nomatch_tab[i].subclass == 1280 pci_get_subclass(child)) { 1281 scp = pci_nomatch_tab[i].desc; 1282 } 1283 } 1284 } 1285 device_printf(dev, "<%s%s%s>", 1286 cp ? cp : "", 1287 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1288 scp ? scp : ""); 1289 } 1290 printf(" at device %d.%d (no driver attached)\n", 1291 pci_get_slot(child), pci_get_function(child)); 1292 if (pci_do_powerstate) 1293 pci_cfg_save(child, 1294 (struct pci_devinfo *) device_get_ivars(child), 1); 1295 return; 1296 } 1297 1298 /* 1299 * Parse the PCI device database, if loaded, and return a pointer to a 1300 * description of the device. 1301 * 1302 * The database is flat text formatted as follows: 1303 * 1304 * Any line not in a valid format is ignored. 1305 * Lines are terminated with newline '\n' characters. 1306 * 1307 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1308 * the vendor name. 1309 * 1310 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1311 * - devices cannot be listed without a corresponding VENDOR line. 1312 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1313 * another TAB, then the device name. 1314 */ 1315 1316 /* 1317 * Assuming (ptr) points to the beginning of a line in the database, 1318 * return the vendor or device and description of the next entry. 1319 * The value of (vendor) or (device) inappropriate for the entry type 1320 * is set to -1. Returns nonzero at the end of the database. 1321 * 1322 * Note that this is slightly unrobust in the face of corrupt data; 1323 * we attempt to safeguard against this by spamming the end of the 1324 * database with a newline when we initialise. 1325 */ 1326 static int 1327 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1328 { 1329 char *cp = *ptr; 1330 int left; 1331 1332 *device = -1; 1333 *vendor = -1; 1334 **desc = '\0'; 1335 for (;;) { 1336 left = pci_vendordata_size - (cp - pci_vendordata); 1337 if (left <= 0) { 1338 *ptr = cp; 1339 return(1); 1340 } 1341 1342 /* vendor entry? */ 1343 if (*cp != '\t' && 1344 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1345 break; 1346 /* device entry? */ 1347 if (*cp == '\t' && 1348 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1349 break; 1350 1351 /* skip to next line */ 1352 while (*cp != '\n' && left > 0) { 1353 cp++; 1354 left--; 1355 } 1356 if (*cp == '\n') { 1357 cp++; 1358 left--; 1359 } 1360 } 1361 /* skip to next line */ 1362 while (*cp != '\n' && left > 0) { 1363 cp++; 1364 left--; 1365 } 1366 if (*cp == '\n' && left > 0) 1367 cp++; 1368 *ptr = cp; 1369 return(0); 1370 } 1371 1372 static char * 1373 pci_describe_device(device_t dev) 1374 { 1375 int vendor, device; 1376 char *desc, *vp, *dp, *line; 1377 1378 desc = vp = dp = NULL; 1379 1380 /* 1381 * If we have no vendor data, we can't do anything. 1382 */ 1383 if (pci_vendordata == NULL) 1384 goto out; 1385 1386 /* 1387 * Scan the vendor data looking for this device 1388 */ 1389 line = pci_vendordata; 1390 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1391 goto out; 1392 for (;;) { 1393 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1394 goto out; 1395 if (vendor == pci_get_vendor(dev)) 1396 break; 1397 } 1398 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1399 goto out; 1400 for (;;) { 1401 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1402 *dp = 0; 1403 break; 1404 } 1405 if (vendor != -1) { 1406 *dp = 0; 1407 break; 1408 } 1409 if (device == pci_get_device(dev)) 1410 break; 1411 } 1412 if (dp[0] == '\0') 1413 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1414 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1415 NULL) 1416 sprintf(desc, "%s, %s", vp, dp); 1417 out: 1418 if (vp != NULL) 1419 free(vp, M_DEVBUF); 1420 if (dp != NULL) 1421 free(dp, M_DEVBUF); 1422 return(desc); 1423 } 1424 1425 int 1426 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1427 { 1428 struct pci_devinfo *dinfo; 1429 pcicfgregs *cfg; 1430 1431 dinfo = device_get_ivars(child); 1432 cfg = &dinfo->cfg; 1433 1434 switch (which) { 1435 case PCI_IVAR_ETHADDR: 1436 /* 1437 * The generic accessor doesn't deal with failure, so 1438 * we set the return value, then return an error. 1439 */ 1440 *((uint8_t **) result) = NULL; 1441 return (EINVAL); 1442 case PCI_IVAR_SUBVENDOR: 1443 *result = cfg->subvendor; 1444 break; 1445 case PCI_IVAR_SUBDEVICE: 1446 *result = cfg->subdevice; 1447 break; 1448 case PCI_IVAR_VENDOR: 1449 *result = cfg->vendor; 1450 break; 1451 case PCI_IVAR_DEVICE: 1452 *result = cfg->device; 1453 break; 1454 case PCI_IVAR_DEVID: 1455 *result = (cfg->device << 16) | cfg->vendor; 1456 break; 1457 case PCI_IVAR_CLASS: 1458 *result = cfg->baseclass; 1459 break; 1460 case PCI_IVAR_SUBCLASS: 1461 *result = cfg->subclass; 1462 break; 1463 case PCI_IVAR_PROGIF: 1464 *result = cfg->progif; 1465 break; 1466 case PCI_IVAR_REVID: 1467 *result = cfg->revid; 1468 break; 1469 case PCI_IVAR_INTPIN: 1470 *result = cfg->intpin; 1471 break; 1472 case PCI_IVAR_IRQ: 1473 *result = cfg->intline; 1474 break; 1475 case PCI_IVAR_BUS: 1476 *result = cfg->bus; 1477 break; 1478 case PCI_IVAR_SLOT: 1479 *result = cfg->slot; 1480 break; 1481 case PCI_IVAR_FUNCTION: 1482 *result = cfg->func; 1483 break; 1484 default: 1485 return (ENOENT); 1486 } 1487 return (0); 1488 } 1489 1490 int 1491 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1492 { 1493 struct pci_devinfo *dinfo; 1494 1495 dinfo = device_get_ivars(child); 1496 1497 switch (which) { 1498 case PCI_IVAR_INTPIN: 1499 dinfo->cfg.intpin = value; 1500 return (0); 1501 case PCI_IVAR_ETHADDR: 1502 case PCI_IVAR_SUBVENDOR: 1503 case PCI_IVAR_SUBDEVICE: 1504 case PCI_IVAR_VENDOR: 1505 case PCI_IVAR_DEVICE: 1506 case PCI_IVAR_DEVID: 1507 case PCI_IVAR_CLASS: 1508 case PCI_IVAR_SUBCLASS: 1509 case PCI_IVAR_PROGIF: 1510 case PCI_IVAR_REVID: 1511 case PCI_IVAR_IRQ: 1512 case PCI_IVAR_BUS: 1513 case PCI_IVAR_SLOT: 1514 case PCI_IVAR_FUNCTION: 1515 return (EINVAL); /* disallow for now */ 1516 1517 default: 1518 return (ENOENT); 1519 } 1520 } 1521 1522 1523 #include "opt_ddb.h" 1524 #ifdef DDB 1525 #include <ddb/ddb.h> 1526 #include <sys/cons.h> 1527 1528 /* 1529 * List resources based on pci map registers, used for within ddb 1530 */ 1531 1532 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1533 { 1534 struct pci_devinfo *dinfo; 1535 struct devlist *devlist_head; 1536 struct pci_conf *p; 1537 const char *name; 1538 int i, error, none_count, quit; 1539 1540 none_count = 0; 1541 /* get the head of the device queue */ 1542 devlist_head = &pci_devq; 1543 1544 /* 1545 * Go through the list of devices and print out devices 1546 */ 1547 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1548 for (error = 0, i = 0, quit = 0, 1549 dinfo = STAILQ_FIRST(devlist_head); 1550 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1551 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1552 1553 /* Populate pd_name and pd_unit */ 1554 name = NULL; 1555 if (dinfo->cfg.dev) 1556 name = device_get_name(dinfo->cfg.dev); 1557 1558 p = &dinfo->conf; 1559 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1560 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1561 (name && *name) ? name : "none", 1562 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1563 none_count++, 1564 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1565 p->pc_sel.pc_func, (p->pc_class << 16) | 1566 (p->pc_subclass << 8) | p->pc_progif, 1567 (p->pc_subdevice << 16) | p->pc_subvendor, 1568 (p->pc_device << 16) | p->pc_vendor, 1569 p->pc_revid, p->pc_hdr); 1570 } 1571 } 1572 #endif /* DDB */ 1573 1574 static struct resource * 1575 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1576 u_long start, u_long end, u_long count, u_int flags) 1577 { 1578 struct pci_devinfo *dinfo = device_get_ivars(child); 1579 struct resource_list *rl = &dinfo->resources; 1580 struct resource_list_entry *rle; 1581 struct resource *res; 1582 uint32_t map, testval; 1583 int mapsize; 1584 1585 /* 1586 * Weed out the bogons, and figure out how large the BAR/map 1587 * is. Bars that read back 0 here are bogus and unimplemented. 1588 * Note: atapci in legacy mode are special and handled elsewhere 1589 * in the code. If you have a atapci device in legacy mode and 1590 * it fails here, that other code is broken. 1591 */ 1592 res = NULL; 1593 map = pci_read_config(child, *rid, 4); 1594 pci_write_config(child, *rid, 0xffffffff, 4); 1595 testval = pci_read_config(child, *rid, 4); 1596 if (testval == 0) 1597 return (NULL); 1598 if (pci_maptype(testval) & PCI_MAPMEM) { 1599 if (type != SYS_RES_MEMORY) { 1600 device_printf(child, 1601 "failed: rid %#x is memory, requested %d\n", 1602 *rid, type); 1603 goto out; 1604 } 1605 } else { 1606 if (type != SYS_RES_IOPORT) { 1607 device_printf(child, 1608 "failed: rid %#x is ioport, requested %d\n", 1609 *rid, type); 1610 goto out; 1611 } 1612 } 1613 /* 1614 * For real BARs, we need to override the size that 1615 * the driver requests, because that's what the BAR 1616 * actually uses and we would otherwise have a 1617 * situation where we might allocate the excess to 1618 * another driver, which won't work. 1619 */ 1620 mapsize = pci_mapsize(testval); 1621 count = 1 << mapsize; 1622 if (RF_ALIGNMENT(flags) < mapsize) 1623 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1624 1625 /* 1626 * Allocate enough resource, and then write back the 1627 * appropriate bar for that resource. 1628 */ 1629 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1630 start, end, count, flags); 1631 if (res == NULL) { 1632 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1633 count, *rid, type); 1634 goto out; 1635 } 1636 resource_list_add(rl, type, *rid, start, end, count); 1637 rle = resource_list_find(rl, type, *rid); 1638 if (rle == NULL) 1639 panic("pci_alloc_map: unexpectedly can't find resource."); 1640 rle->res = res; 1641 if (bootverbose) 1642 device_printf(child, 1643 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1644 count, *rid, type, rman_get_start(res)); 1645 map = rman_get_start(res); 1646 out:; 1647 pci_write_config(child, *rid, map, 4); 1648 return (res); 1649 } 1650 1651 1652 struct resource * 1653 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1654 u_long start, u_long end, u_long count, u_int flags) 1655 { 1656 struct pci_devinfo *dinfo = device_get_ivars(child); 1657 struct resource_list *rl = &dinfo->resources; 1658 struct resource_list_entry *rle; 1659 pcicfgregs *cfg = &dinfo->cfg; 1660 1661 /* 1662 * Perform lazy resource allocation 1663 */ 1664 if (device_get_parent(child) == dev) { 1665 switch (type) { 1666 case SYS_RES_IRQ: 1667 /* 1668 * If the child device doesn't have an 1669 * interrupt routed and is deserving of an 1670 * interrupt, try to assign it one. 1671 */ 1672 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1673 (cfg->intpin != 0)) { 1674 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1675 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1676 pci_write_config(child, PCIR_INTLINE, 1677 cfg->intline, 1); 1678 resource_list_add(rl, SYS_RES_IRQ, 0, 1679 cfg->intline, cfg->intline, 1); 1680 } 1681 } 1682 break; 1683 case SYS_RES_IOPORT: 1684 case SYS_RES_MEMORY: 1685 if (*rid < PCIR_BAR(cfg->nummaps)) { 1686 /* 1687 * Enable the I/O mode. We should 1688 * also be assigning resources too 1689 * when none are present. The 1690 * resource_list_alloc kind of sorta does 1691 * this... 1692 */ 1693 if (PCI_ENABLE_IO(dev, child, type)) 1694 return (NULL); 1695 } 1696 rle = resource_list_find(rl, type, *rid); 1697 if (rle == NULL) 1698 return (pci_alloc_map(dev, child, type, rid, 1699 start, end, count, flags)); 1700 break; 1701 } 1702 /* 1703 * If we've already allocated the resource, then 1704 * return it now. But first we may need to activate 1705 * it, since we don't allocate the resource as active 1706 * above. Normally this would be done down in the 1707 * nexus, but since we short-circuit that path we have 1708 * to do its job here. Not sure if we should free the 1709 * resource if it fails to activate. 1710 */ 1711 rle = resource_list_find(rl, type, *rid); 1712 if (rle != NULL && rle->res != NULL) { 1713 if (bootverbose) 1714 device_printf(child, 1715 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1716 rman_get_size(rle->res), *rid, type, 1717 rman_get_start(rle->res)); 1718 if ((flags & RF_ACTIVE) && 1719 bus_generic_activate_resource(dev, child, type, 1720 *rid, rle->res) != 0) 1721 return NULL; 1722 return (rle->res); 1723 } 1724 } 1725 return (resource_list_alloc(rl, dev, child, type, rid, 1726 start, end, count, flags)); 1727 } 1728 1729 void 1730 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1731 { 1732 struct pci_devinfo *dinfo; 1733 struct resource_list *rl; 1734 struct resource_list_entry *rle; 1735 1736 if (device_get_parent(child) != dev) 1737 return; 1738 1739 dinfo = device_get_ivars(child); 1740 rl = &dinfo->resources; 1741 rle = resource_list_find(rl, type, rid); 1742 if (rle) { 1743 if (rle->res) { 1744 if (rman_get_device(rle->res) != dev || 1745 rman_get_flags(rle->res) & RF_ACTIVE) { 1746 device_printf(dev, "delete_resource: " 1747 "Resource still owned by child, oops. " 1748 "(type=%d, rid=%d, addr=%lx)\n", 1749 rle->type, rle->rid, 1750 rman_get_start(rle->res)); 1751 return; 1752 } 1753 bus_release_resource(dev, type, rid, rle->res); 1754 } 1755 resource_list_delete(rl, type, rid); 1756 } 1757 /* 1758 * Why do we turn off the PCI configuration BAR when we delete a 1759 * resource? -- imp 1760 */ 1761 pci_write_config(child, rid, 0, 4); 1762 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1763 } 1764 1765 struct resource_list * 1766 pci_get_resource_list (device_t dev, device_t child) 1767 { 1768 struct pci_devinfo *dinfo = device_get_ivars(child); 1769 1770 return (&dinfo->resources); 1771 } 1772 1773 uint32_t 1774 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1775 { 1776 struct pci_devinfo *dinfo = device_get_ivars(child); 1777 pcicfgregs *cfg = &dinfo->cfg; 1778 1779 return (PCIB_READ_CONFIG(device_get_parent(dev), 1780 cfg->bus, cfg->slot, cfg->func, reg, width)); 1781 } 1782 1783 void 1784 pci_write_config_method(device_t dev, device_t child, int reg, 1785 uint32_t val, int width) 1786 { 1787 struct pci_devinfo *dinfo = device_get_ivars(child); 1788 pcicfgregs *cfg = &dinfo->cfg; 1789 1790 PCIB_WRITE_CONFIG(device_get_parent(dev), 1791 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1792 } 1793 1794 int 1795 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1796 size_t buflen) 1797 { 1798 struct pci_devinfo *dinfo; 1799 1800 dinfo = device_get_ivars(child); 1801 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1802 pci_get_function(child)); 1803 return (0); 1804 } 1805 1806 int 1807 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1808 size_t buflen) 1809 { 1810 struct pci_devinfo *dinfo; 1811 pcicfgregs *cfg; 1812 1813 dinfo = device_get_ivars(child); 1814 cfg = &dinfo->cfg; 1815 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1816 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1817 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1818 cfg->progif); 1819 return (0); 1820 } 1821 1822 int 1823 pci_assign_interrupt_method(device_t dev, device_t child) 1824 { 1825 struct pci_devinfo *dinfo = device_get_ivars(child); 1826 pcicfgregs *cfg = &dinfo->cfg; 1827 1828 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1829 cfg->intpin)); 1830 } 1831 1832 static int 1833 pci_modevent(module_t mod, int what, void *arg) 1834 { 1835 static struct cdev *pci_cdev; 1836 1837 switch (what) { 1838 case MOD_LOAD: 1839 STAILQ_INIT(&pci_devq); 1840 pci_generation = 0; 1841 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1842 "pci"); 1843 pci_load_vendor_data(); 1844 break; 1845 1846 case MOD_UNLOAD: 1847 destroy_dev(pci_cdev); 1848 break; 1849 } 1850 1851 return (0); 1852 } 1853 1854 static void 1855 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1856 { 1857 int i; 1858 1859 /* 1860 * Only do header type 0 devices. Type 1 devices are bridges, 1861 * which we know need special treatment. Type 2 devices are 1862 * cardbus bridges which also require special treatment. 1863 * Other types are unknown, and we err on the side of safety 1864 * by ignoring them. 1865 */ 1866 if (dinfo->cfg.hdrtype != 0) 1867 return; 1868 1869 /* 1870 * Restore the device to full power mode. We must do this 1871 * before we restore the registers because moving from D3 to 1872 * D0 will cause the chip's BARs and some other registers to 1873 * be reset to some unknown power on reset values. Cut down 1874 * the noise on boot by doing nothing if we are already in 1875 * state D0. 1876 */ 1877 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1878 if (bootverbose) 1879 printf( 1880 "pci%d:%d:%d: Transition from D%d to D0\n", 1881 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1882 pci_get_powerstate(dev)); 1883 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1884 } 1885 for (i = 0; i < dinfo->cfg.nummaps; i++) 1886 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1887 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1888 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1889 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1890 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1891 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1892 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1893 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1894 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1895 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1896 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1897 } 1898 1899 static void 1900 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1901 { 1902 int i; 1903 uint32_t cls; 1904 int ps; 1905 1906 /* 1907 * Only do header type 0 devices. Type 1 devices are bridges, which 1908 * we know need special treatment. Type 2 devices are cardbus bridges 1909 * which also require special treatment. Other types are unknown, and 1910 * we err on the side of safety by ignoring them. Powering down 1911 * bridges should not be undertaken lightly. 1912 */ 1913 if (dinfo->cfg.hdrtype != 0) 1914 return; 1915 for (i = 0; i < dinfo->cfg.nummaps; i++) 1916 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1917 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1918 1919 /* 1920 * Some drivers apparently write to these registers w/o updating our 1921 * cached copy. No harm happens if we update the copy, so do so here 1922 * so we can restore them. The COMMAND register is modified by the 1923 * bus w/o updating the cache. This should represent the normally 1924 * writable portion of the 'defined' part of type 0 headers. In 1925 * theory we also need to save/restore the PCI capability structures 1926 * we know about, but apart from power we don't know any that are 1927 * writable. 1928 */ 1929 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1930 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1931 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1932 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1933 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1934 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1935 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1936 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1937 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1938 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1939 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1940 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1941 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1942 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1943 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1944 1945 /* 1946 * don't set the state for display devices, base peripherals and 1947 * memory devices since bad things happen when they are powered down. 1948 * We should (a) have drivers that can easily detach and (b) use 1949 * generic drivers for these devices so that some device actually 1950 * attaches. We need to make sure that when we implement (a) we don't 1951 * power the device down on a reattach. 1952 */ 1953 cls = pci_get_class(dev); 1954 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1955 cls != PCIC_BASEPERIPH) { 1956 /* 1957 * PCI spec says we can only go into D3 state from D0 state. 1958 * Transition from D[12] into D0 before going to D3 state. 1959 */ 1960 ps = pci_get_powerstate(dev); 1961 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1962 if (bootverbose) 1963 printf( 1964 "pci%d:%d:%d: Transition from D%d to D0\n", 1965 dinfo->cfg.bus, dinfo->cfg.slot, 1966 dinfo->cfg.func, ps); 1967 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1968 } 1969 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1970 if (bootverbose) 1971 printf( 1972 "pci%d:%d:%d: Transition from D0 to D3\n", 1973 dinfo->cfg.bus, dinfo->cfg.slot, 1974 dinfo->cfg.func); 1975 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1976 } 1977 } 1978 } 1979