1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include <dev/acpica/acpivar.h> 67 #include "acpi_if.h" 68 #else 69 #define ACPI_PWR_FOR_SLEEP(x, y, z) 70 #endif 71 72 static uint32_t pci_mapbase(unsigned mapreg); 73 static int pci_maptype(unsigned mapreg); 74 static int pci_mapsize(unsigned testval); 75 static int pci_maprange(unsigned mapreg); 76 static void pci_fixancient(pcicfgregs *cfg); 77 78 static int pci_porten(device_t pcib, int b, int s, int f); 79 static int pci_memen(device_t pcib, int b, int s, int f); 80 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl); 83 static void pci_add_resources(device_t pcib, device_t bus, 84 device_t dev); 85 static int pci_probe(device_t dev); 86 static int pci_attach(device_t dev); 87 static void pci_load_vendor_data(void); 88 static int pci_describe_parse_line(char **ptr, int *vendor, 89 int *device, char **desc); 90 static char *pci_describe_device(device_t dev); 91 static int pci_modevent(module_t mod, int what, void *arg); 92 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 93 pcicfgregs *cfg); 94 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 95 static void pci_cfg_restore(device_t, struct pci_devinfo *); 96 static void pci_cfg_save(device_t, struct pci_devinfo *, int); 97 98 static device_method_t pci_methods[] = { 99 /* Device interface */ 100 DEVMETHOD(device_probe, pci_probe), 101 DEVMETHOD(device_attach, pci_attach), 102 DEVMETHOD(device_shutdown, bus_generic_shutdown), 103 DEVMETHOD(device_suspend, pci_suspend), 104 DEVMETHOD(device_resume, pci_resume), 105 106 /* Bus interface */ 107 DEVMETHOD(bus_print_child, pci_print_child), 108 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 109 DEVMETHOD(bus_read_ivar, pci_read_ivar), 110 DEVMETHOD(bus_write_ivar, pci_write_ivar), 111 DEVMETHOD(bus_driver_added, pci_driver_added), 112 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 113 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 114 115 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 116 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 117 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 118 DEVMETHOD(bus_delete_resource, pci_delete_resource), 119 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 120 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 121 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 122 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 123 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 124 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 125 126 /* PCI interface */ 127 DEVMETHOD(pci_read_config, pci_read_config_method), 128 DEVMETHOD(pci_write_config, pci_write_config_method), 129 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 130 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 131 DEVMETHOD(pci_enable_io, pci_enable_io_method), 132 DEVMETHOD(pci_disable_io, pci_disable_io_method), 133 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 134 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 135 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 136 137 { 0, 0 } 138 }; 139 140 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 141 142 devclass_t pci_devclass; 143 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 144 MODULE_VERSION(pci, 1); 145 146 static char *pci_vendordata; 147 static size_t pci_vendordata_size; 148 149 150 struct pci_quirk { 151 uint32_t devid; /* Vendor/device of the card */ 152 int type; 153 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 154 int arg1; 155 int arg2; 156 }; 157 158 struct pci_quirk pci_quirks[] = { 159 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 160 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 163 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 164 165 { 0 } 166 }; 167 168 /* map register information */ 169 #define PCI_MAPMEM 0x01 /* memory map */ 170 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 171 #define PCI_MAPPORT 0x04 /* port map */ 172 173 struct devlist pci_devq; 174 uint32_t pci_generation; 175 uint32_t pci_numdevs = 0; 176 177 /* sysctl vars */ 178 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 179 180 static int pci_enable_io_modes = 1; 181 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 182 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 183 &pci_enable_io_modes, 1, 184 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 185 enable these bits correctly. We'd like to do this all the time, but there\n\ 186 are some peripherals that this causes problems with."); 187 188 static int pci_do_powerstate = 1; 189 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 190 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 191 &pci_do_powerstate, 1, 192 "Power down devices into D3 state when no driver attaches to them.\n\ 193 Otherwise, leave the device in D0 state when no driver attaches."); 194 195 /* Find a device_t by bus/slot/function */ 196 197 device_t 198 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 199 { 200 struct pci_devinfo *dinfo; 201 202 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 203 if ((dinfo->cfg.bus == bus) && 204 (dinfo->cfg.slot == slot) && 205 (dinfo->cfg.func == func)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211 } 212 213 /* Find a device_t by vendor/device ID */ 214 215 device_t 216 pci_find_device(uint16_t vendor, uint16_t device) 217 { 218 struct pci_devinfo *dinfo; 219 220 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 221 if ((dinfo->cfg.vendor == vendor) && 222 (dinfo->cfg.device == device)) { 223 return (dinfo->cfg.dev); 224 } 225 } 226 227 return (NULL); 228 } 229 230 /* return base address of memory or port map */ 231 232 static uint32_t 233 pci_mapbase(unsigned mapreg) 234 { 235 int mask = 0x03; 236 if ((mapreg & 0x01) == 0) 237 mask = 0x0f; 238 return (mapreg & ~mask); 239 } 240 241 /* return map type of memory or port map */ 242 243 static int 244 pci_maptype(unsigned mapreg) 245 { 246 static uint8_t maptype[0x10] = { 247 PCI_MAPMEM, PCI_MAPPORT, 248 PCI_MAPMEM, 0, 249 PCI_MAPMEM, PCI_MAPPORT, 250 0, 0, 251 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 252 PCI_MAPMEM|PCI_MAPMEMP, 0, 253 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 254 0, 0, 255 }; 256 257 return maptype[mapreg & 0x0f]; 258 } 259 260 /* return log2 of map size decoded for memory or port map */ 261 262 static int 263 pci_mapsize(unsigned testval) 264 { 265 int ln2size; 266 267 testval = pci_mapbase(testval); 268 ln2size = 0; 269 if (testval != 0) { 270 while ((testval & 1) == 0) 271 { 272 ln2size++; 273 testval >>= 1; 274 } 275 } 276 return (ln2size); 277 } 278 279 /* return log2 of address range supported by map register */ 280 281 static int 282 pci_maprange(unsigned mapreg) 283 { 284 int ln2range = 0; 285 switch (mapreg & 0x07) { 286 case 0x00: 287 case 0x01: 288 case 0x05: 289 ln2range = 32; 290 break; 291 case 0x02: 292 ln2range = 20; 293 break; 294 case 0x04: 295 ln2range = 64; 296 break; 297 } 298 return (ln2range); 299 } 300 301 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 302 303 static void 304 pci_fixancient(pcicfgregs *cfg) 305 { 306 if (cfg->hdrtype != 0) 307 return; 308 309 /* PCI to PCI bridges use header type 1 */ 310 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 311 cfg->hdrtype = 1; 312 } 313 314 /* extract header type specific config data */ 315 316 static void 317 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 318 { 319 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 320 switch (cfg->hdrtype) { 321 case 0: 322 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 323 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 324 cfg->nummaps = PCI_MAXMAPS_0; 325 break; 326 case 1: 327 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 328 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 329 cfg->nummaps = PCI_MAXMAPS_1; 330 break; 331 case 2: 332 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 333 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 334 cfg->nummaps = PCI_MAXMAPS_2; 335 break; 336 } 337 #undef REG 338 } 339 340 /* read configuration header into pcicfgregs structure */ 341 342 struct pci_devinfo * 343 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 344 { 345 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 346 pcicfgregs *cfg = NULL; 347 struct pci_devinfo *devlist_entry; 348 struct devlist *devlist_head; 349 350 devlist_head = &pci_devq; 351 352 devlist_entry = NULL; 353 354 if (REG(PCIR_DEVVENDOR, 4) != -1) { 355 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 356 if (devlist_entry == NULL) 357 return (NULL); 358 359 cfg = &devlist_entry->cfg; 360 361 cfg->bus = b; 362 cfg->slot = s; 363 cfg->func = f; 364 cfg->vendor = REG(PCIR_VENDOR, 2); 365 cfg->device = REG(PCIR_DEVICE, 2); 366 cfg->cmdreg = REG(PCIR_COMMAND, 2); 367 cfg->statreg = REG(PCIR_STATUS, 2); 368 cfg->baseclass = REG(PCIR_CLASS, 1); 369 cfg->subclass = REG(PCIR_SUBCLASS, 1); 370 cfg->progif = REG(PCIR_PROGIF, 1); 371 cfg->revid = REG(PCIR_REVID, 1); 372 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 373 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 374 cfg->lattimer = REG(PCIR_LATTIMER, 1); 375 cfg->intpin = REG(PCIR_INTPIN, 1); 376 cfg->intline = REG(PCIR_INTLINE, 1); 377 378 cfg->mingnt = REG(PCIR_MINGNT, 1); 379 cfg->maxlat = REG(PCIR_MAXLAT, 1); 380 381 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 382 cfg->hdrtype &= ~PCIM_MFDEV; 383 384 pci_fixancient(cfg); 385 pci_hdrtypedata(pcib, b, s, f, cfg); 386 387 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 388 pci_read_extcap(pcib, cfg); 389 390 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 391 392 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 393 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 394 devlist_entry->conf.pc_sel.pc_func = cfg->func; 395 devlist_entry->conf.pc_hdr = cfg->hdrtype; 396 397 devlist_entry->conf.pc_subvendor = cfg->subvendor; 398 devlist_entry->conf.pc_subdevice = cfg->subdevice; 399 devlist_entry->conf.pc_vendor = cfg->vendor; 400 devlist_entry->conf.pc_device = cfg->device; 401 402 devlist_entry->conf.pc_class = cfg->baseclass; 403 devlist_entry->conf.pc_subclass = cfg->subclass; 404 devlist_entry->conf.pc_progif = cfg->progif; 405 devlist_entry->conf.pc_revid = cfg->revid; 406 407 pci_numdevs++; 408 pci_generation++; 409 } 410 return (devlist_entry); 411 #undef REG 412 } 413 414 static void 415 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 416 { 417 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 418 int ptr, nextptr, ptrptr; 419 420 switch (cfg->hdrtype & PCIM_HDRTYPE) { 421 case 0: 422 ptrptr = PCIR_CAP_PTR; 423 break; 424 case 2: 425 ptrptr = 0x14; 426 break; 427 default: 428 return; /* no extended capabilities support */ 429 } 430 nextptr = REG(ptrptr, 1); /* sanity check? */ 431 432 /* 433 * Read capability entries. 434 */ 435 while (nextptr != 0) { 436 /* Sanity check */ 437 if (nextptr > 255) { 438 printf("illegal PCI extended capability offset %d\n", 439 nextptr); 440 return; 441 } 442 /* Find the next entry */ 443 ptr = nextptr; 444 nextptr = REG(ptr + 1, 1); 445 446 /* Process this entry */ 447 switch (REG(ptr, 1)) { 448 case PCIY_PMG: /* PCI power management */ 449 if (cfg->pp.pp_cap == 0) { 450 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 451 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 452 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 453 if ((nextptr - ptr) > PCIR_POWER_DATA) 454 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 455 } 456 break; 457 case PCIY_MSI: /* PCI MSI */ 458 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 459 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 460 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 461 else 462 cfg->msi.msi_data = PCIR_MSI_DATA; 463 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 464 PCIM_MSICTRL_MMC_MASK)>>1); 465 default: 466 break; 467 } 468 } 469 #undef REG 470 } 471 472 /* free pcicfgregs structure and all depending data structures */ 473 474 int 475 pci_freecfg(struct pci_devinfo *dinfo) 476 { 477 struct devlist *devlist_head; 478 479 devlist_head = &pci_devq; 480 481 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 482 free(dinfo, M_DEVBUF); 483 484 /* increment the generation count */ 485 pci_generation++; 486 487 /* we're losing one device */ 488 pci_numdevs--; 489 return (0); 490 } 491 492 /* 493 * PCI power manangement 494 */ 495 int 496 pci_set_powerstate_method(device_t dev, device_t child, int state) 497 { 498 struct pci_devinfo *dinfo = device_get_ivars(child); 499 pcicfgregs *cfg = &dinfo->cfg; 500 uint16_t status; 501 int result; 502 503 /* 504 * Dx -> Dx is a nop always. 505 */ 506 if (pci_get_powerstate(child) == state) 507 return (0); 508 509 if (cfg->pp.pp_cap != 0) { 510 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 511 & ~PCIM_PSTAT_DMASK; 512 result = 0; 513 switch (state) { 514 case PCI_POWERSTATE_D0: 515 status |= PCIM_PSTAT_D0; 516 break; 517 case PCI_POWERSTATE_D1: 518 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 519 status |= PCIM_PSTAT_D1; 520 } else { 521 result = EOPNOTSUPP; 522 } 523 break; 524 case PCI_POWERSTATE_D2: 525 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 526 status |= PCIM_PSTAT_D2; 527 } else { 528 result = EOPNOTSUPP; 529 } 530 break; 531 case PCI_POWERSTATE_D3: 532 status |= PCIM_PSTAT_D3; 533 break; 534 default: 535 result = EINVAL; 536 } 537 if (result == 0) 538 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 539 2); 540 } else { 541 result = ENXIO; 542 } 543 return(result); 544 } 545 546 int 547 pci_get_powerstate_method(device_t dev, device_t child) 548 { 549 struct pci_devinfo *dinfo = device_get_ivars(child); 550 pcicfgregs *cfg = &dinfo->cfg; 551 uint16_t status; 552 int result; 553 554 if (cfg->pp.pp_cap != 0) { 555 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 556 switch (status & PCIM_PSTAT_DMASK) { 557 case PCIM_PSTAT_D0: 558 result = PCI_POWERSTATE_D0; 559 break; 560 case PCIM_PSTAT_D1: 561 result = PCI_POWERSTATE_D1; 562 break; 563 case PCIM_PSTAT_D2: 564 result = PCI_POWERSTATE_D2; 565 break; 566 case PCIM_PSTAT_D3: 567 result = PCI_POWERSTATE_D3; 568 break; 569 default: 570 result = PCI_POWERSTATE_UNKNOWN; 571 break; 572 } 573 } else { 574 /* No support, device is always at D0 */ 575 result = PCI_POWERSTATE_D0; 576 } 577 return(result); 578 } 579 580 /* 581 * Some convenience functions for PCI device drivers. 582 */ 583 584 static __inline void 585 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 586 { 587 uint16_t command; 588 589 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 590 command |= bit; 591 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 592 } 593 594 static __inline void 595 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 596 { 597 uint16_t command; 598 599 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 600 command &= ~bit; 601 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 602 } 603 604 int 605 pci_enable_busmaster_method(device_t dev, device_t child) 606 { 607 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 608 return (0); 609 } 610 611 int 612 pci_disable_busmaster_method(device_t dev, device_t child) 613 { 614 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 615 return (0); 616 } 617 618 int 619 pci_enable_io_method(device_t dev, device_t child, int space) 620 { 621 uint16_t command; 622 uint16_t bit; 623 char *error; 624 625 bit = 0; 626 error = NULL; 627 628 switch(space) { 629 case SYS_RES_IOPORT: 630 bit = PCIM_CMD_PORTEN; 631 error = "port"; 632 break; 633 case SYS_RES_MEMORY: 634 bit = PCIM_CMD_MEMEN; 635 error = "memory"; 636 break; 637 default: 638 return (EINVAL); 639 } 640 pci_set_command_bit(dev, child, bit); 641 /* Some devices seem to need a brief stall here, what do to? */ 642 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 643 if (command & bit) 644 return (0); 645 device_printf(child, "failed to enable %s mapping!\n", error); 646 return (ENXIO); 647 } 648 649 int 650 pci_disable_io_method(device_t dev, device_t child, int space) 651 { 652 uint16_t command; 653 uint16_t bit; 654 char *error; 655 656 bit = 0; 657 error = NULL; 658 659 switch(space) { 660 case SYS_RES_IOPORT: 661 bit = PCIM_CMD_PORTEN; 662 error = "port"; 663 break; 664 case SYS_RES_MEMORY: 665 bit = PCIM_CMD_MEMEN; 666 error = "memory"; 667 break; 668 default: 669 return (EINVAL); 670 } 671 pci_clear_command_bit(dev, child, bit); 672 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 673 if (command & bit) { 674 device_printf(child, "failed to disable %s mapping!\n", error); 675 return (ENXIO); 676 } 677 return (0); 678 } 679 680 /* 681 * New style pci driver. Parent device is either a pci-host-bridge or a 682 * pci-pci-bridge. Both kinds are represented by instances of pcib. 683 */ 684 685 void 686 pci_print_verbose(struct pci_devinfo *dinfo) 687 { 688 if (bootverbose) { 689 pcicfgregs *cfg = &dinfo->cfg; 690 691 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 692 cfg->vendor, cfg->device, cfg->revid); 693 printf("\tbus=%d, slot=%d, func=%d\n", 694 cfg->bus, cfg->slot, cfg->func); 695 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 696 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 697 cfg->mfdev); 698 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 699 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 700 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 701 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 702 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 703 if (cfg->intpin > 0) 704 printf("\tintpin=%c, irq=%d\n", 705 cfg->intpin +'a' -1, cfg->intline); 706 if (cfg->pp.pp_cap) { 707 uint16_t status; 708 709 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 710 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 711 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 712 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 713 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 714 status & PCIM_PSTAT_DMASK); 715 } 716 if (cfg->msi.msi_data) { 717 int ctrl; 718 719 ctrl = cfg->msi.msi_ctrl; 720 printf("\tMSI supports %d message%s%s%s\n", 721 cfg->msi.msi_msgnum, 722 (cfg->msi.msi_msgnum == 1) ? "" : "s", 723 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 724 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 725 } 726 } 727 } 728 729 static int 730 pci_porten(device_t pcib, int b, int s, int f) 731 { 732 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 733 & PCIM_CMD_PORTEN) != 0; 734 } 735 736 static int 737 pci_memen(device_t pcib, int b, int s, int f) 738 { 739 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 740 & PCIM_CMD_MEMEN) != 0; 741 } 742 743 /* 744 * Add a resource based on a pci map register. Return 1 if the map 745 * register is a 32bit map register or 2 if it is a 64bit register. 746 */ 747 static int 748 pci_add_map(device_t pcib, device_t bus, device_t dev, 749 int b, int s, int f, int reg, struct resource_list *rl) 750 { 751 uint32_t map; 752 uint64_t base; 753 uint64_t start, end, count; 754 uint8_t ln2size; 755 uint8_t ln2range; 756 uint32_t testval; 757 uint16_t cmd; 758 int type; 759 760 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 761 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 762 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 763 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 764 765 if (pci_maptype(map) & PCI_MAPMEM) 766 type = SYS_RES_MEMORY; 767 else 768 type = SYS_RES_IOPORT; 769 ln2size = pci_mapsize(testval); 770 ln2range = pci_maprange(testval); 771 base = pci_mapbase(map); 772 773 /* 774 * For I/O registers, if bottom bit is set, and the next bit up 775 * isn't clear, we know we have a BAR that doesn't conform to the 776 * spec, so ignore it. Also, sanity check the size of the data 777 * areas to the type of memory involved. Memory must be at least 778 * 32 bytes in size, while I/O ranges must be at least 4. 779 */ 780 if ((testval & 0x1) == 0x1 && 781 (testval & 0x2) != 0) 782 return (1); 783 if ((type == SYS_RES_MEMORY && ln2size < 5) || 784 (type == SYS_RES_IOPORT && ln2size < 2)) 785 return (1); 786 787 if (ln2range == 64) 788 /* Read the other half of a 64bit map register */ 789 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 790 791 if (bootverbose) { 792 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 793 reg, pci_maptype(map), ln2range, 794 (unsigned int) base, ln2size); 795 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 796 printf(", port disabled\n"); 797 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 798 printf(", memory disabled\n"); 799 else 800 printf(", enabled\n"); 801 } 802 803 /* 804 * This code theoretically does the right thing, but has 805 * undesirable side effects in some cases where peripherals 806 * respond oddly to having these bits enabled. Let the user 807 * be able to turn them off (since pci_enable_io_modes is 1 by 808 * default). 809 */ 810 if (pci_enable_io_modes) { 811 /* Turn on resources that have been left off by a lazy BIOS */ 812 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 813 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 814 cmd |= PCIM_CMD_PORTEN; 815 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 816 } 817 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 818 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 819 cmd |= PCIM_CMD_MEMEN; 820 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 821 } 822 } else { 823 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 824 return (1); 825 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 826 return (1); 827 } 828 /* 829 * If base is 0, then we have problems. It is best to ignore 830 * such entires for the moment. These will be allocated later if 831 * the driver specifically requests them. 832 */ 833 if (base == 0) 834 return 1; 835 836 start = base; 837 end = base + (1 << ln2size) - 1; 838 count = 1 << ln2size; 839 resource_list_add(rl, type, reg, start, end, count); 840 841 /* 842 * Not quite sure what to do on failure of allocating the resource 843 * since I can postulate several right answers. 844 */ 845 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 846 return ((ln2range == 64) ? 2 : 1); 847 } 848 849 /* 850 * For ATA devices we need to decide early what addressing mode to use. 851 * Legacy demands that the primary and secondary ATA ports sits on the 852 * same addresses that old ISA hardware did. This dictates that we use 853 * those addresses and ignore the BAR's if we cannot set PCI native 854 * addressing mode. 855 */ 856 static void 857 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 858 int s, int f, struct resource_list *rl) 859 { 860 int rid, type, progif; 861 #if 0 862 /* if this device supports PCI native addressing use it */ 863 progif = pci_read_config(dev, PCIR_PROGIF, 1); 864 if ((progif & 0x8a) == 0x8a) { 865 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 866 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 867 printf("Trying ATA native PCI addressing mode\n"); 868 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 869 } 870 } 871 #endif 872 progif = pci_read_config(dev, PCIR_PROGIF, 1); 873 type = SYS_RES_IOPORT; 874 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 875 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 876 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 877 } 878 else { 879 rid = PCIR_BAR(0); 880 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 881 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 882 rid = PCIR_BAR(1); 883 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 884 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 885 } 886 if (progif & PCIP_STORAGE_IDE_MODESEC) { 887 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 888 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 889 } 890 else { 891 rid = PCIR_BAR(2); 892 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 893 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 894 rid = PCIR_BAR(3); 895 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 896 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 897 } 898 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 899 } 900 901 static void 902 pci_add_resources(device_t pcib, device_t bus, device_t dev) 903 { 904 struct pci_devinfo *dinfo = device_get_ivars(dev); 905 pcicfgregs *cfg = &dinfo->cfg; 906 struct resource_list *rl = &dinfo->resources; 907 struct pci_quirk *q; 908 int b, i, irq, f, s; 909 910 b = cfg->bus; 911 s = cfg->slot; 912 f = cfg->func; 913 914 /* ATA devices needs special map treatment */ 915 if ((pci_get_class(dev) == PCIC_STORAGE) && 916 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 917 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 918 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 919 else 920 for (i = 0; i < cfg->nummaps;) 921 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 922 rl); 923 924 for (q = &pci_quirks[0]; q->devid; q++) { 925 if (q->devid == ((cfg->device << 16) | cfg->vendor) 926 && q->type == PCI_QUIRK_MAP_REG) 927 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 928 } 929 930 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 931 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 932 defined(__arm__) 933 /* 934 * Try to re-route interrupts. Sometimes the BIOS or 935 * firmware may leave bogus values in these registers. 936 * If the re-route fails, then just stick with what we 937 * have. 938 */ 939 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 940 if (PCI_INTERRUPT_VALID(irq)) { 941 pci_write_config(dev, PCIR_INTLINE, irq, 1); 942 cfg->intline = irq; 943 } else 944 #endif 945 irq = cfg->intline; 946 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 947 } 948 } 949 950 void 951 pci_add_children(device_t dev, int busno, size_t dinfo_size) 952 { 953 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 954 device_t pcib = device_get_parent(dev); 955 struct pci_devinfo *dinfo; 956 int maxslots; 957 int s, f, pcifunchigh; 958 uint8_t hdrtype; 959 960 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 961 ("dinfo_size too small")); 962 maxslots = PCIB_MAXSLOTS(pcib); 963 for (s = 0; s <= maxslots; s++) { 964 pcifunchigh = 0; 965 f = 0; 966 hdrtype = REG(PCIR_HDRTYPE, 1); 967 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 968 continue; 969 if (hdrtype & PCIM_MFDEV) 970 pcifunchigh = PCI_FUNCMAX; 971 for (f = 0; f <= pcifunchigh; f++) { 972 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 973 if (dinfo != NULL) { 974 pci_add_child(dev, dinfo); 975 } 976 } 977 } 978 #undef REG 979 } 980 981 void 982 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 983 { 984 device_t pcib; 985 986 pcib = device_get_parent(bus); 987 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 988 device_set_ivars(dinfo->cfg.dev, dinfo); 989 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 990 pci_cfg_restore(dinfo->cfg.dev, dinfo); 991 pci_add_resources(pcib, bus, dinfo->cfg.dev); 992 pci_print_verbose(dinfo); 993 } 994 995 static int 996 pci_probe(device_t dev) 997 { 998 999 device_set_desc(dev, "PCI bus"); 1000 1001 /* Allow other subclasses to override this driver. */ 1002 return (-1000); 1003 } 1004 1005 static int 1006 pci_attach(device_t dev) 1007 { 1008 int busno; 1009 1010 /* 1011 * Since there can be multiple independantly numbered PCI 1012 * busses on some large alpha systems, we can't use the unit 1013 * number to decide what bus we are probing. We ask the parent 1014 * pcib what our bus number is. 1015 */ 1016 busno = pcib_get_bus(dev); 1017 if (bootverbose) 1018 device_printf(dev, "physical bus=%d\n", busno); 1019 1020 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1021 1022 return (bus_generic_attach(dev)); 1023 } 1024 1025 int 1026 pci_suspend(device_t dev) 1027 { 1028 int dstate, error, i, numdevs; 1029 device_t acpi_dev, child, *devlist; 1030 struct pci_devinfo *dinfo; 1031 1032 /* 1033 * Save the PCI configuration space for each child and set the 1034 * device in the appropriate power state for this sleep state. 1035 */ 1036 acpi_dev = NULL; 1037 if (pci_do_powerstate) 1038 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1039 device_get_children(dev, &devlist, &numdevs); 1040 for (i = 0; i < numdevs; i++) { 1041 child = devlist[i]; 1042 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1043 pci_cfg_save(child, dinfo, 0); 1044 } 1045 1046 /* Suspend devices before potentially powering them down. */ 1047 error = bus_generic_suspend(dev); 1048 if (error) 1049 return (error); 1050 1051 /* 1052 * Always set the device to D3. If ACPI suggests a different 1053 * power state, use it instead. If ACPI is not present, the 1054 * firmware is responsible for managing device power. Skip 1055 * children who aren't attached since they are powered down 1056 * separately. Only manage type 0 devices for now. 1057 */ 1058 for (i = 0; acpi_dev && i < numdevs; i++) { 1059 child = devlist[i]; 1060 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1061 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1062 dstate = PCI_POWERSTATE_D3; 1063 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1064 pci_set_powerstate(child, dstate); 1065 } 1066 } 1067 free(devlist, M_TEMP); 1068 return (0); 1069 } 1070 1071 int 1072 pci_resume(device_t dev) 1073 { 1074 int i, numdevs; 1075 device_t acpi_dev, child, *devlist; 1076 struct pci_devinfo *dinfo; 1077 1078 /* 1079 * Set each child to D0 and restore its PCI configuration space. 1080 */ 1081 acpi_dev = NULL; 1082 if (pci_do_powerstate) 1083 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1084 device_get_children(dev, &devlist, &numdevs); 1085 for (i = 0; i < numdevs; i++) { 1086 /* 1087 * Notify ACPI we're going to D0 but ignore the result. If 1088 * ACPI is not present, the firmware is responsible for 1089 * managing device power. Only manage type 0 devices for now. 1090 */ 1091 child = devlist[i]; 1092 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1093 if (acpi_dev && device_is_attached(child) && 1094 dinfo->cfg.hdrtype == 0) { 1095 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1096 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1097 } 1098 1099 /* Now the device is powered up, restore its config space. */ 1100 pci_cfg_restore(child, dinfo); 1101 } 1102 free(devlist, M_TEMP); 1103 return (bus_generic_resume(dev)); 1104 } 1105 1106 static void 1107 pci_load_vendor_data(void) 1108 { 1109 caddr_t vendordata, info; 1110 1111 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1112 info = preload_search_info(vendordata, MODINFO_ADDR); 1113 pci_vendordata = *(char **)info; 1114 info = preload_search_info(vendordata, MODINFO_SIZE); 1115 pci_vendordata_size = *(size_t *)info; 1116 /* terminate the database */ 1117 pci_vendordata[pci_vendordata_size] = '\n'; 1118 } 1119 } 1120 1121 void 1122 pci_driver_added(device_t dev, driver_t *driver) 1123 { 1124 int numdevs; 1125 device_t *devlist; 1126 device_t child; 1127 struct pci_devinfo *dinfo; 1128 int i; 1129 1130 if (bootverbose) 1131 device_printf(dev, "driver added\n"); 1132 DEVICE_IDENTIFY(driver, dev); 1133 device_get_children(dev, &devlist, &numdevs); 1134 for (i = 0; i < numdevs; i++) { 1135 child = devlist[i]; 1136 if (device_get_state(child) != DS_NOTPRESENT) 1137 continue; 1138 dinfo = device_get_ivars(child); 1139 pci_print_verbose(dinfo); 1140 /*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1141 if (bootverbose) 1142 printf("pci%d:%d:%d: reprobing on driver added\n", 1143 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1144 pci_cfg_restore(child, dinfo); 1145 if (device_probe_and_attach(child) != 0) 1146 pci_cfg_save(child, dinfo, 1); 1147 } 1148 free(devlist, M_TEMP); 1149 } 1150 1151 int 1152 pci_print_child(device_t dev, device_t child) 1153 { 1154 struct pci_devinfo *dinfo; 1155 struct resource_list *rl; 1156 int retval = 0; 1157 1158 dinfo = device_get_ivars(child); 1159 rl = &dinfo->resources; 1160 1161 retval += bus_print_child_header(dev, child); 1162 1163 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1164 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1165 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1166 if (device_get_flags(dev)) 1167 retval += printf(" flags %#x", device_get_flags(dev)); 1168 1169 retval += printf(" at device %d.%d", pci_get_slot(child), 1170 pci_get_function(child)); 1171 1172 retval += bus_print_child_footer(dev, child); 1173 1174 return (retval); 1175 } 1176 1177 static struct 1178 { 1179 int class; 1180 int subclass; 1181 char *desc; 1182 } pci_nomatch_tab[] = { 1183 {PCIC_OLD, -1, "old"}, 1184 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1185 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1186 {PCIC_STORAGE, -1, "mass storage"}, 1187 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1188 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1189 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1190 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1191 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1192 {PCIC_NETWORK, -1, "network"}, 1193 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1194 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1195 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1196 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1197 {PCIC_DISPLAY, -1, "display"}, 1198 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1199 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1200 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1201 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1202 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1203 {PCIC_MEMORY, -1, "memory"}, 1204 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1205 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1206 {PCIC_BRIDGE, -1, "bridge"}, 1207 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1208 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1209 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1210 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1211 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1212 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1213 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1214 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1215 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1216 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1217 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1218 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1219 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1220 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1221 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1222 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1223 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1224 {PCIC_INPUTDEV, -1, "input device"}, 1225 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1226 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1227 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1228 {PCIC_DOCKING, -1, "docking station"}, 1229 {PCIC_PROCESSOR, -1, "processor"}, 1230 {PCIC_SERIALBUS, -1, "serial bus"}, 1231 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1232 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1233 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1234 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1235 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1236 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1237 {0, 0, NULL} 1238 }; 1239 1240 void 1241 pci_probe_nomatch(device_t dev, device_t child) 1242 { 1243 int i; 1244 char *cp, *scp, *device; 1245 1246 /* 1247 * Look for a listing for this device in a loaded device database. 1248 */ 1249 if ((device = pci_describe_device(child)) != NULL) { 1250 device_printf(dev, "<%s>", device); 1251 free(device, M_DEVBUF); 1252 } else { 1253 /* 1254 * Scan the class/subclass descriptions for a general 1255 * description. 1256 */ 1257 cp = "unknown"; 1258 scp = NULL; 1259 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1260 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1261 if (pci_nomatch_tab[i].subclass == -1) { 1262 cp = pci_nomatch_tab[i].desc; 1263 } else if (pci_nomatch_tab[i].subclass == 1264 pci_get_subclass(child)) { 1265 scp = pci_nomatch_tab[i].desc; 1266 } 1267 } 1268 } 1269 device_printf(dev, "<%s%s%s>", 1270 cp ? cp : "", 1271 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1272 scp ? scp : ""); 1273 } 1274 printf(" at device %d.%d (no driver attached)\n", 1275 pci_get_slot(child), pci_get_function(child)); 1276 if (pci_do_powerstate) 1277 pci_cfg_save(child, 1278 (struct pci_devinfo *) device_get_ivars(child), 1); 1279 return; 1280 } 1281 1282 /* 1283 * Parse the PCI device database, if loaded, and return a pointer to a 1284 * description of the device. 1285 * 1286 * The database is flat text formatted as follows: 1287 * 1288 * Any line not in a valid format is ignored. 1289 * Lines are terminated with newline '\n' characters. 1290 * 1291 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1292 * the vendor name. 1293 * 1294 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1295 * - devices cannot be listed without a corresponding VENDOR line. 1296 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1297 * another TAB, then the device name. 1298 */ 1299 1300 /* 1301 * Assuming (ptr) points to the beginning of a line in the database, 1302 * return the vendor or device and description of the next entry. 1303 * The value of (vendor) or (device) inappropriate for the entry type 1304 * is set to -1. Returns nonzero at the end of the database. 1305 * 1306 * Note that this is slightly unrobust in the face of corrupt data; 1307 * we attempt to safeguard against this by spamming the end of the 1308 * database with a newline when we initialise. 1309 */ 1310 static int 1311 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1312 { 1313 char *cp = *ptr; 1314 int left; 1315 1316 *device = -1; 1317 *vendor = -1; 1318 **desc = '\0'; 1319 for (;;) { 1320 left = pci_vendordata_size - (cp - pci_vendordata); 1321 if (left <= 0) { 1322 *ptr = cp; 1323 return(1); 1324 } 1325 1326 /* vendor entry? */ 1327 if (*cp != '\t' && 1328 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1329 break; 1330 /* device entry? */ 1331 if (*cp == '\t' && 1332 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1333 break; 1334 1335 /* skip to next line */ 1336 while (*cp != '\n' && left > 0) { 1337 cp++; 1338 left--; 1339 } 1340 if (*cp == '\n') { 1341 cp++; 1342 left--; 1343 } 1344 } 1345 /* skip to next line */ 1346 while (*cp != '\n' && left > 0) { 1347 cp++; 1348 left--; 1349 } 1350 if (*cp == '\n' && left > 0) 1351 cp++; 1352 *ptr = cp; 1353 return(0); 1354 } 1355 1356 static char * 1357 pci_describe_device(device_t dev) 1358 { 1359 int vendor, device; 1360 char *desc, *vp, *dp, *line; 1361 1362 desc = vp = dp = NULL; 1363 1364 /* 1365 * If we have no vendor data, we can't do anything. 1366 */ 1367 if (pci_vendordata == NULL) 1368 goto out; 1369 1370 /* 1371 * Scan the vendor data looking for this device 1372 */ 1373 line = pci_vendordata; 1374 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1375 goto out; 1376 for (;;) { 1377 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1378 goto out; 1379 if (vendor == pci_get_vendor(dev)) 1380 break; 1381 } 1382 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1383 goto out; 1384 for (;;) { 1385 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1386 *dp = 0; 1387 break; 1388 } 1389 if (vendor != -1) { 1390 *dp = 0; 1391 break; 1392 } 1393 if (device == pci_get_device(dev)) 1394 break; 1395 } 1396 if (dp[0] == '\0') 1397 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1398 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1399 NULL) 1400 sprintf(desc, "%s, %s", vp, dp); 1401 out: 1402 if (vp != NULL) 1403 free(vp, M_DEVBUF); 1404 if (dp != NULL) 1405 free(dp, M_DEVBUF); 1406 return(desc); 1407 } 1408 1409 int 1410 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1411 { 1412 struct pci_devinfo *dinfo; 1413 pcicfgregs *cfg; 1414 1415 dinfo = device_get_ivars(child); 1416 cfg = &dinfo->cfg; 1417 1418 switch (which) { 1419 case PCI_IVAR_ETHADDR: 1420 /* 1421 * The generic accessor doesn't deal with failure, so 1422 * we set the return value, then return an error. 1423 */ 1424 *((uint8_t **) result) = NULL; 1425 return (EINVAL); 1426 case PCI_IVAR_SUBVENDOR: 1427 *result = cfg->subvendor; 1428 break; 1429 case PCI_IVAR_SUBDEVICE: 1430 *result = cfg->subdevice; 1431 break; 1432 case PCI_IVAR_VENDOR: 1433 *result = cfg->vendor; 1434 break; 1435 case PCI_IVAR_DEVICE: 1436 *result = cfg->device; 1437 break; 1438 case PCI_IVAR_DEVID: 1439 *result = (cfg->device << 16) | cfg->vendor; 1440 break; 1441 case PCI_IVAR_CLASS: 1442 *result = cfg->baseclass; 1443 break; 1444 case PCI_IVAR_SUBCLASS: 1445 *result = cfg->subclass; 1446 break; 1447 case PCI_IVAR_PROGIF: 1448 *result = cfg->progif; 1449 break; 1450 case PCI_IVAR_REVID: 1451 *result = cfg->revid; 1452 break; 1453 case PCI_IVAR_INTPIN: 1454 *result = cfg->intpin; 1455 break; 1456 case PCI_IVAR_IRQ: 1457 *result = cfg->intline; 1458 break; 1459 case PCI_IVAR_BUS: 1460 *result = cfg->bus; 1461 break; 1462 case PCI_IVAR_SLOT: 1463 *result = cfg->slot; 1464 break; 1465 case PCI_IVAR_FUNCTION: 1466 *result = cfg->func; 1467 break; 1468 default: 1469 return (ENOENT); 1470 } 1471 return (0); 1472 } 1473 1474 int 1475 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1476 { 1477 struct pci_devinfo *dinfo; 1478 1479 dinfo = device_get_ivars(child); 1480 1481 switch (which) { 1482 case PCI_IVAR_INTPIN: 1483 dinfo->cfg.intpin = value; 1484 return (0); 1485 case PCI_IVAR_ETHADDR: 1486 case PCI_IVAR_SUBVENDOR: 1487 case PCI_IVAR_SUBDEVICE: 1488 case PCI_IVAR_VENDOR: 1489 case PCI_IVAR_DEVICE: 1490 case PCI_IVAR_DEVID: 1491 case PCI_IVAR_CLASS: 1492 case PCI_IVAR_SUBCLASS: 1493 case PCI_IVAR_PROGIF: 1494 case PCI_IVAR_REVID: 1495 case PCI_IVAR_IRQ: 1496 case PCI_IVAR_BUS: 1497 case PCI_IVAR_SLOT: 1498 case PCI_IVAR_FUNCTION: 1499 return (EINVAL); /* disallow for now */ 1500 1501 default: 1502 return (ENOENT); 1503 } 1504 } 1505 1506 1507 #include "opt_ddb.h" 1508 #ifdef DDB 1509 #include <ddb/ddb.h> 1510 #include <sys/cons.h> 1511 1512 /* 1513 * List resources based on pci map registers, used for within ddb 1514 */ 1515 1516 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1517 { 1518 struct pci_devinfo *dinfo; 1519 struct devlist *devlist_head; 1520 struct pci_conf *p; 1521 const char *name; 1522 int i, error, none_count, quit; 1523 1524 none_count = 0; 1525 /* get the head of the device queue */ 1526 devlist_head = &pci_devq; 1527 1528 /* 1529 * Go through the list of devices and print out devices 1530 */ 1531 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1532 for (error = 0, i = 0, quit = 0, 1533 dinfo = STAILQ_FIRST(devlist_head); 1534 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1535 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1536 1537 /* Populate pd_name and pd_unit */ 1538 name = NULL; 1539 if (dinfo->cfg.dev) 1540 name = device_get_name(dinfo->cfg.dev); 1541 1542 p = &dinfo->conf; 1543 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1544 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1545 (name && *name) ? name : "none", 1546 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1547 none_count++, 1548 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1549 p->pc_sel.pc_func, (p->pc_class << 16) | 1550 (p->pc_subclass << 8) | p->pc_progif, 1551 (p->pc_subdevice << 16) | p->pc_subvendor, 1552 (p->pc_device << 16) | p->pc_vendor, 1553 p->pc_revid, p->pc_hdr); 1554 } 1555 } 1556 #endif /* DDB */ 1557 1558 static struct resource * 1559 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1560 u_long start, u_long end, u_long count, u_int flags) 1561 { 1562 struct pci_devinfo *dinfo = device_get_ivars(child); 1563 struct resource_list *rl = &dinfo->resources; 1564 struct resource_list_entry *rle; 1565 struct resource *res; 1566 uint32_t map, testval; 1567 int mapsize; 1568 1569 /* 1570 * Weed out the bogons, and figure out how large the BAR/map 1571 * is. Bars that read back 0 here are bogus and unimplemented. 1572 * Note: atapci in legacy mode are special and handled elsewhere 1573 * in the code. If you have a atapci device in legacy mode and 1574 * it fails here, that other code is broken. 1575 */ 1576 res = NULL; 1577 map = pci_read_config(child, *rid, 4); 1578 pci_write_config(child, *rid, 0xffffffff, 4); 1579 testval = pci_read_config(child, *rid, 4); 1580 if (testval == 0) 1581 return (NULL); 1582 if (pci_maptype(testval) & PCI_MAPMEM) { 1583 if (type != SYS_RES_MEMORY) { 1584 device_printf(child, 1585 "failed: rid %#x is memory, requested %d\n", 1586 *rid, type); 1587 goto out; 1588 } 1589 } else { 1590 if (type != SYS_RES_IOPORT) { 1591 device_printf(child, 1592 "failed: rid %#x is ioport, requested %d\n", 1593 *rid, type); 1594 goto out; 1595 } 1596 } 1597 /* 1598 * For real BARs, we need to override the size that 1599 * the driver requests, because that's what the BAR 1600 * actually uses and we would otherwise have a 1601 * situation where we might allocate the excess to 1602 * another driver, which won't work. 1603 */ 1604 mapsize = pci_mapsize(testval); 1605 count = 1 << mapsize; 1606 if (RF_ALIGNMENT(flags) < mapsize) 1607 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1608 1609 /* 1610 * Allocate enough resource, and then write back the 1611 * appropriate bar for that resource. 1612 */ 1613 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1614 start, end, count, flags); 1615 if (res == NULL) { 1616 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1617 count, *rid, type); 1618 goto out; 1619 } 1620 resource_list_add(rl, type, *rid, start, end, count); 1621 rle = resource_list_find(rl, type, *rid); 1622 if (rle == NULL) 1623 panic("pci_alloc_map: unexpectedly can't find resource."); 1624 rle->res = res; 1625 if (bootverbose) 1626 device_printf(child, 1627 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1628 count, *rid, type, rman_get_start(res)); 1629 map = rman_get_start(res); 1630 out:; 1631 pci_write_config(child, *rid, map, 4); 1632 return (res); 1633 } 1634 1635 1636 struct resource * 1637 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1638 u_long start, u_long end, u_long count, u_int flags) 1639 { 1640 struct pci_devinfo *dinfo = device_get_ivars(child); 1641 struct resource_list *rl = &dinfo->resources; 1642 struct resource_list_entry *rle; 1643 pcicfgregs *cfg = &dinfo->cfg; 1644 1645 /* 1646 * Perform lazy resource allocation 1647 */ 1648 if (device_get_parent(child) == dev) { 1649 switch (type) { 1650 case SYS_RES_IRQ: 1651 /* 1652 * If the child device doesn't have an 1653 * interrupt routed and is deserving of an 1654 * interrupt, try to assign it one. 1655 */ 1656 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1657 (cfg->intpin != 0)) { 1658 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1659 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1660 pci_write_config(child, PCIR_INTLINE, 1661 cfg->intline, 1); 1662 resource_list_add(rl, SYS_RES_IRQ, 0, 1663 cfg->intline, cfg->intline, 1); 1664 } 1665 } 1666 break; 1667 case SYS_RES_IOPORT: 1668 case SYS_RES_MEMORY: 1669 if (*rid < PCIR_BAR(cfg->nummaps)) { 1670 /* 1671 * Enable the I/O mode. We should 1672 * also be assigning resources too 1673 * when none are present. The 1674 * resource_list_alloc kind of sorta does 1675 * this... 1676 */ 1677 if (PCI_ENABLE_IO(dev, child, type)) 1678 return (NULL); 1679 } 1680 rle = resource_list_find(rl, type, *rid); 1681 if (rle == NULL) 1682 return (pci_alloc_map(dev, child, type, rid, 1683 start, end, count, flags)); 1684 break; 1685 } 1686 /* 1687 * If we've already allocated the resource, then 1688 * return it now. But first we may need to activate 1689 * it, since we don't allocate the resource as active 1690 * above. Normally this would be done down in the 1691 * nexus, but since we short-circuit that path we have 1692 * to do its job here. Not sure if we should free the 1693 * resource if it fails to activate. 1694 */ 1695 rle = resource_list_find(rl, type, *rid); 1696 if (rle != NULL && rle->res != NULL) { 1697 if (bootverbose) 1698 device_printf(child, 1699 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1700 rman_get_size(rle->res), *rid, type, 1701 rman_get_start(rle->res)); 1702 if ((flags & RF_ACTIVE) && 1703 bus_generic_activate_resource(dev, child, type, 1704 *rid, rle->res) != 0) 1705 return NULL; 1706 return (rle->res); 1707 } 1708 } 1709 return (resource_list_alloc(rl, dev, child, type, rid, 1710 start, end, count, flags)); 1711 } 1712 1713 void 1714 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1715 { 1716 struct pci_devinfo *dinfo; 1717 struct resource_list *rl; 1718 struct resource_list_entry *rle; 1719 1720 if (device_get_parent(child) != dev) 1721 return; 1722 1723 dinfo = device_get_ivars(child); 1724 rl = &dinfo->resources; 1725 rle = resource_list_find(rl, type, rid); 1726 if (rle) { 1727 if (rle->res) { 1728 if (rman_get_device(rle->res) != dev || 1729 rman_get_flags(rle->res) & RF_ACTIVE) { 1730 device_printf(dev, "delete_resource: " 1731 "Resource still owned by child, oops. " 1732 "(type=%d, rid=%d, addr=%lx)\n", 1733 rle->type, rle->rid, 1734 rman_get_start(rle->res)); 1735 return; 1736 } 1737 bus_release_resource(dev, type, rid, rle->res); 1738 } 1739 resource_list_delete(rl, type, rid); 1740 } 1741 /* 1742 * Why do we turn off the PCI configuration BAR when we delete a 1743 * resource? -- imp 1744 */ 1745 pci_write_config(child, rid, 0, 4); 1746 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1747 } 1748 1749 struct resource_list * 1750 pci_get_resource_list (device_t dev, device_t child) 1751 { 1752 struct pci_devinfo *dinfo = device_get_ivars(child); 1753 1754 return (&dinfo->resources); 1755 } 1756 1757 uint32_t 1758 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1759 { 1760 struct pci_devinfo *dinfo = device_get_ivars(child); 1761 pcicfgregs *cfg = &dinfo->cfg; 1762 1763 return (PCIB_READ_CONFIG(device_get_parent(dev), 1764 cfg->bus, cfg->slot, cfg->func, reg, width)); 1765 } 1766 1767 void 1768 pci_write_config_method(device_t dev, device_t child, int reg, 1769 uint32_t val, int width) 1770 { 1771 struct pci_devinfo *dinfo = device_get_ivars(child); 1772 pcicfgregs *cfg = &dinfo->cfg; 1773 1774 PCIB_WRITE_CONFIG(device_get_parent(dev), 1775 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1776 } 1777 1778 int 1779 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1780 size_t buflen) 1781 { 1782 struct pci_devinfo *dinfo; 1783 1784 dinfo = device_get_ivars(child); 1785 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1786 pci_get_function(child)); 1787 return (0); 1788 } 1789 1790 int 1791 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1792 size_t buflen) 1793 { 1794 struct pci_devinfo *dinfo; 1795 pcicfgregs *cfg; 1796 1797 dinfo = device_get_ivars(child); 1798 cfg = &dinfo->cfg; 1799 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1800 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1801 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1802 cfg->progif); 1803 return (0); 1804 } 1805 1806 int 1807 pci_assign_interrupt_method(device_t dev, device_t child) 1808 { 1809 struct pci_devinfo *dinfo = device_get_ivars(child); 1810 pcicfgregs *cfg = &dinfo->cfg; 1811 1812 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1813 cfg->intpin)); 1814 } 1815 1816 static int 1817 pci_modevent(module_t mod, int what, void *arg) 1818 { 1819 static struct cdev *pci_cdev; 1820 1821 switch (what) { 1822 case MOD_LOAD: 1823 STAILQ_INIT(&pci_devq); 1824 pci_generation = 0; 1825 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1826 "pci"); 1827 pci_load_vendor_data(); 1828 break; 1829 1830 case MOD_UNLOAD: 1831 destroy_dev(pci_cdev); 1832 break; 1833 } 1834 1835 return (0); 1836 } 1837 1838 static void 1839 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1840 { 1841 int i; 1842 1843 /* 1844 * Only do header type 0 devices. Type 1 devices are bridges, 1845 * which we know need special treatment. Type 2 devices are 1846 * cardbus bridges which also require special treatment. 1847 * Other types are unknown, and we err on the side of safety 1848 * by ignoring them. 1849 */ 1850 if (dinfo->cfg.hdrtype != 0) 1851 return; 1852 1853 /* 1854 * Restore the device to full power mode. We must do this 1855 * before we restore the registers because moving from D3 to 1856 * D0 will cause the chip's BARs and some other registers to 1857 * be reset to some unknown power on reset values. Cut down 1858 * the noise on boot by doing nothing if we are already in 1859 * state D0. 1860 */ 1861 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1862 if (bootverbose) 1863 printf( 1864 "pci%d:%d:%d: Transition from D%d to D0\n", 1865 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1866 pci_get_powerstate(dev)); 1867 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1868 } 1869 for (i = 0; i < dinfo->cfg.nummaps; i++) 1870 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1871 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1872 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1873 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1874 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1875 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1876 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1877 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1878 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1879 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1880 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1881 } 1882 1883 static void 1884 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1885 { 1886 int i; 1887 uint32_t cls; 1888 int ps; 1889 1890 /* 1891 * Only do header type 0 devices. Type 1 devices are bridges, which 1892 * we know need special treatment. Type 2 devices are cardbus bridges 1893 * which also require special treatment. Other types are unknown, and 1894 * we err on the side of safety by ignoring them. Powering down 1895 * bridges should not be undertaken lightly. 1896 */ 1897 if (dinfo->cfg.hdrtype != 0) 1898 return; 1899 for (i = 0; i < dinfo->cfg.nummaps; i++) 1900 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1901 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1902 1903 /* 1904 * Some drivers apparently write to these registers w/o updating our 1905 * cahced copy. No harm happens if we update the copy, so do so here 1906 * so we can restore them. The COMMAND register is modified by the 1907 * bus w/o updating the cache. This should represent the normally 1908 * writable portion of the 'defined' part of type 0 headers. In 1909 * theory we also need to save/restore the PCI capability structures 1910 * we know about, but apart from power we don't know any that are 1911 * writable. 1912 */ 1913 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1914 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1915 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1916 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1917 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1918 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1919 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1920 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1921 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1922 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1923 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1924 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1925 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1926 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1927 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1928 1929 /* 1930 * don't set the state for display devices, base peripherals and 1931 * memory devices since bad things happen when they are powered down. 1932 * We should (a) have drivers that can easily detach and (b) use 1933 * generic drivers for these devices so that some device actually 1934 * attaches. We need to make sure that when we implement (a) we don't 1935 * power the device down on a reattach. 1936 */ 1937 cls = pci_get_class(dev); 1938 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1939 cls != PCIC_BASEPERIPH) { 1940 /* 1941 * PCI spec says we can only go into D3 state from D0 state. 1942 * Transition from D[12] into D0 before going to D3 state. 1943 */ 1944 ps = pci_get_powerstate(dev); 1945 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1946 if (bootverbose) 1947 printf( 1948 "pci%d:%d:%d: Transition from D%d to D0\n", 1949 dinfo->cfg.bus, dinfo->cfg.slot, 1950 dinfo->cfg.func, ps); 1951 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1952 } 1953 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1954 if (bootverbose) 1955 printf( 1956 "pci%d:%d:%d: Transition from D0 to D3\n", 1957 dinfo->cfg.bus, dinfo->cfg.slot, 1958 dinfo->cfg.func); 1959 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1960 } 1961 } 1962 } 1963