1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_bus.h" 36 37 #include <sys/param.h> 38 #include <sys/conf.h> 39 #include <sys/endian.h> 40 #include <sys/eventhandler.h> 41 #include <sys/fcntl.h> 42 #include <sys/kernel.h> 43 #include <sys/limits.h> 44 #include <sys/linker.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <vm/vm_extern.h> 54 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 #include <machine/stdarg.h> 60 61 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 62 #include <machine/intr_machdep.h> 63 #endif 64 65 #include <sys/pciio.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pci_private.h> 69 70 #ifdef PCI_IOV 71 #include <sys/nv.h> 72 #include <dev/pci/pci_iov_private.h> 73 #endif 74 75 #include <dev/usb/controller/xhcireg.h> 76 #include <dev/usb/controller/ehcireg.h> 77 #include <dev/usb/controller/ohcireg.h> 78 #include <dev/usb/controller/uhcireg.h> 79 80 #include "pcib_if.h" 81 #include "pci_if.h" 82 83 #define PCIR_IS_BIOS(cfg, reg) \ 84 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 85 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 86 87 static int pci_has_quirk(uint32_t devid, int quirk); 88 static pci_addr_t pci_mapbase(uint64_t mapreg); 89 static const char *pci_maptype(uint64_t mapreg); 90 static int pci_maprange(uint64_t mapreg); 91 static pci_addr_t pci_rombase(uint64_t mapreg); 92 static int pci_romsize(uint64_t testval); 93 static void pci_fixancient(pcicfgregs *cfg); 94 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 95 96 static int pci_porten(device_t dev); 97 static int pci_memen(device_t dev); 98 static void pci_assign_interrupt(device_t bus, device_t dev, 99 int force_route); 100 static int pci_add_map(device_t bus, device_t dev, int reg, 101 struct resource_list *rl, int force, int prefetch); 102 static int pci_probe(device_t dev); 103 static void pci_load_vendor_data(void); 104 static int pci_describe_parse_line(char **ptr, int *vendor, 105 int *device, char **desc); 106 static char *pci_describe_device(device_t dev); 107 static int pci_modevent(module_t mod, int what, void *arg); 108 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 109 pcicfgregs *cfg); 110 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 111 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 112 int reg, uint32_t *data); 113 #if 0 114 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 115 int reg, uint32_t data); 116 #endif 117 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 118 static void pci_mask_msix(device_t dev, u_int index); 119 static void pci_unmask_msix(device_t dev, u_int index); 120 static int pci_msi_blacklisted(void); 121 static int pci_msix_blacklisted(void); 122 static void pci_resume_msi(device_t dev); 123 static void pci_resume_msix(device_t dev); 124 static int pci_remap_intr_method(device_t bus, device_t dev, 125 u_int irq); 126 static void pci_hint_device_unit(device_t acdev, device_t child, 127 const char *name, int *unitp); 128 static int pci_reset_post(device_t dev, device_t child); 129 static int pci_reset_prepare(device_t dev, device_t child); 130 static int pci_reset_child(device_t dev, device_t child, 131 int flags); 132 133 static int pci_get_id_method(device_t dev, device_t child, 134 enum pci_id_type type, uintptr_t *rid); 135 136 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 137 int b, int s, int f, uint16_t vid, uint16_t did); 138 139 static device_method_t pci_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, pci_probe), 142 DEVMETHOD(device_attach, pci_attach), 143 DEVMETHOD(device_detach, pci_detach), 144 DEVMETHOD(device_shutdown, bus_generic_shutdown), 145 DEVMETHOD(device_suspend, bus_generic_suspend), 146 DEVMETHOD(device_resume, pci_resume), 147 148 /* Bus interface */ 149 DEVMETHOD(bus_print_child, pci_print_child), 150 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 151 DEVMETHOD(bus_read_ivar, pci_read_ivar), 152 DEVMETHOD(bus_write_ivar, pci_write_ivar), 153 DEVMETHOD(bus_driver_added, pci_driver_added), 154 DEVMETHOD(bus_setup_intr, pci_setup_intr), 155 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 156 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 157 DEVMETHOD(bus_reset_post, pci_reset_post), 158 DEVMETHOD(bus_reset_child, pci_reset_child), 159 160 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 161 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 162 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 163 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 164 DEVMETHOD(bus_delete_resource, pci_delete_resource), 165 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 166 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 167 DEVMETHOD(bus_release_resource, pci_release_resource), 168 DEVMETHOD(bus_activate_resource, pci_activate_resource), 169 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 170 DEVMETHOD(bus_child_deleted, pci_child_deleted), 171 DEVMETHOD(bus_child_detached, pci_child_detached), 172 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 173 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 174 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 175 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 176 DEVMETHOD(bus_suspend_child, pci_suspend_child), 177 DEVMETHOD(bus_resume_child, pci_resume_child), 178 DEVMETHOD(bus_rescan, pci_rescan_method), 179 180 /* PCI interface */ 181 DEVMETHOD(pci_read_config, pci_read_config_method), 182 DEVMETHOD(pci_write_config, pci_write_config_method), 183 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 184 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 185 DEVMETHOD(pci_enable_io, pci_enable_io_method), 186 DEVMETHOD(pci_disable_io, pci_disable_io_method), 187 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 188 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 189 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 190 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 191 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 192 DEVMETHOD(pci_find_cap, pci_find_cap_method), 193 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 194 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 195 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 196 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 197 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 198 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 199 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 200 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 201 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 202 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 203 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 204 DEVMETHOD(pci_release_msi, pci_release_msi_method), 205 DEVMETHOD(pci_msi_count, pci_msi_count_method), 206 DEVMETHOD(pci_msix_count, pci_msix_count_method), 207 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 208 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 209 DEVMETHOD(pci_get_id, pci_get_id_method), 210 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 211 DEVMETHOD(pci_child_added, pci_child_added_method), 212 #ifdef PCI_IOV 213 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 214 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 215 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 216 #endif 217 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 222 223 static devclass_t pci_devclass; 224 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 225 BUS_PASS_BUS); 226 MODULE_VERSION(pci, 1); 227 228 static char *pci_vendordata; 229 static size_t pci_vendordata_size; 230 231 struct pci_quirk { 232 uint32_t devid; /* Vendor/device of the card */ 233 int type; 234 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 235 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 236 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 237 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 238 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 239 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 240 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 241 int arg1; 242 int arg2; 243 }; 244 245 static const struct pci_quirk pci_quirks[] = { 246 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 247 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 248 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 249 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 250 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 252 /* 253 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 254 * or the CMIC-SL (AKA ServerWorks GC_LE). 255 */ 256 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 257 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 258 259 /* 260 * MSI doesn't work on earlier Intel chipsets including 261 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 262 */ 263 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 265 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 271 /* 272 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 273 * bridge. 274 */ 275 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * MSI-X allocation doesn't work properly for devices passed through 279 * by VMware up to at least ESXi 5.1. 280 */ 281 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */ 282 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */ 283 284 /* 285 * Some virtualization environments emulate an older chipset 286 * but support MSI just fine. QEMU uses the Intel 82440. 287 */ 288 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 289 290 /* 291 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 292 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 293 * It prevents us from attaching hpet(4) when the bit is unset. 294 * Note this quirk only affects SB600 revision A13 and earlier. 295 * For SB600 A21 and later, firmware must set the bit to hide it. 296 * For SB700 and later, it is unused and hardcoded to zero. 297 */ 298 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 299 300 /* 301 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 302 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 303 * of the command register is set. 304 */ 305 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 309 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 310 311 /* 312 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 313 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 314 */ 315 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 316 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 317 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 318 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 319 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 320 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 321 322 /* 323 * HPE Gen 10 VGA has a memory range that can't be allocated in the 324 * expected place. 325 */ 326 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 327 328 { 0 } 329 }; 330 331 /* map register information */ 332 #define PCI_MAPMEM 0x01 /* memory map */ 333 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 334 #define PCI_MAPPORT 0x04 /* port map */ 335 336 struct devlist pci_devq; 337 uint32_t pci_generation; 338 uint32_t pci_numdevs = 0; 339 static int pcie_chipset, pcix_chipset; 340 341 /* sysctl vars */ 342 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 343 344 static int pci_enable_io_modes = 1; 345 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 346 &pci_enable_io_modes, 1, 347 "Enable I/O and memory bits in the config register. Some BIOSes do not" 348 " enable these bits correctly. We'd like to do this all the time, but" 349 " there are some peripherals that this causes problems with."); 350 351 static int pci_do_realloc_bars = 1; 352 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 353 &pci_do_realloc_bars, 0, 354 "Attempt to allocate a new range for any BARs whose original " 355 "firmware-assigned ranges fail to allocate during the initial device scan."); 356 357 static int pci_do_power_nodriver = 0; 358 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 359 &pci_do_power_nodriver, 0, 360 "Place a function into D3 state when no driver attaches to it. 0 means" 361 " disable. 1 means conservatively place devices into D3 state. 2 means" 362 " aggressively place devices into D3 state. 3 means put absolutely" 363 " everything in D3 state."); 364 365 int pci_do_power_resume = 1; 366 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 367 &pci_do_power_resume, 1, 368 "Transition from D3 -> D0 on resume."); 369 370 int pci_do_power_suspend = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 372 &pci_do_power_suspend, 1, 373 "Transition from D0 -> D3 on suspend."); 374 375 static int pci_do_msi = 1; 376 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 377 "Enable support for MSI interrupts"); 378 379 static int pci_do_msix = 1; 380 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 381 "Enable support for MSI-X interrupts"); 382 383 static int pci_msix_rewrite_table = 0; 384 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 385 &pci_msix_rewrite_table, 0, 386 "Rewrite entire MSI-X table when updating MSI-X entries"); 387 388 static int pci_honor_msi_blacklist = 1; 389 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 390 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 391 392 #if defined(__i386__) || defined(__amd64__) 393 static int pci_usb_takeover = 1; 394 #else 395 static int pci_usb_takeover = 0; 396 #endif 397 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 398 &pci_usb_takeover, 1, 399 "Enable early takeover of USB controllers. Disable this if you depend on" 400 " BIOS emulation of USB devices, that is you use USB devices (like" 401 " keyboard or mouse) but do not load USB drivers"); 402 403 static int pci_clear_bars; 404 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 405 "Ignore firmware-assigned resources for BARs."); 406 407 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 408 static int pci_clear_buses; 409 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 410 "Ignore firmware-assigned bus numbers."); 411 #endif 412 413 static int pci_enable_ari = 1; 414 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 415 0, "Enable support for PCIe Alternative RID Interpretation"); 416 417 static int pci_clear_aer_on_attach = 0; 418 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 419 &pci_clear_aer_on_attach, 0, 420 "Clear port and device AER state on driver attach"); 421 422 static int 423 pci_has_quirk(uint32_t devid, int quirk) 424 { 425 const struct pci_quirk *q; 426 427 for (q = &pci_quirks[0]; q->devid; q++) { 428 if (q->devid == devid && q->type == quirk) 429 return (1); 430 } 431 return (0); 432 } 433 434 /* Find a device_t by bus/slot/function in domain 0 */ 435 436 device_t 437 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 438 { 439 440 return (pci_find_dbsf(0, bus, slot, func)); 441 } 442 443 /* Find a device_t by domain/bus/slot/function */ 444 445 device_t 446 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 447 { 448 struct pci_devinfo *dinfo = NULL; 449 450 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 451 if ((dinfo->cfg.domain == domain) && 452 (dinfo->cfg.bus == bus) && 453 (dinfo->cfg.slot == slot) && 454 (dinfo->cfg.func == func)) { 455 break; 456 } 457 } 458 459 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 460 } 461 462 /* Find a device_t by vendor/device ID */ 463 464 device_t 465 pci_find_device(uint16_t vendor, uint16_t device) 466 { 467 struct pci_devinfo *dinfo; 468 469 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 470 if ((dinfo->cfg.vendor == vendor) && 471 (dinfo->cfg.device == device)) { 472 return (dinfo->cfg.dev); 473 } 474 } 475 476 return (NULL); 477 } 478 479 device_t 480 pci_find_class(uint8_t class, uint8_t subclass) 481 { 482 struct pci_devinfo *dinfo; 483 484 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 485 if (dinfo->cfg.baseclass == class && 486 dinfo->cfg.subclass == subclass) { 487 return (dinfo->cfg.dev); 488 } 489 } 490 491 return (NULL); 492 } 493 494 static int 495 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 496 { 497 va_list ap; 498 int retval; 499 500 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 501 cfg->func); 502 va_start(ap, fmt); 503 retval += vprintf(fmt, ap); 504 va_end(ap); 505 return (retval); 506 } 507 508 /* return base address of memory or port map */ 509 510 static pci_addr_t 511 pci_mapbase(uint64_t mapreg) 512 { 513 514 if (PCI_BAR_MEM(mapreg)) 515 return (mapreg & PCIM_BAR_MEM_BASE); 516 else 517 return (mapreg & PCIM_BAR_IO_BASE); 518 } 519 520 /* return map type of memory or port map */ 521 522 static const char * 523 pci_maptype(uint64_t mapreg) 524 { 525 526 if (PCI_BAR_IO(mapreg)) 527 return ("I/O Port"); 528 if (mapreg & PCIM_BAR_MEM_PREFETCH) 529 return ("Prefetchable Memory"); 530 return ("Memory"); 531 } 532 533 /* return log2 of map size decoded for memory or port map */ 534 535 int 536 pci_mapsize(uint64_t testval) 537 { 538 int ln2size; 539 540 testval = pci_mapbase(testval); 541 ln2size = 0; 542 if (testval != 0) { 543 while ((testval & 1) == 0) 544 { 545 ln2size++; 546 testval >>= 1; 547 } 548 } 549 return (ln2size); 550 } 551 552 /* return base address of device ROM */ 553 554 static pci_addr_t 555 pci_rombase(uint64_t mapreg) 556 { 557 558 return (mapreg & PCIM_BIOS_ADDR_MASK); 559 } 560 561 /* return log2 of map size decided for device ROM */ 562 563 static int 564 pci_romsize(uint64_t testval) 565 { 566 int ln2size; 567 568 testval = pci_rombase(testval); 569 ln2size = 0; 570 if (testval != 0) { 571 while ((testval & 1) == 0) 572 { 573 ln2size++; 574 testval >>= 1; 575 } 576 } 577 return (ln2size); 578 } 579 580 /* return log2 of address range supported by map register */ 581 582 static int 583 pci_maprange(uint64_t mapreg) 584 { 585 int ln2range = 0; 586 587 if (PCI_BAR_IO(mapreg)) 588 ln2range = 32; 589 else 590 switch (mapreg & PCIM_BAR_MEM_TYPE) { 591 case PCIM_BAR_MEM_32: 592 ln2range = 32; 593 break; 594 case PCIM_BAR_MEM_1MB: 595 ln2range = 20; 596 break; 597 case PCIM_BAR_MEM_64: 598 ln2range = 64; 599 break; 600 } 601 return (ln2range); 602 } 603 604 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 605 606 static void 607 pci_fixancient(pcicfgregs *cfg) 608 { 609 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 610 return; 611 612 /* PCI to PCI bridges use header type 1 */ 613 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 614 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 615 } 616 617 /* extract header type specific config data */ 618 619 static void 620 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 621 { 622 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 623 switch (cfg->hdrtype & PCIM_HDRTYPE) { 624 case PCIM_HDRTYPE_NORMAL: 625 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 626 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 627 cfg->mingnt = REG(PCIR_MINGNT, 1); 628 cfg->maxlat = REG(PCIR_MAXLAT, 1); 629 cfg->nummaps = PCI_MAXMAPS_0; 630 break; 631 case PCIM_HDRTYPE_BRIDGE: 632 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 633 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 634 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 635 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 636 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 637 cfg->nummaps = PCI_MAXMAPS_1; 638 break; 639 case PCIM_HDRTYPE_CARDBUS: 640 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 641 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 642 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 643 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 644 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 645 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 646 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 647 cfg->nummaps = PCI_MAXMAPS_2; 648 break; 649 } 650 #undef REG 651 } 652 653 /* read configuration header into pcicfgregs structure */ 654 struct pci_devinfo * 655 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 656 { 657 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 658 uint16_t vid, did; 659 660 vid = REG(PCIR_VENDOR, 2); 661 did = REG(PCIR_DEVICE, 2); 662 if (vid != 0xffff) 663 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 664 665 return (NULL); 666 } 667 668 struct pci_devinfo * 669 pci_alloc_devinfo_method(device_t dev) 670 { 671 672 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 673 M_WAITOK | M_ZERO)); 674 } 675 676 static struct pci_devinfo * 677 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 678 uint16_t vid, uint16_t did) 679 { 680 struct pci_devinfo *devlist_entry; 681 pcicfgregs *cfg; 682 683 devlist_entry = PCI_ALLOC_DEVINFO(bus); 684 685 cfg = &devlist_entry->cfg; 686 687 cfg->domain = d; 688 cfg->bus = b; 689 cfg->slot = s; 690 cfg->func = f; 691 cfg->vendor = vid; 692 cfg->device = did; 693 cfg->cmdreg = REG(PCIR_COMMAND, 2); 694 cfg->statreg = REG(PCIR_STATUS, 2); 695 cfg->baseclass = REG(PCIR_CLASS, 1); 696 cfg->subclass = REG(PCIR_SUBCLASS, 1); 697 cfg->progif = REG(PCIR_PROGIF, 1); 698 cfg->revid = REG(PCIR_REVID, 1); 699 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 700 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 701 cfg->lattimer = REG(PCIR_LATTIMER, 1); 702 cfg->intpin = REG(PCIR_INTPIN, 1); 703 cfg->intline = REG(PCIR_INTLINE, 1); 704 705 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 706 cfg->hdrtype &= ~PCIM_MFDEV; 707 STAILQ_INIT(&cfg->maps); 708 709 cfg->iov = NULL; 710 711 pci_fixancient(cfg); 712 pci_hdrtypedata(pcib, b, s, f, cfg); 713 714 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 715 pci_read_cap(pcib, cfg); 716 717 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 718 719 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 720 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 721 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 722 devlist_entry->conf.pc_sel.pc_func = cfg->func; 723 devlist_entry->conf.pc_hdr = cfg->hdrtype; 724 725 devlist_entry->conf.pc_subvendor = cfg->subvendor; 726 devlist_entry->conf.pc_subdevice = cfg->subdevice; 727 devlist_entry->conf.pc_vendor = cfg->vendor; 728 devlist_entry->conf.pc_device = cfg->device; 729 730 devlist_entry->conf.pc_class = cfg->baseclass; 731 devlist_entry->conf.pc_subclass = cfg->subclass; 732 devlist_entry->conf.pc_progif = cfg->progif; 733 devlist_entry->conf.pc_revid = cfg->revid; 734 735 pci_numdevs++; 736 pci_generation++; 737 738 return (devlist_entry); 739 } 740 #undef REG 741 742 static void 743 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 744 { 745 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 746 cfg->ea.ea_location + (n), w) 747 int num_ent; 748 int ptr; 749 int a, b; 750 uint32_t val; 751 int ent_size; 752 uint32_t dw[4]; 753 uint64_t base, max_offset; 754 struct pci_ea_entry *eae; 755 756 if (cfg->ea.ea_location == 0) 757 return; 758 759 STAILQ_INIT(&cfg->ea.ea_entries); 760 761 /* Determine the number of entries */ 762 num_ent = REG(PCIR_EA_NUM_ENT, 2); 763 num_ent &= PCIM_EA_NUM_ENT_MASK; 764 765 /* Find the first entry to care of */ 766 ptr = PCIR_EA_FIRST_ENT; 767 768 /* Skip DWORD 2 for type 1 functions */ 769 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 770 ptr += 4; 771 772 for (a = 0; a < num_ent; a++) { 773 774 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 775 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 776 777 /* Read a number of dwords in the entry */ 778 val = REG(ptr, 4); 779 ptr += 4; 780 ent_size = (val & PCIM_EA_ES); 781 782 for (b = 0; b < ent_size; b++) { 783 dw[b] = REG(ptr, 4); 784 ptr += 4; 785 } 786 787 eae->eae_flags = val; 788 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 789 790 base = dw[0] & PCIM_EA_FIELD_MASK; 791 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 792 b = 2; 793 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 794 base |= (uint64_t)dw[b] << 32UL; 795 b++; 796 } 797 if (((dw[1] & PCIM_EA_IS_64) != 0) 798 && (b < ent_size)) { 799 max_offset |= (uint64_t)dw[b] << 32UL; 800 b++; 801 } 802 803 eae->eae_base = base; 804 eae->eae_max_offset = max_offset; 805 806 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 807 808 if (bootverbose) { 809 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 810 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 811 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 812 } 813 } 814 } 815 #undef REG 816 817 static void 818 pci_read_cap(device_t pcib, pcicfgregs *cfg) 819 { 820 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 821 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 822 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 823 uint64_t addr; 824 #endif 825 uint32_t val; 826 int ptr, nextptr, ptrptr; 827 828 switch (cfg->hdrtype & PCIM_HDRTYPE) { 829 case PCIM_HDRTYPE_NORMAL: 830 case PCIM_HDRTYPE_BRIDGE: 831 ptrptr = PCIR_CAP_PTR; 832 break; 833 case PCIM_HDRTYPE_CARDBUS: 834 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 835 break; 836 default: 837 return; /* no extended capabilities support */ 838 } 839 nextptr = REG(ptrptr, 1); /* sanity check? */ 840 841 /* 842 * Read capability entries. 843 */ 844 while (nextptr != 0) { 845 /* Sanity check */ 846 if (nextptr > 255) { 847 printf("illegal PCI extended capability offset %d\n", 848 nextptr); 849 return; 850 } 851 /* Find the next entry */ 852 ptr = nextptr; 853 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 854 855 /* Process this entry */ 856 switch (REG(ptr + PCICAP_ID, 1)) { 857 case PCIY_PMG: /* PCI power management */ 858 if (cfg->pp.pp_cap == 0) { 859 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 860 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 861 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 862 if ((nextptr - ptr) > PCIR_POWER_DATA) 863 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 864 } 865 break; 866 case PCIY_HT: /* HyperTransport */ 867 /* Determine HT-specific capability type. */ 868 val = REG(ptr + PCIR_HT_COMMAND, 2); 869 870 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 871 cfg->ht.ht_slave = ptr; 872 873 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 874 switch (val & PCIM_HTCMD_CAP_MASK) { 875 case PCIM_HTCAP_MSI_MAPPING: 876 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 877 /* Sanity check the mapping window. */ 878 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 879 4); 880 addr <<= 32; 881 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 882 4); 883 if (addr != MSI_INTEL_ADDR_BASE) 884 device_printf(pcib, 885 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 886 cfg->domain, cfg->bus, 887 cfg->slot, cfg->func, 888 (long long)addr); 889 } else 890 addr = MSI_INTEL_ADDR_BASE; 891 892 cfg->ht.ht_msimap = ptr; 893 cfg->ht.ht_msictrl = val; 894 cfg->ht.ht_msiaddr = addr; 895 break; 896 } 897 #endif 898 break; 899 case PCIY_MSI: /* PCI MSI */ 900 cfg->msi.msi_location = ptr; 901 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 902 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 903 PCIM_MSICTRL_MMC_MASK)>>1); 904 break; 905 case PCIY_MSIX: /* PCI MSI-X */ 906 cfg->msix.msix_location = ptr; 907 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 908 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 909 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 910 val = REG(ptr + PCIR_MSIX_TABLE, 4); 911 cfg->msix.msix_table_bar = PCIR_BAR(val & 912 PCIM_MSIX_BIR_MASK); 913 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 914 val = REG(ptr + PCIR_MSIX_PBA, 4); 915 cfg->msix.msix_pba_bar = PCIR_BAR(val & 916 PCIM_MSIX_BIR_MASK); 917 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 918 break; 919 case PCIY_VPD: /* PCI Vital Product Data */ 920 cfg->vpd.vpd_reg = ptr; 921 break; 922 case PCIY_SUBVENDOR: 923 /* Should always be true. */ 924 if ((cfg->hdrtype & PCIM_HDRTYPE) == 925 PCIM_HDRTYPE_BRIDGE) { 926 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 927 cfg->subvendor = val & 0xffff; 928 cfg->subdevice = val >> 16; 929 } 930 break; 931 case PCIY_PCIX: /* PCI-X */ 932 /* 933 * Assume we have a PCI-X chipset if we have 934 * at least one PCI-PCI bridge with a PCI-X 935 * capability. Note that some systems with 936 * PCI-express or HT chipsets might match on 937 * this check as well. 938 */ 939 if ((cfg->hdrtype & PCIM_HDRTYPE) == 940 PCIM_HDRTYPE_BRIDGE) 941 pcix_chipset = 1; 942 cfg->pcix.pcix_location = ptr; 943 break; 944 case PCIY_EXPRESS: /* PCI-express */ 945 /* 946 * Assume we have a PCI-express chipset if we have 947 * at least one PCI-express device. 948 */ 949 pcie_chipset = 1; 950 cfg->pcie.pcie_location = ptr; 951 val = REG(ptr + PCIER_FLAGS, 2); 952 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 953 break; 954 case PCIY_EA: /* Enhanced Allocation */ 955 cfg->ea.ea_location = ptr; 956 pci_ea_fill_info(pcib, cfg); 957 break; 958 default: 959 break; 960 } 961 } 962 963 #if defined(__powerpc__) 964 /* 965 * Enable the MSI mapping window for all HyperTransport 966 * slaves. PCI-PCI bridges have their windows enabled via 967 * PCIB_MAP_MSI(). 968 */ 969 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 970 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 971 device_printf(pcib, 972 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 973 cfg->domain, cfg->bus, cfg->slot, cfg->func); 974 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 975 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 976 2); 977 } 978 #endif 979 /* REG and WREG use carry through to next functions */ 980 } 981 982 /* 983 * PCI Vital Product Data 984 */ 985 986 #define PCI_VPD_TIMEOUT 1000000 987 988 static int 989 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 990 { 991 int count = PCI_VPD_TIMEOUT; 992 993 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 994 995 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 996 997 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 998 if (--count < 0) 999 return (ENXIO); 1000 DELAY(1); /* limit looping */ 1001 } 1002 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1003 1004 return (0); 1005 } 1006 1007 #if 0 1008 static int 1009 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1010 { 1011 int count = PCI_VPD_TIMEOUT; 1012 1013 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1014 1015 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1016 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1017 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1018 if (--count < 0) 1019 return (ENXIO); 1020 DELAY(1); /* limit looping */ 1021 } 1022 1023 return (0); 1024 } 1025 #endif 1026 1027 #undef PCI_VPD_TIMEOUT 1028 1029 struct vpd_readstate { 1030 device_t pcib; 1031 pcicfgregs *cfg; 1032 uint32_t val; 1033 int bytesinval; 1034 int off; 1035 uint8_t cksum; 1036 }; 1037 1038 static int 1039 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1040 { 1041 uint32_t reg; 1042 uint8_t byte; 1043 1044 if (vrs->bytesinval == 0) { 1045 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1046 return (ENXIO); 1047 vrs->val = le32toh(reg); 1048 vrs->off += 4; 1049 byte = vrs->val & 0xff; 1050 vrs->bytesinval = 3; 1051 } else { 1052 vrs->val = vrs->val >> 8; 1053 byte = vrs->val & 0xff; 1054 vrs->bytesinval--; 1055 } 1056 1057 vrs->cksum += byte; 1058 *data = byte; 1059 return (0); 1060 } 1061 1062 static void 1063 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1064 { 1065 struct vpd_readstate vrs; 1066 int state; 1067 int name; 1068 int remain; 1069 int i; 1070 int alloc, off; /* alloc/off for RO/W arrays */ 1071 int cksumvalid; 1072 int dflen; 1073 uint8_t byte; 1074 uint8_t byte2; 1075 1076 /* init vpd reader */ 1077 vrs.bytesinval = 0; 1078 vrs.off = 0; 1079 vrs.pcib = pcib; 1080 vrs.cfg = cfg; 1081 vrs.cksum = 0; 1082 1083 state = 0; 1084 name = remain = i = 0; /* shut up stupid gcc */ 1085 alloc = off = 0; /* shut up stupid gcc */ 1086 dflen = 0; /* shut up stupid gcc */ 1087 cksumvalid = -1; 1088 while (state >= 0) { 1089 if (vpd_nextbyte(&vrs, &byte)) { 1090 state = -2; 1091 break; 1092 } 1093 #if 0 1094 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1095 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1096 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1097 #endif 1098 switch (state) { 1099 case 0: /* item name */ 1100 if (byte & 0x80) { 1101 if (vpd_nextbyte(&vrs, &byte2)) { 1102 state = -2; 1103 break; 1104 } 1105 remain = byte2; 1106 if (vpd_nextbyte(&vrs, &byte2)) { 1107 state = -2; 1108 break; 1109 } 1110 remain |= byte2 << 8; 1111 if (remain > (0x7f*4 - vrs.off)) { 1112 state = -1; 1113 pci_printf(cfg, 1114 "invalid VPD data, remain %#x\n", 1115 remain); 1116 } 1117 name = byte & 0x7f; 1118 } else { 1119 remain = byte & 0x7; 1120 name = (byte >> 3) & 0xf; 1121 } 1122 switch (name) { 1123 case 0x2: /* String */ 1124 cfg->vpd.vpd_ident = malloc(remain + 1, 1125 M_DEVBUF, M_WAITOK); 1126 i = 0; 1127 state = 1; 1128 break; 1129 case 0xf: /* End */ 1130 state = -1; 1131 break; 1132 case 0x10: /* VPD-R */ 1133 alloc = 8; 1134 off = 0; 1135 cfg->vpd.vpd_ros = malloc(alloc * 1136 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1137 M_WAITOK | M_ZERO); 1138 state = 2; 1139 break; 1140 case 0x11: /* VPD-W */ 1141 alloc = 8; 1142 off = 0; 1143 cfg->vpd.vpd_w = malloc(alloc * 1144 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1145 M_WAITOK | M_ZERO); 1146 state = 5; 1147 break; 1148 default: /* Invalid data, abort */ 1149 state = -1; 1150 break; 1151 } 1152 break; 1153 1154 case 1: /* Identifier String */ 1155 cfg->vpd.vpd_ident[i++] = byte; 1156 remain--; 1157 if (remain == 0) { 1158 cfg->vpd.vpd_ident[i] = '\0'; 1159 state = 0; 1160 } 1161 break; 1162 1163 case 2: /* VPD-R Keyword Header */ 1164 if (off == alloc) { 1165 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1166 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1167 M_DEVBUF, M_WAITOK | M_ZERO); 1168 } 1169 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1170 if (vpd_nextbyte(&vrs, &byte2)) { 1171 state = -2; 1172 break; 1173 } 1174 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1175 if (vpd_nextbyte(&vrs, &byte2)) { 1176 state = -2; 1177 break; 1178 } 1179 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1180 if (dflen == 0 && 1181 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1182 2) == 0) { 1183 /* 1184 * if this happens, we can't trust the rest 1185 * of the VPD. 1186 */ 1187 pci_printf(cfg, "bad keyword length: %d\n", 1188 dflen); 1189 cksumvalid = 0; 1190 state = -1; 1191 break; 1192 } else if (dflen == 0) { 1193 cfg->vpd.vpd_ros[off].value = malloc(1 * 1194 sizeof(*cfg->vpd.vpd_ros[off].value), 1195 M_DEVBUF, M_WAITOK); 1196 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1197 } else 1198 cfg->vpd.vpd_ros[off].value = malloc( 1199 (dflen + 1) * 1200 sizeof(*cfg->vpd.vpd_ros[off].value), 1201 M_DEVBUF, M_WAITOK); 1202 remain -= 3; 1203 i = 0; 1204 /* keep in sync w/ state 3's transistions */ 1205 if (dflen == 0 && remain == 0) 1206 state = 0; 1207 else if (dflen == 0) 1208 state = 2; 1209 else 1210 state = 3; 1211 break; 1212 1213 case 3: /* VPD-R Keyword Value */ 1214 cfg->vpd.vpd_ros[off].value[i++] = byte; 1215 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1216 "RV", 2) == 0 && cksumvalid == -1) { 1217 if (vrs.cksum == 0) 1218 cksumvalid = 1; 1219 else { 1220 if (bootverbose) 1221 pci_printf(cfg, 1222 "bad VPD cksum, remain %hhu\n", 1223 vrs.cksum); 1224 cksumvalid = 0; 1225 state = -1; 1226 break; 1227 } 1228 } 1229 dflen--; 1230 remain--; 1231 /* keep in sync w/ state 2's transistions */ 1232 if (dflen == 0) 1233 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1234 if (dflen == 0 && remain == 0) { 1235 cfg->vpd.vpd_rocnt = off; 1236 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1237 off * sizeof(*cfg->vpd.vpd_ros), 1238 M_DEVBUF, M_WAITOK | M_ZERO); 1239 state = 0; 1240 } else if (dflen == 0) 1241 state = 2; 1242 break; 1243 1244 case 4: 1245 remain--; 1246 if (remain == 0) 1247 state = 0; 1248 break; 1249 1250 case 5: /* VPD-W Keyword Header */ 1251 if (off == alloc) { 1252 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1253 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1254 M_DEVBUF, M_WAITOK | M_ZERO); 1255 } 1256 cfg->vpd.vpd_w[off].keyword[0] = byte; 1257 if (vpd_nextbyte(&vrs, &byte2)) { 1258 state = -2; 1259 break; 1260 } 1261 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1262 if (vpd_nextbyte(&vrs, &byte2)) { 1263 state = -2; 1264 break; 1265 } 1266 cfg->vpd.vpd_w[off].len = dflen = byte2; 1267 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1268 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1269 sizeof(*cfg->vpd.vpd_w[off].value), 1270 M_DEVBUF, M_WAITOK); 1271 remain -= 3; 1272 i = 0; 1273 /* keep in sync w/ state 6's transistions */ 1274 if (dflen == 0 && remain == 0) 1275 state = 0; 1276 else if (dflen == 0) 1277 state = 5; 1278 else 1279 state = 6; 1280 break; 1281 1282 case 6: /* VPD-W Keyword Value */ 1283 cfg->vpd.vpd_w[off].value[i++] = byte; 1284 dflen--; 1285 remain--; 1286 /* keep in sync w/ state 5's transistions */ 1287 if (dflen == 0) 1288 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1289 if (dflen == 0 && remain == 0) { 1290 cfg->vpd.vpd_wcnt = off; 1291 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1292 off * sizeof(*cfg->vpd.vpd_w), 1293 M_DEVBUF, M_WAITOK | M_ZERO); 1294 state = 0; 1295 } else if (dflen == 0) 1296 state = 5; 1297 break; 1298 1299 default: 1300 pci_printf(cfg, "invalid state: %d\n", state); 1301 state = -1; 1302 break; 1303 } 1304 } 1305 1306 if (cksumvalid == 0 || state < -1) { 1307 /* read-only data bad, clean up */ 1308 if (cfg->vpd.vpd_ros != NULL) { 1309 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1310 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1311 free(cfg->vpd.vpd_ros, M_DEVBUF); 1312 cfg->vpd.vpd_ros = NULL; 1313 } 1314 } 1315 if (state < -1) { 1316 /* I/O error, clean up */ 1317 pci_printf(cfg, "failed to read VPD data.\n"); 1318 if (cfg->vpd.vpd_ident != NULL) { 1319 free(cfg->vpd.vpd_ident, M_DEVBUF); 1320 cfg->vpd.vpd_ident = NULL; 1321 } 1322 if (cfg->vpd.vpd_w != NULL) { 1323 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1324 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1325 free(cfg->vpd.vpd_w, M_DEVBUF); 1326 cfg->vpd.vpd_w = NULL; 1327 } 1328 } 1329 cfg->vpd.vpd_cached = 1; 1330 #undef REG 1331 #undef WREG 1332 } 1333 1334 int 1335 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1336 { 1337 struct pci_devinfo *dinfo = device_get_ivars(child); 1338 pcicfgregs *cfg = &dinfo->cfg; 1339 1340 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1341 pci_read_vpd(device_get_parent(dev), cfg); 1342 1343 *identptr = cfg->vpd.vpd_ident; 1344 1345 if (*identptr == NULL) 1346 return (ENXIO); 1347 1348 return (0); 1349 } 1350 1351 int 1352 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1353 const char **vptr) 1354 { 1355 struct pci_devinfo *dinfo = device_get_ivars(child); 1356 pcicfgregs *cfg = &dinfo->cfg; 1357 int i; 1358 1359 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1360 pci_read_vpd(device_get_parent(dev), cfg); 1361 1362 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1363 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1364 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1365 *vptr = cfg->vpd.vpd_ros[i].value; 1366 return (0); 1367 } 1368 1369 *vptr = NULL; 1370 return (ENXIO); 1371 } 1372 1373 struct pcicfg_vpd * 1374 pci_fetch_vpd_list(device_t dev) 1375 { 1376 struct pci_devinfo *dinfo = device_get_ivars(dev); 1377 pcicfgregs *cfg = &dinfo->cfg; 1378 1379 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1380 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1381 return (&cfg->vpd); 1382 } 1383 1384 /* 1385 * Find the requested HyperTransport capability and return the offset 1386 * in configuration space via the pointer provided. The function 1387 * returns 0 on success and an error code otherwise. 1388 */ 1389 int 1390 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1391 { 1392 int ptr, error; 1393 uint16_t val; 1394 1395 error = pci_find_cap(child, PCIY_HT, &ptr); 1396 if (error) 1397 return (error); 1398 1399 /* 1400 * Traverse the capabilities list checking each HT capability 1401 * to see if it matches the requested HT capability. 1402 */ 1403 for (;;) { 1404 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1405 if (capability == PCIM_HTCAP_SLAVE || 1406 capability == PCIM_HTCAP_HOST) 1407 val &= 0xe000; 1408 else 1409 val &= PCIM_HTCMD_CAP_MASK; 1410 if (val == capability) { 1411 if (capreg != NULL) 1412 *capreg = ptr; 1413 return (0); 1414 } 1415 1416 /* Skip to the next HT capability. */ 1417 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1418 break; 1419 } 1420 1421 return (ENOENT); 1422 } 1423 1424 /* 1425 * Find the next requested HyperTransport capability after start and return 1426 * the offset in configuration space via the pointer provided. The function 1427 * returns 0 on success and an error code otherwise. 1428 */ 1429 int 1430 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1431 int start, int *capreg) 1432 { 1433 int ptr; 1434 uint16_t val; 1435 1436 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1437 ("start capability is not HyperTransport capability")); 1438 ptr = start; 1439 1440 /* 1441 * Traverse the capabilities list checking each HT capability 1442 * to see if it matches the requested HT capability. 1443 */ 1444 for (;;) { 1445 /* Skip to the next HT capability. */ 1446 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1447 break; 1448 1449 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1450 if (capability == PCIM_HTCAP_SLAVE || 1451 capability == PCIM_HTCAP_HOST) 1452 val &= 0xe000; 1453 else 1454 val &= PCIM_HTCMD_CAP_MASK; 1455 if (val == capability) { 1456 if (capreg != NULL) 1457 *capreg = ptr; 1458 return (0); 1459 } 1460 } 1461 1462 return (ENOENT); 1463 } 1464 1465 /* 1466 * Find the requested capability and return the offset in 1467 * configuration space via the pointer provided. The function returns 1468 * 0 on success and an error code otherwise. 1469 */ 1470 int 1471 pci_find_cap_method(device_t dev, device_t child, int capability, 1472 int *capreg) 1473 { 1474 struct pci_devinfo *dinfo = device_get_ivars(child); 1475 pcicfgregs *cfg = &dinfo->cfg; 1476 uint32_t status; 1477 uint8_t ptr; 1478 1479 /* 1480 * Check the CAP_LIST bit of the PCI status register first. 1481 */ 1482 status = pci_read_config(child, PCIR_STATUS, 2); 1483 if (!(status & PCIM_STATUS_CAPPRESENT)) 1484 return (ENXIO); 1485 1486 /* 1487 * Determine the start pointer of the capabilities list. 1488 */ 1489 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1490 case PCIM_HDRTYPE_NORMAL: 1491 case PCIM_HDRTYPE_BRIDGE: 1492 ptr = PCIR_CAP_PTR; 1493 break; 1494 case PCIM_HDRTYPE_CARDBUS: 1495 ptr = PCIR_CAP_PTR_2; 1496 break; 1497 default: 1498 /* XXX: panic? */ 1499 return (ENXIO); /* no extended capabilities support */ 1500 } 1501 ptr = pci_read_config(child, ptr, 1); 1502 1503 /* 1504 * Traverse the capabilities list. 1505 */ 1506 while (ptr != 0) { 1507 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1508 if (capreg != NULL) 1509 *capreg = ptr; 1510 return (0); 1511 } 1512 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1513 } 1514 1515 return (ENOENT); 1516 } 1517 1518 /* 1519 * Find the next requested capability after start and return the offset in 1520 * configuration space via the pointer provided. The function returns 1521 * 0 on success and an error code otherwise. 1522 */ 1523 int 1524 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1525 int start, int *capreg) 1526 { 1527 uint8_t ptr; 1528 1529 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1530 ("start capability is not expected capability")); 1531 1532 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1533 while (ptr != 0) { 1534 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1535 if (capreg != NULL) 1536 *capreg = ptr; 1537 return (0); 1538 } 1539 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1540 } 1541 1542 return (ENOENT); 1543 } 1544 1545 /* 1546 * Find the requested extended capability and return the offset in 1547 * configuration space via the pointer provided. The function returns 1548 * 0 on success and an error code otherwise. 1549 */ 1550 int 1551 pci_find_extcap_method(device_t dev, device_t child, int capability, 1552 int *capreg) 1553 { 1554 struct pci_devinfo *dinfo = device_get_ivars(child); 1555 pcicfgregs *cfg = &dinfo->cfg; 1556 uint32_t ecap; 1557 uint16_t ptr; 1558 1559 /* Only supported for PCI-express devices. */ 1560 if (cfg->pcie.pcie_location == 0) 1561 return (ENXIO); 1562 1563 ptr = PCIR_EXTCAP; 1564 ecap = pci_read_config(child, ptr, 4); 1565 if (ecap == 0xffffffff || ecap == 0) 1566 return (ENOENT); 1567 for (;;) { 1568 if (PCI_EXTCAP_ID(ecap) == capability) { 1569 if (capreg != NULL) 1570 *capreg = ptr; 1571 return (0); 1572 } 1573 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1574 if (ptr == 0) 1575 break; 1576 ecap = pci_read_config(child, ptr, 4); 1577 } 1578 1579 return (ENOENT); 1580 } 1581 1582 /* 1583 * Find the next requested extended capability after start and return the 1584 * offset in configuration space via the pointer provided. The function 1585 * returns 0 on success and an error code otherwise. 1586 */ 1587 int 1588 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1589 int start, int *capreg) 1590 { 1591 struct pci_devinfo *dinfo = device_get_ivars(child); 1592 pcicfgregs *cfg = &dinfo->cfg; 1593 uint32_t ecap; 1594 uint16_t ptr; 1595 1596 /* Only supported for PCI-express devices. */ 1597 if (cfg->pcie.pcie_location == 0) 1598 return (ENXIO); 1599 1600 ecap = pci_read_config(child, start, 4); 1601 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1602 ("start extended capability is not expected capability")); 1603 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1604 while (ptr != 0) { 1605 ecap = pci_read_config(child, ptr, 4); 1606 if (PCI_EXTCAP_ID(ecap) == capability) { 1607 if (capreg != NULL) 1608 *capreg = ptr; 1609 return (0); 1610 } 1611 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1612 } 1613 1614 return (ENOENT); 1615 } 1616 1617 /* 1618 * Support for MSI-X message interrupts. 1619 */ 1620 static void 1621 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1622 { 1623 struct pci_devinfo *dinfo = device_get_ivars(dev); 1624 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1625 uint32_t offset; 1626 1627 KASSERT(msix->msix_table_len > index, ("bogus index")); 1628 offset = msix->msix_table_offset + index * 16; 1629 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1630 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1631 bus_write_4(msix->msix_table_res, offset + 8, data); 1632 } 1633 1634 void 1635 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1636 uint64_t address, uint32_t data) 1637 { 1638 1639 if (pci_msix_rewrite_table) { 1640 struct pci_devinfo *dinfo = device_get_ivars(child); 1641 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1642 1643 /* 1644 * Some VM hosts require MSIX to be disabled in the 1645 * control register before updating the MSIX table 1646 * entries are allowed. It is not enough to only 1647 * disable MSIX while updating a single entry. MSIX 1648 * must be disabled while updating all entries in the 1649 * table. 1650 */ 1651 pci_write_config(child, 1652 msix->msix_location + PCIR_MSIX_CTRL, 1653 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1654 pci_resume_msix(child); 1655 } else 1656 pci_write_msix_entry(child, index, address, data); 1657 1658 /* Enable MSI -> HT mapping. */ 1659 pci_ht_map_msi(child, address); 1660 } 1661 1662 void 1663 pci_mask_msix(device_t dev, u_int index) 1664 { 1665 struct pci_devinfo *dinfo = device_get_ivars(dev); 1666 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1667 uint32_t offset, val; 1668 1669 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1670 offset = msix->msix_table_offset + index * 16 + 12; 1671 val = bus_read_4(msix->msix_table_res, offset); 1672 val |= PCIM_MSIX_VCTRL_MASK; 1673 1674 /* 1675 * Some devices (e.g. Samsung PM961) do not support reads of this 1676 * register, so always write the new value. 1677 */ 1678 bus_write_4(msix->msix_table_res, offset, val); 1679 } 1680 1681 void 1682 pci_unmask_msix(device_t dev, u_int index) 1683 { 1684 struct pci_devinfo *dinfo = device_get_ivars(dev); 1685 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1686 uint32_t offset, val; 1687 1688 KASSERT(msix->msix_table_len > index, ("bogus index")); 1689 offset = msix->msix_table_offset + index * 16 + 12; 1690 val = bus_read_4(msix->msix_table_res, offset); 1691 val &= ~PCIM_MSIX_VCTRL_MASK; 1692 1693 /* 1694 * Some devices (e.g. Samsung PM961) do not support reads of this 1695 * register, so always write the new value. 1696 */ 1697 bus_write_4(msix->msix_table_res, offset, val); 1698 } 1699 1700 int 1701 pci_pending_msix(device_t dev, u_int index) 1702 { 1703 struct pci_devinfo *dinfo = device_get_ivars(dev); 1704 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1705 uint32_t offset, bit; 1706 1707 KASSERT(msix->msix_table_len > index, ("bogus index")); 1708 offset = msix->msix_pba_offset + (index / 32) * 4; 1709 bit = 1 << index % 32; 1710 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1711 } 1712 1713 /* 1714 * Restore MSI-X registers and table during resume. If MSI-X is 1715 * enabled then walk the virtual table to restore the actual MSI-X 1716 * table. 1717 */ 1718 static void 1719 pci_resume_msix(device_t dev) 1720 { 1721 struct pci_devinfo *dinfo = device_get_ivars(dev); 1722 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1723 struct msix_table_entry *mte; 1724 struct msix_vector *mv; 1725 int i; 1726 1727 if (msix->msix_alloc > 0) { 1728 /* First, mask all vectors. */ 1729 for (i = 0; i < msix->msix_msgnum; i++) 1730 pci_mask_msix(dev, i); 1731 1732 /* Second, program any messages with at least one handler. */ 1733 for (i = 0; i < msix->msix_table_len; i++) { 1734 mte = &msix->msix_table[i]; 1735 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1736 continue; 1737 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1738 pci_write_msix_entry(dev, i, mv->mv_address, 1739 mv->mv_data); 1740 pci_unmask_msix(dev, i); 1741 } 1742 } 1743 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1744 msix->msix_ctrl, 2); 1745 } 1746 1747 /* 1748 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1749 * returned in *count. After this function returns, each message will be 1750 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1751 */ 1752 int 1753 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1754 { 1755 struct pci_devinfo *dinfo = device_get_ivars(child); 1756 pcicfgregs *cfg = &dinfo->cfg; 1757 struct resource_list_entry *rle; 1758 int actual, error, i, irq, max; 1759 1760 /* Don't let count == 0 get us into trouble. */ 1761 if (*count == 0) 1762 return (EINVAL); 1763 1764 /* If rid 0 is allocated, then fail. */ 1765 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1766 if (rle != NULL && rle->res != NULL) 1767 return (ENXIO); 1768 1769 /* Already have allocated messages? */ 1770 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1771 return (ENXIO); 1772 1773 /* If MSI-X is blacklisted for this system, fail. */ 1774 if (pci_msix_blacklisted()) 1775 return (ENXIO); 1776 1777 /* MSI-X capability present? */ 1778 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1779 return (ENODEV); 1780 1781 /* Make sure the appropriate BARs are mapped. */ 1782 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1783 cfg->msix.msix_table_bar); 1784 if (rle == NULL || rle->res == NULL || 1785 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1786 return (ENXIO); 1787 cfg->msix.msix_table_res = rle->res; 1788 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1789 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1790 cfg->msix.msix_pba_bar); 1791 if (rle == NULL || rle->res == NULL || 1792 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1793 return (ENXIO); 1794 } 1795 cfg->msix.msix_pba_res = rle->res; 1796 1797 if (bootverbose) 1798 device_printf(child, 1799 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1800 *count, cfg->msix.msix_msgnum); 1801 max = min(*count, cfg->msix.msix_msgnum); 1802 for (i = 0; i < max; i++) { 1803 /* Allocate a message. */ 1804 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1805 if (error) { 1806 if (i == 0) 1807 return (error); 1808 break; 1809 } 1810 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1811 irq, 1); 1812 } 1813 actual = i; 1814 1815 if (bootverbose) { 1816 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1817 if (actual == 1) 1818 device_printf(child, "using IRQ %ju for MSI-X\n", 1819 rle->start); 1820 else { 1821 int run; 1822 1823 /* 1824 * Be fancy and try to print contiguous runs of 1825 * IRQ values as ranges. 'irq' is the previous IRQ. 1826 * 'run' is true if we are in a range. 1827 */ 1828 device_printf(child, "using IRQs %ju", rle->start); 1829 irq = rle->start; 1830 run = 0; 1831 for (i = 1; i < actual; i++) { 1832 rle = resource_list_find(&dinfo->resources, 1833 SYS_RES_IRQ, i + 1); 1834 1835 /* Still in a run? */ 1836 if (rle->start == irq + 1) { 1837 run = 1; 1838 irq++; 1839 continue; 1840 } 1841 1842 /* Finish previous range. */ 1843 if (run) { 1844 printf("-%d", irq); 1845 run = 0; 1846 } 1847 1848 /* Start new range. */ 1849 printf(",%ju", rle->start); 1850 irq = rle->start; 1851 } 1852 1853 /* Unfinished range? */ 1854 if (run) 1855 printf("-%d", irq); 1856 printf(" for MSI-X\n"); 1857 } 1858 } 1859 1860 /* Mask all vectors. */ 1861 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1862 pci_mask_msix(child, i); 1863 1864 /* Allocate and initialize vector data and virtual table. */ 1865 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1866 M_DEVBUF, M_WAITOK | M_ZERO); 1867 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1868 M_DEVBUF, M_WAITOK | M_ZERO); 1869 for (i = 0; i < actual; i++) { 1870 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1871 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1872 cfg->msix.msix_table[i].mte_vector = i + 1; 1873 } 1874 1875 /* Update control register to enable MSI-X. */ 1876 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1877 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1878 cfg->msix.msix_ctrl, 2); 1879 1880 /* Update counts of alloc'd messages. */ 1881 cfg->msix.msix_alloc = actual; 1882 cfg->msix.msix_table_len = actual; 1883 *count = actual; 1884 return (0); 1885 } 1886 1887 /* 1888 * By default, pci_alloc_msix() will assign the allocated IRQ 1889 * resources consecutively to the first N messages in the MSI-X table. 1890 * However, device drivers may want to use different layouts if they 1891 * either receive fewer messages than they asked for, or they wish to 1892 * populate the MSI-X table sparsely. This method allows the driver 1893 * to specify what layout it wants. It must be called after a 1894 * successful pci_alloc_msix() but before any of the associated 1895 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1896 * 1897 * The 'vectors' array contains 'count' message vectors. The array 1898 * maps directly to the MSI-X table in that index 0 in the array 1899 * specifies the vector for the first message in the MSI-X table, etc. 1900 * The vector value in each array index can either be 0 to indicate 1901 * that no vector should be assigned to a message slot, or it can be a 1902 * number from 1 to N (where N is the count returned from a 1903 * succcessful call to pci_alloc_msix()) to indicate which message 1904 * vector (IRQ) to be used for the corresponding message. 1905 * 1906 * On successful return, each message with a non-zero vector will have 1907 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1908 * 1. Additionally, if any of the IRQs allocated via the previous 1909 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1910 * will be freed back to the system automatically. 1911 * 1912 * For example, suppose a driver has a MSI-X table with 6 messages and 1913 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1914 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1915 * C. After the call to pci_alloc_msix(), the device will be setup to 1916 * have an MSI-X table of ABC--- (where - means no vector assigned). 1917 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1918 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1919 * be freed back to the system. This device will also have valid 1920 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1921 * 1922 * In any case, the SYS_RES_IRQ rid X will always map to the message 1923 * at MSI-X table index X - 1 and will only be valid if a vector is 1924 * assigned to that table entry. 1925 */ 1926 int 1927 pci_remap_msix_method(device_t dev, device_t child, int count, 1928 const u_int *vectors) 1929 { 1930 struct pci_devinfo *dinfo = device_get_ivars(child); 1931 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1932 struct resource_list_entry *rle; 1933 int i, irq, j, *used; 1934 1935 /* 1936 * Have to have at least one message in the table but the 1937 * table can't be bigger than the actual MSI-X table in the 1938 * device. 1939 */ 1940 if (count == 0 || count > msix->msix_msgnum) 1941 return (EINVAL); 1942 1943 /* Sanity check the vectors. */ 1944 for (i = 0; i < count; i++) 1945 if (vectors[i] > msix->msix_alloc) 1946 return (EINVAL); 1947 1948 /* 1949 * Make sure there aren't any holes in the vectors to be used. 1950 * It's a big pain to support it, and it doesn't really make 1951 * sense anyway. Also, at least one vector must be used. 1952 */ 1953 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1954 M_ZERO); 1955 for (i = 0; i < count; i++) 1956 if (vectors[i] != 0) 1957 used[vectors[i] - 1] = 1; 1958 for (i = 0; i < msix->msix_alloc - 1; i++) 1959 if (used[i] == 0 && used[i + 1] == 1) { 1960 free(used, M_DEVBUF); 1961 return (EINVAL); 1962 } 1963 if (used[0] != 1) { 1964 free(used, M_DEVBUF); 1965 return (EINVAL); 1966 } 1967 1968 /* Make sure none of the resources are allocated. */ 1969 for (i = 0; i < msix->msix_table_len; i++) { 1970 if (msix->msix_table[i].mte_vector == 0) 1971 continue; 1972 if (msix->msix_table[i].mte_handlers > 0) { 1973 free(used, M_DEVBUF); 1974 return (EBUSY); 1975 } 1976 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1977 KASSERT(rle != NULL, ("missing resource")); 1978 if (rle->res != NULL) { 1979 free(used, M_DEVBUF); 1980 return (EBUSY); 1981 } 1982 } 1983 1984 /* Free the existing resource list entries. */ 1985 for (i = 0; i < msix->msix_table_len; i++) { 1986 if (msix->msix_table[i].mte_vector == 0) 1987 continue; 1988 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1989 } 1990 1991 /* 1992 * Build the new virtual table keeping track of which vectors are 1993 * used. 1994 */ 1995 free(msix->msix_table, M_DEVBUF); 1996 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1997 M_DEVBUF, M_WAITOK | M_ZERO); 1998 for (i = 0; i < count; i++) 1999 msix->msix_table[i].mte_vector = vectors[i]; 2000 msix->msix_table_len = count; 2001 2002 /* Free any unused IRQs and resize the vectors array if necessary. */ 2003 j = msix->msix_alloc - 1; 2004 if (used[j] == 0) { 2005 struct msix_vector *vec; 2006 2007 while (used[j] == 0) { 2008 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2009 msix->msix_vectors[j].mv_irq); 2010 j--; 2011 } 2012 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2013 M_WAITOK); 2014 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2015 (j + 1)); 2016 free(msix->msix_vectors, M_DEVBUF); 2017 msix->msix_vectors = vec; 2018 msix->msix_alloc = j + 1; 2019 } 2020 free(used, M_DEVBUF); 2021 2022 /* Map the IRQs onto the rids. */ 2023 for (i = 0; i < count; i++) { 2024 if (vectors[i] == 0) 2025 continue; 2026 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2027 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2028 irq, 1); 2029 } 2030 2031 if (bootverbose) { 2032 device_printf(child, "Remapped MSI-X IRQs as: "); 2033 for (i = 0; i < count; i++) { 2034 if (i != 0) 2035 printf(", "); 2036 if (vectors[i] == 0) 2037 printf("---"); 2038 else 2039 printf("%d", 2040 msix->msix_vectors[vectors[i] - 1].mv_irq); 2041 } 2042 printf("\n"); 2043 } 2044 2045 return (0); 2046 } 2047 2048 static int 2049 pci_release_msix(device_t dev, device_t child) 2050 { 2051 struct pci_devinfo *dinfo = device_get_ivars(child); 2052 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2053 struct resource_list_entry *rle; 2054 int i; 2055 2056 /* Do we have any messages to release? */ 2057 if (msix->msix_alloc == 0) 2058 return (ENODEV); 2059 2060 /* Make sure none of the resources are allocated. */ 2061 for (i = 0; i < msix->msix_table_len; i++) { 2062 if (msix->msix_table[i].mte_vector == 0) 2063 continue; 2064 if (msix->msix_table[i].mte_handlers > 0) 2065 return (EBUSY); 2066 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2067 KASSERT(rle != NULL, ("missing resource")); 2068 if (rle->res != NULL) 2069 return (EBUSY); 2070 } 2071 2072 /* Update control register to disable MSI-X. */ 2073 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2074 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2075 msix->msix_ctrl, 2); 2076 2077 /* Free the resource list entries. */ 2078 for (i = 0; i < msix->msix_table_len; i++) { 2079 if (msix->msix_table[i].mte_vector == 0) 2080 continue; 2081 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2082 } 2083 free(msix->msix_table, M_DEVBUF); 2084 msix->msix_table_len = 0; 2085 2086 /* Release the IRQs. */ 2087 for (i = 0; i < msix->msix_alloc; i++) 2088 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2089 msix->msix_vectors[i].mv_irq); 2090 free(msix->msix_vectors, M_DEVBUF); 2091 msix->msix_alloc = 0; 2092 return (0); 2093 } 2094 2095 /* 2096 * Return the max supported MSI-X messages this device supports. 2097 * Basically, assuming the MD code can alloc messages, this function 2098 * should return the maximum value that pci_alloc_msix() can return. 2099 * Thus, it is subject to the tunables, etc. 2100 */ 2101 int 2102 pci_msix_count_method(device_t dev, device_t child) 2103 { 2104 struct pci_devinfo *dinfo = device_get_ivars(child); 2105 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2106 2107 if (pci_do_msix && msix->msix_location != 0) 2108 return (msix->msix_msgnum); 2109 return (0); 2110 } 2111 2112 int 2113 pci_msix_pba_bar_method(device_t dev, device_t child) 2114 { 2115 struct pci_devinfo *dinfo = device_get_ivars(child); 2116 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2117 2118 if (pci_do_msix && msix->msix_location != 0) 2119 return (msix->msix_pba_bar); 2120 return (-1); 2121 } 2122 2123 int 2124 pci_msix_table_bar_method(device_t dev, device_t child) 2125 { 2126 struct pci_devinfo *dinfo = device_get_ivars(child); 2127 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2128 2129 if (pci_do_msix && msix->msix_location != 0) 2130 return (msix->msix_table_bar); 2131 return (-1); 2132 } 2133 2134 /* 2135 * HyperTransport MSI mapping control 2136 */ 2137 void 2138 pci_ht_map_msi(device_t dev, uint64_t addr) 2139 { 2140 struct pci_devinfo *dinfo = device_get_ivars(dev); 2141 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2142 2143 if (!ht->ht_msimap) 2144 return; 2145 2146 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2147 ht->ht_msiaddr >> 20 == addr >> 20) { 2148 /* Enable MSI -> HT mapping. */ 2149 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2150 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2151 ht->ht_msictrl, 2); 2152 } 2153 2154 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2155 /* Disable MSI -> HT mapping. */ 2156 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2157 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2158 ht->ht_msictrl, 2); 2159 } 2160 } 2161 2162 int 2163 pci_get_max_payload(device_t dev) 2164 { 2165 struct pci_devinfo *dinfo = device_get_ivars(dev); 2166 int cap; 2167 uint16_t val; 2168 2169 cap = dinfo->cfg.pcie.pcie_location; 2170 if (cap == 0) 2171 return (0); 2172 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2173 val &= PCIEM_CTL_MAX_PAYLOAD; 2174 val >>= 5; 2175 return (1 << (val + 7)); 2176 } 2177 2178 int 2179 pci_get_max_read_req(device_t dev) 2180 { 2181 struct pci_devinfo *dinfo = device_get_ivars(dev); 2182 int cap; 2183 uint16_t val; 2184 2185 cap = dinfo->cfg.pcie.pcie_location; 2186 if (cap == 0) 2187 return (0); 2188 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2189 val &= PCIEM_CTL_MAX_READ_REQUEST; 2190 val >>= 12; 2191 return (1 << (val + 7)); 2192 } 2193 2194 int 2195 pci_set_max_read_req(device_t dev, int size) 2196 { 2197 struct pci_devinfo *dinfo = device_get_ivars(dev); 2198 int cap; 2199 uint16_t val; 2200 2201 cap = dinfo->cfg.pcie.pcie_location; 2202 if (cap == 0) 2203 return (0); 2204 if (size < 128) 2205 size = 128; 2206 if (size > 4096) 2207 size = 4096; 2208 size = (1 << (fls(size) - 1)); 2209 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2210 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2211 val |= (fls(size) - 8) << 12; 2212 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2213 return (size); 2214 } 2215 2216 uint32_t 2217 pcie_read_config(device_t dev, int reg, int width) 2218 { 2219 struct pci_devinfo *dinfo = device_get_ivars(dev); 2220 int cap; 2221 2222 cap = dinfo->cfg.pcie.pcie_location; 2223 if (cap == 0) { 2224 if (width == 2) 2225 return (0xffff); 2226 return (0xffffffff); 2227 } 2228 2229 return (pci_read_config(dev, cap + reg, width)); 2230 } 2231 2232 void 2233 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2234 { 2235 struct pci_devinfo *dinfo = device_get_ivars(dev); 2236 int cap; 2237 2238 cap = dinfo->cfg.pcie.pcie_location; 2239 if (cap == 0) 2240 return; 2241 pci_write_config(dev, cap + reg, value, width); 2242 } 2243 2244 /* 2245 * Adjusts a PCI-e capability register by clearing the bits in mask 2246 * and setting the bits in (value & mask). Bits not set in mask are 2247 * not adjusted. 2248 * 2249 * Returns the old value on success or all ones on failure. 2250 */ 2251 uint32_t 2252 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2253 int width) 2254 { 2255 struct pci_devinfo *dinfo = device_get_ivars(dev); 2256 uint32_t old, new; 2257 int cap; 2258 2259 cap = dinfo->cfg.pcie.pcie_location; 2260 if (cap == 0) { 2261 if (width == 2) 2262 return (0xffff); 2263 return (0xffffffff); 2264 } 2265 2266 old = pci_read_config(dev, cap + reg, width); 2267 new = old & ~mask; 2268 new |= (value & mask); 2269 pci_write_config(dev, cap + reg, new, width); 2270 return (old); 2271 } 2272 2273 /* 2274 * Support for MSI message signalled interrupts. 2275 */ 2276 void 2277 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2278 uint16_t data) 2279 { 2280 struct pci_devinfo *dinfo = device_get_ivars(child); 2281 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2282 2283 /* Write data and address values. */ 2284 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2285 address & 0xffffffff, 4); 2286 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2287 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2288 address >> 32, 4); 2289 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2290 data, 2); 2291 } else 2292 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2293 2); 2294 2295 /* Enable MSI in the control register. */ 2296 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2297 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2298 msi->msi_ctrl, 2); 2299 2300 /* Enable MSI -> HT mapping. */ 2301 pci_ht_map_msi(child, address); 2302 } 2303 2304 void 2305 pci_disable_msi_method(device_t dev, device_t child) 2306 { 2307 struct pci_devinfo *dinfo = device_get_ivars(child); 2308 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2309 2310 /* Disable MSI -> HT mapping. */ 2311 pci_ht_map_msi(child, 0); 2312 2313 /* Disable MSI in the control register. */ 2314 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2315 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2316 msi->msi_ctrl, 2); 2317 } 2318 2319 /* 2320 * Restore MSI registers during resume. If MSI is enabled then 2321 * restore the data and address registers in addition to the control 2322 * register. 2323 */ 2324 static void 2325 pci_resume_msi(device_t dev) 2326 { 2327 struct pci_devinfo *dinfo = device_get_ivars(dev); 2328 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2329 uint64_t address; 2330 uint16_t data; 2331 2332 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2333 address = msi->msi_addr; 2334 data = msi->msi_data; 2335 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2336 address & 0xffffffff, 4); 2337 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2338 pci_write_config(dev, msi->msi_location + 2339 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2340 pci_write_config(dev, msi->msi_location + 2341 PCIR_MSI_DATA_64BIT, data, 2); 2342 } else 2343 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2344 data, 2); 2345 } 2346 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2347 2); 2348 } 2349 2350 static int 2351 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2352 { 2353 struct pci_devinfo *dinfo = device_get_ivars(dev); 2354 pcicfgregs *cfg = &dinfo->cfg; 2355 struct resource_list_entry *rle; 2356 struct msix_table_entry *mte; 2357 struct msix_vector *mv; 2358 uint64_t addr; 2359 uint32_t data; 2360 int error, i, j; 2361 2362 /* 2363 * Handle MSI first. We try to find this IRQ among our list 2364 * of MSI IRQs. If we find it, we request updated address and 2365 * data registers and apply the results. 2366 */ 2367 if (cfg->msi.msi_alloc > 0) { 2368 2369 /* If we don't have any active handlers, nothing to do. */ 2370 if (cfg->msi.msi_handlers == 0) 2371 return (0); 2372 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2373 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2374 i + 1); 2375 if (rle->start == irq) { 2376 error = PCIB_MAP_MSI(device_get_parent(bus), 2377 dev, irq, &addr, &data); 2378 if (error) 2379 return (error); 2380 pci_disable_msi(dev); 2381 dinfo->cfg.msi.msi_addr = addr; 2382 dinfo->cfg.msi.msi_data = data; 2383 pci_enable_msi(dev, addr, data); 2384 return (0); 2385 } 2386 } 2387 return (ENOENT); 2388 } 2389 2390 /* 2391 * For MSI-X, we check to see if we have this IRQ. If we do, 2392 * we request the updated mapping info. If that works, we go 2393 * through all the slots that use this IRQ and update them. 2394 */ 2395 if (cfg->msix.msix_alloc > 0) { 2396 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2397 mv = &cfg->msix.msix_vectors[i]; 2398 if (mv->mv_irq == irq) { 2399 error = PCIB_MAP_MSI(device_get_parent(bus), 2400 dev, irq, &addr, &data); 2401 if (error) 2402 return (error); 2403 mv->mv_address = addr; 2404 mv->mv_data = data; 2405 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2406 mte = &cfg->msix.msix_table[j]; 2407 if (mte->mte_vector != i + 1) 2408 continue; 2409 if (mte->mte_handlers == 0) 2410 continue; 2411 pci_mask_msix(dev, j); 2412 pci_enable_msix(dev, j, addr, data); 2413 pci_unmask_msix(dev, j); 2414 } 2415 } 2416 } 2417 return (ENOENT); 2418 } 2419 2420 return (ENOENT); 2421 } 2422 2423 /* 2424 * Returns true if the specified device is blacklisted because MSI 2425 * doesn't work. 2426 */ 2427 int 2428 pci_msi_device_blacklisted(device_t dev) 2429 { 2430 2431 if (!pci_honor_msi_blacklist) 2432 return (0); 2433 2434 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2435 } 2436 2437 /* 2438 * Determine if MSI is blacklisted globally on this system. Currently, 2439 * we just check for blacklisted chipsets as represented by the 2440 * host-PCI bridge at device 0:0:0. In the future, it may become 2441 * necessary to check other system attributes, such as the kenv values 2442 * that give the motherboard manufacturer and model number. 2443 */ 2444 static int 2445 pci_msi_blacklisted(void) 2446 { 2447 device_t dev; 2448 2449 if (!pci_honor_msi_blacklist) 2450 return (0); 2451 2452 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2453 if (!(pcie_chipset || pcix_chipset)) { 2454 if (vm_guest != VM_GUEST_NO) { 2455 /* 2456 * Whitelist older chipsets in virtual 2457 * machines known to support MSI. 2458 */ 2459 dev = pci_find_bsf(0, 0, 0); 2460 if (dev != NULL) 2461 return (!pci_has_quirk(pci_get_devid(dev), 2462 PCI_QUIRK_ENABLE_MSI_VM)); 2463 } 2464 return (1); 2465 } 2466 2467 dev = pci_find_bsf(0, 0, 0); 2468 if (dev != NULL) 2469 return (pci_msi_device_blacklisted(dev)); 2470 return (0); 2471 } 2472 2473 /* 2474 * Returns true if the specified device is blacklisted because MSI-X 2475 * doesn't work. Note that this assumes that if MSI doesn't work, 2476 * MSI-X doesn't either. 2477 */ 2478 int 2479 pci_msix_device_blacklisted(device_t dev) 2480 { 2481 2482 if (!pci_honor_msi_blacklist) 2483 return (0); 2484 2485 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2486 return (1); 2487 2488 return (pci_msi_device_blacklisted(dev)); 2489 } 2490 2491 /* 2492 * Determine if MSI-X is blacklisted globally on this system. If MSI 2493 * is blacklisted, assume that MSI-X is as well. Check for additional 2494 * chipsets where MSI works but MSI-X does not. 2495 */ 2496 static int 2497 pci_msix_blacklisted(void) 2498 { 2499 device_t dev; 2500 2501 if (!pci_honor_msi_blacklist) 2502 return (0); 2503 2504 dev = pci_find_bsf(0, 0, 0); 2505 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2506 PCI_QUIRK_DISABLE_MSIX)) 2507 return (1); 2508 2509 return (pci_msi_blacklisted()); 2510 } 2511 2512 /* 2513 * Attempt to allocate *count MSI messages. The actual number allocated is 2514 * returned in *count. After this function returns, each message will be 2515 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2516 */ 2517 int 2518 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2519 { 2520 struct pci_devinfo *dinfo = device_get_ivars(child); 2521 pcicfgregs *cfg = &dinfo->cfg; 2522 struct resource_list_entry *rle; 2523 int actual, error, i, irqs[32]; 2524 uint16_t ctrl; 2525 2526 /* Don't let count == 0 get us into trouble. */ 2527 if (*count == 0) 2528 return (EINVAL); 2529 2530 /* If rid 0 is allocated, then fail. */ 2531 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2532 if (rle != NULL && rle->res != NULL) 2533 return (ENXIO); 2534 2535 /* Already have allocated messages? */ 2536 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2537 return (ENXIO); 2538 2539 /* If MSI is blacklisted for this system, fail. */ 2540 if (pci_msi_blacklisted()) 2541 return (ENXIO); 2542 2543 /* MSI capability present? */ 2544 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2545 return (ENODEV); 2546 2547 if (bootverbose) 2548 device_printf(child, 2549 "attempting to allocate %d MSI vectors (%d supported)\n", 2550 *count, cfg->msi.msi_msgnum); 2551 2552 /* Don't ask for more than the device supports. */ 2553 actual = min(*count, cfg->msi.msi_msgnum); 2554 2555 /* Don't ask for more than 32 messages. */ 2556 actual = min(actual, 32); 2557 2558 /* MSI requires power of 2 number of messages. */ 2559 if (!powerof2(actual)) 2560 return (EINVAL); 2561 2562 for (;;) { 2563 /* Try to allocate N messages. */ 2564 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2565 actual, irqs); 2566 if (error == 0) 2567 break; 2568 if (actual == 1) 2569 return (error); 2570 2571 /* Try N / 2. */ 2572 actual >>= 1; 2573 } 2574 2575 /* 2576 * We now have N actual messages mapped onto SYS_RES_IRQ 2577 * resources in the irqs[] array, so add new resources 2578 * starting at rid 1. 2579 */ 2580 for (i = 0; i < actual; i++) 2581 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2582 irqs[i], irqs[i], 1); 2583 2584 if (bootverbose) { 2585 if (actual == 1) 2586 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2587 else { 2588 int run; 2589 2590 /* 2591 * Be fancy and try to print contiguous runs 2592 * of IRQ values as ranges. 'run' is true if 2593 * we are in a range. 2594 */ 2595 device_printf(child, "using IRQs %d", irqs[0]); 2596 run = 0; 2597 for (i = 1; i < actual; i++) { 2598 2599 /* Still in a run? */ 2600 if (irqs[i] == irqs[i - 1] + 1) { 2601 run = 1; 2602 continue; 2603 } 2604 2605 /* Finish previous range. */ 2606 if (run) { 2607 printf("-%d", irqs[i - 1]); 2608 run = 0; 2609 } 2610 2611 /* Start new range. */ 2612 printf(",%d", irqs[i]); 2613 } 2614 2615 /* Unfinished range? */ 2616 if (run) 2617 printf("-%d", irqs[actual - 1]); 2618 printf(" for MSI\n"); 2619 } 2620 } 2621 2622 /* Update control register with actual count. */ 2623 ctrl = cfg->msi.msi_ctrl; 2624 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2625 ctrl |= (ffs(actual) - 1) << 4; 2626 cfg->msi.msi_ctrl = ctrl; 2627 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2628 2629 /* Update counts of alloc'd messages. */ 2630 cfg->msi.msi_alloc = actual; 2631 cfg->msi.msi_handlers = 0; 2632 *count = actual; 2633 return (0); 2634 } 2635 2636 /* Release the MSI messages associated with this device. */ 2637 int 2638 pci_release_msi_method(device_t dev, device_t child) 2639 { 2640 struct pci_devinfo *dinfo = device_get_ivars(child); 2641 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2642 struct resource_list_entry *rle; 2643 int error, i, irqs[32]; 2644 2645 /* Try MSI-X first. */ 2646 error = pci_release_msix(dev, child); 2647 if (error != ENODEV) 2648 return (error); 2649 2650 /* Do we have any messages to release? */ 2651 if (msi->msi_alloc == 0) 2652 return (ENODEV); 2653 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2654 2655 /* Make sure none of the resources are allocated. */ 2656 if (msi->msi_handlers > 0) 2657 return (EBUSY); 2658 for (i = 0; i < msi->msi_alloc; i++) { 2659 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2660 KASSERT(rle != NULL, ("missing MSI resource")); 2661 if (rle->res != NULL) 2662 return (EBUSY); 2663 irqs[i] = rle->start; 2664 } 2665 2666 /* Update control register with 0 count. */ 2667 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2668 ("%s: MSI still enabled", __func__)); 2669 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2670 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2671 msi->msi_ctrl, 2); 2672 2673 /* Release the messages. */ 2674 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2675 for (i = 0; i < msi->msi_alloc; i++) 2676 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2677 2678 /* Update alloc count. */ 2679 msi->msi_alloc = 0; 2680 msi->msi_addr = 0; 2681 msi->msi_data = 0; 2682 return (0); 2683 } 2684 2685 /* 2686 * Return the max supported MSI messages this device supports. 2687 * Basically, assuming the MD code can alloc messages, this function 2688 * should return the maximum value that pci_alloc_msi() can return. 2689 * Thus, it is subject to the tunables, etc. 2690 */ 2691 int 2692 pci_msi_count_method(device_t dev, device_t child) 2693 { 2694 struct pci_devinfo *dinfo = device_get_ivars(child); 2695 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2696 2697 if (pci_do_msi && msi->msi_location != 0) 2698 return (msi->msi_msgnum); 2699 return (0); 2700 } 2701 2702 /* free pcicfgregs structure and all depending data structures */ 2703 2704 int 2705 pci_freecfg(struct pci_devinfo *dinfo) 2706 { 2707 struct devlist *devlist_head; 2708 struct pci_map *pm, *next; 2709 int i; 2710 2711 devlist_head = &pci_devq; 2712 2713 if (dinfo->cfg.vpd.vpd_reg) { 2714 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2715 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2716 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2717 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2718 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2719 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2720 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2721 } 2722 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2723 free(pm, M_DEVBUF); 2724 } 2725 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2726 free(dinfo, M_DEVBUF); 2727 2728 /* increment the generation count */ 2729 pci_generation++; 2730 2731 /* we're losing one device */ 2732 pci_numdevs--; 2733 return (0); 2734 } 2735 2736 /* 2737 * PCI power manangement 2738 */ 2739 int 2740 pci_set_powerstate_method(device_t dev, device_t child, int state) 2741 { 2742 struct pci_devinfo *dinfo = device_get_ivars(child); 2743 pcicfgregs *cfg = &dinfo->cfg; 2744 uint16_t status; 2745 int oldstate, highest, delay; 2746 2747 if (cfg->pp.pp_cap == 0) 2748 return (EOPNOTSUPP); 2749 2750 /* 2751 * Optimize a no state change request away. While it would be OK to 2752 * write to the hardware in theory, some devices have shown odd 2753 * behavior when going from D3 -> D3. 2754 */ 2755 oldstate = pci_get_powerstate(child); 2756 if (oldstate == state) 2757 return (0); 2758 2759 /* 2760 * The PCI power management specification states that after a state 2761 * transition between PCI power states, system software must 2762 * guarantee a minimal delay before the function accesses the device. 2763 * Compute the worst case delay that we need to guarantee before we 2764 * access the device. Many devices will be responsive much more 2765 * quickly than this delay, but there are some that don't respond 2766 * instantly to state changes. Transitions to/from D3 state require 2767 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2768 * is done below with DELAY rather than a sleeper function because 2769 * this function can be called from contexts where we cannot sleep. 2770 */ 2771 highest = (oldstate > state) ? oldstate : state; 2772 if (highest == PCI_POWERSTATE_D3) 2773 delay = 10000; 2774 else if (highest == PCI_POWERSTATE_D2) 2775 delay = 200; 2776 else 2777 delay = 0; 2778 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2779 & ~PCIM_PSTAT_DMASK; 2780 switch (state) { 2781 case PCI_POWERSTATE_D0: 2782 status |= PCIM_PSTAT_D0; 2783 break; 2784 case PCI_POWERSTATE_D1: 2785 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2786 return (EOPNOTSUPP); 2787 status |= PCIM_PSTAT_D1; 2788 break; 2789 case PCI_POWERSTATE_D2: 2790 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2791 return (EOPNOTSUPP); 2792 status |= PCIM_PSTAT_D2; 2793 break; 2794 case PCI_POWERSTATE_D3: 2795 status |= PCIM_PSTAT_D3; 2796 break; 2797 default: 2798 return (EINVAL); 2799 } 2800 2801 if (bootverbose) 2802 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2803 state); 2804 2805 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2806 if (delay) 2807 DELAY(delay); 2808 return (0); 2809 } 2810 2811 int 2812 pci_get_powerstate_method(device_t dev, device_t child) 2813 { 2814 struct pci_devinfo *dinfo = device_get_ivars(child); 2815 pcicfgregs *cfg = &dinfo->cfg; 2816 uint16_t status; 2817 int result; 2818 2819 if (cfg->pp.pp_cap != 0) { 2820 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2821 switch (status & PCIM_PSTAT_DMASK) { 2822 case PCIM_PSTAT_D0: 2823 result = PCI_POWERSTATE_D0; 2824 break; 2825 case PCIM_PSTAT_D1: 2826 result = PCI_POWERSTATE_D1; 2827 break; 2828 case PCIM_PSTAT_D2: 2829 result = PCI_POWERSTATE_D2; 2830 break; 2831 case PCIM_PSTAT_D3: 2832 result = PCI_POWERSTATE_D3; 2833 break; 2834 default: 2835 result = PCI_POWERSTATE_UNKNOWN; 2836 break; 2837 } 2838 } else { 2839 /* No support, device is always at D0 */ 2840 result = PCI_POWERSTATE_D0; 2841 } 2842 return (result); 2843 } 2844 2845 /* 2846 * Some convenience functions for PCI device drivers. 2847 */ 2848 2849 static __inline void 2850 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2851 { 2852 uint16_t command; 2853 2854 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2855 command |= bit; 2856 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2857 } 2858 2859 static __inline void 2860 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2861 { 2862 uint16_t command; 2863 2864 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2865 command &= ~bit; 2866 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2867 } 2868 2869 int 2870 pci_enable_busmaster_method(device_t dev, device_t child) 2871 { 2872 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2873 return (0); 2874 } 2875 2876 int 2877 pci_disable_busmaster_method(device_t dev, device_t child) 2878 { 2879 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2880 return (0); 2881 } 2882 2883 int 2884 pci_enable_io_method(device_t dev, device_t child, int space) 2885 { 2886 uint16_t bit; 2887 2888 switch(space) { 2889 case SYS_RES_IOPORT: 2890 bit = PCIM_CMD_PORTEN; 2891 break; 2892 case SYS_RES_MEMORY: 2893 bit = PCIM_CMD_MEMEN; 2894 break; 2895 default: 2896 return (EINVAL); 2897 } 2898 pci_set_command_bit(dev, child, bit); 2899 return (0); 2900 } 2901 2902 int 2903 pci_disable_io_method(device_t dev, device_t child, int space) 2904 { 2905 uint16_t bit; 2906 2907 switch(space) { 2908 case SYS_RES_IOPORT: 2909 bit = PCIM_CMD_PORTEN; 2910 break; 2911 case SYS_RES_MEMORY: 2912 bit = PCIM_CMD_MEMEN; 2913 break; 2914 default: 2915 return (EINVAL); 2916 } 2917 pci_clear_command_bit(dev, child, bit); 2918 return (0); 2919 } 2920 2921 /* 2922 * New style pci driver. Parent device is either a pci-host-bridge or a 2923 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2924 */ 2925 2926 void 2927 pci_print_verbose(struct pci_devinfo *dinfo) 2928 { 2929 2930 if (bootverbose) { 2931 pcicfgregs *cfg = &dinfo->cfg; 2932 2933 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2934 cfg->vendor, cfg->device, cfg->revid); 2935 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2936 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2937 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2938 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2939 cfg->mfdev); 2940 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2941 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2942 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2943 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2944 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2945 if (cfg->intpin > 0) 2946 printf("\tintpin=%c, irq=%d\n", 2947 cfg->intpin +'a' -1, cfg->intline); 2948 if (cfg->pp.pp_cap) { 2949 uint16_t status; 2950 2951 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2952 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2953 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2954 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2955 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2956 status & PCIM_PSTAT_DMASK); 2957 } 2958 if (cfg->msi.msi_location) { 2959 int ctrl; 2960 2961 ctrl = cfg->msi.msi_ctrl; 2962 printf("\tMSI supports %d message%s%s%s\n", 2963 cfg->msi.msi_msgnum, 2964 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2965 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2966 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2967 } 2968 if (cfg->msix.msix_location) { 2969 printf("\tMSI-X supports %d message%s ", 2970 cfg->msix.msix_msgnum, 2971 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2972 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2973 printf("in map 0x%x\n", 2974 cfg->msix.msix_table_bar); 2975 else 2976 printf("in maps 0x%x and 0x%x\n", 2977 cfg->msix.msix_table_bar, 2978 cfg->msix.msix_pba_bar); 2979 } 2980 } 2981 } 2982 2983 static int 2984 pci_porten(device_t dev) 2985 { 2986 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2987 } 2988 2989 static int 2990 pci_memen(device_t dev) 2991 { 2992 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2993 } 2994 2995 void 2996 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 2997 int *bar64) 2998 { 2999 struct pci_devinfo *dinfo; 3000 pci_addr_t map, testval; 3001 int ln2range; 3002 uint16_t cmd; 3003 3004 /* 3005 * The device ROM BAR is special. It is always a 32-bit 3006 * memory BAR. Bit 0 is special and should not be set when 3007 * sizing the BAR. 3008 */ 3009 dinfo = device_get_ivars(dev); 3010 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3011 map = pci_read_config(dev, reg, 4); 3012 pci_write_config(dev, reg, 0xfffffffe, 4); 3013 testval = pci_read_config(dev, reg, 4); 3014 pci_write_config(dev, reg, map, 4); 3015 *mapp = map; 3016 *testvalp = testval; 3017 if (bar64 != NULL) 3018 *bar64 = 0; 3019 return; 3020 } 3021 3022 map = pci_read_config(dev, reg, 4); 3023 ln2range = pci_maprange(map); 3024 if (ln2range == 64) 3025 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3026 3027 /* 3028 * Disable decoding via the command register before 3029 * determining the BAR's length since we will be placing it in 3030 * a weird state. 3031 */ 3032 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3033 pci_write_config(dev, PCIR_COMMAND, 3034 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3035 3036 /* 3037 * Determine the BAR's length by writing all 1's. The bottom 3038 * log_2(size) bits of the BAR will stick as 0 when we read 3039 * the value back. 3040 * 3041 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3042 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3043 * and combines the result into a 64-bit value." (section 6.2.5.1) 3044 * 3045 * Writes to both registers must be performed before attempting to 3046 * read back the size value. 3047 */ 3048 testval = 0; 3049 pci_write_config(dev, reg, 0xffffffff, 4); 3050 if (ln2range == 64) { 3051 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3052 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3053 } 3054 testval |= pci_read_config(dev, reg, 4); 3055 3056 /* 3057 * Restore the original value of the BAR. We may have reprogrammed 3058 * the BAR of the low-level console device and when booting verbose, 3059 * we need the console device addressable. 3060 */ 3061 pci_write_config(dev, reg, map, 4); 3062 if (ln2range == 64) 3063 pci_write_config(dev, reg + 4, map >> 32, 4); 3064 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3065 3066 *mapp = map; 3067 *testvalp = testval; 3068 if (bar64 != NULL) 3069 *bar64 = (ln2range == 64); 3070 } 3071 3072 static void 3073 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3074 { 3075 struct pci_devinfo *dinfo; 3076 int ln2range; 3077 3078 /* The device ROM BAR is always a 32-bit memory BAR. */ 3079 dinfo = device_get_ivars(dev); 3080 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3081 ln2range = 32; 3082 else 3083 ln2range = pci_maprange(pm->pm_value); 3084 pci_write_config(dev, pm->pm_reg, base, 4); 3085 if (ln2range == 64) 3086 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3087 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3088 if (ln2range == 64) 3089 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3090 pm->pm_reg + 4, 4) << 32; 3091 } 3092 3093 struct pci_map * 3094 pci_find_bar(device_t dev, int reg) 3095 { 3096 struct pci_devinfo *dinfo; 3097 struct pci_map *pm; 3098 3099 dinfo = device_get_ivars(dev); 3100 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3101 if (pm->pm_reg == reg) 3102 return (pm); 3103 } 3104 return (NULL); 3105 } 3106 3107 int 3108 pci_bar_enabled(device_t dev, struct pci_map *pm) 3109 { 3110 struct pci_devinfo *dinfo; 3111 uint16_t cmd; 3112 3113 dinfo = device_get_ivars(dev); 3114 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3115 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3116 return (0); 3117 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3118 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3119 return ((cmd & PCIM_CMD_MEMEN) != 0); 3120 else 3121 return ((cmd & PCIM_CMD_PORTEN) != 0); 3122 } 3123 3124 struct pci_map * 3125 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3126 { 3127 struct pci_devinfo *dinfo; 3128 struct pci_map *pm, *prev; 3129 3130 dinfo = device_get_ivars(dev); 3131 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3132 pm->pm_reg = reg; 3133 pm->pm_value = value; 3134 pm->pm_size = size; 3135 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3136 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3137 reg)); 3138 if (STAILQ_NEXT(prev, pm_link) == NULL || 3139 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3140 break; 3141 } 3142 if (prev != NULL) 3143 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3144 else 3145 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3146 return (pm); 3147 } 3148 3149 static void 3150 pci_restore_bars(device_t dev) 3151 { 3152 struct pci_devinfo *dinfo; 3153 struct pci_map *pm; 3154 int ln2range; 3155 3156 dinfo = device_get_ivars(dev); 3157 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3158 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3159 ln2range = 32; 3160 else 3161 ln2range = pci_maprange(pm->pm_value); 3162 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3163 if (ln2range == 64) 3164 pci_write_config(dev, pm->pm_reg + 4, 3165 pm->pm_value >> 32, 4); 3166 } 3167 } 3168 3169 /* 3170 * Add a resource based on a pci map register. Return 1 if the map 3171 * register is a 32bit map register or 2 if it is a 64bit register. 3172 */ 3173 static int 3174 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3175 int force, int prefetch) 3176 { 3177 struct pci_map *pm; 3178 pci_addr_t base, map, testval; 3179 pci_addr_t start, end, count; 3180 int barlen, basezero, flags, maprange, mapsize, type; 3181 uint16_t cmd; 3182 struct resource *res; 3183 3184 /* 3185 * The BAR may already exist if the device is a CardBus card 3186 * whose CIS is stored in this BAR. 3187 */ 3188 pm = pci_find_bar(dev, reg); 3189 if (pm != NULL) { 3190 maprange = pci_maprange(pm->pm_value); 3191 barlen = maprange == 64 ? 2 : 1; 3192 return (barlen); 3193 } 3194 3195 pci_read_bar(dev, reg, &map, &testval, NULL); 3196 if (PCI_BAR_MEM(map)) { 3197 type = SYS_RES_MEMORY; 3198 if (map & PCIM_BAR_MEM_PREFETCH) 3199 prefetch = 1; 3200 } else 3201 type = SYS_RES_IOPORT; 3202 mapsize = pci_mapsize(testval); 3203 base = pci_mapbase(map); 3204 #ifdef __PCI_BAR_ZERO_VALID 3205 basezero = 0; 3206 #else 3207 basezero = base == 0; 3208 #endif 3209 maprange = pci_maprange(map); 3210 barlen = maprange == 64 ? 2 : 1; 3211 3212 /* 3213 * For I/O registers, if bottom bit is set, and the next bit up 3214 * isn't clear, we know we have a BAR that doesn't conform to the 3215 * spec, so ignore it. Also, sanity check the size of the data 3216 * areas to the type of memory involved. Memory must be at least 3217 * 16 bytes in size, while I/O ranges must be at least 4. 3218 */ 3219 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3220 return (barlen); 3221 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3222 (type == SYS_RES_IOPORT && mapsize < 2)) 3223 return (barlen); 3224 3225 /* Save a record of this BAR. */ 3226 pm = pci_add_bar(dev, reg, map, mapsize); 3227 if (bootverbose) { 3228 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3229 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3230 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3231 printf(", port disabled\n"); 3232 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3233 printf(", memory disabled\n"); 3234 else 3235 printf(", enabled\n"); 3236 } 3237 3238 /* 3239 * If base is 0, then we have problems if this architecture does 3240 * not allow that. It is best to ignore such entries for the 3241 * moment. These will be allocated later if the driver specifically 3242 * requests them. However, some removable buses look better when 3243 * all resources are allocated, so allow '0' to be overriden. 3244 * 3245 * Similarly treat maps whose values is the same as the test value 3246 * read back. These maps have had all f's written to them by the 3247 * BIOS in an attempt to disable the resources. 3248 */ 3249 if (!force && (basezero || map == testval)) 3250 return (barlen); 3251 if ((u_long)base != base) { 3252 device_printf(bus, 3253 "pci%d:%d:%d:%d bar %#x too many address bits", 3254 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3255 pci_get_function(dev), reg); 3256 return (barlen); 3257 } 3258 3259 /* 3260 * This code theoretically does the right thing, but has 3261 * undesirable side effects in some cases where peripherals 3262 * respond oddly to having these bits enabled. Let the user 3263 * be able to turn them off (since pci_enable_io_modes is 1 by 3264 * default). 3265 */ 3266 if (pci_enable_io_modes) { 3267 /* Turn on resources that have been left off by a lazy BIOS */ 3268 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3269 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3270 cmd |= PCIM_CMD_PORTEN; 3271 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3272 } 3273 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3274 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3275 cmd |= PCIM_CMD_MEMEN; 3276 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3277 } 3278 } else { 3279 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3280 return (barlen); 3281 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3282 return (barlen); 3283 } 3284 3285 count = (pci_addr_t)1 << mapsize; 3286 flags = RF_ALIGNMENT_LOG2(mapsize); 3287 if (prefetch) 3288 flags |= RF_PREFETCHABLE; 3289 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3290 start = 0; /* Let the parent decide. */ 3291 end = ~0; 3292 } else { 3293 start = base; 3294 end = base + count - 1; 3295 } 3296 resource_list_add(rl, type, reg, start, end, count); 3297 3298 /* 3299 * Try to allocate the resource for this BAR from our parent 3300 * so that this resource range is already reserved. The 3301 * driver for this device will later inherit this resource in 3302 * pci_alloc_resource(). 3303 */ 3304 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3305 flags); 3306 if ((pci_do_realloc_bars 3307 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3308 && res == NULL && (start != 0 || end != ~0)) { 3309 /* 3310 * If the allocation fails, try to allocate a resource for 3311 * this BAR using any available range. The firmware felt 3312 * it was important enough to assign a resource, so don't 3313 * disable decoding if we can help it. 3314 */ 3315 resource_list_delete(rl, type, reg); 3316 resource_list_add(rl, type, reg, 0, ~0, count); 3317 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3318 count, flags); 3319 } 3320 if (res == NULL) { 3321 /* 3322 * If the allocation fails, delete the resource list entry 3323 * and disable decoding for this device. 3324 * 3325 * If the driver requests this resource in the future, 3326 * pci_reserve_map() will try to allocate a fresh 3327 * resource range. 3328 */ 3329 resource_list_delete(rl, type, reg); 3330 pci_disable_io(dev, type); 3331 if (bootverbose) 3332 device_printf(bus, 3333 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3334 pci_get_domain(dev), pci_get_bus(dev), 3335 pci_get_slot(dev), pci_get_function(dev), reg); 3336 } else { 3337 start = rman_get_start(res); 3338 pci_write_bar(dev, pm, start); 3339 } 3340 return (barlen); 3341 } 3342 3343 /* 3344 * For ATA devices we need to decide early what addressing mode to use. 3345 * Legacy demands that the primary and secondary ATA ports sits on the 3346 * same addresses that old ISA hardware did. This dictates that we use 3347 * those addresses and ignore the BAR's if we cannot set PCI native 3348 * addressing mode. 3349 */ 3350 static void 3351 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3352 uint32_t prefetchmask) 3353 { 3354 int rid, type, progif; 3355 #if 0 3356 /* if this device supports PCI native addressing use it */ 3357 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3358 if ((progif & 0x8a) == 0x8a) { 3359 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3360 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3361 printf("Trying ATA native PCI addressing mode\n"); 3362 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3363 } 3364 } 3365 #endif 3366 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3367 type = SYS_RES_IOPORT; 3368 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3369 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3370 prefetchmask & (1 << 0)); 3371 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3372 prefetchmask & (1 << 1)); 3373 } else { 3374 rid = PCIR_BAR(0); 3375 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3376 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3377 0x1f7, 8, 0); 3378 rid = PCIR_BAR(1); 3379 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3380 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3381 0x3f6, 1, 0); 3382 } 3383 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3384 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3385 prefetchmask & (1 << 2)); 3386 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3387 prefetchmask & (1 << 3)); 3388 } else { 3389 rid = PCIR_BAR(2); 3390 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3391 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3392 0x177, 8, 0); 3393 rid = PCIR_BAR(3); 3394 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3395 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3396 0x376, 1, 0); 3397 } 3398 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3399 prefetchmask & (1 << 4)); 3400 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3401 prefetchmask & (1 << 5)); 3402 } 3403 3404 static void 3405 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3406 { 3407 struct pci_devinfo *dinfo = device_get_ivars(dev); 3408 pcicfgregs *cfg = &dinfo->cfg; 3409 char tunable_name[64]; 3410 int irq; 3411 3412 /* Has to have an intpin to have an interrupt. */ 3413 if (cfg->intpin == 0) 3414 return; 3415 3416 /* Let the user override the IRQ with a tunable. */ 3417 irq = PCI_INVALID_IRQ; 3418 snprintf(tunable_name, sizeof(tunable_name), 3419 "hw.pci%d.%d.%d.INT%c.irq", 3420 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3421 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3422 irq = PCI_INVALID_IRQ; 3423 3424 /* 3425 * If we didn't get an IRQ via the tunable, then we either use the 3426 * IRQ value in the intline register or we ask the bus to route an 3427 * interrupt for us. If force_route is true, then we only use the 3428 * value in the intline register if the bus was unable to assign an 3429 * IRQ. 3430 */ 3431 if (!PCI_INTERRUPT_VALID(irq)) { 3432 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3433 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3434 if (!PCI_INTERRUPT_VALID(irq)) 3435 irq = cfg->intline; 3436 } 3437 3438 /* If after all that we don't have an IRQ, just bail. */ 3439 if (!PCI_INTERRUPT_VALID(irq)) 3440 return; 3441 3442 /* Update the config register if it changed. */ 3443 if (irq != cfg->intline) { 3444 cfg->intline = irq; 3445 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3446 } 3447 3448 /* Add this IRQ as rid 0 interrupt resource. */ 3449 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3450 } 3451 3452 /* Perform early OHCI takeover from SMM. */ 3453 static void 3454 ohci_early_takeover(device_t self) 3455 { 3456 struct resource *res; 3457 uint32_t ctl; 3458 int rid; 3459 int i; 3460 3461 rid = PCIR_BAR(0); 3462 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3463 if (res == NULL) 3464 return; 3465 3466 ctl = bus_read_4(res, OHCI_CONTROL); 3467 if (ctl & OHCI_IR) { 3468 if (bootverbose) 3469 printf("ohci early: " 3470 "SMM active, request owner change\n"); 3471 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3472 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3473 DELAY(1000); 3474 ctl = bus_read_4(res, OHCI_CONTROL); 3475 } 3476 if (ctl & OHCI_IR) { 3477 if (bootverbose) 3478 printf("ohci early: " 3479 "SMM does not respond, resetting\n"); 3480 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3481 } 3482 /* Disable interrupts */ 3483 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3484 } 3485 3486 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3487 } 3488 3489 /* Perform early UHCI takeover from SMM. */ 3490 static void 3491 uhci_early_takeover(device_t self) 3492 { 3493 struct resource *res; 3494 int rid; 3495 3496 /* 3497 * Set the PIRQD enable bit and switch off all the others. We don't 3498 * want legacy support to interfere with us XXX Does this also mean 3499 * that the BIOS won't touch the keyboard anymore if it is connected 3500 * to the ports of the root hub? 3501 */ 3502 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3503 3504 /* Disable interrupts */ 3505 rid = PCI_UHCI_BASE_REG; 3506 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3507 if (res != NULL) { 3508 bus_write_2(res, UHCI_INTR, 0); 3509 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3510 } 3511 } 3512 3513 /* Perform early EHCI takeover from SMM. */ 3514 static void 3515 ehci_early_takeover(device_t self) 3516 { 3517 struct resource *res; 3518 uint32_t cparams; 3519 uint32_t eec; 3520 uint8_t eecp; 3521 uint8_t bios_sem; 3522 uint8_t offs; 3523 int rid; 3524 int i; 3525 3526 rid = PCIR_BAR(0); 3527 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3528 if (res == NULL) 3529 return; 3530 3531 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3532 3533 /* Synchronise with the BIOS if it owns the controller. */ 3534 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3535 eecp = EHCI_EECP_NEXT(eec)) { 3536 eec = pci_read_config(self, eecp, 4); 3537 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3538 continue; 3539 } 3540 bios_sem = pci_read_config(self, eecp + 3541 EHCI_LEGSUP_BIOS_SEM, 1); 3542 if (bios_sem == 0) { 3543 continue; 3544 } 3545 if (bootverbose) 3546 printf("ehci early: " 3547 "SMM active, request owner change\n"); 3548 3549 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3550 3551 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3552 DELAY(1000); 3553 bios_sem = pci_read_config(self, eecp + 3554 EHCI_LEGSUP_BIOS_SEM, 1); 3555 } 3556 3557 if (bios_sem != 0) { 3558 if (bootverbose) 3559 printf("ehci early: " 3560 "SMM does not respond\n"); 3561 } 3562 /* Disable interrupts */ 3563 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3564 bus_write_4(res, offs + EHCI_USBINTR, 0); 3565 } 3566 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3567 } 3568 3569 /* Perform early XHCI takeover from SMM. */ 3570 static void 3571 xhci_early_takeover(device_t self) 3572 { 3573 struct resource *res; 3574 uint32_t cparams; 3575 uint32_t eec; 3576 uint8_t eecp; 3577 uint8_t bios_sem; 3578 uint8_t offs; 3579 int rid; 3580 int i; 3581 3582 rid = PCIR_BAR(0); 3583 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3584 if (res == NULL) 3585 return; 3586 3587 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3588 3589 eec = -1; 3590 3591 /* Synchronise with the BIOS if it owns the controller. */ 3592 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3593 eecp += XHCI_XECP_NEXT(eec) << 2) { 3594 eec = bus_read_4(res, eecp); 3595 3596 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3597 continue; 3598 3599 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3600 if (bios_sem == 0) 3601 continue; 3602 3603 if (bootverbose) 3604 printf("xhci early: " 3605 "SMM active, request owner change\n"); 3606 3607 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3608 3609 /* wait a maximum of 5 second */ 3610 3611 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3612 DELAY(1000); 3613 bios_sem = bus_read_1(res, eecp + 3614 XHCI_XECP_BIOS_SEM); 3615 } 3616 3617 if (bios_sem != 0) { 3618 if (bootverbose) 3619 printf("xhci early: " 3620 "SMM does not respond\n"); 3621 } 3622 3623 /* Disable interrupts */ 3624 offs = bus_read_1(res, XHCI_CAPLENGTH); 3625 bus_write_4(res, offs + XHCI_USBCMD, 0); 3626 bus_read_4(res, offs + XHCI_USBSTS); 3627 } 3628 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3629 } 3630 3631 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3632 static void 3633 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3634 struct resource_list *rl) 3635 { 3636 struct resource *res; 3637 char *cp; 3638 rman_res_t start, end, count; 3639 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3640 3641 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3642 case PCIM_HDRTYPE_BRIDGE: 3643 sec_reg = PCIR_SECBUS_1; 3644 sub_reg = PCIR_SUBBUS_1; 3645 break; 3646 case PCIM_HDRTYPE_CARDBUS: 3647 sec_reg = PCIR_SECBUS_2; 3648 sub_reg = PCIR_SUBBUS_2; 3649 break; 3650 default: 3651 return; 3652 } 3653 3654 /* 3655 * If the existing bus range is valid, attempt to reserve it 3656 * from our parent. If this fails for any reason, clear the 3657 * secbus and subbus registers. 3658 * 3659 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3660 * This would at least preserve the existing sec_bus if it is 3661 * valid. 3662 */ 3663 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3664 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3665 3666 /* Quirk handling. */ 3667 switch (pci_get_devid(dev)) { 3668 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3669 sup_bus = pci_read_config(dev, 0x41, 1); 3670 if (sup_bus != 0xff) { 3671 sec_bus = sup_bus + 1; 3672 sub_bus = sup_bus + 1; 3673 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3674 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3675 } 3676 break; 3677 3678 case 0x00dd10de: 3679 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3680 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3681 break; 3682 if (strncmp(cp, "Compal", 6) != 0) { 3683 freeenv(cp); 3684 break; 3685 } 3686 freeenv(cp); 3687 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3688 break; 3689 if (strncmp(cp, "08A0", 4) != 0) { 3690 freeenv(cp); 3691 break; 3692 } 3693 freeenv(cp); 3694 if (sub_bus < 0xa) { 3695 sub_bus = 0xa; 3696 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3697 } 3698 break; 3699 } 3700 3701 if (bootverbose) 3702 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3703 if (sec_bus > 0 && sub_bus >= sec_bus) { 3704 start = sec_bus; 3705 end = sub_bus; 3706 count = end - start + 1; 3707 3708 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3709 3710 /* 3711 * If requested, clear secondary bus registers in 3712 * bridge devices to force a complete renumbering 3713 * rather than reserving the existing range. However, 3714 * preserve the existing size. 3715 */ 3716 if (pci_clear_buses) 3717 goto clear; 3718 3719 rid = 0; 3720 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3721 start, end, count, 0); 3722 if (res != NULL) 3723 return; 3724 3725 if (bootverbose) 3726 device_printf(bus, 3727 "pci%d:%d:%d:%d secbus failed to allocate\n", 3728 pci_get_domain(dev), pci_get_bus(dev), 3729 pci_get_slot(dev), pci_get_function(dev)); 3730 } 3731 3732 clear: 3733 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3734 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3735 } 3736 3737 static struct resource * 3738 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3739 rman_res_t end, rman_res_t count, u_int flags) 3740 { 3741 struct pci_devinfo *dinfo; 3742 pcicfgregs *cfg; 3743 struct resource_list *rl; 3744 struct resource *res; 3745 int sec_reg, sub_reg; 3746 3747 dinfo = device_get_ivars(child); 3748 cfg = &dinfo->cfg; 3749 rl = &dinfo->resources; 3750 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3751 case PCIM_HDRTYPE_BRIDGE: 3752 sec_reg = PCIR_SECBUS_1; 3753 sub_reg = PCIR_SUBBUS_1; 3754 break; 3755 case PCIM_HDRTYPE_CARDBUS: 3756 sec_reg = PCIR_SECBUS_2; 3757 sub_reg = PCIR_SUBBUS_2; 3758 break; 3759 default: 3760 return (NULL); 3761 } 3762 3763 if (*rid != 0) 3764 return (NULL); 3765 3766 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3767 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3768 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3769 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3770 start, end, count, flags & ~RF_ACTIVE); 3771 if (res == NULL) { 3772 resource_list_delete(rl, PCI_RES_BUS, *rid); 3773 device_printf(child, "allocating %ju bus%s failed\n", 3774 count, count == 1 ? "" : "es"); 3775 return (NULL); 3776 } 3777 if (bootverbose) 3778 device_printf(child, 3779 "Lazy allocation of %ju bus%s at %ju\n", count, 3780 count == 1 ? "" : "es", rman_get_start(res)); 3781 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3782 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3783 } 3784 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3785 end, count, flags)); 3786 } 3787 #endif 3788 3789 static int 3790 pci_ea_bei_to_rid(device_t dev, int bei) 3791 { 3792 #ifdef PCI_IOV 3793 struct pci_devinfo *dinfo; 3794 int iov_pos; 3795 struct pcicfg_iov *iov; 3796 3797 dinfo = device_get_ivars(dev); 3798 iov = dinfo->cfg.iov; 3799 if (iov != NULL) 3800 iov_pos = iov->iov_pos; 3801 else 3802 iov_pos = 0; 3803 #endif 3804 3805 /* Check if matches BAR */ 3806 if ((bei >= PCIM_EA_BEI_BAR_0) && 3807 (bei <= PCIM_EA_BEI_BAR_5)) 3808 return (PCIR_BAR(bei)); 3809 3810 /* Check ROM */ 3811 if (bei == PCIM_EA_BEI_ROM) 3812 return (PCIR_BIOS); 3813 3814 #ifdef PCI_IOV 3815 /* Check if matches VF_BAR */ 3816 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3817 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3818 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3819 iov_pos); 3820 #endif 3821 3822 return (-1); 3823 } 3824 3825 int 3826 pci_ea_is_enabled(device_t dev, int rid) 3827 { 3828 struct pci_ea_entry *ea; 3829 struct pci_devinfo *dinfo; 3830 3831 dinfo = device_get_ivars(dev); 3832 3833 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3834 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3835 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3836 } 3837 3838 return (0); 3839 } 3840 3841 void 3842 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3843 { 3844 struct pci_ea_entry *ea; 3845 struct pci_devinfo *dinfo; 3846 pci_addr_t start, end, count; 3847 struct resource_list *rl; 3848 int type, flags, rid; 3849 struct resource *res; 3850 uint32_t tmp; 3851 #ifdef PCI_IOV 3852 struct pcicfg_iov *iov; 3853 #endif 3854 3855 dinfo = device_get_ivars(dev); 3856 rl = &dinfo->resources; 3857 flags = 0; 3858 3859 #ifdef PCI_IOV 3860 iov = dinfo->cfg.iov; 3861 #endif 3862 3863 if (dinfo->cfg.ea.ea_location == 0) 3864 return; 3865 3866 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3867 3868 /* 3869 * TODO: Ignore EA-BAR if is not enabled. 3870 * Currently the EA implementation supports 3871 * only situation, where EA structure contains 3872 * predefined entries. In case they are not enabled 3873 * leave them unallocated and proceed with 3874 * a legacy-BAR mechanism. 3875 */ 3876 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3877 continue; 3878 3879 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3880 case PCIM_EA_P_MEM_PREFETCH: 3881 case PCIM_EA_P_VF_MEM_PREFETCH: 3882 flags = RF_PREFETCHABLE; 3883 /* FALLTHROUGH */ 3884 case PCIM_EA_P_VF_MEM: 3885 case PCIM_EA_P_MEM: 3886 type = SYS_RES_MEMORY; 3887 break; 3888 case PCIM_EA_P_IO: 3889 type = SYS_RES_IOPORT; 3890 break; 3891 default: 3892 continue; 3893 } 3894 3895 if (alloc_iov != 0) { 3896 #ifdef PCI_IOV 3897 /* Allocating IOV, confirm BEI matches */ 3898 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3899 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3900 continue; 3901 #else 3902 continue; 3903 #endif 3904 } else { 3905 /* Allocating BAR, confirm BEI matches */ 3906 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3907 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3908 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3909 continue; 3910 } 3911 3912 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3913 if (rid < 0) 3914 continue; 3915 3916 /* Skip resources already allocated by EA */ 3917 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3918 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3919 continue; 3920 3921 start = ea->eae_base; 3922 count = ea->eae_max_offset + 1; 3923 #ifdef PCI_IOV 3924 if (iov != NULL) 3925 count = count * iov->iov_num_vfs; 3926 #endif 3927 end = start + count - 1; 3928 if (count == 0) 3929 continue; 3930 3931 resource_list_add(rl, type, rid, start, end, count); 3932 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3933 flags); 3934 if (res == NULL) { 3935 resource_list_delete(rl, type, rid); 3936 3937 /* 3938 * Failed to allocate using EA, disable entry. 3939 * Another attempt to allocation will be performed 3940 * further, but this time using legacy BAR registers 3941 */ 3942 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3943 tmp &= ~PCIM_EA_ENABLE; 3944 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3945 3946 /* 3947 * Disabling entry might fail in case it is hardwired. 3948 * Read flags again to match current status. 3949 */ 3950 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3951 3952 continue; 3953 } 3954 3955 /* As per specification, fill BAR with zeros */ 3956 pci_write_config(dev, rid, 0, 4); 3957 } 3958 } 3959 3960 void 3961 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3962 { 3963 struct pci_devinfo *dinfo; 3964 pcicfgregs *cfg; 3965 struct resource_list *rl; 3966 const struct pci_quirk *q; 3967 uint32_t devid; 3968 int i; 3969 3970 dinfo = device_get_ivars(dev); 3971 cfg = &dinfo->cfg; 3972 rl = &dinfo->resources; 3973 devid = (cfg->device << 16) | cfg->vendor; 3974 3975 /* Allocate resources using Enhanced Allocation */ 3976 pci_add_resources_ea(bus, dev, 0); 3977 3978 /* ATA devices needs special map treatment */ 3979 if ((pci_get_class(dev) == PCIC_STORAGE) && 3980 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3981 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3982 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3983 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3984 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3985 else 3986 for (i = 0; i < cfg->nummaps;) { 3987 /* Skip resources already managed by EA */ 3988 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 3989 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 3990 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 3991 i++; 3992 continue; 3993 } 3994 3995 /* 3996 * Skip quirked resources. 3997 */ 3998 for (q = &pci_quirks[0]; q->devid != 0; q++) 3999 if (q->devid == devid && 4000 q->type == PCI_QUIRK_UNMAP_REG && 4001 q->arg1 == PCIR_BAR(i)) 4002 break; 4003 if (q->devid != 0) { 4004 i++; 4005 continue; 4006 } 4007 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4008 prefetchmask & (1 << i)); 4009 } 4010 4011 /* 4012 * Add additional, quirked resources. 4013 */ 4014 for (q = &pci_quirks[0]; q->devid != 0; q++) 4015 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4016 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4017 4018 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4019 #ifdef __PCI_REROUTE_INTERRUPT 4020 /* 4021 * Try to re-route interrupts. Sometimes the BIOS or 4022 * firmware may leave bogus values in these registers. 4023 * If the re-route fails, then just stick with what we 4024 * have. 4025 */ 4026 pci_assign_interrupt(bus, dev, 1); 4027 #else 4028 pci_assign_interrupt(bus, dev, 0); 4029 #endif 4030 } 4031 4032 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4033 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4034 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4035 xhci_early_takeover(dev); 4036 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4037 ehci_early_takeover(dev); 4038 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4039 ohci_early_takeover(dev); 4040 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4041 uhci_early_takeover(dev); 4042 } 4043 4044 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4045 /* 4046 * Reserve resources for secondary bus ranges behind bridge 4047 * devices. 4048 */ 4049 pci_reserve_secbus(bus, dev, cfg, rl); 4050 #endif 4051 } 4052 4053 static struct pci_devinfo * 4054 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4055 int slot, int func) 4056 { 4057 struct pci_devinfo *dinfo; 4058 4059 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4060 if (dinfo != NULL) 4061 pci_add_child(dev, dinfo); 4062 4063 return (dinfo); 4064 } 4065 4066 void 4067 pci_add_children(device_t dev, int domain, int busno) 4068 { 4069 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4070 device_t pcib = device_get_parent(dev); 4071 struct pci_devinfo *dinfo; 4072 int maxslots; 4073 int s, f, pcifunchigh; 4074 uint8_t hdrtype; 4075 int first_func; 4076 4077 /* 4078 * Try to detect a device at slot 0, function 0. If it exists, try to 4079 * enable ARI. We must enable ARI before detecting the rest of the 4080 * functions on this bus as ARI changes the set of slots and functions 4081 * that are legal on this bus. 4082 */ 4083 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4084 if (dinfo != NULL && pci_enable_ari) 4085 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4086 4087 /* 4088 * Start looking for new devices on slot 0 at function 1 because we 4089 * just identified the device at slot 0, function 0. 4090 */ 4091 first_func = 1; 4092 4093 maxslots = PCIB_MAXSLOTS(pcib); 4094 for (s = 0; s <= maxslots; s++, first_func = 0) { 4095 pcifunchigh = 0; 4096 f = 0; 4097 DELAY(1); 4098 hdrtype = REG(PCIR_HDRTYPE, 1); 4099 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4100 continue; 4101 if (hdrtype & PCIM_MFDEV) 4102 pcifunchigh = PCIB_MAXFUNCS(pcib); 4103 for (f = first_func; f <= pcifunchigh; f++) 4104 pci_identify_function(pcib, dev, domain, busno, s, f); 4105 } 4106 #undef REG 4107 } 4108 4109 int 4110 pci_rescan_method(device_t dev) 4111 { 4112 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4113 device_t pcib = device_get_parent(dev); 4114 device_t child, *devlist, *unchanged; 4115 int devcount, error, i, j, maxslots, oldcount; 4116 int busno, domain, s, f, pcifunchigh; 4117 uint8_t hdrtype; 4118 4119 /* No need to check for ARI on a rescan. */ 4120 error = device_get_children(dev, &devlist, &devcount); 4121 if (error) 4122 return (error); 4123 if (devcount != 0) { 4124 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4125 M_NOWAIT | M_ZERO); 4126 if (unchanged == NULL) { 4127 free(devlist, M_TEMP); 4128 return (ENOMEM); 4129 } 4130 } else 4131 unchanged = NULL; 4132 4133 domain = pcib_get_domain(dev); 4134 busno = pcib_get_bus(dev); 4135 maxslots = PCIB_MAXSLOTS(pcib); 4136 for (s = 0; s <= maxslots; s++) { 4137 /* If function 0 is not present, skip to the next slot. */ 4138 f = 0; 4139 if (REG(PCIR_VENDOR, 2) == 0xffff) 4140 continue; 4141 pcifunchigh = 0; 4142 hdrtype = REG(PCIR_HDRTYPE, 1); 4143 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4144 continue; 4145 if (hdrtype & PCIM_MFDEV) 4146 pcifunchigh = PCIB_MAXFUNCS(pcib); 4147 for (f = 0; f <= pcifunchigh; f++) { 4148 if (REG(PCIR_VENDOR, 2) == 0xffff) 4149 continue; 4150 4151 /* 4152 * Found a valid function. Check if a 4153 * device_t for this device already exists. 4154 */ 4155 for (i = 0; i < devcount; i++) { 4156 child = devlist[i]; 4157 if (child == NULL) 4158 continue; 4159 if (pci_get_slot(child) == s && 4160 pci_get_function(child) == f) { 4161 unchanged[i] = child; 4162 goto next_func; 4163 } 4164 } 4165 4166 pci_identify_function(pcib, dev, domain, busno, s, f); 4167 next_func:; 4168 } 4169 } 4170 4171 /* Remove devices that are no longer present. */ 4172 for (i = 0; i < devcount; i++) { 4173 if (unchanged[i] != NULL) 4174 continue; 4175 device_delete_child(dev, devlist[i]); 4176 } 4177 4178 free(devlist, M_TEMP); 4179 oldcount = devcount; 4180 4181 /* Try to attach the devices just added. */ 4182 error = device_get_children(dev, &devlist, &devcount); 4183 if (error) { 4184 free(unchanged, M_TEMP); 4185 return (error); 4186 } 4187 4188 for (i = 0; i < devcount; i++) { 4189 for (j = 0; j < oldcount; j++) { 4190 if (devlist[i] == unchanged[j]) 4191 goto next_device; 4192 } 4193 4194 device_probe_and_attach(devlist[i]); 4195 next_device:; 4196 } 4197 4198 free(unchanged, M_TEMP); 4199 free(devlist, M_TEMP); 4200 return (0); 4201 #undef REG 4202 } 4203 4204 #ifdef PCI_IOV 4205 device_t 4206 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4207 uint16_t did) 4208 { 4209 struct pci_devinfo *vf_dinfo; 4210 device_t pcib; 4211 int busno, slot, func; 4212 4213 pcib = device_get_parent(bus); 4214 4215 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4216 4217 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4218 slot, func, vid, did); 4219 4220 vf_dinfo->cfg.flags |= PCICFG_VF; 4221 pci_add_child(bus, vf_dinfo); 4222 4223 return (vf_dinfo->cfg.dev); 4224 } 4225 4226 device_t 4227 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4228 uint16_t vid, uint16_t did) 4229 { 4230 4231 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4232 } 4233 #endif 4234 4235 static void 4236 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4237 { 4238 int aer; 4239 uint32_t r; 4240 uint16_t r2; 4241 4242 if (dinfo->cfg.pcie.pcie_location != 0 && 4243 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4244 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4245 PCIER_ROOT_CTL, 2); 4246 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4247 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4248 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4249 PCIER_ROOT_CTL, r2, 2); 4250 } 4251 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4252 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4253 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4254 if (r != 0 && bootverbose) { 4255 pci_printf(&dinfo->cfg, 4256 "clearing AER UC 0x%08x -> 0x%08x\n", 4257 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4258 4)); 4259 } 4260 4261 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4262 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4263 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4264 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4265 PCIM_AER_UC_POISONED_TLP | 4266 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4267 PCIM_AER_UC_COMPLETION_TIMEOUT | 4268 PCIM_AER_UC_COMPLETER_ABORT | 4269 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4270 PCIM_AER_UC_RECEIVER_OVERFLOW | 4271 PCIM_AER_UC_MALFORMED_TLP | 4272 PCIM_AER_UC_ECRC_ERROR | 4273 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4274 PCIM_AER_UC_ACS_VIOLATION | 4275 PCIM_AER_UC_INTERNAL_ERROR | 4276 PCIM_AER_UC_MC_BLOCKED_TLP | 4277 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4278 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4279 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4280 4281 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4282 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4283 if (r != 0 && bootverbose) { 4284 pci_printf(&dinfo->cfg, 4285 "clearing AER COR 0x%08x -> 0x%08x\n", 4286 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4287 4)); 4288 } 4289 4290 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4291 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4292 PCIM_AER_COR_BAD_TLP | 4293 PCIM_AER_COR_BAD_DLLP | 4294 PCIM_AER_COR_REPLAY_ROLLOVER | 4295 PCIM_AER_COR_REPLAY_TIMEOUT | 4296 PCIM_AER_COR_ADVISORY_NF_ERROR | 4297 PCIM_AER_COR_INTERNAL_ERROR | 4298 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4299 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4300 4301 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4302 PCIER_DEVICE_CTL, 2); 4303 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4304 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4305 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4306 PCIER_DEVICE_CTL, r, 2); 4307 } 4308 } 4309 4310 void 4311 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4312 { 4313 device_t dev; 4314 4315 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4316 device_set_ivars(dev, dinfo); 4317 resource_list_init(&dinfo->resources); 4318 pci_cfg_save(dev, dinfo, 0); 4319 pci_cfg_restore(dev, dinfo); 4320 pci_print_verbose(dinfo); 4321 pci_add_resources(bus, dev, 0, 0); 4322 pci_child_added(dinfo->cfg.dev); 4323 4324 if (pci_clear_aer_on_attach) 4325 pci_add_child_clear_aer(dev, dinfo); 4326 4327 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4328 } 4329 4330 void 4331 pci_child_added_method(device_t dev, device_t child) 4332 { 4333 4334 } 4335 4336 static int 4337 pci_probe(device_t dev) 4338 { 4339 4340 device_set_desc(dev, "PCI bus"); 4341 4342 /* Allow other subclasses to override this driver. */ 4343 return (BUS_PROBE_GENERIC); 4344 } 4345 4346 int 4347 pci_attach_common(device_t dev) 4348 { 4349 struct pci_softc *sc; 4350 int busno, domain; 4351 #ifdef PCI_RES_BUS 4352 int rid; 4353 #endif 4354 4355 sc = device_get_softc(dev); 4356 domain = pcib_get_domain(dev); 4357 busno = pcib_get_bus(dev); 4358 #ifdef PCI_RES_BUS 4359 rid = 0; 4360 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4361 1, 0); 4362 if (sc->sc_bus == NULL) { 4363 device_printf(dev, "failed to allocate bus number\n"); 4364 return (ENXIO); 4365 } 4366 #endif 4367 if (bootverbose) 4368 device_printf(dev, "domain=%d, physical bus=%d\n", 4369 domain, busno); 4370 sc->sc_dma_tag = bus_get_dma_tag(dev); 4371 return (0); 4372 } 4373 4374 int 4375 pci_attach(device_t dev) 4376 { 4377 int busno, domain, error; 4378 4379 error = pci_attach_common(dev); 4380 if (error) 4381 return (error); 4382 4383 /* 4384 * Since there can be multiple independently numbered PCI 4385 * buses on systems with multiple PCI domains, we can't use 4386 * the unit number to decide which bus we are probing. We ask 4387 * the parent pcib what our domain and bus numbers are. 4388 */ 4389 domain = pcib_get_domain(dev); 4390 busno = pcib_get_bus(dev); 4391 pci_add_children(dev, domain, busno); 4392 return (bus_generic_attach(dev)); 4393 } 4394 4395 int 4396 pci_detach(device_t dev) 4397 { 4398 #ifdef PCI_RES_BUS 4399 struct pci_softc *sc; 4400 #endif 4401 int error; 4402 4403 error = bus_generic_detach(dev); 4404 if (error) 4405 return (error); 4406 #ifdef PCI_RES_BUS 4407 sc = device_get_softc(dev); 4408 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4409 if (error) 4410 return (error); 4411 #endif 4412 return (device_delete_children(dev)); 4413 } 4414 4415 static void 4416 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4417 { 4418 int line, unit; 4419 const char *at; 4420 char me1[24], me2[32]; 4421 uint8_t b, s, f; 4422 uint32_t d; 4423 4424 d = pci_get_domain(child); 4425 b = pci_get_bus(child); 4426 s = pci_get_slot(child); 4427 f = pci_get_function(child); 4428 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4429 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4430 line = 0; 4431 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4432 resource_string_value(name, unit, "at", &at); 4433 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4434 continue; /* No match, try next candidate */ 4435 *unitp = unit; 4436 return; 4437 } 4438 } 4439 4440 static void 4441 pci_set_power_child(device_t dev, device_t child, int state) 4442 { 4443 device_t pcib; 4444 int dstate; 4445 4446 /* 4447 * Set the device to the given state. If the firmware suggests 4448 * a different power state, use it instead. If power management 4449 * is not present, the firmware is responsible for managing 4450 * device power. Skip children who aren't attached since they 4451 * are handled separately. 4452 */ 4453 pcib = device_get_parent(dev); 4454 dstate = state; 4455 if (device_is_attached(child) && 4456 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4457 pci_set_powerstate(child, dstate); 4458 } 4459 4460 int 4461 pci_suspend_child(device_t dev, device_t child) 4462 { 4463 struct pci_devinfo *dinfo; 4464 struct resource_list_entry *rle; 4465 int error; 4466 4467 dinfo = device_get_ivars(child); 4468 4469 /* 4470 * Save the PCI configuration space for the child and set the 4471 * device in the appropriate power state for this sleep state. 4472 */ 4473 pci_cfg_save(child, dinfo, 0); 4474 4475 /* Suspend devices before potentially powering them down. */ 4476 error = bus_generic_suspend_child(dev, child); 4477 4478 if (error) 4479 return (error); 4480 4481 if (pci_do_power_suspend) { 4482 /* 4483 * Make sure this device's interrupt handler is not invoked 4484 * in the case the device uses a shared interrupt that can 4485 * be raised by some other device. 4486 * This is applicable only to regular (legacy) PCI interrupts 4487 * as MSI/MSI-X interrupts are never shared. 4488 */ 4489 rle = resource_list_find(&dinfo->resources, 4490 SYS_RES_IRQ, 0); 4491 if (rle != NULL && rle->res != NULL) 4492 (void)bus_suspend_intr(child, rle->res); 4493 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4494 } 4495 4496 return (0); 4497 } 4498 4499 int 4500 pci_resume_child(device_t dev, device_t child) 4501 { 4502 struct pci_devinfo *dinfo; 4503 struct resource_list_entry *rle; 4504 4505 if (pci_do_power_resume) 4506 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4507 4508 dinfo = device_get_ivars(child); 4509 pci_cfg_restore(child, dinfo); 4510 if (!device_is_attached(child)) 4511 pci_cfg_save(child, dinfo, 1); 4512 4513 bus_generic_resume_child(dev, child); 4514 4515 /* 4516 * Allow interrupts only after fully resuming the driver and hardware. 4517 */ 4518 if (pci_do_power_suspend) { 4519 /* See pci_suspend_child for details. */ 4520 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4521 if (rle != NULL && rle->res != NULL) 4522 (void)bus_resume_intr(child, rle->res); 4523 } 4524 4525 return (0); 4526 } 4527 4528 int 4529 pci_resume(device_t dev) 4530 { 4531 device_t child, *devlist; 4532 int error, i, numdevs; 4533 4534 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4535 return (error); 4536 4537 /* 4538 * Resume critical devices first, then everything else later. 4539 */ 4540 for (i = 0; i < numdevs; i++) { 4541 child = devlist[i]; 4542 switch (pci_get_class(child)) { 4543 case PCIC_DISPLAY: 4544 case PCIC_MEMORY: 4545 case PCIC_BRIDGE: 4546 case PCIC_BASEPERIPH: 4547 BUS_RESUME_CHILD(dev, child); 4548 break; 4549 } 4550 } 4551 for (i = 0; i < numdevs; i++) { 4552 child = devlist[i]; 4553 switch (pci_get_class(child)) { 4554 case PCIC_DISPLAY: 4555 case PCIC_MEMORY: 4556 case PCIC_BRIDGE: 4557 case PCIC_BASEPERIPH: 4558 break; 4559 default: 4560 BUS_RESUME_CHILD(dev, child); 4561 } 4562 } 4563 free(devlist, M_TEMP); 4564 return (0); 4565 } 4566 4567 static void 4568 pci_load_vendor_data(void) 4569 { 4570 caddr_t data; 4571 void *ptr; 4572 size_t sz; 4573 4574 data = preload_search_by_type("pci_vendor_data"); 4575 if (data != NULL) { 4576 ptr = preload_fetch_addr(data); 4577 sz = preload_fetch_size(data); 4578 if (ptr != NULL && sz != 0) { 4579 pci_vendordata = ptr; 4580 pci_vendordata_size = sz; 4581 /* terminate the database */ 4582 pci_vendordata[pci_vendordata_size] = '\n'; 4583 } 4584 } 4585 } 4586 4587 void 4588 pci_driver_added(device_t dev, driver_t *driver) 4589 { 4590 int numdevs; 4591 device_t *devlist; 4592 device_t child; 4593 struct pci_devinfo *dinfo; 4594 int i; 4595 4596 if (bootverbose) 4597 device_printf(dev, "driver added\n"); 4598 DEVICE_IDENTIFY(driver, dev); 4599 if (device_get_children(dev, &devlist, &numdevs) != 0) 4600 return; 4601 for (i = 0; i < numdevs; i++) { 4602 child = devlist[i]; 4603 if (device_get_state(child) != DS_NOTPRESENT) 4604 continue; 4605 dinfo = device_get_ivars(child); 4606 pci_print_verbose(dinfo); 4607 if (bootverbose) 4608 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4609 pci_cfg_restore(child, dinfo); 4610 if (device_probe_and_attach(child) != 0) 4611 pci_child_detached(dev, child); 4612 } 4613 free(devlist, M_TEMP); 4614 } 4615 4616 int 4617 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4618 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4619 { 4620 struct pci_devinfo *dinfo; 4621 struct msix_table_entry *mte; 4622 struct msix_vector *mv; 4623 uint64_t addr; 4624 uint32_t data; 4625 void *cookie; 4626 int error, rid; 4627 4628 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4629 arg, &cookie); 4630 if (error) 4631 return (error); 4632 4633 /* If this is not a direct child, just bail out. */ 4634 if (device_get_parent(child) != dev) { 4635 *cookiep = cookie; 4636 return(0); 4637 } 4638 4639 rid = rman_get_rid(irq); 4640 if (rid == 0) { 4641 /* Make sure that INTx is enabled */ 4642 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4643 } else { 4644 /* 4645 * Check to see if the interrupt is MSI or MSI-X. 4646 * Ask our parent to map the MSI and give 4647 * us the address and data register values. 4648 * If we fail for some reason, teardown the 4649 * interrupt handler. 4650 */ 4651 dinfo = device_get_ivars(child); 4652 if (dinfo->cfg.msi.msi_alloc > 0) { 4653 if (dinfo->cfg.msi.msi_addr == 0) { 4654 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4655 ("MSI has handlers, but vectors not mapped")); 4656 error = PCIB_MAP_MSI(device_get_parent(dev), 4657 child, rman_get_start(irq), &addr, &data); 4658 if (error) 4659 goto bad; 4660 dinfo->cfg.msi.msi_addr = addr; 4661 dinfo->cfg.msi.msi_data = data; 4662 } 4663 if (dinfo->cfg.msi.msi_handlers == 0) 4664 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4665 dinfo->cfg.msi.msi_data); 4666 dinfo->cfg.msi.msi_handlers++; 4667 } else { 4668 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4669 ("No MSI or MSI-X interrupts allocated")); 4670 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4671 ("MSI-X index too high")); 4672 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4673 KASSERT(mte->mte_vector != 0, ("no message vector")); 4674 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4675 KASSERT(mv->mv_irq == rman_get_start(irq), 4676 ("IRQ mismatch")); 4677 if (mv->mv_address == 0) { 4678 KASSERT(mte->mte_handlers == 0, 4679 ("MSI-X table entry has handlers, but vector not mapped")); 4680 error = PCIB_MAP_MSI(device_get_parent(dev), 4681 child, rman_get_start(irq), &addr, &data); 4682 if (error) 4683 goto bad; 4684 mv->mv_address = addr; 4685 mv->mv_data = data; 4686 } 4687 4688 /* 4689 * The MSIX table entry must be made valid by 4690 * incrementing the mte_handlers before 4691 * calling pci_enable_msix() and 4692 * pci_resume_msix(). Else the MSIX rewrite 4693 * table quirk will not work as expected. 4694 */ 4695 mte->mte_handlers++; 4696 if (mte->mte_handlers == 1) { 4697 pci_enable_msix(child, rid - 1, mv->mv_address, 4698 mv->mv_data); 4699 pci_unmask_msix(child, rid - 1); 4700 } 4701 } 4702 4703 /* 4704 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4705 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4706 * in which case we "enable" INTx so MSI/MSI-X actually works. 4707 */ 4708 if (!pci_has_quirk(pci_get_devid(child), 4709 PCI_QUIRK_MSI_INTX_BUG)) 4710 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4711 else 4712 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4713 bad: 4714 if (error) { 4715 (void)bus_generic_teardown_intr(dev, child, irq, 4716 cookie); 4717 return (error); 4718 } 4719 } 4720 *cookiep = cookie; 4721 return (0); 4722 } 4723 4724 int 4725 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4726 void *cookie) 4727 { 4728 struct msix_table_entry *mte; 4729 struct resource_list_entry *rle; 4730 struct pci_devinfo *dinfo; 4731 int error, rid; 4732 4733 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4734 return (EINVAL); 4735 4736 /* If this isn't a direct child, just bail out */ 4737 if (device_get_parent(child) != dev) 4738 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4739 4740 rid = rman_get_rid(irq); 4741 if (rid == 0) { 4742 /* Mask INTx */ 4743 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4744 } else { 4745 /* 4746 * Check to see if the interrupt is MSI or MSI-X. If so, 4747 * decrement the appropriate handlers count and mask the 4748 * MSI-X message, or disable MSI messages if the count 4749 * drops to 0. 4750 */ 4751 dinfo = device_get_ivars(child); 4752 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4753 if (rle->res != irq) 4754 return (EINVAL); 4755 if (dinfo->cfg.msi.msi_alloc > 0) { 4756 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4757 ("MSI-X index too high")); 4758 if (dinfo->cfg.msi.msi_handlers == 0) 4759 return (EINVAL); 4760 dinfo->cfg.msi.msi_handlers--; 4761 if (dinfo->cfg.msi.msi_handlers == 0) 4762 pci_disable_msi(child); 4763 } else { 4764 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4765 ("No MSI or MSI-X interrupts allocated")); 4766 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4767 ("MSI-X index too high")); 4768 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4769 if (mte->mte_handlers == 0) 4770 return (EINVAL); 4771 mte->mte_handlers--; 4772 if (mte->mte_handlers == 0) 4773 pci_mask_msix(child, rid - 1); 4774 } 4775 } 4776 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4777 if (rid > 0) 4778 KASSERT(error == 0, 4779 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4780 return (error); 4781 } 4782 4783 int 4784 pci_print_child(device_t dev, device_t child) 4785 { 4786 struct pci_devinfo *dinfo; 4787 struct resource_list *rl; 4788 int retval = 0; 4789 4790 dinfo = device_get_ivars(child); 4791 rl = &dinfo->resources; 4792 4793 retval += bus_print_child_header(dev, child); 4794 4795 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4796 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4797 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4798 if (device_get_flags(dev)) 4799 retval += printf(" flags %#x", device_get_flags(dev)); 4800 4801 retval += printf(" at device %d.%d", pci_get_slot(child), 4802 pci_get_function(child)); 4803 4804 retval += bus_print_child_domain(dev, child); 4805 retval += bus_print_child_footer(dev, child); 4806 4807 return (retval); 4808 } 4809 4810 static const struct 4811 { 4812 int class; 4813 int subclass; 4814 int report; /* 0 = bootverbose, 1 = always */ 4815 const char *desc; 4816 } pci_nomatch_tab[] = { 4817 {PCIC_OLD, -1, 1, "old"}, 4818 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4819 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4820 {PCIC_STORAGE, -1, 1, "mass storage"}, 4821 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4822 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4823 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4824 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4825 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4826 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4827 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4828 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4829 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4830 {PCIC_NETWORK, -1, 1, "network"}, 4831 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4832 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4833 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4834 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4835 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4836 {PCIC_DISPLAY, -1, 1, "display"}, 4837 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4838 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4839 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4840 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4841 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4842 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4843 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4844 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4845 {PCIC_MEMORY, -1, 1, "memory"}, 4846 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4847 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4848 {PCIC_BRIDGE, -1, 1, "bridge"}, 4849 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4850 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4851 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4852 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4853 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4854 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4855 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4856 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4857 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4858 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4859 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4860 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4861 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4862 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4863 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4864 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4865 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4866 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4867 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4868 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4869 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4870 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4871 {PCIC_INPUTDEV, -1, 1, "input device"}, 4872 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4873 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4874 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4875 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4876 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4877 {PCIC_DOCKING, -1, 1, "docking station"}, 4878 {PCIC_PROCESSOR, -1, 1, "processor"}, 4879 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4880 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4881 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4882 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4883 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4884 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4885 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4886 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4887 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4888 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4889 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4890 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4891 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4892 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4893 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4894 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4895 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4896 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4897 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4898 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4899 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4900 {PCIC_DASP, -1, 0, "dasp"}, 4901 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4902 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4903 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4904 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4905 {0, 0, 0, NULL} 4906 }; 4907 4908 void 4909 pci_probe_nomatch(device_t dev, device_t child) 4910 { 4911 int i, report; 4912 const char *cp, *scp; 4913 char *device; 4914 4915 /* 4916 * Look for a listing for this device in a loaded device database. 4917 */ 4918 report = 1; 4919 if ((device = pci_describe_device(child)) != NULL) { 4920 device_printf(dev, "<%s>", device); 4921 free(device, M_DEVBUF); 4922 } else { 4923 /* 4924 * Scan the class/subclass descriptions for a general 4925 * description. 4926 */ 4927 cp = "unknown"; 4928 scp = NULL; 4929 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4930 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4931 if (pci_nomatch_tab[i].subclass == -1) { 4932 cp = pci_nomatch_tab[i].desc; 4933 report = pci_nomatch_tab[i].report; 4934 } else if (pci_nomatch_tab[i].subclass == 4935 pci_get_subclass(child)) { 4936 scp = pci_nomatch_tab[i].desc; 4937 report = pci_nomatch_tab[i].report; 4938 } 4939 } 4940 } 4941 if (report || bootverbose) { 4942 device_printf(dev, "<%s%s%s>", 4943 cp ? cp : "", 4944 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4945 scp ? scp : ""); 4946 } 4947 } 4948 if (report || bootverbose) { 4949 printf(" at device %d.%d (no driver attached)\n", 4950 pci_get_slot(child), pci_get_function(child)); 4951 } 4952 pci_cfg_save(child, device_get_ivars(child), 1); 4953 } 4954 4955 void 4956 pci_child_detached(device_t dev, device_t child) 4957 { 4958 struct pci_devinfo *dinfo; 4959 struct resource_list *rl; 4960 4961 dinfo = device_get_ivars(child); 4962 rl = &dinfo->resources; 4963 4964 /* 4965 * Have to deallocate IRQs before releasing any MSI messages and 4966 * have to release MSI messages before deallocating any memory 4967 * BARs. 4968 */ 4969 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4970 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4971 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4972 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4973 (void)pci_release_msi(child); 4974 } 4975 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4976 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4977 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4978 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4979 #ifdef PCI_RES_BUS 4980 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4981 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4982 #endif 4983 4984 pci_cfg_save(child, dinfo, 1); 4985 } 4986 4987 /* 4988 * Parse the PCI device database, if loaded, and return a pointer to a 4989 * description of the device. 4990 * 4991 * The database is flat text formatted as follows: 4992 * 4993 * Any line not in a valid format is ignored. 4994 * Lines are terminated with newline '\n' characters. 4995 * 4996 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4997 * the vendor name. 4998 * 4999 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5000 * - devices cannot be listed without a corresponding VENDOR line. 5001 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5002 * another TAB, then the device name. 5003 */ 5004 5005 /* 5006 * Assuming (ptr) points to the beginning of a line in the database, 5007 * return the vendor or device and description of the next entry. 5008 * The value of (vendor) or (device) inappropriate for the entry type 5009 * is set to -1. Returns nonzero at the end of the database. 5010 * 5011 * Note that this is slightly unrobust in the face of corrupt data; 5012 * we attempt to safeguard against this by spamming the end of the 5013 * database with a newline when we initialise. 5014 */ 5015 static int 5016 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5017 { 5018 char *cp = *ptr; 5019 int left; 5020 5021 *device = -1; 5022 *vendor = -1; 5023 **desc = '\0'; 5024 for (;;) { 5025 left = pci_vendordata_size - (cp - pci_vendordata); 5026 if (left <= 0) { 5027 *ptr = cp; 5028 return(1); 5029 } 5030 5031 /* vendor entry? */ 5032 if (*cp != '\t' && 5033 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5034 break; 5035 /* device entry? */ 5036 if (*cp == '\t' && 5037 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5038 break; 5039 5040 /* skip to next line */ 5041 while (*cp != '\n' && left > 0) { 5042 cp++; 5043 left--; 5044 } 5045 if (*cp == '\n') { 5046 cp++; 5047 left--; 5048 } 5049 } 5050 /* skip to next line */ 5051 while (*cp != '\n' && left > 0) { 5052 cp++; 5053 left--; 5054 } 5055 if (*cp == '\n' && left > 0) 5056 cp++; 5057 *ptr = cp; 5058 return(0); 5059 } 5060 5061 static char * 5062 pci_describe_device(device_t dev) 5063 { 5064 int vendor, device; 5065 char *desc, *vp, *dp, *line; 5066 5067 desc = vp = dp = NULL; 5068 5069 /* 5070 * If we have no vendor data, we can't do anything. 5071 */ 5072 if (pci_vendordata == NULL) 5073 goto out; 5074 5075 /* 5076 * Scan the vendor data looking for this device 5077 */ 5078 line = pci_vendordata; 5079 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5080 goto out; 5081 for (;;) { 5082 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5083 goto out; 5084 if (vendor == pci_get_vendor(dev)) 5085 break; 5086 } 5087 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5088 goto out; 5089 for (;;) { 5090 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5091 *dp = 0; 5092 break; 5093 } 5094 if (vendor != -1) { 5095 *dp = 0; 5096 break; 5097 } 5098 if (device == pci_get_device(dev)) 5099 break; 5100 } 5101 if (dp[0] == '\0') 5102 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5103 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5104 NULL) 5105 sprintf(desc, "%s, %s", vp, dp); 5106 out: 5107 if (vp != NULL) 5108 free(vp, M_DEVBUF); 5109 if (dp != NULL) 5110 free(dp, M_DEVBUF); 5111 return(desc); 5112 } 5113 5114 int 5115 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5116 { 5117 struct pci_devinfo *dinfo; 5118 pcicfgregs *cfg; 5119 5120 dinfo = device_get_ivars(child); 5121 cfg = &dinfo->cfg; 5122 5123 switch (which) { 5124 case PCI_IVAR_ETHADDR: 5125 /* 5126 * The generic accessor doesn't deal with failure, so 5127 * we set the return value, then return an error. 5128 */ 5129 *((uint8_t **) result) = NULL; 5130 return (EINVAL); 5131 case PCI_IVAR_SUBVENDOR: 5132 *result = cfg->subvendor; 5133 break; 5134 case PCI_IVAR_SUBDEVICE: 5135 *result = cfg->subdevice; 5136 break; 5137 case PCI_IVAR_VENDOR: 5138 *result = cfg->vendor; 5139 break; 5140 case PCI_IVAR_DEVICE: 5141 *result = cfg->device; 5142 break; 5143 case PCI_IVAR_DEVID: 5144 *result = (cfg->device << 16) | cfg->vendor; 5145 break; 5146 case PCI_IVAR_CLASS: 5147 *result = cfg->baseclass; 5148 break; 5149 case PCI_IVAR_SUBCLASS: 5150 *result = cfg->subclass; 5151 break; 5152 case PCI_IVAR_PROGIF: 5153 *result = cfg->progif; 5154 break; 5155 case PCI_IVAR_REVID: 5156 *result = cfg->revid; 5157 break; 5158 case PCI_IVAR_INTPIN: 5159 *result = cfg->intpin; 5160 break; 5161 case PCI_IVAR_IRQ: 5162 *result = cfg->intline; 5163 break; 5164 case PCI_IVAR_DOMAIN: 5165 *result = cfg->domain; 5166 break; 5167 case PCI_IVAR_BUS: 5168 *result = cfg->bus; 5169 break; 5170 case PCI_IVAR_SLOT: 5171 *result = cfg->slot; 5172 break; 5173 case PCI_IVAR_FUNCTION: 5174 *result = cfg->func; 5175 break; 5176 case PCI_IVAR_CMDREG: 5177 *result = cfg->cmdreg; 5178 break; 5179 case PCI_IVAR_CACHELNSZ: 5180 *result = cfg->cachelnsz; 5181 break; 5182 case PCI_IVAR_MINGNT: 5183 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5184 *result = -1; 5185 return (EINVAL); 5186 } 5187 *result = cfg->mingnt; 5188 break; 5189 case PCI_IVAR_MAXLAT: 5190 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5191 *result = -1; 5192 return (EINVAL); 5193 } 5194 *result = cfg->maxlat; 5195 break; 5196 case PCI_IVAR_LATTIMER: 5197 *result = cfg->lattimer; 5198 break; 5199 default: 5200 return (ENOENT); 5201 } 5202 return (0); 5203 } 5204 5205 int 5206 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5207 { 5208 struct pci_devinfo *dinfo; 5209 5210 dinfo = device_get_ivars(child); 5211 5212 switch (which) { 5213 case PCI_IVAR_INTPIN: 5214 dinfo->cfg.intpin = value; 5215 return (0); 5216 case PCI_IVAR_ETHADDR: 5217 case PCI_IVAR_SUBVENDOR: 5218 case PCI_IVAR_SUBDEVICE: 5219 case PCI_IVAR_VENDOR: 5220 case PCI_IVAR_DEVICE: 5221 case PCI_IVAR_DEVID: 5222 case PCI_IVAR_CLASS: 5223 case PCI_IVAR_SUBCLASS: 5224 case PCI_IVAR_PROGIF: 5225 case PCI_IVAR_REVID: 5226 case PCI_IVAR_IRQ: 5227 case PCI_IVAR_DOMAIN: 5228 case PCI_IVAR_BUS: 5229 case PCI_IVAR_SLOT: 5230 case PCI_IVAR_FUNCTION: 5231 return (EINVAL); /* disallow for now */ 5232 5233 default: 5234 return (ENOENT); 5235 } 5236 } 5237 5238 #include "opt_ddb.h" 5239 #ifdef DDB 5240 #include <ddb/ddb.h> 5241 #include <sys/cons.h> 5242 5243 /* 5244 * List resources based on pci map registers, used for within ddb 5245 */ 5246 5247 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5248 { 5249 struct pci_devinfo *dinfo; 5250 struct devlist *devlist_head; 5251 struct pci_conf *p; 5252 const char *name; 5253 int i, error, none_count; 5254 5255 none_count = 0; 5256 /* get the head of the device queue */ 5257 devlist_head = &pci_devq; 5258 5259 /* 5260 * Go through the list of devices and print out devices 5261 */ 5262 for (error = 0, i = 0, 5263 dinfo = STAILQ_FIRST(devlist_head); 5264 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5265 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5266 5267 /* Populate pd_name and pd_unit */ 5268 name = NULL; 5269 if (dinfo->cfg.dev) 5270 name = device_get_name(dinfo->cfg.dev); 5271 5272 p = &dinfo->conf; 5273 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5274 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5275 (name && *name) ? name : "none", 5276 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5277 none_count++, 5278 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5279 p->pc_sel.pc_func, (p->pc_class << 16) | 5280 (p->pc_subclass << 8) | p->pc_progif, 5281 (p->pc_subdevice << 16) | p->pc_subvendor, 5282 (p->pc_device << 16) | p->pc_vendor, 5283 p->pc_revid, p->pc_hdr); 5284 } 5285 } 5286 #endif /* DDB */ 5287 5288 static struct resource * 5289 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5290 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5291 u_int flags) 5292 { 5293 struct pci_devinfo *dinfo = device_get_ivars(child); 5294 struct resource_list *rl = &dinfo->resources; 5295 struct resource *res; 5296 struct pci_map *pm; 5297 uint16_t cmd; 5298 pci_addr_t map, testval; 5299 int mapsize; 5300 5301 res = NULL; 5302 5303 /* If rid is managed by EA, ignore it */ 5304 if (pci_ea_is_enabled(child, *rid)) 5305 goto out; 5306 5307 pm = pci_find_bar(child, *rid); 5308 if (pm != NULL) { 5309 /* This is a BAR that we failed to allocate earlier. */ 5310 mapsize = pm->pm_size; 5311 map = pm->pm_value; 5312 } else { 5313 /* 5314 * Weed out the bogons, and figure out how large the 5315 * BAR/map is. BARs that read back 0 here are bogus 5316 * and unimplemented. Note: atapci in legacy mode are 5317 * special and handled elsewhere in the code. If you 5318 * have a atapci device in legacy mode and it fails 5319 * here, that other code is broken. 5320 */ 5321 pci_read_bar(child, *rid, &map, &testval, NULL); 5322 5323 /* 5324 * Determine the size of the BAR and ignore BARs with a size 5325 * of 0. Device ROM BARs use a different mask value. 5326 */ 5327 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5328 mapsize = pci_romsize(testval); 5329 else 5330 mapsize = pci_mapsize(testval); 5331 if (mapsize == 0) 5332 goto out; 5333 pm = pci_add_bar(child, *rid, map, mapsize); 5334 } 5335 5336 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5337 if (type != SYS_RES_MEMORY) { 5338 if (bootverbose) 5339 device_printf(dev, 5340 "child %s requested type %d for rid %#x," 5341 " but the BAR says it is an memio\n", 5342 device_get_nameunit(child), type, *rid); 5343 goto out; 5344 } 5345 } else { 5346 if (type != SYS_RES_IOPORT) { 5347 if (bootverbose) 5348 device_printf(dev, 5349 "child %s requested type %d for rid %#x," 5350 " but the BAR says it is an ioport\n", 5351 device_get_nameunit(child), type, *rid); 5352 goto out; 5353 } 5354 } 5355 5356 /* 5357 * For real BARs, we need to override the size that 5358 * the driver requests, because that's what the BAR 5359 * actually uses and we would otherwise have a 5360 * situation where we might allocate the excess to 5361 * another driver, which won't work. 5362 */ 5363 count = ((pci_addr_t)1 << mapsize) * num; 5364 if (RF_ALIGNMENT(flags) < mapsize) 5365 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5366 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5367 flags |= RF_PREFETCHABLE; 5368 5369 /* 5370 * Allocate enough resource, and then write back the 5371 * appropriate BAR for that resource. 5372 */ 5373 resource_list_add(rl, type, *rid, start, end, count); 5374 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5375 count, flags & ~RF_ACTIVE); 5376 if (res == NULL) { 5377 resource_list_delete(rl, type, *rid); 5378 device_printf(child, 5379 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5380 count, *rid, type, start, end); 5381 goto out; 5382 } 5383 if (bootverbose) 5384 device_printf(child, 5385 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5386 count, *rid, type, rman_get_start(res)); 5387 5388 /* Disable decoding via the CMD register before updating the BAR */ 5389 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5390 pci_write_config(child, PCIR_COMMAND, 5391 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5392 5393 map = rman_get_start(res); 5394 pci_write_bar(child, pm, map); 5395 5396 /* Restore the original value of the CMD register */ 5397 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5398 out: 5399 return (res); 5400 } 5401 5402 struct resource * 5403 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5404 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5405 u_int flags) 5406 { 5407 struct pci_devinfo *dinfo; 5408 struct resource_list *rl; 5409 struct resource_list_entry *rle; 5410 struct resource *res; 5411 pcicfgregs *cfg; 5412 5413 /* 5414 * Perform lazy resource allocation 5415 */ 5416 dinfo = device_get_ivars(child); 5417 rl = &dinfo->resources; 5418 cfg = &dinfo->cfg; 5419 switch (type) { 5420 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5421 case PCI_RES_BUS: 5422 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5423 flags)); 5424 #endif 5425 case SYS_RES_IRQ: 5426 /* 5427 * Can't alloc legacy interrupt once MSI messages have 5428 * been allocated. 5429 */ 5430 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5431 cfg->msix.msix_alloc > 0)) 5432 return (NULL); 5433 5434 /* 5435 * If the child device doesn't have an interrupt 5436 * routed and is deserving of an interrupt, try to 5437 * assign it one. 5438 */ 5439 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5440 (cfg->intpin != 0)) 5441 pci_assign_interrupt(dev, child, 0); 5442 break; 5443 case SYS_RES_IOPORT: 5444 case SYS_RES_MEMORY: 5445 #ifdef NEW_PCIB 5446 /* 5447 * PCI-PCI bridge I/O window resources are not BARs. 5448 * For those allocations just pass the request up the 5449 * tree. 5450 */ 5451 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5452 switch (*rid) { 5453 case PCIR_IOBASEL_1: 5454 case PCIR_MEMBASE_1: 5455 case PCIR_PMBASEL_1: 5456 /* 5457 * XXX: Should we bother creating a resource 5458 * list entry? 5459 */ 5460 return (bus_generic_alloc_resource(dev, child, 5461 type, rid, start, end, count, flags)); 5462 } 5463 } 5464 #endif 5465 /* Reserve resources for this BAR if needed. */ 5466 rle = resource_list_find(rl, type, *rid); 5467 if (rle == NULL) { 5468 res = pci_reserve_map(dev, child, type, rid, start, end, 5469 count, num, flags); 5470 if (res == NULL) 5471 return (NULL); 5472 } 5473 } 5474 return (resource_list_alloc(rl, dev, child, type, rid, 5475 start, end, count, flags)); 5476 } 5477 5478 struct resource * 5479 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5480 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5481 { 5482 #ifdef PCI_IOV 5483 struct pci_devinfo *dinfo; 5484 #endif 5485 5486 if (device_get_parent(child) != dev) 5487 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5488 type, rid, start, end, count, flags)); 5489 5490 #ifdef PCI_IOV 5491 dinfo = device_get_ivars(child); 5492 if (dinfo->cfg.flags & PCICFG_VF) { 5493 switch (type) { 5494 /* VFs can't have I/O BARs. */ 5495 case SYS_RES_IOPORT: 5496 return (NULL); 5497 case SYS_RES_MEMORY: 5498 return (pci_vf_alloc_mem_resource(dev, child, rid, 5499 start, end, count, flags)); 5500 } 5501 5502 /* Fall through for other types of resource allocations. */ 5503 } 5504 #endif 5505 5506 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5507 count, 1, flags)); 5508 } 5509 5510 int 5511 pci_release_resource(device_t dev, device_t child, int type, int rid, 5512 struct resource *r) 5513 { 5514 struct pci_devinfo *dinfo; 5515 struct resource_list *rl; 5516 pcicfgregs *cfg; 5517 5518 if (device_get_parent(child) != dev) 5519 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5520 type, rid, r)); 5521 5522 dinfo = device_get_ivars(child); 5523 cfg = &dinfo->cfg; 5524 5525 #ifdef PCI_IOV 5526 if (dinfo->cfg.flags & PCICFG_VF) { 5527 switch (type) { 5528 /* VFs can't have I/O BARs. */ 5529 case SYS_RES_IOPORT: 5530 return (EDOOFUS); 5531 case SYS_RES_MEMORY: 5532 return (pci_vf_release_mem_resource(dev, child, rid, 5533 r)); 5534 } 5535 5536 /* Fall through for other types of resource allocations. */ 5537 } 5538 #endif 5539 5540 #ifdef NEW_PCIB 5541 /* 5542 * PCI-PCI bridge I/O window resources are not BARs. For 5543 * those allocations just pass the request up the tree. 5544 */ 5545 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5546 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5547 switch (rid) { 5548 case PCIR_IOBASEL_1: 5549 case PCIR_MEMBASE_1: 5550 case PCIR_PMBASEL_1: 5551 return (bus_generic_release_resource(dev, child, type, 5552 rid, r)); 5553 } 5554 } 5555 #endif 5556 5557 rl = &dinfo->resources; 5558 return (resource_list_release(rl, dev, child, type, rid, r)); 5559 } 5560 5561 int 5562 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5563 struct resource *r) 5564 { 5565 struct pci_devinfo *dinfo; 5566 int error; 5567 5568 error = bus_generic_activate_resource(dev, child, type, rid, r); 5569 if (error) 5570 return (error); 5571 5572 /* Enable decoding in the command register when activating BARs. */ 5573 if (device_get_parent(child) == dev) { 5574 /* Device ROMs need their decoding explicitly enabled. */ 5575 dinfo = device_get_ivars(child); 5576 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5577 pci_write_bar(child, pci_find_bar(child, rid), 5578 rman_get_start(r) | PCIM_BIOS_ENABLE); 5579 switch (type) { 5580 case SYS_RES_IOPORT: 5581 case SYS_RES_MEMORY: 5582 error = PCI_ENABLE_IO(dev, child, type); 5583 break; 5584 } 5585 } 5586 return (error); 5587 } 5588 5589 int 5590 pci_deactivate_resource(device_t dev, device_t child, int type, 5591 int rid, struct resource *r) 5592 { 5593 struct pci_devinfo *dinfo; 5594 int error; 5595 5596 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5597 if (error) 5598 return (error); 5599 5600 /* Disable decoding for device ROMs. */ 5601 if (device_get_parent(child) == dev) { 5602 dinfo = device_get_ivars(child); 5603 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5604 pci_write_bar(child, pci_find_bar(child, rid), 5605 rman_get_start(r)); 5606 } 5607 return (0); 5608 } 5609 5610 void 5611 pci_child_deleted(device_t dev, device_t child) 5612 { 5613 struct resource_list_entry *rle; 5614 struct resource_list *rl; 5615 struct pci_devinfo *dinfo; 5616 5617 dinfo = device_get_ivars(child); 5618 rl = &dinfo->resources; 5619 5620 EVENTHANDLER_INVOKE(pci_delete_device, child); 5621 5622 /* Turn off access to resources we're about to free */ 5623 if (bus_child_present(child) != 0) { 5624 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5625 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5626 5627 pci_disable_busmaster(child); 5628 } 5629 5630 /* Free all allocated resources */ 5631 STAILQ_FOREACH(rle, rl, link) { 5632 if (rle->res) { 5633 if (rman_get_flags(rle->res) & RF_ACTIVE || 5634 resource_list_busy(rl, rle->type, rle->rid)) { 5635 pci_printf(&dinfo->cfg, 5636 "Resource still owned, oops. " 5637 "(type=%d, rid=%d, addr=%lx)\n", 5638 rle->type, rle->rid, 5639 rman_get_start(rle->res)); 5640 bus_release_resource(child, rle->type, rle->rid, 5641 rle->res); 5642 } 5643 resource_list_unreserve(rl, dev, child, rle->type, 5644 rle->rid); 5645 } 5646 } 5647 resource_list_free(rl); 5648 5649 pci_freecfg(dinfo); 5650 } 5651 5652 void 5653 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5654 { 5655 struct pci_devinfo *dinfo; 5656 struct resource_list *rl; 5657 struct resource_list_entry *rle; 5658 5659 if (device_get_parent(child) != dev) 5660 return; 5661 5662 dinfo = device_get_ivars(child); 5663 rl = &dinfo->resources; 5664 rle = resource_list_find(rl, type, rid); 5665 if (rle == NULL) 5666 return; 5667 5668 if (rle->res) { 5669 if (rman_get_flags(rle->res) & RF_ACTIVE || 5670 resource_list_busy(rl, type, rid)) { 5671 device_printf(dev, "delete_resource: " 5672 "Resource still owned by child, oops. " 5673 "(type=%d, rid=%d, addr=%jx)\n", 5674 type, rid, rman_get_start(rle->res)); 5675 return; 5676 } 5677 resource_list_unreserve(rl, dev, child, type, rid); 5678 } 5679 resource_list_delete(rl, type, rid); 5680 } 5681 5682 struct resource_list * 5683 pci_get_resource_list (device_t dev, device_t child) 5684 { 5685 struct pci_devinfo *dinfo = device_get_ivars(child); 5686 5687 return (&dinfo->resources); 5688 } 5689 5690 #ifdef ACPI_DMAR 5691 bus_dma_tag_t dmar_get_dma_tag(device_t dev, device_t child); 5692 bus_dma_tag_t 5693 pci_get_dma_tag(device_t bus, device_t dev) 5694 { 5695 bus_dma_tag_t tag; 5696 struct pci_softc *sc; 5697 5698 if (device_get_parent(dev) == bus) { 5699 /* try dmar and return if it works */ 5700 tag = dmar_get_dma_tag(bus, dev); 5701 } else 5702 tag = NULL; 5703 if (tag == NULL) { 5704 sc = device_get_softc(bus); 5705 tag = sc->sc_dma_tag; 5706 } 5707 return (tag); 5708 } 5709 #else 5710 bus_dma_tag_t 5711 pci_get_dma_tag(device_t bus, device_t dev) 5712 { 5713 struct pci_softc *sc = device_get_softc(bus); 5714 5715 return (sc->sc_dma_tag); 5716 } 5717 #endif 5718 5719 uint32_t 5720 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5721 { 5722 struct pci_devinfo *dinfo = device_get_ivars(child); 5723 pcicfgregs *cfg = &dinfo->cfg; 5724 5725 #ifdef PCI_IOV 5726 /* 5727 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5728 * emulate them here. 5729 */ 5730 if (cfg->flags & PCICFG_VF) { 5731 if (reg == PCIR_VENDOR) { 5732 switch (width) { 5733 case 4: 5734 return (cfg->device << 16 | cfg->vendor); 5735 case 2: 5736 return (cfg->vendor); 5737 case 1: 5738 return (cfg->vendor & 0xff); 5739 default: 5740 return (0xffffffff); 5741 } 5742 } else if (reg == PCIR_DEVICE) { 5743 switch (width) { 5744 /* Note that an unaligned 4-byte read is an error. */ 5745 case 2: 5746 return (cfg->device); 5747 case 1: 5748 return (cfg->device & 0xff); 5749 default: 5750 return (0xffffffff); 5751 } 5752 } 5753 } 5754 #endif 5755 5756 return (PCIB_READ_CONFIG(device_get_parent(dev), 5757 cfg->bus, cfg->slot, cfg->func, reg, width)); 5758 } 5759 5760 void 5761 pci_write_config_method(device_t dev, device_t child, int reg, 5762 uint32_t val, int width) 5763 { 5764 struct pci_devinfo *dinfo = device_get_ivars(child); 5765 pcicfgregs *cfg = &dinfo->cfg; 5766 5767 PCIB_WRITE_CONFIG(device_get_parent(dev), 5768 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5769 } 5770 5771 int 5772 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5773 size_t buflen) 5774 { 5775 5776 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5777 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5778 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5779 return (0); 5780 } 5781 5782 int 5783 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5784 size_t buflen) 5785 { 5786 struct pci_devinfo *dinfo; 5787 pcicfgregs *cfg; 5788 5789 dinfo = device_get_ivars(child); 5790 cfg = &dinfo->cfg; 5791 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5792 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5793 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5794 cfg->progif); 5795 return (0); 5796 } 5797 5798 int 5799 pci_assign_interrupt_method(device_t dev, device_t child) 5800 { 5801 struct pci_devinfo *dinfo = device_get_ivars(child); 5802 pcicfgregs *cfg = &dinfo->cfg; 5803 5804 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5805 cfg->intpin)); 5806 } 5807 5808 static void 5809 pci_lookup(void *arg, const char *name, device_t *dev) 5810 { 5811 long val; 5812 char *end; 5813 int domain, bus, slot, func; 5814 5815 if (*dev != NULL) 5816 return; 5817 5818 /* 5819 * Accept pciconf-style selectors of either pciD:B:S:F or 5820 * pciB:S:F. In the latter case, the domain is assumed to 5821 * be zero. 5822 */ 5823 if (strncmp(name, "pci", 3) != 0) 5824 return; 5825 val = strtol(name + 3, &end, 10); 5826 if (val < 0 || val > INT_MAX || *end != ':') 5827 return; 5828 domain = val; 5829 val = strtol(end + 1, &end, 10); 5830 if (val < 0 || val > INT_MAX || *end != ':') 5831 return; 5832 bus = val; 5833 val = strtol(end + 1, &end, 10); 5834 if (val < 0 || val > INT_MAX) 5835 return; 5836 slot = val; 5837 if (*end == ':') { 5838 val = strtol(end + 1, &end, 10); 5839 if (val < 0 || val > INT_MAX || *end != '\0') 5840 return; 5841 func = val; 5842 } else if (*end == '\0') { 5843 func = slot; 5844 slot = bus; 5845 bus = domain; 5846 domain = 0; 5847 } else 5848 return; 5849 5850 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5851 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5852 return; 5853 5854 *dev = pci_find_dbsf(domain, bus, slot, func); 5855 } 5856 5857 static int 5858 pci_modevent(module_t mod, int what, void *arg) 5859 { 5860 static struct cdev *pci_cdev; 5861 static eventhandler_tag tag; 5862 5863 switch (what) { 5864 case MOD_LOAD: 5865 STAILQ_INIT(&pci_devq); 5866 pci_generation = 0; 5867 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5868 "pci"); 5869 pci_load_vendor_data(); 5870 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5871 1000); 5872 break; 5873 5874 case MOD_UNLOAD: 5875 if (tag != NULL) 5876 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5877 destroy_dev(pci_cdev); 5878 break; 5879 } 5880 5881 return (0); 5882 } 5883 5884 static void 5885 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5886 { 5887 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5888 struct pcicfg_pcie *cfg; 5889 int version, pos; 5890 5891 cfg = &dinfo->cfg.pcie; 5892 pos = cfg->pcie_location; 5893 5894 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5895 5896 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5897 5898 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5899 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5900 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5901 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5902 5903 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5904 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5905 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5906 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5907 5908 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5909 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5910 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5911 5912 if (version > 1) { 5913 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5914 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5915 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5916 } 5917 #undef WREG 5918 } 5919 5920 static void 5921 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5922 { 5923 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5924 dinfo->cfg.pcix.pcix_command, 2); 5925 } 5926 5927 void 5928 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5929 { 5930 5931 /* 5932 * Restore the device to full power mode. We must do this 5933 * before we restore the registers because moving from D3 to 5934 * D0 will cause the chip's BARs and some other registers to 5935 * be reset to some unknown power on reset values. Cut down 5936 * the noise on boot by doing nothing if we are already in 5937 * state D0. 5938 */ 5939 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5940 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5941 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5942 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5943 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5944 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5945 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5946 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5947 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5948 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5949 case PCIM_HDRTYPE_NORMAL: 5950 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5951 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5952 break; 5953 case PCIM_HDRTYPE_BRIDGE: 5954 pci_write_config(dev, PCIR_SECLAT_1, 5955 dinfo->cfg.bridge.br_seclat, 1); 5956 pci_write_config(dev, PCIR_SUBBUS_1, 5957 dinfo->cfg.bridge.br_subbus, 1); 5958 pci_write_config(dev, PCIR_SECBUS_1, 5959 dinfo->cfg.bridge.br_secbus, 1); 5960 pci_write_config(dev, PCIR_PRIBUS_1, 5961 dinfo->cfg.bridge.br_pribus, 1); 5962 pci_write_config(dev, PCIR_BRIDGECTL_1, 5963 dinfo->cfg.bridge.br_control, 2); 5964 break; 5965 case PCIM_HDRTYPE_CARDBUS: 5966 pci_write_config(dev, PCIR_SECLAT_2, 5967 dinfo->cfg.bridge.br_seclat, 1); 5968 pci_write_config(dev, PCIR_SUBBUS_2, 5969 dinfo->cfg.bridge.br_subbus, 1); 5970 pci_write_config(dev, PCIR_SECBUS_2, 5971 dinfo->cfg.bridge.br_secbus, 1); 5972 pci_write_config(dev, PCIR_PRIBUS_2, 5973 dinfo->cfg.bridge.br_pribus, 1); 5974 pci_write_config(dev, PCIR_BRIDGECTL_2, 5975 dinfo->cfg.bridge.br_control, 2); 5976 break; 5977 } 5978 pci_restore_bars(dev); 5979 5980 /* 5981 * Restore extended capabilities for PCI-Express and PCI-X 5982 */ 5983 if (dinfo->cfg.pcie.pcie_location != 0) 5984 pci_cfg_restore_pcie(dev, dinfo); 5985 if (dinfo->cfg.pcix.pcix_location != 0) 5986 pci_cfg_restore_pcix(dev, dinfo); 5987 5988 /* Restore MSI and MSI-X configurations if they are present. */ 5989 if (dinfo->cfg.msi.msi_location != 0) 5990 pci_resume_msi(dev); 5991 if (dinfo->cfg.msix.msix_location != 0) 5992 pci_resume_msix(dev); 5993 5994 #ifdef PCI_IOV 5995 if (dinfo->cfg.iov != NULL) 5996 pci_iov_cfg_restore(dev, dinfo); 5997 #endif 5998 } 5999 6000 static void 6001 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6002 { 6003 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6004 struct pcicfg_pcie *cfg; 6005 int version, pos; 6006 6007 cfg = &dinfo->cfg.pcie; 6008 pos = cfg->pcie_location; 6009 6010 cfg->pcie_flags = RREG(PCIER_FLAGS); 6011 6012 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6013 6014 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6015 6016 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6017 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6018 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6019 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6020 6021 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6022 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6023 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6024 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6025 6026 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6027 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6028 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6029 6030 if (version > 1) { 6031 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6032 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6033 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6034 } 6035 #undef RREG 6036 } 6037 6038 static void 6039 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6040 { 6041 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6042 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6043 } 6044 6045 void 6046 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6047 { 6048 uint32_t cls; 6049 int ps; 6050 6051 /* 6052 * Some drivers apparently write to these registers w/o updating our 6053 * cached copy. No harm happens if we update the copy, so do so here 6054 * so we can restore them. The COMMAND register is modified by the 6055 * bus w/o updating the cache. This should represent the normally 6056 * writable portion of the 'defined' part of type 0/1/2 headers. 6057 */ 6058 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6059 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6060 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6061 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6062 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6063 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6064 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6065 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6066 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6067 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6068 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6069 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6070 case PCIM_HDRTYPE_NORMAL: 6071 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6072 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6073 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6074 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6075 break; 6076 case PCIM_HDRTYPE_BRIDGE: 6077 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6078 PCIR_SECLAT_1, 1); 6079 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6080 PCIR_SUBBUS_1, 1); 6081 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6082 PCIR_SECBUS_1, 1); 6083 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6084 PCIR_PRIBUS_1, 1); 6085 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6086 PCIR_BRIDGECTL_1, 2); 6087 break; 6088 case PCIM_HDRTYPE_CARDBUS: 6089 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6090 PCIR_SECLAT_2, 1); 6091 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6092 PCIR_SUBBUS_2, 1); 6093 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6094 PCIR_SECBUS_2, 1); 6095 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6096 PCIR_PRIBUS_2, 1); 6097 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6098 PCIR_BRIDGECTL_2, 2); 6099 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6100 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6101 break; 6102 } 6103 6104 if (dinfo->cfg.pcie.pcie_location != 0) 6105 pci_cfg_save_pcie(dev, dinfo); 6106 6107 if (dinfo->cfg.pcix.pcix_location != 0) 6108 pci_cfg_save_pcix(dev, dinfo); 6109 6110 #ifdef PCI_IOV 6111 if (dinfo->cfg.iov != NULL) 6112 pci_iov_cfg_save(dev, dinfo); 6113 #endif 6114 6115 /* 6116 * don't set the state for display devices, base peripherals and 6117 * memory devices since bad things happen when they are powered down. 6118 * We should (a) have drivers that can easily detach and (b) use 6119 * generic drivers for these devices so that some device actually 6120 * attaches. We need to make sure that when we implement (a) we don't 6121 * power the device down on a reattach. 6122 */ 6123 cls = pci_get_class(dev); 6124 if (!setstate) 6125 return; 6126 switch (pci_do_power_nodriver) 6127 { 6128 case 0: /* NO powerdown at all */ 6129 return; 6130 case 1: /* Conservative about what to power down */ 6131 if (cls == PCIC_STORAGE) 6132 return; 6133 /*FALLTHROUGH*/ 6134 case 2: /* Aggressive about what to power down */ 6135 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6136 cls == PCIC_BASEPERIPH) 6137 return; 6138 /*FALLTHROUGH*/ 6139 case 3: /* Power down everything */ 6140 break; 6141 } 6142 /* 6143 * PCI spec says we can only go into D3 state from D0 state. 6144 * Transition from D[12] into D0 before going to D3 state. 6145 */ 6146 ps = pci_get_powerstate(dev); 6147 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6148 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6149 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6150 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6151 } 6152 6153 /* Wrapper APIs suitable for device driver use. */ 6154 void 6155 pci_save_state(device_t dev) 6156 { 6157 struct pci_devinfo *dinfo; 6158 6159 dinfo = device_get_ivars(dev); 6160 pci_cfg_save(dev, dinfo, 0); 6161 } 6162 6163 void 6164 pci_restore_state(device_t dev) 6165 { 6166 struct pci_devinfo *dinfo; 6167 6168 dinfo = device_get_ivars(dev); 6169 pci_cfg_restore(dev, dinfo); 6170 } 6171 6172 static int 6173 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6174 uintptr_t *id) 6175 { 6176 6177 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6178 } 6179 6180 /* Find the upstream port of a given PCI device in a root complex. */ 6181 device_t 6182 pci_find_pcie_root_port(device_t dev) 6183 { 6184 struct pci_devinfo *dinfo; 6185 devclass_t pci_class; 6186 device_t pcib, bus; 6187 6188 pci_class = devclass_find("pci"); 6189 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6190 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6191 6192 /* 6193 * Walk the bridge hierarchy until we find a PCI-e root 6194 * port or a non-PCI device. 6195 */ 6196 for (;;) { 6197 bus = device_get_parent(dev); 6198 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6199 device_get_nameunit(dev))); 6200 6201 pcib = device_get_parent(bus); 6202 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6203 device_get_nameunit(bus))); 6204 6205 /* 6206 * pcib's parent must be a PCI bus for this to be a 6207 * PCI-PCI bridge. 6208 */ 6209 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6210 return (NULL); 6211 6212 dinfo = device_get_ivars(pcib); 6213 if (dinfo->cfg.pcie.pcie_location != 0 && 6214 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6215 return (pcib); 6216 6217 dev = pcib; 6218 } 6219 } 6220 6221 /* 6222 * Wait for pending transactions to complete on a PCI-express function. 6223 * 6224 * The maximum delay is specified in milliseconds in max_delay. Note 6225 * that this function may sleep. 6226 * 6227 * Returns true if the function is idle and false if the timeout is 6228 * exceeded. If dev is not a PCI-express function, this returns true. 6229 */ 6230 bool 6231 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6232 { 6233 struct pci_devinfo *dinfo = device_get_ivars(dev); 6234 uint16_t sta; 6235 int cap; 6236 6237 cap = dinfo->cfg.pcie.pcie_location; 6238 if (cap == 0) 6239 return (true); 6240 6241 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6242 while (sta & PCIEM_STA_TRANSACTION_PND) { 6243 if (max_delay == 0) 6244 return (false); 6245 6246 /* Poll once every 100 milliseconds up to the timeout. */ 6247 if (max_delay > 100) { 6248 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6249 max_delay -= 100; 6250 } else { 6251 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6252 C_HARDCLOCK); 6253 max_delay = 0; 6254 } 6255 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6256 } 6257 6258 return (true); 6259 } 6260 6261 /* 6262 * Determine the maximum Completion Timeout in microseconds. 6263 * 6264 * For non-PCI-express functions this returns 0. 6265 */ 6266 int 6267 pcie_get_max_completion_timeout(device_t dev) 6268 { 6269 struct pci_devinfo *dinfo = device_get_ivars(dev); 6270 int cap; 6271 6272 cap = dinfo->cfg.pcie.pcie_location; 6273 if (cap == 0) 6274 return (0); 6275 6276 /* 6277 * Functions using the 1.x spec use the default timeout range of 6278 * 50 microseconds to 50 milliseconds. Functions that do not 6279 * support programmable timeouts also use this range. 6280 */ 6281 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6282 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6283 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6284 return (50 * 1000); 6285 6286 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6287 PCIEM_CTL2_COMP_TIMO_VAL) { 6288 case PCIEM_CTL2_COMP_TIMO_100US: 6289 return (100); 6290 case PCIEM_CTL2_COMP_TIMO_10MS: 6291 return (10 * 1000); 6292 case PCIEM_CTL2_COMP_TIMO_55MS: 6293 return (55 * 1000); 6294 case PCIEM_CTL2_COMP_TIMO_210MS: 6295 return (210 * 1000); 6296 case PCIEM_CTL2_COMP_TIMO_900MS: 6297 return (900 * 1000); 6298 case PCIEM_CTL2_COMP_TIMO_3500MS: 6299 return (3500 * 1000); 6300 case PCIEM_CTL2_COMP_TIMO_13S: 6301 return (13 * 1000 * 1000); 6302 case PCIEM_CTL2_COMP_TIMO_64S: 6303 return (64 * 1000 * 1000); 6304 default: 6305 return (50 * 1000); 6306 } 6307 } 6308 6309 /* 6310 * Perform a Function Level Reset (FLR) on a device. 6311 * 6312 * This function first waits for any pending transactions to complete 6313 * within the timeout specified by max_delay. If transactions are 6314 * still pending, the function will return false without attempting a 6315 * reset. 6316 * 6317 * If dev is not a PCI-express function or does not support FLR, this 6318 * function returns false. 6319 * 6320 * Note that no registers are saved or restored. The caller is 6321 * responsible for saving and restoring any registers including 6322 * PCI-standard registers via pci_save_state() and 6323 * pci_restore_state(). 6324 */ 6325 bool 6326 pcie_flr(device_t dev, u_int max_delay, bool force) 6327 { 6328 struct pci_devinfo *dinfo = device_get_ivars(dev); 6329 uint16_t cmd, ctl; 6330 int compl_delay; 6331 int cap; 6332 6333 cap = dinfo->cfg.pcie.pcie_location; 6334 if (cap == 0) 6335 return (false); 6336 6337 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6338 return (false); 6339 6340 /* 6341 * Disable busmastering to prevent generation of new 6342 * transactions while waiting for the device to go idle. If 6343 * the idle timeout fails, the command register is restored 6344 * which will re-enable busmastering. 6345 */ 6346 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6347 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6348 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6349 if (!force) { 6350 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6351 return (false); 6352 } 6353 pci_printf(&dinfo->cfg, 6354 "Resetting with transactions pending after %d ms\n", 6355 max_delay); 6356 6357 /* 6358 * Extend the post-FLR delay to cover the maximum 6359 * Completion Timeout delay of anything in flight 6360 * during the FLR delay. Enforce a minimum delay of 6361 * at least 10ms. 6362 */ 6363 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6364 if (compl_delay < 10) 6365 compl_delay = 10; 6366 } else 6367 compl_delay = 0; 6368 6369 /* Initiate the reset. */ 6370 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6371 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6372 PCIEM_CTL_INITIATE_FLR, 2); 6373 6374 /* Wait for 100ms. */ 6375 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6376 6377 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6378 PCIEM_STA_TRANSACTION_PND) 6379 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6380 return (true); 6381 } 6382 6383 /* 6384 * Attempt a power-management reset by cycling the device in/out of D3 6385 * state. PCI spec says we can only go into D3 state from D0 state. 6386 * Transition from D[12] into D0 before going to D3 state. 6387 */ 6388 int 6389 pci_power_reset(device_t dev) 6390 { 6391 int ps; 6392 6393 ps = pci_get_powerstate(dev); 6394 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6395 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6396 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6397 pci_set_powerstate(dev, ps); 6398 return (0); 6399 } 6400 6401 /* 6402 * Try link drop and retrain of the downstream port of upstream 6403 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6404 * cause Conventional Hot reset of the device in the slot. 6405 * Alternative, for PCIe, could be the secondary bus reset initiatied 6406 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6407 */ 6408 int 6409 pcie_link_reset(device_t port, int pcie_location) 6410 { 6411 uint16_t v; 6412 6413 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6414 v |= PCIEM_LINK_CTL_LINK_DIS; 6415 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6416 pause_sbt("pcier1", mstosbt(20), 0, 0); 6417 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6418 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6419 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6420 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6421 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6422 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6423 } 6424 6425 static int 6426 pci_reset_post(device_t dev, device_t child) 6427 { 6428 6429 if (dev == device_get_parent(child)) 6430 pci_restore_state(child); 6431 return (0); 6432 } 6433 6434 static int 6435 pci_reset_prepare(device_t dev, device_t child) 6436 { 6437 6438 if (dev == device_get_parent(child)) 6439 pci_save_state(child); 6440 return (0); 6441 } 6442 6443 static int 6444 pci_reset_child(device_t dev, device_t child, int flags) 6445 { 6446 int error; 6447 6448 if (dev == NULL || device_get_parent(child) != dev) 6449 return (0); 6450 if ((flags & DEVF_RESET_DETACH) != 0) { 6451 error = device_get_state(child) == DS_ATTACHED ? 6452 device_detach(child) : 0; 6453 } else { 6454 error = BUS_SUSPEND_CHILD(dev, child); 6455 } 6456 if (error == 0) { 6457 if (!pcie_flr(child, 1000, false)) { 6458 error = BUS_RESET_PREPARE(dev, child); 6459 if (error == 0) 6460 pci_power_reset(child); 6461 BUS_RESET_POST(dev, child); 6462 } 6463 if ((flags & DEVF_RESET_DETACH) != 0) 6464 device_probe_and_attach(child); 6465 else 6466 BUS_RESUME_CHILD(dev, child); 6467 } 6468 return (error); 6469 } 6470 6471 const struct pci_device_table * 6472 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6473 { 6474 bool match; 6475 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6476 6477 vendor = pci_get_vendor(child); 6478 device = pci_get_device(child); 6479 subvendor = pci_get_subvendor(child); 6480 subdevice = pci_get_subdevice(child); 6481 class = pci_get_class(child); 6482 subclass = pci_get_subclass(child); 6483 revid = pci_get_revid(child); 6484 while (nelt-- > 0) { 6485 match = true; 6486 if (id->match_flag_vendor) 6487 match &= vendor == id->vendor; 6488 if (id->match_flag_device) 6489 match &= device == id->device; 6490 if (id->match_flag_subvendor) 6491 match &= subvendor == id->subvendor; 6492 if (id->match_flag_subdevice) 6493 match &= subdevice == id->subdevice; 6494 if (id->match_flag_class) 6495 match &= class == id->class_id; 6496 if (id->match_flag_subclass) 6497 match &= subclass == id->subclass; 6498 if (id->match_flag_revid) 6499 match &= revid == id->revid; 6500 if (match) 6501 return (id); 6502 id++; 6503 } 6504 return (NULL); 6505 } 6506 6507 static void 6508 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6509 { 6510 const char *dev_name; 6511 device_t dev; 6512 6513 dev = dinfo->cfg.dev; 6514 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6515 dinfo->cfg.slot, dinfo->cfg.func); 6516 dev_name = device_get_name(dev); 6517 if (dev_name != NULL) 6518 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6519 } 6520 6521 void 6522 pci_print_faulted_dev(void) 6523 { 6524 struct pci_devinfo *dinfo; 6525 device_t dev; 6526 int aer, i; 6527 uint32_t r1, r2; 6528 uint16_t status; 6529 6530 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6531 dev = dinfo->cfg.dev; 6532 status = pci_read_config(dev, PCIR_STATUS, 2); 6533 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6534 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6535 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6536 if (status != 0) { 6537 pci_print_faulted_dev_name(dinfo); 6538 printf(" error 0x%04x\n", status); 6539 } 6540 if (dinfo->cfg.pcie.pcie_location != 0) { 6541 status = pci_read_config(dev, 6542 dinfo->cfg.pcie.pcie_location + 6543 PCIER_DEVICE_STA, 2); 6544 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6545 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6546 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6547 pci_print_faulted_dev_name(dinfo); 6548 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6549 pci_read_config(dev, 6550 dinfo->cfg.pcie.pcie_location + 6551 PCIER_DEVICE_CTL, 2), 6552 status); 6553 } 6554 } 6555 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6556 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6557 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6558 if (r1 != 0 || r2 != 0) { 6559 pci_print_faulted_dev_name(dinfo); 6560 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6561 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6562 r1, pci_read_config(dev, aer + 6563 PCIR_AER_UC_MASK, 4), 6564 pci_read_config(dev, aer + 6565 PCIR_AER_UC_SEVERITY, 4), 6566 r2, pci_read_config(dev, aer + 6567 PCIR_AER_COR_MASK, 4), 6568 pci_read_config(dev, aer + 6569 PCIR_AER_CAP_CONTROL, 4)); 6570 for (i = 0; i < 4; i++) { 6571 r1 = pci_read_config(dev, aer + 6572 PCIR_AER_HEADER_LOG + i * 4, 4); 6573 printf(" HL%d: 0x%08x\n", i, r1); 6574 } 6575 } 6576 } 6577 } 6578 } 6579 6580 #ifdef DDB 6581 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6582 { 6583 6584 pci_print_faulted_dev(); 6585 } 6586 6587 static void 6588 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6589 { 6590 device_t dev; 6591 int aer; 6592 uint32_t r; 6593 6594 dev = dinfo->cfg.dev; 6595 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6596 PCIER_DEVICE_STA, 2); 6597 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6598 PCIER_DEVICE_STA, r, 2); 6599 6600 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6601 return; 6602 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6603 if (r != 0) 6604 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6605 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6606 if (r != 0) 6607 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6608 } 6609 6610 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6611 { 6612 struct pci_devinfo *dinfo; 6613 device_t dev; 6614 uint16_t status, status1; 6615 6616 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6617 dev = dinfo->cfg.dev; 6618 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6619 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6620 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6621 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6622 if (status1 != 0) { 6623 status &= ~status1; 6624 pci_write_config(dev, PCIR_STATUS, status, 2); 6625 } 6626 if (dinfo->cfg.pcie.pcie_location != 0) 6627 db_clear_pcie_errors(dinfo); 6628 } 6629 } 6630 #endif 6631