1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #ifdef __HAVE_ACPI 64 #include <contrib/dev/acpica/acpi.h> 65 #include "acpi_if.h" 66 #else 67 #define ACPI_PWR_FOR_SLEEP(x, y, z) 68 #endif 69 70 static uint32_t pci_mapbase(unsigned mapreg); 71 static int pci_maptype(unsigned mapreg); 72 static int pci_mapsize(unsigned testval); 73 static int pci_maprange(unsigned mapreg); 74 static void pci_fixancient(pcicfgregs *cfg); 75 76 static int pci_porten(device_t pcib, int b, int s, int f); 77 static int pci_memen(device_t pcib, int b, int s, int f); 78 static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83 static int pci_probe(device_t dev); 84 static int pci_attach(device_t dev); 85 static void pci_load_vendor_data(void); 86 static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88 static char *pci_describe_device(device_t dev); 89 static int pci_modevent(module_t mod, int what, void *arg); 90 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93 static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 94 int reg); 95 #if 0 96 static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 97 int reg, uint32_t data); 98 #endif 99 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 100 101 static device_method_t pci_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, pci_probe), 104 DEVMETHOD(device_attach, pci_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, pci_suspend), 108 DEVMETHOD(device_resume, pci_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, pci_print_child), 112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 113 DEVMETHOD(bus_read_ivar, pci_read_ivar), 114 DEVMETHOD(bus_write_ivar, pci_write_ivar), 115 DEVMETHOD(bus_driver_added, pci_driver_added), 116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 118 119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 122 DEVMETHOD(bus_delete_resource, pci_delete_resource), 123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 135 DEVMETHOD(pci_enable_io, pci_enable_io_method), 136 DEVMETHOD(pci_disable_io, pci_disable_io_method), 137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 143 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 144 DEVMETHOD(pci_release_msi, pci_release_msi_method), 145 DEVMETHOD(pci_msi_count, pci_msi_count_method), 146 147 { 0, 0 } 148 }; 149 150 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 151 152 static devclass_t pci_devclass; 153 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 154 MODULE_VERSION(pci, 1); 155 156 static char *pci_vendordata; 157 static size_t pci_vendordata_size; 158 159 160 struct pci_quirk { 161 uint32_t devid; /* Vendor/device of the card */ 162 int type; 163 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 164 int arg1; 165 int arg2; 166 }; 167 168 struct pci_quirk pci_quirks[] = { 169 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 170 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 171 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 172 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 173 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 174 175 { 0 } 176 }; 177 178 /* map register information */ 179 #define PCI_MAPMEM 0x01 /* memory map */ 180 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 181 #define PCI_MAPPORT 0x04 /* port map */ 182 183 struct devlist pci_devq; 184 uint32_t pci_generation; 185 uint32_t pci_numdevs = 0; 186 187 /* sysctl vars */ 188 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 189 190 static int pci_enable_io_modes = 1; 191 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 192 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 193 &pci_enable_io_modes, 1, 194 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 195 enable these bits correctly. We'd like to do this all the time, but there\n\ 196 are some peripherals that this causes problems with."); 197 198 static int pci_do_power_nodriver = 0; 199 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 200 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 201 &pci_do_power_nodriver, 0, 202 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 203 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 204 agressively place devices into D3 state. 3 means put absolutely everything\n\ 205 in D3 state."); 206 207 static int pci_do_power_resume = 1; 208 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 209 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 210 &pci_do_power_resume, 1, 211 "Transition from D3 -> D0 on resume."); 212 213 static int pci_do_msi = 1; 214 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 215 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 216 "Enable support for MSI interrupts"); 217 218 static int pci_do_msix = 1; 219 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 220 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 221 "Enable support for MSI-X interrupts"); 222 223 /* Find a device_t by bus/slot/function */ 224 225 device_t 226 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 227 { 228 struct pci_devinfo *dinfo; 229 230 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 231 if ((dinfo->cfg.bus == bus) && 232 (dinfo->cfg.slot == slot) && 233 (dinfo->cfg.func == func)) { 234 return (dinfo->cfg.dev); 235 } 236 } 237 238 return (NULL); 239 } 240 241 /* Find a device_t by vendor/device ID */ 242 243 device_t 244 pci_find_device(uint16_t vendor, uint16_t device) 245 { 246 struct pci_devinfo *dinfo; 247 248 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 249 if ((dinfo->cfg.vendor == vendor) && 250 (dinfo->cfg.device == device)) { 251 return (dinfo->cfg.dev); 252 } 253 } 254 255 return (NULL); 256 } 257 258 /* return base address of memory or port map */ 259 260 static uint32_t 261 pci_mapbase(uint32_t mapreg) 262 { 263 int mask = 0x03; 264 if ((mapreg & 0x01) == 0) 265 mask = 0x0f; 266 return (mapreg & ~mask); 267 } 268 269 /* return map type of memory or port map */ 270 271 static int 272 pci_maptype(unsigned mapreg) 273 { 274 static uint8_t maptype[0x10] = { 275 PCI_MAPMEM, PCI_MAPPORT, 276 PCI_MAPMEM, 0, 277 PCI_MAPMEM, PCI_MAPPORT, 278 0, 0, 279 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 280 PCI_MAPMEM|PCI_MAPMEMP, 0, 281 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 282 0, 0, 283 }; 284 285 return maptype[mapreg & 0x0f]; 286 } 287 288 /* return log2 of map size decoded for memory or port map */ 289 290 static int 291 pci_mapsize(uint32_t testval) 292 { 293 int ln2size; 294 295 testval = pci_mapbase(testval); 296 ln2size = 0; 297 if (testval != 0) { 298 while ((testval & 1) == 0) 299 { 300 ln2size++; 301 testval >>= 1; 302 } 303 } 304 return (ln2size); 305 } 306 307 /* return log2 of address range supported by map register */ 308 309 static int 310 pci_maprange(unsigned mapreg) 311 { 312 int ln2range = 0; 313 switch (mapreg & 0x07) { 314 case 0x00: 315 case 0x01: 316 case 0x05: 317 ln2range = 32; 318 break; 319 case 0x02: 320 ln2range = 20; 321 break; 322 case 0x04: 323 ln2range = 64; 324 break; 325 } 326 return (ln2range); 327 } 328 329 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 330 331 static void 332 pci_fixancient(pcicfgregs *cfg) 333 { 334 if (cfg->hdrtype != 0) 335 return; 336 337 /* PCI to PCI bridges use header type 1 */ 338 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 339 cfg->hdrtype = 1; 340 } 341 342 /* extract header type specific config data */ 343 344 static void 345 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 346 { 347 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 348 switch (cfg->hdrtype) { 349 case 0: 350 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 351 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 352 cfg->nummaps = PCI_MAXMAPS_0; 353 break; 354 case 1: 355 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 356 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 357 cfg->nummaps = PCI_MAXMAPS_1; 358 break; 359 case 2: 360 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 361 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 362 cfg->nummaps = PCI_MAXMAPS_2; 363 break; 364 } 365 #undef REG 366 } 367 368 /* read configuration header into pcicfgregs structure */ 369 struct pci_devinfo * 370 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 371 { 372 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 373 pcicfgregs *cfg = NULL; 374 struct pci_devinfo *devlist_entry; 375 struct devlist *devlist_head; 376 377 devlist_head = &pci_devq; 378 379 devlist_entry = NULL; 380 381 if (REG(PCIR_DEVVENDOR, 4) != -1) { 382 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 383 if (devlist_entry == NULL) 384 return (NULL); 385 386 cfg = &devlist_entry->cfg; 387 388 cfg->bus = b; 389 cfg->slot = s; 390 cfg->func = f; 391 cfg->vendor = REG(PCIR_VENDOR, 2); 392 cfg->device = REG(PCIR_DEVICE, 2); 393 cfg->cmdreg = REG(PCIR_COMMAND, 2); 394 cfg->statreg = REG(PCIR_STATUS, 2); 395 cfg->baseclass = REG(PCIR_CLASS, 1); 396 cfg->subclass = REG(PCIR_SUBCLASS, 1); 397 cfg->progif = REG(PCIR_PROGIF, 1); 398 cfg->revid = REG(PCIR_REVID, 1); 399 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 400 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 401 cfg->lattimer = REG(PCIR_LATTIMER, 1); 402 cfg->intpin = REG(PCIR_INTPIN, 1); 403 cfg->intline = REG(PCIR_INTLINE, 1); 404 405 cfg->mingnt = REG(PCIR_MINGNT, 1); 406 cfg->maxlat = REG(PCIR_MAXLAT, 1); 407 408 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 409 cfg->hdrtype &= ~PCIM_MFDEV; 410 411 pci_fixancient(cfg); 412 pci_hdrtypedata(pcib, b, s, f, cfg); 413 414 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 415 pci_read_extcap(pcib, cfg); 416 417 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 418 419 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 420 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 421 devlist_entry->conf.pc_sel.pc_func = cfg->func; 422 devlist_entry->conf.pc_hdr = cfg->hdrtype; 423 424 devlist_entry->conf.pc_subvendor = cfg->subvendor; 425 devlist_entry->conf.pc_subdevice = cfg->subdevice; 426 devlist_entry->conf.pc_vendor = cfg->vendor; 427 devlist_entry->conf.pc_device = cfg->device; 428 429 devlist_entry->conf.pc_class = cfg->baseclass; 430 devlist_entry->conf.pc_subclass = cfg->subclass; 431 devlist_entry->conf.pc_progif = cfg->progif; 432 devlist_entry->conf.pc_revid = cfg->revid; 433 434 pci_numdevs++; 435 pci_generation++; 436 } 437 return (devlist_entry); 438 #undef REG 439 } 440 441 static void 442 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 443 { 444 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 445 uint32_t val; 446 int ptr, nextptr, ptrptr; 447 448 switch (cfg->hdrtype & PCIM_HDRTYPE) { 449 case 0: 450 ptrptr = PCIR_CAP_PTR; 451 break; 452 case 2: 453 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 454 break; 455 default: 456 return; /* no extended capabilities support */ 457 } 458 nextptr = REG(ptrptr, 1); /* sanity check? */ 459 460 /* 461 * Read capability entries. 462 */ 463 while (nextptr != 0) { 464 /* Sanity check */ 465 if (nextptr > 255) { 466 printf("illegal PCI extended capability offset %d\n", 467 nextptr); 468 return; 469 } 470 /* Find the next entry */ 471 ptr = nextptr; 472 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 473 474 /* Process this entry */ 475 switch (REG(ptr + PCICAP_ID, 1)) { 476 case PCIY_PMG: /* PCI power management */ 477 if (cfg->pp.pp_cap == 0) { 478 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 479 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 480 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 481 if ((nextptr - ptr) > PCIR_POWER_DATA) 482 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 483 } 484 break; 485 case PCIY_MSI: /* PCI MSI */ 486 cfg->msi.msi_location = ptr; 487 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 488 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 489 PCIM_MSICTRL_MMC_MASK)>>1); 490 break; 491 case PCIY_MSIX: /* PCI MSI-X */ 492 cfg->msix.msix_location = ptr; 493 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 494 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 495 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 496 val = REG(ptr + PCIR_MSIX_TABLE, 4); 497 cfg->msix.msix_table_bar = PCIR_BAR(val & 498 PCIM_MSIX_BIR_MASK); 499 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 500 val = REG(ptr + PCIR_MSIX_PBA, 4); 501 cfg->msix.msix_pba_bar = PCIR_BAR(val & 502 PCIM_MSIX_BIR_MASK); 503 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 504 break; 505 case PCIY_VPD: /* PCI Vital Product Data */ 506 cfg->vpd.vpd_reg = ptr; 507 pci_read_vpd(pcib, cfg); 508 break; 509 default: 510 break; 511 } 512 } 513 /* REG use carry through to next functions */ 514 } 515 516 /* 517 * PCI Vital Product Data 518 */ 519 static uint32_t 520 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 521 { 522 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 523 524 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 525 526 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 527 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 528 DELAY(1); /* limit looping */ 529 530 return REG(cfg->vpd.vpd_reg + 4, 4); 531 } 532 533 #if 0 534 static void 535 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 536 { 537 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 538 539 WREG(cfg->vpd.vpd_reg + 4, data, 4); 540 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 541 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 542 DELAY(1); /* limit looping */ 543 544 return; 545 } 546 #endif 547 #undef WREG 548 549 struct vpd_readstate { 550 device_t pcib; 551 pcicfgregs *cfg; 552 uint32_t val; 553 int bytesinval; 554 int off; 555 uint8_t cksum; 556 }; 557 558 static uint8_t 559 vpd_nextbyte(struct vpd_readstate *vrs) 560 { 561 uint8_t byte; 562 563 if (vrs->bytesinval == 0) { 564 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 565 vrs->off)); 566 vrs->off += 4; 567 byte = vrs->val & 0xff; 568 vrs->bytesinval = 3; 569 } else { 570 vrs->val = vrs->val >> 8; 571 byte = vrs->val & 0xff; 572 vrs->bytesinval--; 573 } 574 575 vrs->cksum += byte; 576 return byte; 577 } 578 579 static void 580 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 581 { 582 struct vpd_readstate vrs; 583 int state; 584 int name; 585 int remain; 586 int end; 587 int i; 588 uint8_t byte; 589 int alloc, off; /* alloc/off for RO/W arrays */ 590 int cksumvalid; 591 int dflen; 592 593 /* init vpd reader */ 594 vrs.bytesinval = 0; 595 vrs.off = 0; 596 vrs.pcib = pcib; 597 vrs.cfg = cfg; 598 vrs.cksum = 0; 599 600 state = 0; 601 name = remain = i = 0; /* shut up stupid gcc */ 602 alloc = off = 0; /* shut up stupid gcc */ 603 dflen = 0; /* shut up stupid gcc */ 604 end = 0; 605 cksumvalid = -1; 606 for (; !end;) { 607 byte = vpd_nextbyte(&vrs); 608 #if 0 609 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 610 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 611 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 612 #endif 613 switch (state) { 614 case 0: /* item name */ 615 if (byte & 0x80) { 616 remain = vpd_nextbyte(&vrs); 617 remain |= vpd_nextbyte(&vrs) << 8; 618 if (remain > (0x7f*4 - vrs.off)) { 619 end = 1; 620 printf( 621 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 622 cfg->bus, cfg->slot, cfg->func, 623 remain); 624 } 625 name = byte & 0x7f; 626 } else { 627 remain = byte & 0x7; 628 name = (byte >> 3) & 0xf; 629 } 630 switch (name) { 631 case 0x2: /* String */ 632 cfg->vpd.vpd_ident = malloc(remain + 1, 633 M_DEVBUF, M_WAITOK); 634 i = 0; 635 state = 1; 636 break; 637 case 0xf: /* End */ 638 end = 1; 639 state = -1; 640 break; 641 case 0x10: /* VPD-R */ 642 alloc = 8; 643 off = 0; 644 cfg->vpd.vpd_ros = malloc(alloc * 645 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 646 M_WAITOK); 647 state = 2; 648 break; 649 case 0x11: /* VPD-W */ 650 alloc = 8; 651 off = 0; 652 cfg->vpd.vpd_w = malloc(alloc * 653 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 654 M_WAITOK); 655 state = 5; 656 break; 657 default: /* Invalid data, abort */ 658 end = 1; 659 cksumvalid = 0; 660 continue; 661 } 662 break; 663 664 case 1: /* Identifier String */ 665 cfg->vpd.vpd_ident[i++] = byte; 666 remain--; 667 if (remain == 0) { 668 cfg->vpd.vpd_ident[i] = '\0'; 669 state = 0; 670 } 671 break; 672 673 case 2: /* VPD-R Keyword Header */ 674 if (off == alloc) { 675 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 676 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 677 M_DEVBUF, M_WAITOK); 678 } 679 cfg->vpd.vpd_ros[off].keyword[0] = byte; 680 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 681 dflen = vpd_nextbyte(&vrs); 682 if (dflen == 0 && 683 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 684 2) == 0) { 685 /* 686 * if this happens, we can't trust the rest 687 * of the VPD. 688 */ 689 printf("pci%d:%d:%d: bad keyword length: %d\n", 690 cfg->bus, cfg->slot, cfg->func, dflen); 691 cksumvalid = 0; 692 end = 1; 693 break; 694 } else if (dflen == 0) { 695 cfg->vpd.vpd_ros[off].value = malloc(1 * 696 sizeof *cfg->vpd.vpd_ros[off].value, 697 M_DEVBUF, M_WAITOK); 698 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 699 } else 700 cfg->vpd.vpd_ros[off].value = malloc( 701 (dflen + 1) * 702 sizeof *cfg->vpd.vpd_ros[off].value, 703 M_DEVBUF, M_WAITOK); 704 remain -= 3; 705 i = 0; 706 /* keep in sync w/ state 3's transistions */ 707 if (dflen == 0 && remain == 0) 708 state = 0; 709 else if (dflen == 0) 710 state = 2; 711 else 712 state = 3; 713 break; 714 715 case 3: /* VPD-R Keyword Value */ 716 cfg->vpd.vpd_ros[off].value[i++] = byte; 717 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 718 "RV", 2) == 0 && cksumvalid == -1) { 719 if (vrs.cksum == 0) 720 cksumvalid = 1; 721 else { 722 printf( 723 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 724 cfg->bus, cfg->slot, cfg->func, 725 vrs.cksum); 726 cksumvalid = 0; 727 end = 1; 728 break; 729 } 730 } 731 dflen--; 732 remain--; 733 /* keep in sync w/ state 2's transistions */ 734 if (dflen == 0) 735 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 736 if (dflen == 0 && remain == 0) { 737 cfg->vpd.vpd_rocnt = off; 738 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 739 off * sizeof *cfg->vpd.vpd_ros, 740 M_DEVBUF, M_WAITOK); 741 state = 0; 742 } else if (dflen == 0) 743 state = 2; 744 break; 745 746 case 4: 747 remain--; 748 if (remain == 0) 749 state = 0; 750 break; 751 752 case 5: /* VPD-W Keyword Header */ 753 if (off == alloc) { 754 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 755 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 756 M_DEVBUF, M_WAITOK); 757 } 758 cfg->vpd.vpd_w[off].keyword[0] = byte; 759 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 760 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 761 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 762 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 763 sizeof *cfg->vpd.vpd_w[off].value, 764 M_DEVBUF, M_WAITOK); 765 remain -= 3; 766 i = 0; 767 /* keep in sync w/ state 6's transistions */ 768 if (dflen == 0 && remain == 0) 769 state = 0; 770 else if (dflen == 0) 771 state = 5; 772 else 773 state = 6; 774 break; 775 776 case 6: /* VPD-W Keyword Value */ 777 cfg->vpd.vpd_w[off].value[i++] = byte; 778 dflen--; 779 remain--; 780 /* keep in sync w/ state 5's transistions */ 781 if (dflen == 0) 782 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 783 if (dflen == 0 && remain == 0) { 784 cfg->vpd.vpd_wcnt = off; 785 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 786 off * sizeof *cfg->vpd.vpd_w, 787 M_DEVBUF, M_WAITOK); 788 state = 0; 789 } else if (dflen == 0) 790 state = 5; 791 break; 792 793 default: 794 printf("pci%d:%d:%d: invalid state: %d\n", 795 cfg->bus, cfg->slot, cfg->func, state); 796 end = 1; 797 break; 798 } 799 } 800 801 if (cksumvalid == 0) { 802 /* read-only data bad, clean up */ 803 for (; off; off--) 804 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 805 806 free(cfg->vpd.vpd_ros, M_DEVBUF); 807 cfg->vpd.vpd_ros = NULL; 808 } 809 #undef REG 810 } 811 812 int 813 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 814 { 815 struct pci_devinfo *dinfo = device_get_ivars(child); 816 pcicfgregs *cfg = &dinfo->cfg; 817 818 *identptr = cfg->vpd.vpd_ident; 819 820 if (*identptr == NULL) 821 return ENXIO; 822 823 return 0; 824 } 825 826 int 827 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 828 const char **vptr) 829 { 830 struct pci_devinfo *dinfo = device_get_ivars(child); 831 pcicfgregs *cfg = &dinfo->cfg; 832 int i; 833 834 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 835 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 836 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 837 *vptr = cfg->vpd.vpd_ros[i].value; 838 } 839 840 if (i != cfg->vpd.vpd_rocnt) 841 return 0; 842 843 *vptr = NULL; 844 return ENXIO; 845 } 846 847 /* 848 * Return the offset in configuration space of the requested extended 849 * capability entry or 0 if the specified capability was not found. 850 */ 851 int 852 pci_find_extcap_method(device_t dev, device_t child, int capability, 853 int *capreg) 854 { 855 struct pci_devinfo *dinfo = device_get_ivars(child); 856 pcicfgregs *cfg = &dinfo->cfg; 857 u_int32_t status; 858 u_int8_t ptr; 859 860 /* 861 * Check the CAP_LIST bit of the PCI status register first. 862 */ 863 status = pci_read_config(child, PCIR_STATUS, 2); 864 if (!(status & PCIM_STATUS_CAPPRESENT)) 865 return (ENXIO); 866 867 /* 868 * Determine the start pointer of the capabilities list. 869 */ 870 switch (cfg->hdrtype & PCIM_HDRTYPE) { 871 case 0: 872 ptr = PCIR_CAP_PTR; 873 break; 874 case 2: 875 ptr = PCIR_CAP_PTR_2; 876 break; 877 default: 878 /* XXX: panic? */ 879 return (ENXIO); /* no extended capabilities support */ 880 } 881 ptr = pci_read_config(child, ptr, 1); 882 883 /* 884 * Traverse the capabilities list. 885 */ 886 while (ptr != 0) { 887 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 888 if (capreg != NULL) 889 *capreg = ptr; 890 return (0); 891 } 892 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 893 } 894 895 return (ENOENT); 896 } 897 898 /* 899 * Support for MSI-X message interrupts. 900 */ 901 void 902 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 903 { 904 struct pci_devinfo *dinfo = device_get_ivars(dev); 905 pcicfgregs *cfg = &dinfo->cfg; 906 uint32_t offset; 907 908 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 909 offset = cfg->msix.msix_table_offset + index * 16; 910 bus_write_4(cfg->msix.msix_table_res, offset, address & 0xffffffff); 911 bus_write_4(cfg->msix.msix_table_res, offset + 4, address >> 32); 912 bus_write_4(cfg->msix.msix_table_res, offset + 8, data); 913 } 914 915 void 916 pci_mask_msix(device_t dev, u_int index) 917 { 918 struct pci_devinfo *dinfo = device_get_ivars(dev); 919 pcicfgregs *cfg = &dinfo->cfg; 920 uint32_t offset, val; 921 922 KASSERT(cfg->msix.msix_msgnum > index, ("bogus index")); 923 offset = cfg->msix.msix_table_offset + index * 16 + 12; 924 val = bus_read_4(cfg->msix.msix_table_res, offset); 925 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 926 val |= PCIM_MSIX_VCTRL_MASK; 927 bus_write_4(cfg->msix.msix_table_res, offset, val); 928 } 929 } 930 931 void 932 pci_unmask_msix(device_t dev, u_int index) 933 { 934 struct pci_devinfo *dinfo = device_get_ivars(dev); 935 pcicfgregs *cfg = &dinfo->cfg; 936 uint32_t offset, val; 937 938 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 939 offset = cfg->msix.msix_table_offset + index * 16 + 12; 940 val = bus_read_4(cfg->msix.msix_table_res, offset); 941 if (val & PCIM_MSIX_VCTRL_MASK) { 942 val &= ~PCIM_MSIX_VCTRL_MASK; 943 bus_write_4(cfg->msix.msix_table_res, offset, val); 944 } 945 } 946 947 int 948 pci_pending_msix(device_t dev, u_int index) 949 { 950 struct pci_devinfo *dinfo = device_get_ivars(dev); 951 pcicfgregs *cfg = &dinfo->cfg; 952 uint32_t offset, bit; 953 954 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 955 offset = cfg->msix.msix_pba_offset + (index / 4) * 4; 956 bit = 1 << index % 32; 957 return (bus_read_4(cfg->msix.msix_pba_res, offset) & bit); 958 } 959 960 static int 961 pci_alloc_msix(device_t dev, device_t child, int *count) 962 { 963 struct pci_devinfo *dinfo = device_get_ivars(child); 964 pcicfgregs *cfg = &dinfo->cfg; 965 struct resource_list_entry *rle; 966 int actual, error, i, irq, max; 967 968 /* MSI-X capability present? */ 969 if (cfg->msix.msix_location == 0 || !pci_do_msix) 970 return (ENODEV); 971 972 /* Make sure the appropriate BARs are mapped. */ 973 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 974 cfg->msix.msix_table_bar); 975 if (rle == NULL || rle->res == NULL || 976 !(rman_get_flags(rle->res) & RF_ACTIVE)) 977 return (ENXIO); 978 cfg->msix.msix_table_res = rle->res; 979 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 980 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 981 cfg->msix.msix_pba_bar); 982 if (rle == NULL || rle->res == NULL || 983 !(rman_get_flags(rle->res) & RF_ACTIVE)) 984 return (ENXIO); 985 } 986 cfg->msix.msix_pba_res = rle->res; 987 988 /* Already have allocated messages? */ 989 if (cfg->msix.msix_alloc != 0) 990 return (ENXIO); 991 992 max = min(*count, cfg->msix.msix_msgnum); 993 for (i = 0; i < max; i++) { 994 /* Allocate a message. */ 995 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, i, 996 &irq); 997 if (error) 998 break; 999 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1000 irq, 1); 1001 } 1002 actual = i; 1003 1004 /* Mask all vectors. */ 1005 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1006 pci_mask_msix(child, i); 1007 1008 /* Update control register to enable MSI-X. */ 1009 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1010 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1011 cfg->msix.msix_ctrl, 2); 1012 1013 /* Update counts of alloc'd messages. */ 1014 cfg->msix.msix_alloc = actual; 1015 *count = actual; 1016 return (0); 1017 } 1018 1019 static int 1020 pci_release_msix(device_t dev, device_t child) 1021 { 1022 struct pci_devinfo *dinfo = device_get_ivars(child); 1023 pcicfgregs *cfg = &dinfo->cfg; 1024 struct resource_list_entry *rle; 1025 int i; 1026 1027 /* Do we have any messages to release? */ 1028 if (cfg->msix.msix_alloc == 0) 1029 return (ENODEV); 1030 1031 /* Make sure none of the resources are allocated. */ 1032 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1033 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1034 KASSERT(rle != NULL, ("missing MSI resource")); 1035 if (rle->res != NULL) 1036 return (EBUSY); 1037 } 1038 1039 /* Update control register with to disable MSI-X. */ 1040 cfg->msix.msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1041 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1042 cfg->msix.msix_ctrl, 2); 1043 1044 /* Release the messages. */ 1045 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1046 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1047 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1048 rle->start); 1049 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1050 } 1051 1052 /* Update alloc count. */ 1053 cfg->msix.msix_alloc = 0; 1054 return (0); 1055 } 1056 1057 /* 1058 * Support for MSI message signalled interrupts. 1059 */ 1060 void 1061 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1062 { 1063 struct pci_devinfo *dinfo = device_get_ivars(dev); 1064 pcicfgregs *cfg = &dinfo->cfg; 1065 1066 /* Write data and address values. */ 1067 cfg->msi.msi_addr = address; 1068 cfg->msi.msi_data = data; 1069 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1070 address & 0xffffffff, 4); 1071 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1072 pci_write_config(dev, cfg->msi.msi_location + 1073 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1074 pci_write_config(dev, cfg->msi.msi_location + 1075 PCIR_MSI_DATA_64BIT, data, 2); 1076 } else 1077 pci_write_config(dev, cfg->msi.msi_location + 1078 PCIR_MSI_DATA, data, 2); 1079 1080 /* Enable MSI in the control register. */ 1081 cfg->msi.msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1082 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1083 cfg->msi.msi_ctrl, 2); 1084 } 1085 1086 /* 1087 * Restore MSI registers during resume. If MSI is enabled then 1088 * restore the data and address registers in addition to the control 1089 * register. 1090 */ 1091 static void 1092 pci_resume_msi(device_t dev) 1093 { 1094 struct pci_devinfo *dinfo = device_get_ivars(dev); 1095 pcicfgregs *cfg = &dinfo->cfg; 1096 uint64_t address; 1097 uint16_t data; 1098 1099 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1100 address = cfg->msi.msi_addr; 1101 data = cfg->msi.msi_data; 1102 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1103 address & 0xffffffff, 4); 1104 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1105 pci_write_config(dev, cfg->msi.msi_location + 1106 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1107 pci_write_config(dev, cfg->msi.msi_location + 1108 PCIR_MSI_DATA_64BIT, data, 2); 1109 } else 1110 pci_write_config(dev, cfg->msi.msi_location + 1111 PCIR_MSI_DATA, data, 2); 1112 } 1113 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1114 cfg->msi.msi_ctrl, 2); 1115 } 1116 1117 /* 1118 * Attempt to allocate *count MSI messages. The actual number allocated is 1119 * returned in *count. After this function returns, each message will be 1120 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1121 */ 1122 int 1123 pci_alloc_msi_method(device_t dev, device_t child, int *count) 1124 { 1125 struct pci_devinfo *dinfo = device_get_ivars(child); 1126 pcicfgregs *cfg = &dinfo->cfg; 1127 struct resource_list_entry *rle; 1128 int actual, error, i, irqs[32]; 1129 uint16_t ctrl; 1130 1131 /* Don't let count == 0 get us into trouble. */ 1132 if (*count == 0) 1133 return (EINVAL); 1134 1135 /* If rid 0 is allocated, then fail. */ 1136 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1137 if (rle != NULL && rle->res != NULL) 1138 return (ENXIO); 1139 1140 /* Try MSI-X first. */ 1141 error = pci_alloc_msix(dev, child, count); 1142 if (error != ENODEV) 1143 return (error); 1144 1145 /* MSI capability present? */ 1146 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1147 return (ENODEV); 1148 1149 /* Already have allocated messages? */ 1150 if (cfg->msi.msi_alloc != 0) 1151 return (ENXIO); 1152 1153 /* Don't ask for more than the device supports. */ 1154 actual = min(*count, cfg->msi.msi_msgnum); 1155 1156 /* Don't ask for more than 32 messages. */ 1157 actual = min(actual, 32); 1158 1159 /* MSI requires power of 2 number of messages. */ 1160 if (!powerof2(actual)) 1161 return (EINVAL); 1162 1163 for (;;) { 1164 /* Try to allocate N messages. */ 1165 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1166 cfg->msi.msi_msgnum, irqs); 1167 if (error == 0) 1168 break; 1169 if (actual == 1) 1170 return (error); 1171 1172 /* Try N / 2. */ 1173 actual >>= 1; 1174 } 1175 1176 /* 1177 * We now have N actual messages mapped onto SYS_RES_IRQ 1178 * resources in the irqs[] array, so add new resources 1179 * starting at rid 1. 1180 */ 1181 for (i = 0; i < actual; i++) 1182 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1183 irqs[i], irqs[i], 1); 1184 1185 /* Update control register with actual count and enable MSI. */ 1186 ctrl = cfg->msi.msi_ctrl; 1187 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1188 ctrl |= (ffs(actual) - 1) << 4; 1189 cfg->msi.msi_ctrl = ctrl; 1190 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1191 1192 /* Update counts of alloc'd messages. */ 1193 cfg->msi.msi_alloc = actual; 1194 *count = actual; 1195 return (0); 1196 } 1197 1198 /* Release the MSI messages associated with this device. */ 1199 int 1200 pci_release_msi_method(device_t dev, device_t child) 1201 { 1202 struct pci_devinfo *dinfo = device_get_ivars(child); 1203 pcicfgregs *cfg = &dinfo->cfg; 1204 struct resource_list_entry *rle; 1205 int error, i, irqs[32]; 1206 1207 /* Try MSI-X first. */ 1208 error = pci_release_msix(dev, child); 1209 if (error != ENODEV) 1210 return (error); 1211 1212 /* Do we have any messages to release? */ 1213 if (cfg->msi.msi_alloc == 0) 1214 return (ENODEV); 1215 KASSERT(cfg->msi.msi_alloc <= 32, ("more than 32 alloc'd messages")); 1216 1217 /* Make sure none of the resources are allocated. */ 1218 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1219 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1220 KASSERT(rle != NULL, ("missing MSI resource")); 1221 if (rle->res != NULL) 1222 return (EBUSY); 1223 irqs[i] = rle->start; 1224 } 1225 1226 /* Update control register with 0 count and disable MSI. */ 1227 cfg->msi.msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE); 1228 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 1229 cfg->msi.msi_ctrl, 2); 1230 1231 /* Release the messages. */ 1232 PCIB_RELEASE_MSI(device_get_parent(dev), child, cfg->msi.msi_alloc, 1233 irqs); 1234 for (i = 0; i < cfg->msi.msi_alloc; i++) 1235 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1236 1237 /* Update alloc count. */ 1238 cfg->msi.msi_alloc = 0; 1239 return (0); 1240 } 1241 1242 /* 1243 * Return the max supported MSI or MSI-X messages this device supports. 1244 * Basically, assuming the MD code can alloc messages, this function 1245 * should return the maximum value that pci_alloc_msi() can return. Thus, 1246 * it is subject to the tunables, etc. 1247 */ 1248 int 1249 pci_msi_count_method(device_t dev, device_t child) 1250 { 1251 struct pci_devinfo *dinfo = device_get_ivars(child); 1252 pcicfgregs *cfg = &dinfo->cfg; 1253 1254 if (pci_do_msix && cfg->msix.msix_location != 0) 1255 return (cfg->msix.msix_msgnum); 1256 if (pci_do_msi && cfg->msi.msi_location != 0) 1257 return (cfg->msi.msi_msgnum); 1258 return (0); 1259 } 1260 1261 /* free pcicfgregs structure and all depending data structures */ 1262 1263 int 1264 pci_freecfg(struct pci_devinfo *dinfo) 1265 { 1266 struct devlist *devlist_head; 1267 int i; 1268 1269 devlist_head = &pci_devq; 1270 1271 if (dinfo->cfg.vpd.vpd_reg) { 1272 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 1273 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 1274 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 1275 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 1276 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 1277 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 1278 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 1279 } 1280 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 1281 free(dinfo, M_DEVBUF); 1282 1283 /* increment the generation count */ 1284 pci_generation++; 1285 1286 /* we're losing one device */ 1287 pci_numdevs--; 1288 return (0); 1289 } 1290 1291 /* 1292 * PCI power manangement 1293 */ 1294 int 1295 pci_set_powerstate_method(device_t dev, device_t child, int state) 1296 { 1297 struct pci_devinfo *dinfo = device_get_ivars(child); 1298 pcicfgregs *cfg = &dinfo->cfg; 1299 uint16_t status; 1300 int result, oldstate, highest, delay; 1301 1302 if (cfg->pp.pp_cap == 0) 1303 return (EOPNOTSUPP); 1304 1305 /* 1306 * Optimize a no state change request away. While it would be OK to 1307 * write to the hardware in theory, some devices have shown odd 1308 * behavior when going from D3 -> D3. 1309 */ 1310 oldstate = pci_get_powerstate(child); 1311 if (oldstate == state) 1312 return (0); 1313 1314 /* 1315 * The PCI power management specification states that after a state 1316 * transition between PCI power states, system software must 1317 * guarantee a minimal delay before the function accesses the device. 1318 * Compute the worst case delay that we need to guarantee before we 1319 * access the device. Many devices will be responsive much more 1320 * quickly than this delay, but there are some that don't respond 1321 * instantly to state changes. Transitions to/from D3 state require 1322 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 1323 * is done below with DELAY rather than a sleeper function because 1324 * this function can be called from contexts where we cannot sleep. 1325 */ 1326 highest = (oldstate > state) ? oldstate : state; 1327 if (highest == PCI_POWERSTATE_D3) 1328 delay = 10000; 1329 else if (highest == PCI_POWERSTATE_D2) 1330 delay = 200; 1331 else 1332 delay = 0; 1333 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 1334 & ~PCIM_PSTAT_DMASK; 1335 result = 0; 1336 switch (state) { 1337 case PCI_POWERSTATE_D0: 1338 status |= PCIM_PSTAT_D0; 1339 break; 1340 case PCI_POWERSTATE_D1: 1341 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 1342 return (EOPNOTSUPP); 1343 status |= PCIM_PSTAT_D1; 1344 break; 1345 case PCI_POWERSTATE_D2: 1346 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 1347 return (EOPNOTSUPP); 1348 status |= PCIM_PSTAT_D2; 1349 break; 1350 case PCI_POWERSTATE_D3: 1351 status |= PCIM_PSTAT_D3; 1352 break; 1353 default: 1354 return (EINVAL); 1355 } 1356 1357 if (bootverbose) 1358 printf( 1359 "pci%d:%d:%d: Transition from D%d to D%d\n", 1360 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1361 oldstate, state); 1362 1363 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 1364 if (delay) 1365 DELAY(delay); 1366 return (0); 1367 } 1368 1369 int 1370 pci_get_powerstate_method(device_t dev, device_t child) 1371 { 1372 struct pci_devinfo *dinfo = device_get_ivars(child); 1373 pcicfgregs *cfg = &dinfo->cfg; 1374 uint16_t status; 1375 int result; 1376 1377 if (cfg->pp.pp_cap != 0) { 1378 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 1379 switch (status & PCIM_PSTAT_DMASK) { 1380 case PCIM_PSTAT_D0: 1381 result = PCI_POWERSTATE_D0; 1382 break; 1383 case PCIM_PSTAT_D1: 1384 result = PCI_POWERSTATE_D1; 1385 break; 1386 case PCIM_PSTAT_D2: 1387 result = PCI_POWERSTATE_D2; 1388 break; 1389 case PCIM_PSTAT_D3: 1390 result = PCI_POWERSTATE_D3; 1391 break; 1392 default: 1393 result = PCI_POWERSTATE_UNKNOWN; 1394 break; 1395 } 1396 } else { 1397 /* No support, device is always at D0 */ 1398 result = PCI_POWERSTATE_D0; 1399 } 1400 return (result); 1401 } 1402 1403 /* 1404 * Some convenience functions for PCI device drivers. 1405 */ 1406 1407 static __inline void 1408 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1409 { 1410 uint16_t command; 1411 1412 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1413 command |= bit; 1414 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1415 } 1416 1417 static __inline void 1418 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1419 { 1420 uint16_t command; 1421 1422 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1423 command &= ~bit; 1424 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1425 } 1426 1427 int 1428 pci_enable_busmaster_method(device_t dev, device_t child) 1429 { 1430 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1431 return (0); 1432 } 1433 1434 int 1435 pci_disable_busmaster_method(device_t dev, device_t child) 1436 { 1437 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1438 return (0); 1439 } 1440 1441 int 1442 pci_enable_io_method(device_t dev, device_t child, int space) 1443 { 1444 uint16_t command; 1445 uint16_t bit; 1446 char *error; 1447 1448 bit = 0; 1449 error = NULL; 1450 1451 switch(space) { 1452 case SYS_RES_IOPORT: 1453 bit = PCIM_CMD_PORTEN; 1454 error = "port"; 1455 break; 1456 case SYS_RES_MEMORY: 1457 bit = PCIM_CMD_MEMEN; 1458 error = "memory"; 1459 break; 1460 default: 1461 return (EINVAL); 1462 } 1463 pci_set_command_bit(dev, child, bit); 1464 /* Some devices seem to need a brief stall here, what do to? */ 1465 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1466 if (command & bit) 1467 return (0); 1468 device_printf(child, "failed to enable %s mapping!\n", error); 1469 return (ENXIO); 1470 } 1471 1472 int 1473 pci_disable_io_method(device_t dev, device_t child, int space) 1474 { 1475 uint16_t command; 1476 uint16_t bit; 1477 char *error; 1478 1479 bit = 0; 1480 error = NULL; 1481 1482 switch(space) { 1483 case SYS_RES_IOPORT: 1484 bit = PCIM_CMD_PORTEN; 1485 error = "port"; 1486 break; 1487 case SYS_RES_MEMORY: 1488 bit = PCIM_CMD_MEMEN; 1489 error = "memory"; 1490 break; 1491 default: 1492 return (EINVAL); 1493 } 1494 pci_clear_command_bit(dev, child, bit); 1495 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1496 if (command & bit) { 1497 device_printf(child, "failed to disable %s mapping!\n", error); 1498 return (ENXIO); 1499 } 1500 return (0); 1501 } 1502 1503 /* 1504 * New style pci driver. Parent device is either a pci-host-bridge or a 1505 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1506 */ 1507 1508 void 1509 pci_print_verbose(struct pci_devinfo *dinfo) 1510 { 1511 int i; 1512 1513 if (bootverbose) { 1514 pcicfgregs *cfg = &dinfo->cfg; 1515 1516 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1517 cfg->vendor, cfg->device, cfg->revid); 1518 printf("\tbus=%d, slot=%d, func=%d\n", 1519 cfg->bus, cfg->slot, cfg->func); 1520 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1521 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1522 cfg->mfdev); 1523 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1524 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1525 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1526 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1527 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1528 if (cfg->intpin > 0) 1529 printf("\tintpin=%c, irq=%d\n", 1530 cfg->intpin +'a' -1, cfg->intline); 1531 if (cfg->pp.pp_cap) { 1532 uint16_t status; 1533 1534 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1535 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1536 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1537 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1538 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1539 status & PCIM_PSTAT_DMASK); 1540 } 1541 if (cfg->vpd.vpd_reg) { 1542 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1543 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1544 struct vpd_readonly *vrop; 1545 vrop = &cfg->vpd.vpd_ros[i]; 1546 if (strncmp("CP", vrop->keyword, 2) == 0) 1547 printf("\tCP: id %d, BAR%d, off %#x\n", 1548 vrop->value[0], vrop->value[1], 1549 le16toh( 1550 *(uint16_t *)&vrop->value[2])); 1551 else if (strncmp("RV", vrop->keyword, 2) == 0) 1552 printf("\tRV: %#hhx\n", vrop->value[0]); 1553 else 1554 printf("\t%.2s: %s\n", vrop->keyword, 1555 vrop->value); 1556 } 1557 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1558 struct vpd_write *vwp; 1559 vwp = &cfg->vpd.vpd_w[i]; 1560 if (strncmp("RW", vwp->keyword, 2) != 0) 1561 printf("\t%.2s(%#x-%#x): %s\n", 1562 vwp->keyword, vwp->start, 1563 vwp->start + vwp->len, vwp->value); 1564 } 1565 } 1566 if (cfg->msi.msi_location) { 1567 int ctrl; 1568 1569 ctrl = cfg->msi.msi_ctrl; 1570 printf("\tMSI supports %d message%s%s%s\n", 1571 cfg->msi.msi_msgnum, 1572 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1573 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1574 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1575 } 1576 if (cfg->msix.msix_location) { 1577 printf("\tMSI-X supports %d message%s ", 1578 cfg->msix.msix_msgnum, 1579 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 1580 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 1581 printf("in map 0x%x\n", 1582 cfg->msix.msix_table_bar); 1583 else 1584 printf("in maps 0x%x and 0x%x\n", 1585 cfg->msix.msix_table_bar, 1586 cfg->msix.msix_pba_bar); 1587 } 1588 } 1589 } 1590 1591 static int 1592 pci_porten(device_t pcib, int b, int s, int f) 1593 { 1594 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1595 & PCIM_CMD_PORTEN) != 0; 1596 } 1597 1598 static int 1599 pci_memen(device_t pcib, int b, int s, int f) 1600 { 1601 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1602 & PCIM_CMD_MEMEN) != 0; 1603 } 1604 1605 /* 1606 * Add a resource based on a pci map register. Return 1 if the map 1607 * register is a 32bit map register or 2 if it is a 64bit register. 1608 */ 1609 static int 1610 pci_add_map(device_t pcib, device_t bus, device_t dev, 1611 int b, int s, int f, int reg, struct resource_list *rl, int force, 1612 int prefetch) 1613 { 1614 uint32_t map; 1615 pci_addr_t base; 1616 pci_addr_t start, end, count; 1617 uint8_t ln2size; 1618 uint8_t ln2range; 1619 uint32_t testval; 1620 uint16_t cmd; 1621 int type; 1622 int barlen; 1623 struct resource *res; 1624 1625 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1626 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1627 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1628 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1629 1630 if (pci_maptype(map) & PCI_MAPMEM) 1631 type = SYS_RES_MEMORY; 1632 else 1633 type = SYS_RES_IOPORT; 1634 ln2size = pci_mapsize(testval); 1635 ln2range = pci_maprange(testval); 1636 base = pci_mapbase(map); 1637 barlen = ln2range == 64 ? 2 : 1; 1638 1639 /* 1640 * For I/O registers, if bottom bit is set, and the next bit up 1641 * isn't clear, we know we have a BAR that doesn't conform to the 1642 * spec, so ignore it. Also, sanity check the size of the data 1643 * areas to the type of memory involved. Memory must be at least 1644 * 16 bytes in size, while I/O ranges must be at least 4. 1645 */ 1646 if ((testval & 0x1) == 0x1 && 1647 (testval & 0x2) != 0) 1648 return (barlen); 1649 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1650 (type == SYS_RES_IOPORT && ln2size < 2)) 1651 return (barlen); 1652 1653 if (ln2range == 64) 1654 /* Read the other half of a 64bit map register */ 1655 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1656 if (bootverbose) { 1657 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d", 1658 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size); 1659 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1660 printf(", port disabled\n"); 1661 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1662 printf(", memory disabled\n"); 1663 else 1664 printf(", enabled\n"); 1665 } 1666 1667 /* 1668 * If base is 0, then we have problems. It is best to ignore 1669 * such entries for the moment. These will be allocated later if 1670 * the driver specifically requests them. However, some 1671 * removable busses look better when all resources are allocated, 1672 * so allow '0' to be overriden. 1673 * 1674 * Similarly treat maps whose values is the same as the test value 1675 * read back. These maps have had all f's written to them by the 1676 * BIOS in an attempt to disable the resources. 1677 */ 1678 if (!force && (base == 0 || map == testval)) 1679 return (barlen); 1680 if ((u_long)base != base) { 1681 device_printf(bus, 1682 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg); 1683 return (barlen); 1684 } 1685 1686 /* 1687 * This code theoretically does the right thing, but has 1688 * undesirable side effects in some cases where peripherals 1689 * respond oddly to having these bits enabled. Let the user 1690 * be able to turn them off (since pci_enable_io_modes is 1 by 1691 * default). 1692 */ 1693 if (pci_enable_io_modes) { 1694 /* Turn on resources that have been left off by a lazy BIOS */ 1695 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1696 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1697 cmd |= PCIM_CMD_PORTEN; 1698 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1699 } 1700 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1701 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1702 cmd |= PCIM_CMD_MEMEN; 1703 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1704 } 1705 } else { 1706 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1707 return (barlen); 1708 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1709 return (barlen); 1710 } 1711 1712 count = 1 << ln2size; 1713 if (base == 0 || base == pci_mapbase(testval)) { 1714 start = 0; /* Let the parent deside */ 1715 end = ~0ULL; 1716 } else { 1717 start = base; 1718 end = base + (1 << ln2size) - 1; 1719 } 1720 resource_list_add(rl, type, reg, start, end, count); 1721 1722 /* 1723 * Not quite sure what to do on failure of allocating the resource 1724 * since I can postulate several right answers. 1725 */ 1726 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1727 prefetch ? RF_PREFETCHABLE : 0); 1728 if (res == NULL) 1729 return (barlen); 1730 start = rman_get_start(res); 1731 if ((u_long)start != start) { 1732 /* Wait a minute! this platform can't do this address. */ 1733 device_printf(bus, 1734 "pci%d.%d.%x bar %#x start %#jx, too many bits.", 1735 b, s, f, reg, (uintmax_t)start); 1736 resource_list_release(rl, bus, dev, type, reg, res); 1737 return (barlen); 1738 } 1739 pci_write_config(dev, reg, start, 4); 1740 if (ln2range == 64) 1741 pci_write_config(dev, reg + 4, start >> 32, 4); 1742 return (barlen); 1743 } 1744 1745 /* 1746 * For ATA devices we need to decide early what addressing mode to use. 1747 * Legacy demands that the primary and secondary ATA ports sits on the 1748 * same addresses that old ISA hardware did. This dictates that we use 1749 * those addresses and ignore the BAR's if we cannot set PCI native 1750 * addressing mode. 1751 */ 1752 static void 1753 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1754 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1755 { 1756 int rid, type, progif; 1757 #if 0 1758 /* if this device supports PCI native addressing use it */ 1759 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1760 if ((progif & 0x8a) == 0x8a) { 1761 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1762 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1763 printf("Trying ATA native PCI addressing mode\n"); 1764 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1765 } 1766 } 1767 #endif 1768 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1769 type = SYS_RES_IOPORT; 1770 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1771 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1772 prefetchmask & (1 << 0)); 1773 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1774 prefetchmask & (1 << 1)); 1775 } else { 1776 rid = PCIR_BAR(0); 1777 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1778 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1779 0); 1780 rid = PCIR_BAR(1); 1781 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1782 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1783 0); 1784 } 1785 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1786 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1787 prefetchmask & (1 << 2)); 1788 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1789 prefetchmask & (1 << 3)); 1790 } else { 1791 rid = PCIR_BAR(2); 1792 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1793 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1794 0); 1795 rid = PCIR_BAR(3); 1796 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1797 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1798 0); 1799 } 1800 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1801 prefetchmask & (1 << 4)); 1802 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1803 prefetchmask & (1 << 5)); 1804 } 1805 1806 static void 1807 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1808 { 1809 struct pci_devinfo *dinfo = device_get_ivars(dev); 1810 pcicfgregs *cfg = &dinfo->cfg; 1811 char tunable_name[64]; 1812 int irq; 1813 1814 /* Has to have an intpin to have an interrupt. */ 1815 if (cfg->intpin == 0) 1816 return; 1817 1818 /* Let the user override the IRQ with a tunable. */ 1819 irq = PCI_INVALID_IRQ; 1820 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1821 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1822 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1823 irq = PCI_INVALID_IRQ; 1824 1825 /* 1826 * If we didn't get an IRQ via the tunable, then we either use the 1827 * IRQ value in the intline register or we ask the bus to route an 1828 * interrupt for us. If force_route is true, then we only use the 1829 * value in the intline register if the bus was unable to assign an 1830 * IRQ. 1831 */ 1832 if (!PCI_INTERRUPT_VALID(irq)) { 1833 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1834 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1835 if (!PCI_INTERRUPT_VALID(irq)) 1836 irq = cfg->intline; 1837 } 1838 1839 /* If after all that we don't have an IRQ, just bail. */ 1840 if (!PCI_INTERRUPT_VALID(irq)) 1841 return; 1842 1843 /* Update the config register if it changed. */ 1844 if (irq != cfg->intline) { 1845 cfg->intline = irq; 1846 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1847 } 1848 1849 /* Add this IRQ as rid 0 interrupt resource. */ 1850 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1851 } 1852 1853 void 1854 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1855 { 1856 device_t pcib; 1857 struct pci_devinfo *dinfo = device_get_ivars(dev); 1858 pcicfgregs *cfg = &dinfo->cfg; 1859 struct resource_list *rl = &dinfo->resources; 1860 struct pci_quirk *q; 1861 int b, i, f, s; 1862 1863 pcib = device_get_parent(bus); 1864 1865 b = cfg->bus; 1866 s = cfg->slot; 1867 f = cfg->func; 1868 1869 /* ATA devices needs special map treatment */ 1870 if ((pci_get_class(dev) == PCIC_STORAGE) && 1871 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1872 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1873 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1874 else 1875 for (i = 0; i < cfg->nummaps;) 1876 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1877 rl, force, prefetchmask & (1 << i)); 1878 1879 /* 1880 * Add additional, quirked resources. 1881 */ 1882 for (q = &pci_quirks[0]; q->devid; q++) { 1883 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1884 && q->type == PCI_QUIRK_MAP_REG) 1885 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1886 force, 0); 1887 } 1888 1889 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1890 #ifdef __PCI_REROUTE_INTERRUPT 1891 /* 1892 * Try to re-route interrupts. Sometimes the BIOS or 1893 * firmware may leave bogus values in these registers. 1894 * If the re-route fails, then just stick with what we 1895 * have. 1896 */ 1897 pci_assign_interrupt(bus, dev, 1); 1898 #else 1899 pci_assign_interrupt(bus, dev, 0); 1900 #endif 1901 } 1902 } 1903 1904 void 1905 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1906 { 1907 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1908 device_t pcib = device_get_parent(dev); 1909 struct pci_devinfo *dinfo; 1910 int maxslots; 1911 int s, f, pcifunchigh; 1912 uint8_t hdrtype; 1913 1914 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1915 ("dinfo_size too small")); 1916 maxslots = PCIB_MAXSLOTS(pcib); 1917 for (s = 0; s <= maxslots; s++) { 1918 pcifunchigh = 0; 1919 f = 0; 1920 DELAY(1); 1921 hdrtype = REG(PCIR_HDRTYPE, 1); 1922 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1923 continue; 1924 if (hdrtype & PCIM_MFDEV) 1925 pcifunchigh = PCI_FUNCMAX; 1926 for (f = 0; f <= pcifunchigh; f++) { 1927 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1928 if (dinfo != NULL) { 1929 pci_add_child(dev, dinfo); 1930 } 1931 } 1932 } 1933 #undef REG 1934 } 1935 1936 void 1937 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1938 { 1939 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1940 device_set_ivars(dinfo->cfg.dev, dinfo); 1941 resource_list_init(&dinfo->resources); 1942 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1943 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1944 pci_print_verbose(dinfo); 1945 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1946 } 1947 1948 static int 1949 pci_probe(device_t dev) 1950 { 1951 1952 device_set_desc(dev, "PCI bus"); 1953 1954 /* Allow other subclasses to override this driver. */ 1955 return (-1000); 1956 } 1957 1958 static int 1959 pci_attach(device_t dev) 1960 { 1961 int busno; 1962 1963 /* 1964 * Since there can be multiple independantly numbered PCI 1965 * busses on systems with multiple PCI domains, we can't use 1966 * the unit number to decide which bus we are probing. We ask 1967 * the parent pcib what our bus number is. 1968 */ 1969 busno = pcib_get_bus(dev); 1970 if (bootverbose) 1971 device_printf(dev, "physical bus=%d\n", busno); 1972 1973 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1974 1975 return (bus_generic_attach(dev)); 1976 } 1977 1978 int 1979 pci_suspend(device_t dev) 1980 { 1981 int dstate, error, i, numdevs; 1982 device_t acpi_dev, child, *devlist; 1983 struct pci_devinfo *dinfo; 1984 1985 /* 1986 * Save the PCI configuration space for each child and set the 1987 * device in the appropriate power state for this sleep state. 1988 */ 1989 acpi_dev = NULL; 1990 if (pci_do_power_resume) 1991 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1992 device_get_children(dev, &devlist, &numdevs); 1993 for (i = 0; i < numdevs; i++) { 1994 child = devlist[i]; 1995 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1996 pci_cfg_save(child, dinfo, 0); 1997 } 1998 1999 /* Suspend devices before potentially powering them down. */ 2000 error = bus_generic_suspend(dev); 2001 if (error) { 2002 free(devlist, M_TEMP); 2003 return (error); 2004 } 2005 2006 /* 2007 * Always set the device to D3. If ACPI suggests a different 2008 * power state, use it instead. If ACPI is not present, the 2009 * firmware is responsible for managing device power. Skip 2010 * children who aren't attached since they are powered down 2011 * separately. Only manage type 0 devices for now. 2012 */ 2013 for (i = 0; acpi_dev && i < numdevs; i++) { 2014 child = devlist[i]; 2015 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2016 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2017 dstate = PCI_POWERSTATE_D3; 2018 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2019 pci_set_powerstate(child, dstate); 2020 } 2021 } 2022 free(devlist, M_TEMP); 2023 return (0); 2024 } 2025 2026 int 2027 pci_resume(device_t dev) 2028 { 2029 int i, numdevs; 2030 device_t acpi_dev, child, *devlist; 2031 struct pci_devinfo *dinfo; 2032 2033 /* 2034 * Set each child to D0 and restore its PCI configuration space. 2035 */ 2036 acpi_dev = NULL; 2037 if (pci_do_power_resume) 2038 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2039 device_get_children(dev, &devlist, &numdevs); 2040 for (i = 0; i < numdevs; i++) { 2041 /* 2042 * Notify ACPI we're going to D0 but ignore the result. If 2043 * ACPI is not present, the firmware is responsible for 2044 * managing device power. Only manage type 0 devices for now. 2045 */ 2046 child = devlist[i]; 2047 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2048 if (acpi_dev && device_is_attached(child) && 2049 dinfo->cfg.hdrtype == 0) { 2050 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2051 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2052 } 2053 2054 /* Now the device is powered up, restore its config space. */ 2055 pci_cfg_restore(child, dinfo); 2056 } 2057 free(devlist, M_TEMP); 2058 return (bus_generic_resume(dev)); 2059 } 2060 2061 static void 2062 pci_load_vendor_data(void) 2063 { 2064 caddr_t vendordata, info; 2065 2066 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 2067 info = preload_search_info(vendordata, MODINFO_ADDR); 2068 pci_vendordata = *(char **)info; 2069 info = preload_search_info(vendordata, MODINFO_SIZE); 2070 pci_vendordata_size = *(size_t *)info; 2071 /* terminate the database */ 2072 pci_vendordata[pci_vendordata_size] = '\n'; 2073 } 2074 } 2075 2076 void 2077 pci_driver_added(device_t dev, driver_t *driver) 2078 { 2079 int numdevs; 2080 device_t *devlist; 2081 device_t child; 2082 struct pci_devinfo *dinfo; 2083 int i; 2084 2085 if (bootverbose) 2086 device_printf(dev, "driver added\n"); 2087 DEVICE_IDENTIFY(driver, dev); 2088 device_get_children(dev, &devlist, &numdevs); 2089 for (i = 0; i < numdevs; i++) { 2090 child = devlist[i]; 2091 if (device_get_state(child) != DS_NOTPRESENT) 2092 continue; 2093 dinfo = device_get_ivars(child); 2094 pci_print_verbose(dinfo); 2095 if (bootverbose) 2096 printf("pci%d:%d:%d: reprobing on driver added\n", 2097 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 2098 pci_cfg_restore(child, dinfo); 2099 if (device_probe_and_attach(child) != 0) 2100 pci_cfg_save(child, dinfo, 1); 2101 } 2102 free(devlist, M_TEMP); 2103 } 2104 2105 int 2106 pci_print_child(device_t dev, device_t child) 2107 { 2108 struct pci_devinfo *dinfo; 2109 struct resource_list *rl; 2110 int retval = 0; 2111 2112 dinfo = device_get_ivars(child); 2113 rl = &dinfo->resources; 2114 2115 retval += bus_print_child_header(dev, child); 2116 2117 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 2118 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 2119 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 2120 if (device_get_flags(dev)) 2121 retval += printf(" flags %#x", device_get_flags(dev)); 2122 2123 retval += printf(" at device %d.%d", pci_get_slot(child), 2124 pci_get_function(child)); 2125 2126 retval += bus_print_child_footer(dev, child); 2127 2128 return (retval); 2129 } 2130 2131 static struct 2132 { 2133 int class; 2134 int subclass; 2135 char *desc; 2136 } pci_nomatch_tab[] = { 2137 {PCIC_OLD, -1, "old"}, 2138 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 2139 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 2140 {PCIC_STORAGE, -1, "mass storage"}, 2141 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 2142 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 2143 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 2144 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 2145 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 2146 {PCIC_NETWORK, -1, "network"}, 2147 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 2148 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 2149 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 2150 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 2151 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 2152 {PCIC_DISPLAY, -1, "display"}, 2153 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 2154 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 2155 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 2156 {PCIC_MULTIMEDIA, -1, "multimedia"}, 2157 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 2158 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 2159 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 2160 {PCIC_MEMORY, -1, "memory"}, 2161 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 2162 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 2163 {PCIC_BRIDGE, -1, "bridge"}, 2164 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 2165 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 2166 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 2167 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 2168 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 2169 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 2170 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 2171 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 2172 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 2173 {PCIC_SIMPLECOMM, -1, "simple comms"}, 2174 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 2175 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 2176 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 2177 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 2178 {PCIC_BASEPERIPH, -1, "base peripheral"}, 2179 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 2180 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 2181 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 2182 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 2183 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 2184 {PCIC_INPUTDEV, -1, "input device"}, 2185 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 2186 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 2187 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 2188 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 2189 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 2190 {PCIC_DOCKING, -1, "docking station"}, 2191 {PCIC_PROCESSOR, -1, "processor"}, 2192 {PCIC_SERIALBUS, -1, "serial bus"}, 2193 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 2194 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 2195 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 2196 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 2197 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 2198 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 2199 {PCIC_WIRELESS, -1, "wireless controller"}, 2200 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 2201 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 2202 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 2203 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 2204 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 2205 {PCIC_SATCOM, -1, "satellite communication"}, 2206 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 2207 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 2208 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 2209 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 2210 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 2211 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 2212 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 2213 {PCIC_DASP, -1, "dasp"}, 2214 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 2215 {0, 0, NULL} 2216 }; 2217 2218 void 2219 pci_probe_nomatch(device_t dev, device_t child) 2220 { 2221 int i; 2222 char *cp, *scp, *device; 2223 2224 /* 2225 * Look for a listing for this device in a loaded device database. 2226 */ 2227 if ((device = pci_describe_device(child)) != NULL) { 2228 device_printf(dev, "<%s>", device); 2229 free(device, M_DEVBUF); 2230 } else { 2231 /* 2232 * Scan the class/subclass descriptions for a general 2233 * description. 2234 */ 2235 cp = "unknown"; 2236 scp = NULL; 2237 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 2238 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 2239 if (pci_nomatch_tab[i].subclass == -1) { 2240 cp = pci_nomatch_tab[i].desc; 2241 } else if (pci_nomatch_tab[i].subclass == 2242 pci_get_subclass(child)) { 2243 scp = pci_nomatch_tab[i].desc; 2244 } 2245 } 2246 } 2247 device_printf(dev, "<%s%s%s>", 2248 cp ? cp : "", 2249 ((cp != NULL) && (scp != NULL)) ? ", " : "", 2250 scp ? scp : ""); 2251 } 2252 printf(" at device %d.%d (no driver attached)\n", 2253 pci_get_slot(child), pci_get_function(child)); 2254 if (pci_do_power_nodriver) 2255 pci_cfg_save(child, 2256 (struct pci_devinfo *) device_get_ivars(child), 1); 2257 return; 2258 } 2259 2260 /* 2261 * Parse the PCI device database, if loaded, and return a pointer to a 2262 * description of the device. 2263 * 2264 * The database is flat text formatted as follows: 2265 * 2266 * Any line not in a valid format is ignored. 2267 * Lines are terminated with newline '\n' characters. 2268 * 2269 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 2270 * the vendor name. 2271 * 2272 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 2273 * - devices cannot be listed without a corresponding VENDOR line. 2274 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 2275 * another TAB, then the device name. 2276 */ 2277 2278 /* 2279 * Assuming (ptr) points to the beginning of a line in the database, 2280 * return the vendor or device and description of the next entry. 2281 * The value of (vendor) or (device) inappropriate for the entry type 2282 * is set to -1. Returns nonzero at the end of the database. 2283 * 2284 * Note that this is slightly unrobust in the face of corrupt data; 2285 * we attempt to safeguard against this by spamming the end of the 2286 * database with a newline when we initialise. 2287 */ 2288 static int 2289 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 2290 { 2291 char *cp = *ptr; 2292 int left; 2293 2294 *device = -1; 2295 *vendor = -1; 2296 **desc = '\0'; 2297 for (;;) { 2298 left = pci_vendordata_size - (cp - pci_vendordata); 2299 if (left <= 0) { 2300 *ptr = cp; 2301 return(1); 2302 } 2303 2304 /* vendor entry? */ 2305 if (*cp != '\t' && 2306 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 2307 break; 2308 /* device entry? */ 2309 if (*cp == '\t' && 2310 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 2311 break; 2312 2313 /* skip to next line */ 2314 while (*cp != '\n' && left > 0) { 2315 cp++; 2316 left--; 2317 } 2318 if (*cp == '\n') { 2319 cp++; 2320 left--; 2321 } 2322 } 2323 /* skip to next line */ 2324 while (*cp != '\n' && left > 0) { 2325 cp++; 2326 left--; 2327 } 2328 if (*cp == '\n' && left > 0) 2329 cp++; 2330 *ptr = cp; 2331 return(0); 2332 } 2333 2334 static char * 2335 pci_describe_device(device_t dev) 2336 { 2337 int vendor, device; 2338 char *desc, *vp, *dp, *line; 2339 2340 desc = vp = dp = NULL; 2341 2342 /* 2343 * If we have no vendor data, we can't do anything. 2344 */ 2345 if (pci_vendordata == NULL) 2346 goto out; 2347 2348 /* 2349 * Scan the vendor data looking for this device 2350 */ 2351 line = pci_vendordata; 2352 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2353 goto out; 2354 for (;;) { 2355 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 2356 goto out; 2357 if (vendor == pci_get_vendor(dev)) 2358 break; 2359 } 2360 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2361 goto out; 2362 for (;;) { 2363 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 2364 *dp = 0; 2365 break; 2366 } 2367 if (vendor != -1) { 2368 *dp = 0; 2369 break; 2370 } 2371 if (device == pci_get_device(dev)) 2372 break; 2373 } 2374 if (dp[0] == '\0') 2375 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 2376 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 2377 NULL) 2378 sprintf(desc, "%s, %s", vp, dp); 2379 out: 2380 if (vp != NULL) 2381 free(vp, M_DEVBUF); 2382 if (dp != NULL) 2383 free(dp, M_DEVBUF); 2384 return(desc); 2385 } 2386 2387 int 2388 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 2389 { 2390 struct pci_devinfo *dinfo; 2391 pcicfgregs *cfg; 2392 2393 dinfo = device_get_ivars(child); 2394 cfg = &dinfo->cfg; 2395 2396 switch (which) { 2397 case PCI_IVAR_ETHADDR: 2398 /* 2399 * The generic accessor doesn't deal with failure, so 2400 * we set the return value, then return an error. 2401 */ 2402 *((uint8_t **) result) = NULL; 2403 return (EINVAL); 2404 case PCI_IVAR_SUBVENDOR: 2405 *result = cfg->subvendor; 2406 break; 2407 case PCI_IVAR_SUBDEVICE: 2408 *result = cfg->subdevice; 2409 break; 2410 case PCI_IVAR_VENDOR: 2411 *result = cfg->vendor; 2412 break; 2413 case PCI_IVAR_DEVICE: 2414 *result = cfg->device; 2415 break; 2416 case PCI_IVAR_DEVID: 2417 *result = (cfg->device << 16) | cfg->vendor; 2418 break; 2419 case PCI_IVAR_CLASS: 2420 *result = cfg->baseclass; 2421 break; 2422 case PCI_IVAR_SUBCLASS: 2423 *result = cfg->subclass; 2424 break; 2425 case PCI_IVAR_PROGIF: 2426 *result = cfg->progif; 2427 break; 2428 case PCI_IVAR_REVID: 2429 *result = cfg->revid; 2430 break; 2431 case PCI_IVAR_INTPIN: 2432 *result = cfg->intpin; 2433 break; 2434 case PCI_IVAR_IRQ: 2435 *result = cfg->intline; 2436 break; 2437 case PCI_IVAR_BUS: 2438 *result = cfg->bus; 2439 break; 2440 case PCI_IVAR_SLOT: 2441 *result = cfg->slot; 2442 break; 2443 case PCI_IVAR_FUNCTION: 2444 *result = cfg->func; 2445 break; 2446 case PCI_IVAR_CMDREG: 2447 *result = cfg->cmdreg; 2448 break; 2449 case PCI_IVAR_CACHELNSZ: 2450 *result = cfg->cachelnsz; 2451 break; 2452 case PCI_IVAR_MINGNT: 2453 *result = cfg->mingnt; 2454 break; 2455 case PCI_IVAR_MAXLAT: 2456 *result = cfg->maxlat; 2457 break; 2458 case PCI_IVAR_LATTIMER: 2459 *result = cfg->lattimer; 2460 break; 2461 default: 2462 return (ENOENT); 2463 } 2464 return (0); 2465 } 2466 2467 int 2468 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2469 { 2470 struct pci_devinfo *dinfo; 2471 2472 dinfo = device_get_ivars(child); 2473 2474 switch (which) { 2475 case PCI_IVAR_INTPIN: 2476 dinfo->cfg.intpin = value; 2477 return (0); 2478 case PCI_IVAR_ETHADDR: 2479 case PCI_IVAR_SUBVENDOR: 2480 case PCI_IVAR_SUBDEVICE: 2481 case PCI_IVAR_VENDOR: 2482 case PCI_IVAR_DEVICE: 2483 case PCI_IVAR_DEVID: 2484 case PCI_IVAR_CLASS: 2485 case PCI_IVAR_SUBCLASS: 2486 case PCI_IVAR_PROGIF: 2487 case PCI_IVAR_REVID: 2488 case PCI_IVAR_IRQ: 2489 case PCI_IVAR_BUS: 2490 case PCI_IVAR_SLOT: 2491 case PCI_IVAR_FUNCTION: 2492 return (EINVAL); /* disallow for now */ 2493 2494 default: 2495 return (ENOENT); 2496 } 2497 } 2498 2499 2500 #include "opt_ddb.h" 2501 #ifdef DDB 2502 #include <ddb/ddb.h> 2503 #include <sys/cons.h> 2504 2505 /* 2506 * List resources based on pci map registers, used for within ddb 2507 */ 2508 2509 DB_SHOW_COMMAND(pciregs, db_pci_dump) 2510 { 2511 struct pci_devinfo *dinfo; 2512 struct devlist *devlist_head; 2513 struct pci_conf *p; 2514 const char *name; 2515 int i, error, none_count; 2516 2517 none_count = 0; 2518 /* get the head of the device queue */ 2519 devlist_head = &pci_devq; 2520 2521 /* 2522 * Go through the list of devices and print out devices 2523 */ 2524 for (error = 0, i = 0, 2525 dinfo = STAILQ_FIRST(devlist_head); 2526 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2527 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2528 2529 /* Populate pd_name and pd_unit */ 2530 name = NULL; 2531 if (dinfo->cfg.dev) 2532 name = device_get_name(dinfo->cfg.dev); 2533 2534 p = &dinfo->conf; 2535 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2536 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2537 (name && *name) ? name : "none", 2538 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2539 none_count++, 2540 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2541 p->pc_sel.pc_func, (p->pc_class << 16) | 2542 (p->pc_subclass << 8) | p->pc_progif, 2543 (p->pc_subdevice << 16) | p->pc_subvendor, 2544 (p->pc_device << 16) | p->pc_vendor, 2545 p->pc_revid, p->pc_hdr); 2546 } 2547 } 2548 #endif /* DDB */ 2549 2550 static struct resource * 2551 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2552 u_long start, u_long end, u_long count, u_int flags) 2553 { 2554 struct pci_devinfo *dinfo = device_get_ivars(child); 2555 struct resource_list *rl = &dinfo->resources; 2556 struct resource_list_entry *rle; 2557 struct resource *res; 2558 pci_addr_t map, testval; 2559 int mapsize; 2560 2561 /* 2562 * Weed out the bogons, and figure out how large the BAR/map 2563 * is. Bars that read back 0 here are bogus and unimplemented. 2564 * Note: atapci in legacy mode are special and handled elsewhere 2565 * in the code. If you have a atapci device in legacy mode and 2566 * it fails here, that other code is broken. 2567 */ 2568 res = NULL; 2569 map = pci_read_config(child, *rid, 4); 2570 pci_write_config(child, *rid, 0xffffffff, 4); 2571 testval = pci_read_config(child, *rid, 4); 2572 if (pci_maprange(testval) == 64) 2573 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32; 2574 if (pci_mapbase(testval) == 0) 2575 goto out; 2576 if (pci_maptype(testval) & PCI_MAPMEM) { 2577 if (type != SYS_RES_MEMORY) { 2578 if (bootverbose) 2579 device_printf(dev, 2580 "child %s requested type %d for rid %#x," 2581 " but the BAR says it is an memio\n", 2582 device_get_nameunit(child), type, *rid); 2583 goto out; 2584 } 2585 } else { 2586 if (type != SYS_RES_IOPORT) { 2587 if (bootverbose) 2588 device_printf(dev, 2589 "child %s requested type %d for rid %#x," 2590 " but the BAR says it is an ioport\n", 2591 device_get_nameunit(child), type, *rid); 2592 goto out; 2593 } 2594 } 2595 /* 2596 * For real BARs, we need to override the size that 2597 * the driver requests, because that's what the BAR 2598 * actually uses and we would otherwise have a 2599 * situation where we might allocate the excess to 2600 * another driver, which won't work. 2601 */ 2602 mapsize = pci_mapsize(testval); 2603 count = 1UL << mapsize; 2604 if (RF_ALIGNMENT(flags) < mapsize) 2605 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2606 2607 /* 2608 * Allocate enough resource, and then write back the 2609 * appropriate bar for that resource. 2610 */ 2611 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2612 start, end, count, flags); 2613 if (res == NULL) { 2614 device_printf(child, 2615 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2616 count, *rid, type, start, end); 2617 goto out; 2618 } 2619 resource_list_add(rl, type, *rid, start, end, count); 2620 rle = resource_list_find(rl, type, *rid); 2621 if (rle == NULL) 2622 panic("pci_alloc_map: unexpectedly can't find resource."); 2623 rle->res = res; 2624 rle->start = rman_get_start(res); 2625 rle->end = rman_get_end(res); 2626 rle->count = count; 2627 if (bootverbose) 2628 device_printf(child, 2629 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2630 count, *rid, type, rman_get_start(res)); 2631 map = rman_get_start(res); 2632 out:; 2633 pci_write_config(child, *rid, map, 4); 2634 if (pci_maprange(testval) == 64) 2635 pci_write_config(child, *rid + 4, map >> 32, 4); 2636 return (res); 2637 } 2638 2639 2640 struct resource * 2641 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2642 u_long start, u_long end, u_long count, u_int flags) 2643 { 2644 struct pci_devinfo *dinfo = device_get_ivars(child); 2645 struct resource_list *rl = &dinfo->resources; 2646 struct resource_list_entry *rle; 2647 pcicfgregs *cfg = &dinfo->cfg; 2648 2649 /* 2650 * Perform lazy resource allocation 2651 */ 2652 if (device_get_parent(child) == dev) { 2653 switch (type) { 2654 case SYS_RES_IRQ: 2655 /* 2656 * Can't alloc legacy interrupt once MSI messages 2657 * have been allocated. 2658 */ 2659 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 2660 cfg->msix.msix_alloc > 0)) 2661 return (NULL); 2662 /* 2663 * If the child device doesn't have an 2664 * interrupt routed and is deserving of an 2665 * interrupt, try to assign it one. 2666 */ 2667 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 2668 (cfg->intpin != 0)) 2669 pci_assign_interrupt(dev, child, 0); 2670 break; 2671 case SYS_RES_IOPORT: 2672 case SYS_RES_MEMORY: 2673 if (*rid < PCIR_BAR(cfg->nummaps)) { 2674 /* 2675 * Enable the I/O mode. We should 2676 * also be assigning resources too 2677 * when none are present. The 2678 * resource_list_alloc kind of sorta does 2679 * this... 2680 */ 2681 if (PCI_ENABLE_IO(dev, child, type)) 2682 return (NULL); 2683 } 2684 rle = resource_list_find(rl, type, *rid); 2685 if (rle == NULL) 2686 return (pci_alloc_map(dev, child, type, rid, 2687 start, end, count, flags)); 2688 break; 2689 } 2690 /* 2691 * If we've already allocated the resource, then 2692 * return it now. But first we may need to activate 2693 * it, since we don't allocate the resource as active 2694 * above. Normally this would be done down in the 2695 * nexus, but since we short-circuit that path we have 2696 * to do its job here. Not sure if we should free the 2697 * resource if it fails to activate. 2698 */ 2699 rle = resource_list_find(rl, type, *rid); 2700 if (rle != NULL && rle->res != NULL) { 2701 if (bootverbose) 2702 device_printf(child, 2703 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2704 rman_get_size(rle->res), *rid, type, 2705 rman_get_start(rle->res)); 2706 if ((flags & RF_ACTIVE) && 2707 bus_generic_activate_resource(dev, child, type, 2708 *rid, rle->res) != 0) 2709 return NULL; 2710 return (rle->res); 2711 } 2712 } 2713 return (resource_list_alloc(rl, dev, child, type, rid, 2714 start, end, count, flags)); 2715 } 2716 2717 void 2718 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2719 { 2720 struct pci_devinfo *dinfo; 2721 struct resource_list *rl; 2722 struct resource_list_entry *rle; 2723 2724 if (device_get_parent(child) != dev) 2725 return; 2726 2727 dinfo = device_get_ivars(child); 2728 rl = &dinfo->resources; 2729 rle = resource_list_find(rl, type, rid); 2730 if (rle) { 2731 if (rle->res) { 2732 if (rman_get_device(rle->res) != dev || 2733 rman_get_flags(rle->res) & RF_ACTIVE) { 2734 device_printf(dev, "delete_resource: " 2735 "Resource still owned by child, oops. " 2736 "(type=%d, rid=%d, addr=%lx)\n", 2737 rle->type, rle->rid, 2738 rman_get_start(rle->res)); 2739 return; 2740 } 2741 bus_release_resource(dev, type, rid, rle->res); 2742 } 2743 resource_list_delete(rl, type, rid); 2744 } 2745 /* 2746 * Why do we turn off the PCI configuration BAR when we delete a 2747 * resource? -- imp 2748 */ 2749 pci_write_config(child, rid, 0, 4); 2750 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2751 } 2752 2753 struct resource_list * 2754 pci_get_resource_list (device_t dev, device_t child) 2755 { 2756 struct pci_devinfo *dinfo = device_get_ivars(child); 2757 2758 return (&dinfo->resources); 2759 } 2760 2761 uint32_t 2762 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2763 { 2764 struct pci_devinfo *dinfo = device_get_ivars(child); 2765 pcicfgregs *cfg = &dinfo->cfg; 2766 2767 return (PCIB_READ_CONFIG(device_get_parent(dev), 2768 cfg->bus, cfg->slot, cfg->func, reg, width)); 2769 } 2770 2771 void 2772 pci_write_config_method(device_t dev, device_t child, int reg, 2773 uint32_t val, int width) 2774 { 2775 struct pci_devinfo *dinfo = device_get_ivars(child); 2776 pcicfgregs *cfg = &dinfo->cfg; 2777 2778 PCIB_WRITE_CONFIG(device_get_parent(dev), 2779 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2780 } 2781 2782 int 2783 pci_child_location_str_method(device_t dev, device_t child, char *buf, 2784 size_t buflen) 2785 { 2786 2787 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2788 pci_get_function(child)); 2789 return (0); 2790 } 2791 2792 int 2793 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2794 size_t buflen) 2795 { 2796 struct pci_devinfo *dinfo; 2797 pcicfgregs *cfg; 2798 2799 dinfo = device_get_ivars(child); 2800 cfg = &dinfo->cfg; 2801 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2802 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2803 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2804 cfg->progif); 2805 return (0); 2806 } 2807 2808 int 2809 pci_assign_interrupt_method(device_t dev, device_t child) 2810 { 2811 struct pci_devinfo *dinfo = device_get_ivars(child); 2812 pcicfgregs *cfg = &dinfo->cfg; 2813 2814 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2815 cfg->intpin)); 2816 } 2817 2818 static int 2819 pci_modevent(module_t mod, int what, void *arg) 2820 { 2821 static struct cdev *pci_cdev; 2822 2823 switch (what) { 2824 case MOD_LOAD: 2825 STAILQ_INIT(&pci_devq); 2826 pci_generation = 0; 2827 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2828 "pci"); 2829 pci_load_vendor_data(); 2830 break; 2831 2832 case MOD_UNLOAD: 2833 destroy_dev(pci_cdev); 2834 break; 2835 } 2836 2837 return (0); 2838 } 2839 2840 void 2841 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2842 { 2843 int i; 2844 2845 /* 2846 * Only do header type 0 devices. Type 1 devices are bridges, 2847 * which we know need special treatment. Type 2 devices are 2848 * cardbus bridges which also require special treatment. 2849 * Other types are unknown, and we err on the side of safety 2850 * by ignoring them. 2851 */ 2852 if (dinfo->cfg.hdrtype != 0) 2853 return; 2854 2855 /* 2856 * Restore the device to full power mode. We must do this 2857 * before we restore the registers because moving from D3 to 2858 * D0 will cause the chip's BARs and some other registers to 2859 * be reset to some unknown power on reset values. Cut down 2860 * the noise on boot by doing nothing if we are already in 2861 * state D0. 2862 */ 2863 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2864 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2865 } 2866 for (i = 0; i < dinfo->cfg.nummaps; i++) 2867 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2868 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2869 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2870 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2871 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2872 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2873 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2874 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2875 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2876 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2877 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2878 2879 /* 2880 * Restore MSI configuration if it is present. If MSI is enabled, 2881 * then restore the data and addr registers. 2882 */ 2883 if (dinfo->cfg.msi.msi_location != 0) 2884 pci_resume_msi(dev); 2885 } 2886 2887 void 2888 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2889 { 2890 int i; 2891 uint32_t cls; 2892 int ps; 2893 2894 /* 2895 * Only do header type 0 devices. Type 1 devices are bridges, which 2896 * we know need special treatment. Type 2 devices are cardbus bridges 2897 * which also require special treatment. Other types are unknown, and 2898 * we err on the side of safety by ignoring them. Powering down 2899 * bridges should not be undertaken lightly. 2900 */ 2901 if (dinfo->cfg.hdrtype != 0) 2902 return; 2903 for (i = 0; i < dinfo->cfg.nummaps; i++) 2904 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2905 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2906 2907 /* 2908 * Some drivers apparently write to these registers w/o updating our 2909 * cached copy. No harm happens if we update the copy, so do so here 2910 * so we can restore them. The COMMAND register is modified by the 2911 * bus w/o updating the cache. This should represent the normally 2912 * writable portion of the 'defined' part of type 0 headers. In 2913 * theory we also need to save/restore the PCI capability structures 2914 * we know about, but apart from power we don't know any that are 2915 * writable. 2916 */ 2917 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2918 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2919 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2920 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2921 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2922 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2923 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2924 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2925 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2926 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2927 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2928 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2929 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2930 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2931 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2932 2933 /* 2934 * don't set the state for display devices, base peripherals and 2935 * memory devices since bad things happen when they are powered down. 2936 * We should (a) have drivers that can easily detach and (b) use 2937 * generic drivers for these devices so that some device actually 2938 * attaches. We need to make sure that when we implement (a) we don't 2939 * power the device down on a reattach. 2940 */ 2941 cls = pci_get_class(dev); 2942 if (!setstate) 2943 return; 2944 switch (pci_do_power_nodriver) 2945 { 2946 case 0: /* NO powerdown at all */ 2947 return; 2948 case 1: /* Conservative about what to power down */ 2949 if (cls == PCIC_STORAGE) 2950 return; 2951 /*FALLTHROUGH*/ 2952 case 2: /* Agressive about what to power down */ 2953 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2954 cls == PCIC_BASEPERIPH) 2955 return; 2956 /*FALLTHROUGH*/ 2957 case 3: /* Power down everything */ 2958 break; 2959 } 2960 /* 2961 * PCI spec says we can only go into D3 state from D0 state. 2962 * Transition from D[12] into D0 before going to D3 state. 2963 */ 2964 ps = pci_get_powerstate(dev); 2965 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2966 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2967 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2968 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2969 } 2970