1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 #include <vm/vm_extern.h> 56 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 #include <machine/stdarg.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include "pcib_if.h" 85 #include "pci_if.h" 86 87 #define PCIR_IS_BIOS(cfg, reg) \ 88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 90 91 static device_probe_t pci_probe; 92 93 static bus_reset_post_t pci_reset_post; 94 static bus_reset_prepare_t pci_reset_prepare; 95 static bus_reset_child_t pci_reset_child; 96 static bus_hint_device_unit_t pci_hint_device_unit; 97 static bus_remap_intr_t pci_remap_intr_method; 98 99 static pci_get_id_t pci_get_id_method; 100 101 static int pci_has_quirk(uint32_t devid, int quirk); 102 static pci_addr_t pci_mapbase(uint64_t mapreg); 103 static const char *pci_maptype(uint64_t mapreg); 104 static int pci_maprange(uint64_t mapreg); 105 static pci_addr_t pci_rombase(uint64_t mapreg); 106 static int pci_romsize(uint64_t testval); 107 static void pci_fixancient(pcicfgregs *cfg); 108 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 109 110 static int pci_porten(device_t dev); 111 static int pci_memen(device_t dev); 112 static void pci_assign_interrupt(device_t bus, device_t dev, 113 int force_route); 114 static int pci_add_map(device_t bus, device_t dev, int reg, 115 struct resource_list *rl, int force, int prefetch); 116 static void pci_load_vendor_data(void); 117 static int pci_describe_parse_line(char **ptr, int *vendor, 118 int *device, char **desc); 119 static char *pci_describe_device(device_t dev); 120 static int pci_modevent(module_t mod, int what, void *arg); 121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 122 pcicfgregs *cfg); 123 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 124 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 125 int reg, uint32_t *data); 126 #if 0 127 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t data); 129 #endif 130 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 131 static void pci_mask_msix(device_t dev, u_int index); 132 static void pci_unmask_msix(device_t dev, u_int index); 133 static int pci_msi_blacklisted(void); 134 static int pci_msix_blacklisted(void); 135 static void pci_resume_msi(device_t dev); 136 static void pci_resume_msix(device_t dev); 137 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 138 int b, int s, int f, uint16_t vid, uint16_t did); 139 140 static device_method_t pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, pci_probe), 143 DEVMETHOD(device_attach, pci_attach), 144 DEVMETHOD(device_detach, pci_detach), 145 DEVMETHOD(device_shutdown, bus_generic_shutdown), 146 DEVMETHOD(device_suspend, bus_generic_suspend), 147 DEVMETHOD(device_resume, pci_resume), 148 149 /* Bus interface */ 150 DEVMETHOD(bus_print_child, pci_print_child), 151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 152 DEVMETHOD(bus_read_ivar, pci_read_ivar), 153 DEVMETHOD(bus_write_ivar, pci_write_ivar), 154 DEVMETHOD(bus_driver_added, pci_driver_added), 155 DEVMETHOD(bus_setup_intr, pci_setup_intr), 156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 157 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 158 DEVMETHOD(bus_reset_post, pci_reset_post), 159 DEVMETHOD(bus_reset_child, pci_reset_child), 160 161 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 162 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 163 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 164 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 165 DEVMETHOD(bus_delete_resource, pci_delete_resource), 166 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 167 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 168 DEVMETHOD(bus_release_resource, pci_release_resource), 169 DEVMETHOD(bus_activate_resource, pci_activate_resource), 170 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 171 DEVMETHOD(bus_map_resource, pci_map_resource), 172 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 173 DEVMETHOD(bus_child_deleted, pci_child_deleted), 174 DEVMETHOD(bus_child_detached, pci_child_detached), 175 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 176 DEVMETHOD(bus_child_location, pci_child_location_method), 177 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 178 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 179 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 180 DEVMETHOD(bus_suspend_child, pci_suspend_child), 181 DEVMETHOD(bus_resume_child, pci_resume_child), 182 DEVMETHOD(bus_rescan, pci_rescan_method), 183 184 /* PCI interface */ 185 DEVMETHOD(pci_read_config, pci_read_config_method), 186 DEVMETHOD(pci_write_config, pci_write_config_method), 187 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 188 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 189 DEVMETHOD(pci_enable_io, pci_enable_io_method), 190 DEVMETHOD(pci_disable_io, pci_disable_io_method), 191 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 192 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 193 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 194 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 195 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 196 DEVMETHOD(pci_find_cap, pci_find_cap_method), 197 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 198 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 199 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 200 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 201 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 202 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 203 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 204 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 205 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 206 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 207 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 208 DEVMETHOD(pci_release_msi, pci_release_msi_method), 209 DEVMETHOD(pci_msi_count, pci_msi_count_method), 210 DEVMETHOD(pci_msix_count, pci_msix_count_method), 211 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 212 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 213 DEVMETHOD(pci_get_id, pci_get_id_method), 214 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 215 DEVMETHOD(pci_child_added, pci_child_added_method), 216 #ifdef PCI_IOV 217 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 218 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 219 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 220 #endif 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 226 227 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 int arg1; 244 int arg2; 245 }; 246 247 static const struct pci_quirk pci_quirks[] = { 248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 249 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 250 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 252 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 254 /* 255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 256 * or the CMIC-SL (AKA ServerWorks GC_LE). 257 */ 258 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 259 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 261 /* 262 * MSI doesn't work on earlier Intel chipsets including 263 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 264 */ 265 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 273 /* 274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 275 * bridge. 276 */ 277 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 278 279 /* 280 * Some virtualization environments emulate an older chipset 281 * but support MSI just fine. QEMU uses the Intel 82440. 282 */ 283 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 284 285 /* 286 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 287 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 288 * It prevents us from attaching hpet(4) when the bit is unset. 289 * Note this quirk only affects SB600 revision A13 and earlier. 290 * For SB600 A21 and later, firmware must set the bit to hide it. 291 * For SB700 and later, it is unused and hardcoded to zero. 292 */ 293 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 294 295 /* 296 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 297 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 298 * of the command register is set. 299 */ 300 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 306 /* 307 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 308 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 309 */ 310 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 311 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 312 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 313 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 314 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 315 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 316 317 /* 318 * HPE Gen 10 VGA has a memory range that can't be allocated in the 319 * expected place. 320 */ 321 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 322 { 0 } 323 }; 324 325 /* map register information */ 326 #define PCI_MAPMEM 0x01 /* memory map */ 327 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 328 #define PCI_MAPPORT 0x04 /* port map */ 329 330 struct devlist pci_devq; 331 uint32_t pci_generation; 332 uint32_t pci_numdevs = 0; 333 static int pcie_chipset, pcix_chipset; 334 335 /* sysctl vars */ 336 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 337 "PCI bus tuning parameters"); 338 339 static int pci_enable_io_modes = 1; 340 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 341 &pci_enable_io_modes, 1, 342 "Enable I/O and memory bits in the config register. Some BIOSes do not" 343 " enable these bits correctly. We'd like to do this all the time, but" 344 " there are some peripherals that this causes problems with."); 345 346 static int pci_do_realloc_bars = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 348 &pci_do_realloc_bars, 0, 349 "Attempt to allocate a new range for any BARs whose original " 350 "firmware-assigned ranges fail to allocate during the initial device scan."); 351 352 static int pci_do_power_nodriver = 0; 353 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 354 &pci_do_power_nodriver, 0, 355 "Place a function into D3 state when no driver attaches to it. 0 means" 356 " disable. 1 means conservatively place devices into D3 state. 2 means" 357 " aggressively place devices into D3 state. 3 means put absolutely" 358 " everything in D3 state."); 359 360 int pci_do_power_resume = 1; 361 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 362 &pci_do_power_resume, 1, 363 "Transition from D3 -> D0 on resume."); 364 365 int pci_do_power_suspend = 1; 366 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 367 &pci_do_power_suspend, 1, 368 "Transition from D0 -> D3 on suspend."); 369 370 static int pci_do_msi = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 372 "Enable support for MSI interrupts"); 373 374 static int pci_do_msix = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 376 "Enable support for MSI-X interrupts"); 377 378 static int pci_msix_rewrite_table = 0; 379 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 380 &pci_msix_rewrite_table, 0, 381 "Rewrite entire MSI-X table when updating MSI-X entries"); 382 383 static int pci_honor_msi_blacklist = 1; 384 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 386 387 #if defined(__i386__) || defined(__amd64__) 388 static int pci_usb_takeover = 1; 389 #else 390 static int pci_usb_takeover = 0; 391 #endif 392 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 393 &pci_usb_takeover, 1, 394 "Enable early takeover of USB controllers. Disable this if you depend on" 395 " BIOS emulation of USB devices, that is you use USB devices (like" 396 " keyboard or mouse) but do not load USB drivers"); 397 398 static int pci_clear_bars; 399 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 400 "Ignore firmware-assigned resources for BARs."); 401 402 static int pci_clear_buses; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 404 "Ignore firmware-assigned bus numbers."); 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 /* 411 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 412 * however enabling it breaks some arm64 firmware as it powers off devices. 413 */ 414 #if defined(__i386__) || defined(__amd64__) 415 int pci_enable_aspm = 1; 416 #else 417 int pci_enable_aspm = 0; 418 #endif 419 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 420 0, "Enable support for PCIe Active State Power Management"); 421 422 static int pci_clear_aer_on_attach = 0; 423 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 424 &pci_clear_aer_on_attach, 0, 425 "Clear port and device AER state on driver attach"); 426 427 static bool pci_enable_mps_tune = true; 428 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 429 &pci_enable_mps_tune, 1, 430 "Enable tuning of MPS(maximum payload size)." ); 431 432 static int 433 pci_has_quirk(uint32_t devid, int quirk) 434 { 435 const struct pci_quirk *q; 436 437 for (q = &pci_quirks[0]; q->devid; q++) { 438 if (q->devid == devid && q->type == quirk) 439 return (1); 440 } 441 return (0); 442 } 443 444 /* Find a device_t by bus/slot/function in domain 0 */ 445 446 device_t 447 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 448 { 449 450 return (pci_find_dbsf(0, bus, slot, func)); 451 } 452 453 /* Find a device_t by domain/bus/slot/function */ 454 455 device_t 456 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 457 { 458 struct pci_devinfo *dinfo = NULL; 459 460 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 461 if ((dinfo->cfg.domain == domain) && 462 (dinfo->cfg.bus == bus) && 463 (dinfo->cfg.slot == slot) && 464 (dinfo->cfg.func == func)) { 465 break; 466 } 467 } 468 469 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 470 } 471 472 /* Find a device_t by vendor/device ID */ 473 474 device_t 475 pci_find_device(uint16_t vendor, uint16_t device) 476 { 477 struct pci_devinfo *dinfo; 478 479 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 480 if ((dinfo->cfg.vendor == vendor) && 481 (dinfo->cfg.device == device)) { 482 return (dinfo->cfg.dev); 483 } 484 } 485 486 return (NULL); 487 } 488 489 device_t 490 pci_find_class(uint8_t class, uint8_t subclass) 491 { 492 struct pci_devinfo *dinfo; 493 494 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 495 if (dinfo->cfg.baseclass == class && 496 dinfo->cfg.subclass == subclass) { 497 return (dinfo->cfg.dev); 498 } 499 } 500 501 return (NULL); 502 } 503 504 device_t 505 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 506 { 507 struct pci_devinfo *dinfo; 508 bool found = false; 509 510 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 511 if (from != NULL && found == false) { 512 if (from != dinfo->cfg.dev) 513 continue; 514 found = true; 515 continue; 516 } 517 if (dinfo->cfg.baseclass == class && 518 dinfo->cfg.subclass == subclass) { 519 return (dinfo->cfg.dev); 520 } 521 } 522 523 return (NULL); 524 } 525 526 static int 527 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 528 { 529 va_list ap; 530 int retval; 531 532 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 533 cfg->func); 534 va_start(ap, fmt); 535 retval += vprintf(fmt, ap); 536 va_end(ap); 537 return (retval); 538 } 539 540 /* return base address of memory or port map */ 541 542 static pci_addr_t 543 pci_mapbase(uint64_t mapreg) 544 { 545 546 if (PCI_BAR_MEM(mapreg)) 547 return (mapreg & PCIM_BAR_MEM_BASE); 548 else 549 return (mapreg & PCIM_BAR_IO_BASE); 550 } 551 552 /* return map type of memory or port map */ 553 554 static const char * 555 pci_maptype(uint64_t mapreg) 556 { 557 558 if (PCI_BAR_IO(mapreg)) 559 return ("I/O Port"); 560 if (mapreg & PCIM_BAR_MEM_PREFETCH) 561 return ("Prefetchable Memory"); 562 return ("Memory"); 563 } 564 565 /* return log2 of map size decoded for memory or port map */ 566 567 int 568 pci_mapsize(uint64_t testval) 569 { 570 int ln2size; 571 572 testval = pci_mapbase(testval); 573 ln2size = 0; 574 if (testval != 0) { 575 while ((testval & 1) == 0) 576 { 577 ln2size++; 578 testval >>= 1; 579 } 580 } 581 return (ln2size); 582 } 583 584 /* return base address of device ROM */ 585 586 static pci_addr_t 587 pci_rombase(uint64_t mapreg) 588 { 589 590 return (mapreg & PCIM_BIOS_ADDR_MASK); 591 } 592 593 /* return log2 of map size decided for device ROM */ 594 595 static int 596 pci_romsize(uint64_t testval) 597 { 598 int ln2size; 599 600 testval = pci_rombase(testval); 601 ln2size = 0; 602 if (testval != 0) { 603 while ((testval & 1) == 0) 604 { 605 ln2size++; 606 testval >>= 1; 607 } 608 } 609 return (ln2size); 610 } 611 612 /* return log2 of address range supported by map register */ 613 614 static int 615 pci_maprange(uint64_t mapreg) 616 { 617 int ln2range = 0; 618 619 if (PCI_BAR_IO(mapreg)) 620 ln2range = 32; 621 else 622 switch (mapreg & PCIM_BAR_MEM_TYPE) { 623 case PCIM_BAR_MEM_32: 624 ln2range = 32; 625 break; 626 case PCIM_BAR_MEM_1MB: 627 ln2range = 20; 628 break; 629 case PCIM_BAR_MEM_64: 630 ln2range = 64; 631 break; 632 } 633 return (ln2range); 634 } 635 636 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 637 638 static void 639 pci_fixancient(pcicfgregs *cfg) 640 { 641 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 642 return; 643 644 /* PCI to PCI bridges use header type 1 */ 645 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 646 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 647 } 648 649 /* extract header type specific config data */ 650 651 static void 652 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 653 { 654 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 655 switch (cfg->hdrtype & PCIM_HDRTYPE) { 656 case PCIM_HDRTYPE_NORMAL: 657 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 658 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 659 cfg->mingnt = REG(PCIR_MINGNT, 1); 660 cfg->maxlat = REG(PCIR_MAXLAT, 1); 661 cfg->nummaps = PCI_MAXMAPS_0; 662 break; 663 case PCIM_HDRTYPE_BRIDGE: 664 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 665 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 666 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 667 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 668 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 669 cfg->nummaps = PCI_MAXMAPS_1; 670 break; 671 case PCIM_HDRTYPE_CARDBUS: 672 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 673 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 674 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 675 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 676 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 677 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 678 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 679 cfg->nummaps = PCI_MAXMAPS_2; 680 break; 681 } 682 #undef REG 683 } 684 685 /* read configuration header into pcicfgregs structure */ 686 struct pci_devinfo * 687 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 688 { 689 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 690 uint16_t vid, did; 691 692 vid = REG(PCIR_VENDOR, 2); 693 if (vid == PCIV_INVALID) 694 return (NULL); 695 696 did = REG(PCIR_DEVICE, 2); 697 698 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 699 } 700 701 struct pci_devinfo * 702 pci_alloc_devinfo_method(device_t dev) 703 { 704 705 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 706 M_WAITOK | M_ZERO)); 707 } 708 709 static struct pci_devinfo * 710 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 711 uint16_t vid, uint16_t did) 712 { 713 struct pci_devinfo *devlist_entry; 714 pcicfgregs *cfg; 715 716 devlist_entry = PCI_ALLOC_DEVINFO(bus); 717 718 cfg = &devlist_entry->cfg; 719 720 cfg->domain = d; 721 cfg->bus = b; 722 cfg->slot = s; 723 cfg->func = f; 724 cfg->vendor = vid; 725 cfg->device = did; 726 cfg->cmdreg = REG(PCIR_COMMAND, 2); 727 cfg->statreg = REG(PCIR_STATUS, 2); 728 cfg->baseclass = REG(PCIR_CLASS, 1); 729 cfg->subclass = REG(PCIR_SUBCLASS, 1); 730 cfg->progif = REG(PCIR_PROGIF, 1); 731 cfg->revid = REG(PCIR_REVID, 1); 732 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 733 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 734 cfg->lattimer = REG(PCIR_LATTIMER, 1); 735 cfg->intpin = REG(PCIR_INTPIN, 1); 736 cfg->intline = REG(PCIR_INTLINE, 1); 737 738 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 739 cfg->hdrtype &= ~PCIM_MFDEV; 740 STAILQ_INIT(&cfg->maps); 741 742 cfg->iov = NULL; 743 744 pci_fixancient(cfg); 745 pci_hdrtypedata(pcib, b, s, f, cfg); 746 747 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 748 pci_read_cap(pcib, cfg); 749 750 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 751 752 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 753 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 754 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 755 devlist_entry->conf.pc_sel.pc_func = cfg->func; 756 devlist_entry->conf.pc_hdr = cfg->hdrtype; 757 758 devlist_entry->conf.pc_subvendor = cfg->subvendor; 759 devlist_entry->conf.pc_subdevice = cfg->subdevice; 760 devlist_entry->conf.pc_vendor = cfg->vendor; 761 devlist_entry->conf.pc_device = cfg->device; 762 763 devlist_entry->conf.pc_class = cfg->baseclass; 764 devlist_entry->conf.pc_subclass = cfg->subclass; 765 devlist_entry->conf.pc_progif = cfg->progif; 766 devlist_entry->conf.pc_revid = cfg->revid; 767 768 pci_numdevs++; 769 pci_generation++; 770 771 return (devlist_entry); 772 } 773 #undef REG 774 775 static void 776 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 777 { 778 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 779 cfg->ea.ea_location + (n), w) 780 int num_ent; 781 int ptr; 782 int a, b; 783 uint32_t val; 784 int ent_size; 785 uint32_t dw[4]; 786 uint64_t base, max_offset; 787 struct pci_ea_entry *eae; 788 789 if (cfg->ea.ea_location == 0) 790 return; 791 792 STAILQ_INIT(&cfg->ea.ea_entries); 793 794 /* Determine the number of entries */ 795 num_ent = REG(PCIR_EA_NUM_ENT, 2); 796 num_ent &= PCIM_EA_NUM_ENT_MASK; 797 798 /* Find the first entry to care of */ 799 ptr = PCIR_EA_FIRST_ENT; 800 801 /* Skip DWORD 2 for type 1 functions */ 802 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 803 ptr += 4; 804 805 for (a = 0; a < num_ent; a++) { 806 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 807 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 808 809 /* Read a number of dwords in the entry */ 810 val = REG(ptr, 4); 811 ptr += 4; 812 ent_size = (val & PCIM_EA_ES); 813 814 for (b = 0; b < ent_size; b++) { 815 dw[b] = REG(ptr, 4); 816 ptr += 4; 817 } 818 819 eae->eae_flags = val; 820 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 821 822 base = dw[0] & PCIM_EA_FIELD_MASK; 823 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 824 b = 2; 825 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 826 base |= (uint64_t)dw[b] << 32UL; 827 b++; 828 } 829 if (((dw[1] & PCIM_EA_IS_64) != 0) 830 && (b < ent_size)) { 831 max_offset |= (uint64_t)dw[b] << 32UL; 832 b++; 833 } 834 835 eae->eae_base = base; 836 eae->eae_max_offset = max_offset; 837 838 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 839 840 if (bootverbose) { 841 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 842 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 843 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 844 } 845 } 846 } 847 #undef REG 848 849 static void 850 pci_read_cap(device_t pcib, pcicfgregs *cfg) 851 { 852 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 853 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 854 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 855 uint64_t addr; 856 #endif 857 uint32_t val; 858 int ptr, nextptr, ptrptr; 859 860 switch (cfg->hdrtype & PCIM_HDRTYPE) { 861 case PCIM_HDRTYPE_NORMAL: 862 case PCIM_HDRTYPE_BRIDGE: 863 ptrptr = PCIR_CAP_PTR; 864 break; 865 case PCIM_HDRTYPE_CARDBUS: 866 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 867 break; 868 default: 869 return; /* no extended capabilities support */ 870 } 871 nextptr = REG(ptrptr, 1); /* sanity check? */ 872 873 /* 874 * Read capability entries. 875 */ 876 while (nextptr != 0) { 877 /* Sanity check */ 878 if (nextptr > 255) { 879 printf("illegal PCI extended capability offset %d\n", 880 nextptr); 881 return; 882 } 883 /* Find the next entry */ 884 ptr = nextptr; 885 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 886 887 /* Process this entry */ 888 switch (REG(ptr + PCICAP_ID, 1)) { 889 case PCIY_PMG: /* PCI power management */ 890 if (cfg->pp.pp_cap == 0) { 891 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 892 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 893 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 894 if ((nextptr - ptr) > PCIR_POWER_DATA) 895 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 896 } 897 break; 898 case PCIY_HT: /* HyperTransport */ 899 /* Determine HT-specific capability type. */ 900 val = REG(ptr + PCIR_HT_COMMAND, 2); 901 902 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 903 cfg->ht.ht_slave = ptr; 904 905 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 906 switch (val & PCIM_HTCMD_CAP_MASK) { 907 case PCIM_HTCAP_MSI_MAPPING: 908 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 909 /* Sanity check the mapping window. */ 910 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 911 4); 912 addr <<= 32; 913 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 914 4); 915 if (addr != MSI_INTEL_ADDR_BASE) 916 device_printf(pcib, 917 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 918 cfg->domain, cfg->bus, 919 cfg->slot, cfg->func, 920 (long long)addr); 921 } else 922 addr = MSI_INTEL_ADDR_BASE; 923 924 cfg->ht.ht_msimap = ptr; 925 cfg->ht.ht_msictrl = val; 926 cfg->ht.ht_msiaddr = addr; 927 break; 928 } 929 #endif 930 break; 931 case PCIY_MSI: /* PCI MSI */ 932 cfg->msi.msi_location = ptr; 933 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 934 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 935 PCIM_MSICTRL_MMC_MASK)>>1); 936 break; 937 case PCIY_MSIX: /* PCI MSI-X */ 938 cfg->msix.msix_location = ptr; 939 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 940 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 941 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 942 val = REG(ptr + PCIR_MSIX_TABLE, 4); 943 cfg->msix.msix_table_bar = PCIR_BAR(val & 944 PCIM_MSIX_BIR_MASK); 945 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 946 val = REG(ptr + PCIR_MSIX_PBA, 4); 947 cfg->msix.msix_pba_bar = PCIR_BAR(val & 948 PCIM_MSIX_BIR_MASK); 949 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 950 break; 951 case PCIY_VPD: /* PCI Vital Product Data */ 952 cfg->vpd.vpd_reg = ptr; 953 break; 954 case PCIY_SUBVENDOR: 955 /* Should always be true. */ 956 if ((cfg->hdrtype & PCIM_HDRTYPE) == 957 PCIM_HDRTYPE_BRIDGE) { 958 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 959 cfg->subvendor = val & 0xffff; 960 cfg->subdevice = val >> 16; 961 } 962 break; 963 case PCIY_PCIX: /* PCI-X */ 964 /* 965 * Assume we have a PCI-X chipset if we have 966 * at least one PCI-PCI bridge with a PCI-X 967 * capability. Note that some systems with 968 * PCI-express or HT chipsets might match on 969 * this check as well. 970 */ 971 if ((cfg->hdrtype & PCIM_HDRTYPE) == 972 PCIM_HDRTYPE_BRIDGE) 973 pcix_chipset = 1; 974 cfg->pcix.pcix_location = ptr; 975 break; 976 case PCIY_EXPRESS: /* PCI-express */ 977 /* 978 * Assume we have a PCI-express chipset if we have 979 * at least one PCI-express device. 980 */ 981 pcie_chipset = 1; 982 cfg->pcie.pcie_location = ptr; 983 val = REG(ptr + PCIER_FLAGS, 2); 984 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 985 break; 986 case PCIY_EA: /* Enhanced Allocation */ 987 cfg->ea.ea_location = ptr; 988 pci_ea_fill_info(pcib, cfg); 989 break; 990 default: 991 break; 992 } 993 } 994 995 #if defined(__powerpc__) 996 /* 997 * Enable the MSI mapping window for all HyperTransport 998 * slaves. PCI-PCI bridges have their windows enabled via 999 * PCIB_MAP_MSI(). 1000 */ 1001 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1002 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1003 device_printf(pcib, 1004 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1005 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1006 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1007 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1008 2); 1009 } 1010 #endif 1011 /* REG and WREG use carry through to next functions */ 1012 } 1013 1014 /* 1015 * PCI Vital Product Data 1016 */ 1017 1018 #define PCI_VPD_TIMEOUT 1000000 1019 1020 static int 1021 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1022 { 1023 int count = PCI_VPD_TIMEOUT; 1024 1025 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1026 1027 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1028 1029 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1030 if (--count < 0) 1031 return (ENXIO); 1032 DELAY(1); /* limit looping */ 1033 } 1034 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1035 1036 return (0); 1037 } 1038 1039 #if 0 1040 static int 1041 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1042 { 1043 int count = PCI_VPD_TIMEOUT; 1044 1045 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1046 1047 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1048 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1049 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1050 if (--count < 0) 1051 return (ENXIO); 1052 DELAY(1); /* limit looping */ 1053 } 1054 1055 return (0); 1056 } 1057 #endif 1058 1059 #undef PCI_VPD_TIMEOUT 1060 1061 struct vpd_readstate { 1062 device_t pcib; 1063 pcicfgregs *cfg; 1064 uint32_t val; 1065 int bytesinval; 1066 int off; 1067 uint8_t cksum; 1068 }; 1069 1070 /* return 0 and one byte in *data if no read error, -1 else */ 1071 static int 1072 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1073 { 1074 uint32_t reg; 1075 uint8_t byte; 1076 1077 if (vrs->bytesinval == 0) { 1078 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1079 return (-1); 1080 vrs->val = le32toh(reg); 1081 vrs->off += 4; 1082 byte = vrs->val & 0xff; 1083 vrs->bytesinval = 3; 1084 } else { 1085 vrs->val = vrs->val >> 8; 1086 byte = vrs->val & 0xff; 1087 vrs->bytesinval--; 1088 } 1089 1090 vrs->cksum += byte; 1091 *data = byte; 1092 return (0); 1093 } 1094 1095 /* return 0 on match, -1 and "unget" byte on no match */ 1096 static int 1097 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1098 { 1099 uint8_t data; 1100 1101 if (vpd_nextbyte(vrs, &data) != 0) 1102 return (-1); 1103 1104 if (data == expected) 1105 return (0); 1106 1107 vrs->cksum -= data; 1108 vrs->val = (vrs->val << 8) + data; 1109 vrs->bytesinval++; 1110 return (-1); 1111 } 1112 1113 /* return size if tag matches, -1 on no match, -2 on read error */ 1114 static int 1115 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1116 { 1117 uint8_t byte1, byte2; 1118 1119 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1120 return (-1); 1121 1122 if ((vpd_tag & 0x80) == 0) 1123 return (vpd_tag & 0x07); 1124 1125 if (vpd_nextbyte(vrs, &byte1) != 0) 1126 return (-2); 1127 if (vpd_nextbyte(vrs, &byte2) != 0) 1128 return (-2); 1129 1130 return ((byte2 << 8) + byte1); 1131 } 1132 1133 /* (re)allocate buffer in multiples of 8 elements */ 1134 static void* 1135 alloc_buffer(void* buffer, size_t element_size, int needed) 1136 { 1137 int alloc, new_alloc; 1138 1139 alloc = roundup2(needed, 8); 1140 new_alloc = roundup2(needed + 1, 8); 1141 if (alloc != new_alloc) { 1142 buffer = reallocf(buffer, 1143 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1144 } 1145 1146 return (buffer); 1147 } 1148 1149 /* read VPD keyword and return element size, return -1 on read error */ 1150 static int 1151 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1152 { 1153 uint8_t data; 1154 1155 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1156 return (-1); 1157 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1158 return (-1); 1159 if (vpd_nextbyte(vrs, &data) != 0) 1160 return (-1); 1161 1162 return (data); 1163 } 1164 1165 /* read VPD data element of given size into allocated buffer */ 1166 static char * 1167 vpd_read_value(struct vpd_readstate *vrs, int size) 1168 { 1169 int i; 1170 char char1; 1171 char *value; 1172 1173 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1174 for (i = 0; i < size; i++) { 1175 if (vpd_nextbyte(vrs, &char1) != 0) { 1176 free(value, M_DEVBUF); 1177 return (NULL); 1178 } 1179 value[i] = char1; 1180 } 1181 value[size] = '\0'; 1182 1183 return (value); 1184 } 1185 1186 /* read VPD into *keyword and *value, return length of data element */ 1187 static int 1188 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1189 { 1190 int len; 1191 1192 len = vpd_read_elem_head(vrs, keyword); 1193 if (len < 0 || len > maxlen) 1194 return (-1); 1195 *value = vpd_read_value(vrs, len); 1196 1197 return (len); 1198 } 1199 1200 /* subtract all data following first byte from checksum of RV element */ 1201 static void 1202 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1203 { 1204 int i; 1205 uint8_t fixup; 1206 1207 fixup = 0; 1208 for (i = 1; i < len; i++) 1209 fixup += rvstring[i]; 1210 vrs->cksum -= fixup; 1211 } 1212 1213 /* fetch one read-only element and return size of heading + data */ 1214 static int 1215 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1216 { 1217 struct pcicfg_vpd *vpd; 1218 pcicfgregs *cfg; 1219 struct vpd_readonly *vpd_ros; 1220 int len; 1221 1222 cfg = vrs->cfg; 1223 vpd = &cfg->vpd; 1224 1225 if (maxsize < 3) 1226 return (-1); 1227 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1228 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1229 maxsize -= 3; 1230 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1231 if (vpd_ros->value == NULL) 1232 return (-1); 1233 vpd_ros->len = len; 1234 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1235 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1236 if (vrs->cksum != 0) { 1237 pci_printf(cfg, 1238 "invalid VPD checksum %#hhx\n", vrs->cksum); 1239 return (-1); 1240 } 1241 } 1242 vpd->vpd_rocnt++; 1243 1244 return (len + 3); 1245 } 1246 1247 /* fetch one writable element and return size of heading + data */ 1248 static int 1249 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1250 { 1251 struct pcicfg_vpd *vpd; 1252 pcicfgregs *cfg; 1253 struct vpd_write *vpd_w; 1254 int len; 1255 1256 cfg = vrs->cfg; 1257 vpd = &cfg->vpd; 1258 1259 if (maxsize < 3) 1260 return (-1); 1261 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1262 if (vpd->vpd_w == NULL) { 1263 pci_printf(cfg, "out of memory"); 1264 return (-1); 1265 } 1266 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1267 maxsize -= 3; 1268 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1269 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1270 if (vpd_w->value == NULL) 1271 return (-1); 1272 vpd_w->len = len; 1273 vpd->vpd_wcnt++; 1274 1275 return (len + 3); 1276 } 1277 1278 /* free all memory allocated for VPD data */ 1279 static void 1280 vpd_free(struct pcicfg_vpd *vpd) 1281 { 1282 int i; 1283 1284 free(vpd->vpd_ident, M_DEVBUF); 1285 for (i = 0; i < vpd->vpd_rocnt; i++) 1286 free(vpd->vpd_ros[i].value, M_DEVBUF); 1287 free(vpd->vpd_ros, M_DEVBUF); 1288 vpd->vpd_rocnt = 0; 1289 for (i = 0; i < vpd->vpd_wcnt; i++) 1290 free(vpd->vpd_w[i].value, M_DEVBUF); 1291 free(vpd->vpd_w, M_DEVBUF); 1292 vpd->vpd_wcnt = 0; 1293 } 1294 1295 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1296 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1297 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1298 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1299 1300 static int 1301 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1302 { 1303 struct vpd_readstate vrs; 1304 int cksumvalid; 1305 int size, elem_size; 1306 1307 /* init vpd reader */ 1308 vrs.bytesinval = 0; 1309 vrs.off = 0; 1310 vrs.pcib = pcib; 1311 vrs.cfg = cfg; 1312 vrs.cksum = 0; 1313 1314 /* read VPD ident element - mandatory */ 1315 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1316 if (size <= 0) { 1317 pci_printf(cfg, "no VPD ident found\n"); 1318 return (0); 1319 } 1320 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1321 if (cfg->vpd.vpd_ident == NULL) { 1322 pci_printf(cfg, "error accessing VPD ident data\n"); 1323 return (0); 1324 } 1325 1326 /* read VPD RO elements - mandatory */ 1327 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1328 if (size <= 0) { 1329 pci_printf(cfg, "no read-only VPD data found\n"); 1330 return (0); 1331 } 1332 while (size > 0) { 1333 elem_size = next_vpd_ro_elem(&vrs, size); 1334 if (elem_size < 0) { 1335 pci_printf(cfg, "error accessing read-only VPD data\n"); 1336 return (-1); 1337 } 1338 size -= elem_size; 1339 } 1340 cksumvalid = (vrs.cksum == 0); 1341 if (!cksumvalid) 1342 return (-1); 1343 1344 /* read VPD RW elements - optional */ 1345 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1346 if (size == -2) 1347 return (-1); 1348 while (size > 0) { 1349 elem_size = next_vpd_rw_elem(&vrs, size); 1350 if (elem_size < 0) { 1351 pci_printf(cfg, "error accessing writeable VPD data\n"); 1352 return (-1); 1353 } 1354 size -= elem_size; 1355 } 1356 1357 /* read empty END tag - mandatory */ 1358 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1359 if (size != 0) { 1360 pci_printf(cfg, "No valid VPD end tag found\n"); 1361 } 1362 return (0); 1363 } 1364 1365 static void 1366 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1367 { 1368 int status; 1369 1370 status = pci_parse_vpd(pcib, cfg); 1371 if (status < 0) 1372 vpd_free(&cfg->vpd); 1373 cfg->vpd.vpd_cached = 1; 1374 #undef REG 1375 #undef WREG 1376 } 1377 1378 int 1379 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1380 { 1381 struct pci_devinfo *dinfo = device_get_ivars(child); 1382 pcicfgregs *cfg = &dinfo->cfg; 1383 1384 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1385 pci_read_vpd(device_get_parent(dev), cfg); 1386 1387 *identptr = cfg->vpd.vpd_ident; 1388 1389 if (*identptr == NULL) 1390 return (ENXIO); 1391 1392 return (0); 1393 } 1394 1395 int 1396 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1397 const char **vptr) 1398 { 1399 struct pci_devinfo *dinfo = device_get_ivars(child); 1400 pcicfgregs *cfg = &dinfo->cfg; 1401 int i; 1402 1403 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1404 pci_read_vpd(device_get_parent(dev), cfg); 1405 1406 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1407 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1408 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1409 *vptr = cfg->vpd.vpd_ros[i].value; 1410 return (0); 1411 } 1412 1413 *vptr = NULL; 1414 return (ENXIO); 1415 } 1416 1417 struct pcicfg_vpd * 1418 pci_fetch_vpd_list(device_t dev) 1419 { 1420 struct pci_devinfo *dinfo = device_get_ivars(dev); 1421 pcicfgregs *cfg = &dinfo->cfg; 1422 1423 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1424 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1425 return (&cfg->vpd); 1426 } 1427 1428 /* 1429 * Find the requested HyperTransport capability and return the offset 1430 * in configuration space via the pointer provided. The function 1431 * returns 0 on success and an error code otherwise. 1432 */ 1433 int 1434 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1435 { 1436 int ptr, error; 1437 uint16_t val; 1438 1439 error = pci_find_cap(child, PCIY_HT, &ptr); 1440 if (error) 1441 return (error); 1442 1443 /* 1444 * Traverse the capabilities list checking each HT capability 1445 * to see if it matches the requested HT capability. 1446 */ 1447 for (;;) { 1448 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1449 if (capability == PCIM_HTCAP_SLAVE || 1450 capability == PCIM_HTCAP_HOST) 1451 val &= 0xe000; 1452 else 1453 val &= PCIM_HTCMD_CAP_MASK; 1454 if (val == capability) { 1455 if (capreg != NULL) 1456 *capreg = ptr; 1457 return (0); 1458 } 1459 1460 /* Skip to the next HT capability. */ 1461 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1462 break; 1463 } 1464 1465 return (ENOENT); 1466 } 1467 1468 /* 1469 * Find the next requested HyperTransport capability after start and return 1470 * the offset in configuration space via the pointer provided. The function 1471 * returns 0 on success and an error code otherwise. 1472 */ 1473 int 1474 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1475 int start, int *capreg) 1476 { 1477 int ptr; 1478 uint16_t val; 1479 1480 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1481 ("start capability is not HyperTransport capability")); 1482 ptr = start; 1483 1484 /* 1485 * Traverse the capabilities list checking each HT capability 1486 * to see if it matches the requested HT capability. 1487 */ 1488 for (;;) { 1489 /* Skip to the next HT capability. */ 1490 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1491 break; 1492 1493 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1494 if (capability == PCIM_HTCAP_SLAVE || 1495 capability == PCIM_HTCAP_HOST) 1496 val &= 0xe000; 1497 else 1498 val &= PCIM_HTCMD_CAP_MASK; 1499 if (val == capability) { 1500 if (capreg != NULL) 1501 *capreg = ptr; 1502 return (0); 1503 } 1504 } 1505 1506 return (ENOENT); 1507 } 1508 1509 /* 1510 * Find the requested capability and return the offset in 1511 * configuration space via the pointer provided. The function returns 1512 * 0 on success and an error code otherwise. 1513 */ 1514 int 1515 pci_find_cap_method(device_t dev, device_t child, int capability, 1516 int *capreg) 1517 { 1518 struct pci_devinfo *dinfo = device_get_ivars(child); 1519 pcicfgregs *cfg = &dinfo->cfg; 1520 uint32_t status; 1521 uint8_t ptr; 1522 int cnt; 1523 1524 /* 1525 * Check the CAP_LIST bit of the PCI status register first. 1526 */ 1527 status = pci_read_config(child, PCIR_STATUS, 2); 1528 if (!(status & PCIM_STATUS_CAPPRESENT)) 1529 return (ENXIO); 1530 1531 /* 1532 * Determine the start pointer of the capabilities list. 1533 */ 1534 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1535 case PCIM_HDRTYPE_NORMAL: 1536 case PCIM_HDRTYPE_BRIDGE: 1537 ptr = PCIR_CAP_PTR; 1538 break; 1539 case PCIM_HDRTYPE_CARDBUS: 1540 ptr = PCIR_CAP_PTR_2; 1541 break; 1542 default: 1543 /* XXX: panic? */ 1544 return (ENXIO); /* no extended capabilities support */ 1545 } 1546 ptr = pci_read_config(child, ptr, 1); 1547 1548 /* 1549 * Traverse the capabilities list. Limit by total theoretical 1550 * maximum number of caps: capability needs at least id and 1551 * next registers, and any type X header cannot contain caps. 1552 */ 1553 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1554 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1555 if (capreg != NULL) 1556 *capreg = ptr; 1557 return (0); 1558 } 1559 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1560 } 1561 1562 return (ENOENT); 1563 } 1564 1565 /* 1566 * Find the next requested capability after start and return the offset in 1567 * configuration space via the pointer provided. The function returns 1568 * 0 on success and an error code otherwise. 1569 */ 1570 int 1571 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1572 int start, int *capreg) 1573 { 1574 uint8_t ptr; 1575 1576 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1577 ("start capability is not expected capability")); 1578 1579 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1580 while (ptr != 0) { 1581 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1582 if (capreg != NULL) 1583 *capreg = ptr; 1584 return (0); 1585 } 1586 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1587 } 1588 1589 return (ENOENT); 1590 } 1591 1592 /* 1593 * Find the requested extended capability and return the offset in 1594 * configuration space via the pointer provided. The function returns 1595 * 0 on success and an error code otherwise. 1596 */ 1597 int 1598 pci_find_extcap_method(device_t dev, device_t child, int capability, 1599 int *capreg) 1600 { 1601 struct pci_devinfo *dinfo = device_get_ivars(child); 1602 pcicfgregs *cfg = &dinfo->cfg; 1603 uint32_t ecap; 1604 uint16_t ptr; 1605 1606 /* Only supported for PCI-express devices. */ 1607 if (cfg->pcie.pcie_location == 0) 1608 return (ENXIO); 1609 1610 ptr = PCIR_EXTCAP; 1611 ecap = pci_read_config(child, ptr, 4); 1612 if (ecap == 0xffffffff || ecap == 0) 1613 return (ENOENT); 1614 for (;;) { 1615 if (PCI_EXTCAP_ID(ecap) == capability) { 1616 if (capreg != NULL) 1617 *capreg = ptr; 1618 return (0); 1619 } 1620 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1621 if (ptr == 0) 1622 break; 1623 ecap = pci_read_config(child, ptr, 4); 1624 } 1625 1626 return (ENOENT); 1627 } 1628 1629 /* 1630 * Find the next requested extended capability after start and return the 1631 * offset in configuration space via the pointer provided. The function 1632 * returns 0 on success and an error code otherwise. 1633 */ 1634 int 1635 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1636 int start, int *capreg) 1637 { 1638 struct pci_devinfo *dinfo = device_get_ivars(child); 1639 pcicfgregs *cfg = &dinfo->cfg; 1640 uint32_t ecap; 1641 uint16_t ptr; 1642 1643 /* Only supported for PCI-express devices. */ 1644 if (cfg->pcie.pcie_location == 0) 1645 return (ENXIO); 1646 1647 ecap = pci_read_config(child, start, 4); 1648 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1649 ("start extended capability is not expected capability")); 1650 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1651 while (ptr != 0) { 1652 ecap = pci_read_config(child, ptr, 4); 1653 if (PCI_EXTCAP_ID(ecap) == capability) { 1654 if (capreg != NULL) 1655 *capreg = ptr; 1656 return (0); 1657 } 1658 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1659 } 1660 1661 return (ENOENT); 1662 } 1663 1664 /* 1665 * Support for MSI-X message interrupts. 1666 */ 1667 static void 1668 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1669 { 1670 struct pci_devinfo *dinfo = device_get_ivars(dev); 1671 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1672 uint32_t offset; 1673 1674 KASSERT(msix->msix_table_len > index, ("bogus index")); 1675 offset = msix->msix_table_offset + index * 16; 1676 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1677 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1678 bus_write_4(msix->msix_table_res, offset + 8, data); 1679 } 1680 1681 void 1682 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1683 uint64_t address, uint32_t data) 1684 { 1685 1686 if (pci_msix_rewrite_table) { 1687 struct pci_devinfo *dinfo = device_get_ivars(child); 1688 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1689 1690 /* 1691 * Some VM hosts require MSIX to be disabled in the 1692 * control register before updating the MSIX table 1693 * entries are allowed. It is not enough to only 1694 * disable MSIX while updating a single entry. MSIX 1695 * must be disabled while updating all entries in the 1696 * table. 1697 */ 1698 pci_write_config(child, 1699 msix->msix_location + PCIR_MSIX_CTRL, 1700 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1701 pci_resume_msix(child); 1702 } else 1703 pci_write_msix_entry(child, index, address, data); 1704 1705 /* Enable MSI -> HT mapping. */ 1706 pci_ht_map_msi(child, address); 1707 } 1708 1709 void 1710 pci_mask_msix(device_t dev, u_int index) 1711 { 1712 struct pci_devinfo *dinfo = device_get_ivars(dev); 1713 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1714 uint32_t offset, val; 1715 1716 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1717 offset = msix->msix_table_offset + index * 16 + 12; 1718 val = bus_read_4(msix->msix_table_res, offset); 1719 val |= PCIM_MSIX_VCTRL_MASK; 1720 1721 /* 1722 * Some devices (e.g. Samsung PM961) do not support reads of this 1723 * register, so always write the new value. 1724 */ 1725 bus_write_4(msix->msix_table_res, offset, val); 1726 } 1727 1728 void 1729 pci_unmask_msix(device_t dev, u_int index) 1730 { 1731 struct pci_devinfo *dinfo = device_get_ivars(dev); 1732 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1733 uint32_t offset, val; 1734 1735 KASSERT(msix->msix_table_len > index, ("bogus index")); 1736 offset = msix->msix_table_offset + index * 16 + 12; 1737 val = bus_read_4(msix->msix_table_res, offset); 1738 val &= ~PCIM_MSIX_VCTRL_MASK; 1739 1740 /* 1741 * Some devices (e.g. Samsung PM961) do not support reads of this 1742 * register, so always write the new value. 1743 */ 1744 bus_write_4(msix->msix_table_res, offset, val); 1745 } 1746 1747 int 1748 pci_pending_msix(device_t dev, u_int index) 1749 { 1750 struct pci_devinfo *dinfo = device_get_ivars(dev); 1751 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1752 uint32_t offset, bit; 1753 1754 KASSERT(msix->msix_table_len > index, ("bogus index")); 1755 offset = msix->msix_pba_offset + (index / 32) * 4; 1756 bit = 1 << index % 32; 1757 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1758 } 1759 1760 /* 1761 * Restore MSI-X registers and table during resume. If MSI-X is 1762 * enabled then walk the virtual table to restore the actual MSI-X 1763 * table. 1764 */ 1765 static void 1766 pci_resume_msix(device_t dev) 1767 { 1768 struct pci_devinfo *dinfo = device_get_ivars(dev); 1769 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1770 struct msix_table_entry *mte; 1771 struct msix_vector *mv; 1772 int i; 1773 1774 if (msix->msix_alloc > 0) { 1775 /* First, mask all vectors. */ 1776 for (i = 0; i < msix->msix_msgnum; i++) 1777 pci_mask_msix(dev, i); 1778 1779 /* Second, program any messages with at least one handler. */ 1780 for (i = 0; i < msix->msix_table_len; i++) { 1781 mte = &msix->msix_table[i]; 1782 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1783 continue; 1784 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1785 pci_write_msix_entry(dev, i, mv->mv_address, 1786 mv->mv_data); 1787 pci_unmask_msix(dev, i); 1788 } 1789 } 1790 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1791 msix->msix_ctrl, 2); 1792 } 1793 1794 /* 1795 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1796 * returned in *count. After this function returns, each message will be 1797 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1798 */ 1799 int 1800 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1801 { 1802 struct pci_devinfo *dinfo = device_get_ivars(child); 1803 pcicfgregs *cfg = &dinfo->cfg; 1804 struct resource_list_entry *rle; 1805 int actual, error, i, irq, max; 1806 1807 /* Don't let count == 0 get us into trouble. */ 1808 if (*count == 0) 1809 return (EINVAL); 1810 1811 /* If rid 0 is allocated, then fail. */ 1812 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1813 if (rle != NULL && rle->res != NULL) 1814 return (ENXIO); 1815 1816 /* Already have allocated messages? */ 1817 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1818 return (ENXIO); 1819 1820 /* If MSI-X is blacklisted for this system, fail. */ 1821 if (pci_msix_blacklisted()) 1822 return (ENXIO); 1823 1824 /* MSI-X capability present? */ 1825 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1826 return (ENODEV); 1827 1828 /* Make sure the appropriate BARs are mapped. */ 1829 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1830 cfg->msix.msix_table_bar); 1831 if (rle == NULL || rle->res == NULL || 1832 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1833 return (ENXIO); 1834 cfg->msix.msix_table_res = rle->res; 1835 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1836 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1837 cfg->msix.msix_pba_bar); 1838 if (rle == NULL || rle->res == NULL || 1839 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1840 return (ENXIO); 1841 } 1842 cfg->msix.msix_pba_res = rle->res; 1843 1844 if (bootverbose) 1845 device_printf(child, 1846 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1847 *count, cfg->msix.msix_msgnum); 1848 max = min(*count, cfg->msix.msix_msgnum); 1849 for (i = 0; i < max; i++) { 1850 /* Allocate a message. */ 1851 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1852 if (error) { 1853 if (i == 0) 1854 return (error); 1855 break; 1856 } 1857 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1858 irq, 1); 1859 } 1860 actual = i; 1861 1862 if (bootverbose) { 1863 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1864 if (actual == 1) 1865 device_printf(child, "using IRQ %ju for MSI-X\n", 1866 rle->start); 1867 else { 1868 int run; 1869 1870 /* 1871 * Be fancy and try to print contiguous runs of 1872 * IRQ values as ranges. 'irq' is the previous IRQ. 1873 * 'run' is true if we are in a range. 1874 */ 1875 device_printf(child, "using IRQs %ju", rle->start); 1876 irq = rle->start; 1877 run = 0; 1878 for (i = 1; i < actual; i++) { 1879 rle = resource_list_find(&dinfo->resources, 1880 SYS_RES_IRQ, i + 1); 1881 1882 /* Still in a run? */ 1883 if (rle->start == irq + 1) { 1884 run = 1; 1885 irq++; 1886 continue; 1887 } 1888 1889 /* Finish previous range. */ 1890 if (run) { 1891 printf("-%d", irq); 1892 run = 0; 1893 } 1894 1895 /* Start new range. */ 1896 printf(",%ju", rle->start); 1897 irq = rle->start; 1898 } 1899 1900 /* Unfinished range? */ 1901 if (run) 1902 printf("-%d", irq); 1903 printf(" for MSI-X\n"); 1904 } 1905 } 1906 1907 /* Mask all vectors. */ 1908 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1909 pci_mask_msix(child, i); 1910 1911 /* Allocate and initialize vector data and virtual table. */ 1912 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1913 M_DEVBUF, M_WAITOK | M_ZERO); 1914 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1915 M_DEVBUF, M_WAITOK | M_ZERO); 1916 for (i = 0; i < actual; i++) { 1917 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1918 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1919 cfg->msix.msix_table[i].mte_vector = i + 1; 1920 } 1921 1922 /* Update control register to enable MSI-X. */ 1923 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1924 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1925 cfg->msix.msix_ctrl, 2); 1926 1927 /* Update counts of alloc'd messages. */ 1928 cfg->msix.msix_alloc = actual; 1929 cfg->msix.msix_table_len = actual; 1930 *count = actual; 1931 return (0); 1932 } 1933 1934 /* 1935 * By default, pci_alloc_msix() will assign the allocated IRQ 1936 * resources consecutively to the first N messages in the MSI-X table. 1937 * However, device drivers may want to use different layouts if they 1938 * either receive fewer messages than they asked for, or they wish to 1939 * populate the MSI-X table sparsely. This method allows the driver 1940 * to specify what layout it wants. It must be called after a 1941 * successful pci_alloc_msix() but before any of the associated 1942 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1943 * 1944 * The 'vectors' array contains 'count' message vectors. The array 1945 * maps directly to the MSI-X table in that index 0 in the array 1946 * specifies the vector for the first message in the MSI-X table, etc. 1947 * The vector value in each array index can either be 0 to indicate 1948 * that no vector should be assigned to a message slot, or it can be a 1949 * number from 1 to N (where N is the count returned from a 1950 * succcessful call to pci_alloc_msix()) to indicate which message 1951 * vector (IRQ) to be used for the corresponding message. 1952 * 1953 * On successful return, each message with a non-zero vector will have 1954 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1955 * 1. Additionally, if any of the IRQs allocated via the previous 1956 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1957 * will be freed back to the system automatically. 1958 * 1959 * For example, suppose a driver has a MSI-X table with 6 messages and 1960 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1961 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1962 * C. After the call to pci_alloc_msix(), the device will be setup to 1963 * have an MSI-X table of ABC--- (where - means no vector assigned). 1964 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1965 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1966 * be freed back to the system. This device will also have valid 1967 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1968 * 1969 * In any case, the SYS_RES_IRQ rid X will always map to the message 1970 * at MSI-X table index X - 1 and will only be valid if a vector is 1971 * assigned to that table entry. 1972 */ 1973 int 1974 pci_remap_msix_method(device_t dev, device_t child, int count, 1975 const u_int *vectors) 1976 { 1977 struct pci_devinfo *dinfo = device_get_ivars(child); 1978 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1979 struct resource_list_entry *rle; 1980 int i, irq, j, *used; 1981 1982 /* 1983 * Have to have at least one message in the table but the 1984 * table can't be bigger than the actual MSI-X table in the 1985 * device. 1986 */ 1987 if (count == 0 || count > msix->msix_msgnum) 1988 return (EINVAL); 1989 1990 /* Sanity check the vectors. */ 1991 for (i = 0; i < count; i++) 1992 if (vectors[i] > msix->msix_alloc) 1993 return (EINVAL); 1994 1995 /* 1996 * Make sure there aren't any holes in the vectors to be used. 1997 * It's a big pain to support it, and it doesn't really make 1998 * sense anyway. Also, at least one vector must be used. 1999 */ 2000 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 2001 M_ZERO); 2002 for (i = 0; i < count; i++) 2003 if (vectors[i] != 0) 2004 used[vectors[i] - 1] = 1; 2005 for (i = 0; i < msix->msix_alloc - 1; i++) 2006 if (used[i] == 0 && used[i + 1] == 1) { 2007 free(used, M_DEVBUF); 2008 return (EINVAL); 2009 } 2010 if (used[0] != 1) { 2011 free(used, M_DEVBUF); 2012 return (EINVAL); 2013 } 2014 2015 /* Make sure none of the resources are allocated. */ 2016 for (i = 0; i < msix->msix_table_len; i++) { 2017 if (msix->msix_table[i].mte_vector == 0) 2018 continue; 2019 if (msix->msix_table[i].mte_handlers > 0) { 2020 free(used, M_DEVBUF); 2021 return (EBUSY); 2022 } 2023 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2024 KASSERT(rle != NULL, ("missing resource")); 2025 if (rle->res != NULL) { 2026 free(used, M_DEVBUF); 2027 return (EBUSY); 2028 } 2029 } 2030 2031 /* Free the existing resource list entries. */ 2032 for (i = 0; i < msix->msix_table_len; i++) { 2033 if (msix->msix_table[i].mte_vector == 0) 2034 continue; 2035 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2036 } 2037 2038 /* 2039 * Build the new virtual table keeping track of which vectors are 2040 * used. 2041 */ 2042 free(msix->msix_table, M_DEVBUF); 2043 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 2044 M_DEVBUF, M_WAITOK | M_ZERO); 2045 for (i = 0; i < count; i++) 2046 msix->msix_table[i].mte_vector = vectors[i]; 2047 msix->msix_table_len = count; 2048 2049 /* Free any unused IRQs and resize the vectors array if necessary. */ 2050 j = msix->msix_alloc - 1; 2051 if (used[j] == 0) { 2052 struct msix_vector *vec; 2053 2054 while (used[j] == 0) { 2055 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2056 msix->msix_vectors[j].mv_irq); 2057 j--; 2058 } 2059 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2060 M_WAITOK); 2061 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2062 (j + 1)); 2063 free(msix->msix_vectors, M_DEVBUF); 2064 msix->msix_vectors = vec; 2065 msix->msix_alloc = j + 1; 2066 } 2067 free(used, M_DEVBUF); 2068 2069 /* Map the IRQs onto the rids. */ 2070 for (i = 0; i < count; i++) { 2071 if (vectors[i] == 0) 2072 continue; 2073 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2074 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2075 irq, 1); 2076 } 2077 2078 if (bootverbose) { 2079 device_printf(child, "Remapped MSI-X IRQs as: "); 2080 for (i = 0; i < count; i++) { 2081 if (i != 0) 2082 printf(", "); 2083 if (vectors[i] == 0) 2084 printf("---"); 2085 else 2086 printf("%d", 2087 msix->msix_vectors[vectors[i] - 1].mv_irq); 2088 } 2089 printf("\n"); 2090 } 2091 2092 return (0); 2093 } 2094 2095 static int 2096 pci_release_msix(device_t dev, device_t child) 2097 { 2098 struct pci_devinfo *dinfo = device_get_ivars(child); 2099 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2100 struct resource_list_entry *rle; 2101 int i; 2102 2103 /* Do we have any messages to release? */ 2104 if (msix->msix_alloc == 0) 2105 return (ENODEV); 2106 2107 /* Make sure none of the resources are allocated. */ 2108 for (i = 0; i < msix->msix_table_len; i++) { 2109 if (msix->msix_table[i].mte_vector == 0) 2110 continue; 2111 if (msix->msix_table[i].mte_handlers > 0) 2112 return (EBUSY); 2113 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2114 KASSERT(rle != NULL, ("missing resource")); 2115 if (rle->res != NULL) 2116 return (EBUSY); 2117 } 2118 2119 /* Update control register to disable MSI-X. */ 2120 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2121 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2122 msix->msix_ctrl, 2); 2123 2124 /* Free the resource list entries. */ 2125 for (i = 0; i < msix->msix_table_len; i++) { 2126 if (msix->msix_table[i].mte_vector == 0) 2127 continue; 2128 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2129 } 2130 free(msix->msix_table, M_DEVBUF); 2131 msix->msix_table_len = 0; 2132 2133 /* Release the IRQs. */ 2134 for (i = 0; i < msix->msix_alloc; i++) 2135 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2136 msix->msix_vectors[i].mv_irq); 2137 free(msix->msix_vectors, M_DEVBUF); 2138 msix->msix_alloc = 0; 2139 return (0); 2140 } 2141 2142 /* 2143 * Return the max supported MSI-X messages this device supports. 2144 * Basically, assuming the MD code can alloc messages, this function 2145 * should return the maximum value that pci_alloc_msix() can return. 2146 * Thus, it is subject to the tunables, etc. 2147 */ 2148 int 2149 pci_msix_count_method(device_t dev, device_t child) 2150 { 2151 struct pci_devinfo *dinfo = device_get_ivars(child); 2152 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2153 2154 if (pci_do_msix && msix->msix_location != 0) 2155 return (msix->msix_msgnum); 2156 return (0); 2157 } 2158 2159 int 2160 pci_msix_pba_bar_method(device_t dev, device_t child) 2161 { 2162 struct pci_devinfo *dinfo = device_get_ivars(child); 2163 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2164 2165 if (pci_do_msix && msix->msix_location != 0) 2166 return (msix->msix_pba_bar); 2167 return (-1); 2168 } 2169 2170 int 2171 pci_msix_table_bar_method(device_t dev, device_t child) 2172 { 2173 struct pci_devinfo *dinfo = device_get_ivars(child); 2174 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2175 2176 if (pci_do_msix && msix->msix_location != 0) 2177 return (msix->msix_table_bar); 2178 return (-1); 2179 } 2180 2181 /* 2182 * HyperTransport MSI mapping control 2183 */ 2184 void 2185 pci_ht_map_msi(device_t dev, uint64_t addr) 2186 { 2187 struct pci_devinfo *dinfo = device_get_ivars(dev); 2188 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2189 2190 if (!ht->ht_msimap) 2191 return; 2192 2193 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2194 ht->ht_msiaddr >> 20 == addr >> 20) { 2195 /* Enable MSI -> HT mapping. */ 2196 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2197 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2198 ht->ht_msictrl, 2); 2199 } 2200 2201 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2202 /* Disable MSI -> HT mapping. */ 2203 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2204 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2205 ht->ht_msictrl, 2); 2206 } 2207 } 2208 2209 int 2210 pci_get_relaxed_ordering_enabled(device_t dev) 2211 { 2212 struct pci_devinfo *dinfo = device_get_ivars(dev); 2213 int cap; 2214 uint16_t val; 2215 2216 cap = dinfo->cfg.pcie.pcie_location; 2217 if (cap == 0) 2218 return (0); 2219 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2220 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2221 return (val != 0); 2222 } 2223 2224 int 2225 pci_get_max_payload(device_t dev) 2226 { 2227 struct pci_devinfo *dinfo = device_get_ivars(dev); 2228 int cap; 2229 uint16_t val; 2230 2231 cap = dinfo->cfg.pcie.pcie_location; 2232 if (cap == 0) 2233 return (0); 2234 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2235 val &= PCIEM_CTL_MAX_PAYLOAD; 2236 val >>= 5; 2237 return (1 << (val + 7)); 2238 } 2239 2240 int 2241 pci_get_max_read_req(device_t dev) 2242 { 2243 struct pci_devinfo *dinfo = device_get_ivars(dev); 2244 int cap; 2245 uint16_t val; 2246 2247 cap = dinfo->cfg.pcie.pcie_location; 2248 if (cap == 0) 2249 return (0); 2250 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2251 val &= PCIEM_CTL_MAX_READ_REQUEST; 2252 val >>= 12; 2253 return (1 << (val + 7)); 2254 } 2255 2256 int 2257 pci_set_max_read_req(device_t dev, int size) 2258 { 2259 struct pci_devinfo *dinfo = device_get_ivars(dev); 2260 int cap; 2261 uint16_t val; 2262 2263 cap = dinfo->cfg.pcie.pcie_location; 2264 if (cap == 0) 2265 return (0); 2266 if (size < 128) 2267 size = 128; 2268 if (size > 4096) 2269 size = 4096; 2270 size = (1 << (fls(size) - 1)); 2271 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2272 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2273 val |= (fls(size) - 8) << 12; 2274 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2275 return (size); 2276 } 2277 2278 uint32_t 2279 pcie_read_config(device_t dev, int reg, int width) 2280 { 2281 struct pci_devinfo *dinfo = device_get_ivars(dev); 2282 int cap; 2283 2284 cap = dinfo->cfg.pcie.pcie_location; 2285 if (cap == 0) { 2286 if (width == 2) 2287 return (0xffff); 2288 return (0xffffffff); 2289 } 2290 2291 return (pci_read_config(dev, cap + reg, width)); 2292 } 2293 2294 void 2295 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2296 { 2297 struct pci_devinfo *dinfo = device_get_ivars(dev); 2298 int cap; 2299 2300 cap = dinfo->cfg.pcie.pcie_location; 2301 if (cap == 0) 2302 return; 2303 pci_write_config(dev, cap + reg, value, width); 2304 } 2305 2306 /* 2307 * Adjusts a PCI-e capability register by clearing the bits in mask 2308 * and setting the bits in (value & mask). Bits not set in mask are 2309 * not adjusted. 2310 * 2311 * Returns the old value on success or all ones on failure. 2312 */ 2313 uint32_t 2314 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2315 int width) 2316 { 2317 struct pci_devinfo *dinfo = device_get_ivars(dev); 2318 uint32_t old, new; 2319 int cap; 2320 2321 cap = dinfo->cfg.pcie.pcie_location; 2322 if (cap == 0) { 2323 if (width == 2) 2324 return (0xffff); 2325 return (0xffffffff); 2326 } 2327 2328 old = pci_read_config(dev, cap + reg, width); 2329 new = old & ~mask; 2330 new |= (value & mask); 2331 pci_write_config(dev, cap + reg, new, width); 2332 return (old); 2333 } 2334 2335 /* 2336 * Support for MSI message signalled interrupts. 2337 */ 2338 void 2339 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2340 uint16_t data) 2341 { 2342 struct pci_devinfo *dinfo = device_get_ivars(child); 2343 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2344 2345 /* Write data and address values. */ 2346 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2347 address & 0xffffffff, 4); 2348 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2349 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2350 address >> 32, 4); 2351 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2352 data, 2); 2353 } else 2354 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2355 2); 2356 2357 /* Enable MSI in the control register. */ 2358 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2359 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2360 msi->msi_ctrl, 2); 2361 2362 /* Enable MSI -> HT mapping. */ 2363 pci_ht_map_msi(child, address); 2364 } 2365 2366 void 2367 pci_disable_msi_method(device_t dev, device_t child) 2368 { 2369 struct pci_devinfo *dinfo = device_get_ivars(child); 2370 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2371 2372 /* Disable MSI -> HT mapping. */ 2373 pci_ht_map_msi(child, 0); 2374 2375 /* Disable MSI in the control register. */ 2376 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2377 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2378 msi->msi_ctrl, 2); 2379 } 2380 2381 /* 2382 * Restore MSI registers during resume. If MSI is enabled then 2383 * restore the data and address registers in addition to the control 2384 * register. 2385 */ 2386 static void 2387 pci_resume_msi(device_t dev) 2388 { 2389 struct pci_devinfo *dinfo = device_get_ivars(dev); 2390 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2391 uint64_t address; 2392 uint16_t data; 2393 2394 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2395 address = msi->msi_addr; 2396 data = msi->msi_data; 2397 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2398 address & 0xffffffff, 4); 2399 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2400 pci_write_config(dev, msi->msi_location + 2401 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2402 pci_write_config(dev, msi->msi_location + 2403 PCIR_MSI_DATA_64BIT, data, 2); 2404 } else 2405 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2406 data, 2); 2407 } 2408 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2409 2); 2410 } 2411 2412 static int 2413 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2414 { 2415 struct pci_devinfo *dinfo = device_get_ivars(dev); 2416 pcicfgregs *cfg = &dinfo->cfg; 2417 struct resource_list_entry *rle; 2418 struct msix_table_entry *mte; 2419 struct msix_vector *mv; 2420 uint64_t addr; 2421 uint32_t data; 2422 int error, i, j; 2423 2424 /* 2425 * Handle MSI first. We try to find this IRQ among our list 2426 * of MSI IRQs. If we find it, we request updated address and 2427 * data registers and apply the results. 2428 */ 2429 if (cfg->msi.msi_alloc > 0) { 2430 /* If we don't have any active handlers, nothing to do. */ 2431 if (cfg->msi.msi_handlers == 0) 2432 return (0); 2433 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2434 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2435 i + 1); 2436 if (rle->start == irq) { 2437 error = PCIB_MAP_MSI(device_get_parent(bus), 2438 dev, irq, &addr, &data); 2439 if (error) 2440 return (error); 2441 pci_disable_msi(dev); 2442 dinfo->cfg.msi.msi_addr = addr; 2443 dinfo->cfg.msi.msi_data = data; 2444 pci_enable_msi(dev, addr, data); 2445 return (0); 2446 } 2447 } 2448 return (ENOENT); 2449 } 2450 2451 /* 2452 * For MSI-X, we check to see if we have this IRQ. If we do, 2453 * we request the updated mapping info. If that works, we go 2454 * through all the slots that use this IRQ and update them. 2455 */ 2456 if (cfg->msix.msix_alloc > 0) { 2457 bool found = false; 2458 2459 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2460 mv = &cfg->msix.msix_vectors[i]; 2461 if (mv->mv_irq == irq) { 2462 error = PCIB_MAP_MSI(device_get_parent(bus), 2463 dev, irq, &addr, &data); 2464 if (error) 2465 return (error); 2466 mv->mv_address = addr; 2467 mv->mv_data = data; 2468 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2469 mte = &cfg->msix.msix_table[j]; 2470 if (mte->mte_vector != i + 1) 2471 continue; 2472 if (mte->mte_handlers == 0) 2473 continue; 2474 pci_mask_msix(dev, j); 2475 pci_enable_msix(dev, j, addr, data); 2476 pci_unmask_msix(dev, j); 2477 } 2478 found = true; 2479 } 2480 } 2481 return (found ? 0 : ENOENT); 2482 } 2483 2484 return (ENOENT); 2485 } 2486 2487 /* 2488 * Returns true if the specified device is blacklisted because MSI 2489 * doesn't work. 2490 */ 2491 int 2492 pci_msi_device_blacklisted(device_t dev) 2493 { 2494 2495 if (!pci_honor_msi_blacklist) 2496 return (0); 2497 2498 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2499 } 2500 2501 /* 2502 * Determine if MSI is blacklisted globally on this system. Currently, 2503 * we just check for blacklisted chipsets as represented by the 2504 * host-PCI bridge at device 0:0:0. In the future, it may become 2505 * necessary to check other system attributes, such as the kenv values 2506 * that give the motherboard manufacturer and model number. 2507 */ 2508 static int 2509 pci_msi_blacklisted(void) 2510 { 2511 device_t dev; 2512 2513 if (!pci_honor_msi_blacklist) 2514 return (0); 2515 2516 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2517 if (!(pcie_chipset || pcix_chipset)) { 2518 if (vm_guest != VM_GUEST_NO) { 2519 /* 2520 * Whitelist older chipsets in virtual 2521 * machines known to support MSI. 2522 */ 2523 dev = pci_find_bsf(0, 0, 0); 2524 if (dev != NULL) 2525 return (!pci_has_quirk(pci_get_devid(dev), 2526 PCI_QUIRK_ENABLE_MSI_VM)); 2527 } 2528 return (1); 2529 } 2530 2531 dev = pci_find_bsf(0, 0, 0); 2532 if (dev != NULL) 2533 return (pci_msi_device_blacklisted(dev)); 2534 return (0); 2535 } 2536 2537 /* 2538 * Returns true if the specified device is blacklisted because MSI-X 2539 * doesn't work. Note that this assumes that if MSI doesn't work, 2540 * MSI-X doesn't either. 2541 */ 2542 int 2543 pci_msix_device_blacklisted(device_t dev) 2544 { 2545 2546 if (!pci_honor_msi_blacklist) 2547 return (0); 2548 2549 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2550 return (1); 2551 2552 return (pci_msi_device_blacklisted(dev)); 2553 } 2554 2555 /* 2556 * Determine if MSI-X is blacklisted globally on this system. If MSI 2557 * is blacklisted, assume that MSI-X is as well. Check for additional 2558 * chipsets where MSI works but MSI-X does not. 2559 */ 2560 static int 2561 pci_msix_blacklisted(void) 2562 { 2563 device_t dev; 2564 2565 if (!pci_honor_msi_blacklist) 2566 return (0); 2567 2568 dev = pci_find_bsf(0, 0, 0); 2569 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2570 PCI_QUIRK_DISABLE_MSIX)) 2571 return (1); 2572 2573 return (pci_msi_blacklisted()); 2574 } 2575 2576 /* 2577 * Attempt to allocate *count MSI messages. The actual number allocated is 2578 * returned in *count. After this function returns, each message will be 2579 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2580 */ 2581 int 2582 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2583 { 2584 struct pci_devinfo *dinfo = device_get_ivars(child); 2585 pcicfgregs *cfg = &dinfo->cfg; 2586 struct resource_list_entry *rle; 2587 int actual, error, i, irqs[32]; 2588 uint16_t ctrl; 2589 2590 /* Don't let count == 0 get us into trouble. */ 2591 if (*count == 0) 2592 return (EINVAL); 2593 2594 /* If rid 0 is allocated, then fail. */ 2595 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2596 if (rle != NULL && rle->res != NULL) 2597 return (ENXIO); 2598 2599 /* Already have allocated messages? */ 2600 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2601 return (ENXIO); 2602 2603 /* If MSI is blacklisted for this system, fail. */ 2604 if (pci_msi_blacklisted()) 2605 return (ENXIO); 2606 2607 /* MSI capability present? */ 2608 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2609 return (ENODEV); 2610 2611 if (bootverbose) 2612 device_printf(child, 2613 "attempting to allocate %d MSI vectors (%d supported)\n", 2614 *count, cfg->msi.msi_msgnum); 2615 2616 /* Don't ask for more than the device supports. */ 2617 actual = min(*count, cfg->msi.msi_msgnum); 2618 2619 /* Don't ask for more than 32 messages. */ 2620 actual = min(actual, 32); 2621 2622 /* MSI requires power of 2 number of messages. */ 2623 if (!powerof2(actual)) 2624 return (EINVAL); 2625 2626 for (;;) { 2627 /* Try to allocate N messages. */ 2628 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2629 actual, irqs); 2630 if (error == 0) 2631 break; 2632 if (actual == 1) 2633 return (error); 2634 2635 /* Try N / 2. */ 2636 actual >>= 1; 2637 } 2638 2639 /* 2640 * We now have N actual messages mapped onto SYS_RES_IRQ 2641 * resources in the irqs[] array, so add new resources 2642 * starting at rid 1. 2643 */ 2644 for (i = 0; i < actual; i++) 2645 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2646 irqs[i], irqs[i], 1); 2647 2648 if (bootverbose) { 2649 if (actual == 1) 2650 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2651 else { 2652 int run; 2653 2654 /* 2655 * Be fancy and try to print contiguous runs 2656 * of IRQ values as ranges. 'run' is true if 2657 * we are in a range. 2658 */ 2659 device_printf(child, "using IRQs %d", irqs[0]); 2660 run = 0; 2661 for (i = 1; i < actual; i++) { 2662 /* Still in a run? */ 2663 if (irqs[i] == irqs[i - 1] + 1) { 2664 run = 1; 2665 continue; 2666 } 2667 2668 /* Finish previous range. */ 2669 if (run) { 2670 printf("-%d", irqs[i - 1]); 2671 run = 0; 2672 } 2673 2674 /* Start new range. */ 2675 printf(",%d", irqs[i]); 2676 } 2677 2678 /* Unfinished range? */ 2679 if (run) 2680 printf("-%d", irqs[actual - 1]); 2681 printf(" for MSI\n"); 2682 } 2683 } 2684 2685 /* Update control register with actual count. */ 2686 ctrl = cfg->msi.msi_ctrl; 2687 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2688 ctrl |= (ffs(actual) - 1) << 4; 2689 cfg->msi.msi_ctrl = ctrl; 2690 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2691 2692 /* Update counts of alloc'd messages. */ 2693 cfg->msi.msi_alloc = actual; 2694 cfg->msi.msi_handlers = 0; 2695 *count = actual; 2696 return (0); 2697 } 2698 2699 /* Release the MSI messages associated with this device. */ 2700 int 2701 pci_release_msi_method(device_t dev, device_t child) 2702 { 2703 struct pci_devinfo *dinfo = device_get_ivars(child); 2704 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2705 struct resource_list_entry *rle; 2706 int error, i, irqs[32]; 2707 2708 /* Try MSI-X first. */ 2709 error = pci_release_msix(dev, child); 2710 if (error != ENODEV) 2711 return (error); 2712 2713 /* Do we have any messages to release? */ 2714 if (msi->msi_alloc == 0) 2715 return (ENODEV); 2716 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2717 2718 /* Make sure none of the resources are allocated. */ 2719 if (msi->msi_handlers > 0) 2720 return (EBUSY); 2721 for (i = 0; i < msi->msi_alloc; i++) { 2722 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2723 KASSERT(rle != NULL, ("missing MSI resource")); 2724 if (rle->res != NULL) 2725 return (EBUSY); 2726 irqs[i] = rle->start; 2727 } 2728 2729 /* Update control register with 0 count. */ 2730 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2731 ("%s: MSI still enabled", __func__)); 2732 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2733 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2734 msi->msi_ctrl, 2); 2735 2736 /* Release the messages. */ 2737 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2738 for (i = 0; i < msi->msi_alloc; i++) 2739 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2740 2741 /* Update alloc count. */ 2742 msi->msi_alloc = 0; 2743 msi->msi_addr = 0; 2744 msi->msi_data = 0; 2745 return (0); 2746 } 2747 2748 /* 2749 * Return the max supported MSI messages this device supports. 2750 * Basically, assuming the MD code can alloc messages, this function 2751 * should return the maximum value that pci_alloc_msi() can return. 2752 * Thus, it is subject to the tunables, etc. 2753 */ 2754 int 2755 pci_msi_count_method(device_t dev, device_t child) 2756 { 2757 struct pci_devinfo *dinfo = device_get_ivars(child); 2758 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2759 2760 if (pci_do_msi && msi->msi_location != 0) 2761 return (msi->msi_msgnum); 2762 return (0); 2763 } 2764 2765 /* free pcicfgregs structure and all depending data structures */ 2766 2767 int 2768 pci_freecfg(struct pci_devinfo *dinfo) 2769 { 2770 struct devlist *devlist_head; 2771 struct pci_map *pm, *next; 2772 2773 devlist_head = &pci_devq; 2774 2775 if (dinfo->cfg.vpd.vpd_reg) 2776 vpd_free(&dinfo->cfg.vpd); 2777 2778 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2779 free(pm, M_DEVBUF); 2780 } 2781 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2782 free(dinfo, M_DEVBUF); 2783 2784 /* increment the generation count */ 2785 pci_generation++; 2786 2787 /* we're losing one device */ 2788 pci_numdevs--; 2789 return (0); 2790 } 2791 2792 /* 2793 * PCI power manangement 2794 */ 2795 int 2796 pci_set_powerstate_method(device_t dev, device_t child, int state) 2797 { 2798 struct pci_devinfo *dinfo = device_get_ivars(child); 2799 pcicfgregs *cfg = &dinfo->cfg; 2800 uint16_t status; 2801 int oldstate, highest, delay; 2802 2803 if (cfg->pp.pp_cap == 0) 2804 return (EOPNOTSUPP); 2805 2806 /* 2807 * Optimize a no state change request away. While it would be OK to 2808 * write to the hardware in theory, some devices have shown odd 2809 * behavior when going from D3 -> D3. 2810 */ 2811 oldstate = pci_get_powerstate(child); 2812 if (oldstate == state) 2813 return (0); 2814 2815 /* 2816 * The PCI power management specification states that after a state 2817 * transition between PCI power states, system software must 2818 * guarantee a minimal delay before the function accesses the device. 2819 * Compute the worst case delay that we need to guarantee before we 2820 * access the device. Many devices will be responsive much more 2821 * quickly than this delay, but there are some that don't respond 2822 * instantly to state changes. Transitions to/from D3 state require 2823 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2824 * is done below with DELAY rather than a sleeper function because 2825 * this function can be called from contexts where we cannot sleep. 2826 */ 2827 highest = (oldstate > state) ? oldstate : state; 2828 if (highest == PCI_POWERSTATE_D3) 2829 delay = 10000; 2830 else if (highest == PCI_POWERSTATE_D2) 2831 delay = 200; 2832 else 2833 delay = 0; 2834 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2835 & ~PCIM_PSTAT_DMASK; 2836 switch (state) { 2837 case PCI_POWERSTATE_D0: 2838 status |= PCIM_PSTAT_D0; 2839 break; 2840 case PCI_POWERSTATE_D1: 2841 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2842 return (EOPNOTSUPP); 2843 status |= PCIM_PSTAT_D1; 2844 break; 2845 case PCI_POWERSTATE_D2: 2846 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2847 return (EOPNOTSUPP); 2848 status |= PCIM_PSTAT_D2; 2849 break; 2850 case PCI_POWERSTATE_D3: 2851 status |= PCIM_PSTAT_D3; 2852 break; 2853 default: 2854 return (EINVAL); 2855 } 2856 2857 if (bootverbose) 2858 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2859 state); 2860 2861 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2862 if (delay) 2863 DELAY(delay); 2864 return (0); 2865 } 2866 2867 int 2868 pci_get_powerstate_method(device_t dev, device_t child) 2869 { 2870 struct pci_devinfo *dinfo = device_get_ivars(child); 2871 pcicfgregs *cfg = &dinfo->cfg; 2872 uint16_t status; 2873 int result; 2874 2875 if (cfg->pp.pp_cap != 0) { 2876 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2877 switch (status & PCIM_PSTAT_DMASK) { 2878 case PCIM_PSTAT_D0: 2879 result = PCI_POWERSTATE_D0; 2880 break; 2881 case PCIM_PSTAT_D1: 2882 result = PCI_POWERSTATE_D1; 2883 break; 2884 case PCIM_PSTAT_D2: 2885 result = PCI_POWERSTATE_D2; 2886 break; 2887 case PCIM_PSTAT_D3: 2888 result = PCI_POWERSTATE_D3; 2889 break; 2890 default: 2891 result = PCI_POWERSTATE_UNKNOWN; 2892 break; 2893 } 2894 } else { 2895 /* No support, device is always at D0 */ 2896 result = PCI_POWERSTATE_D0; 2897 } 2898 return (result); 2899 } 2900 2901 /* 2902 * Some convenience functions for PCI device drivers. 2903 */ 2904 2905 static __inline void 2906 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2907 { 2908 uint16_t command; 2909 2910 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2911 command |= bit; 2912 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2913 } 2914 2915 static __inline void 2916 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2917 { 2918 uint16_t command; 2919 2920 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2921 command &= ~bit; 2922 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2923 } 2924 2925 int 2926 pci_enable_busmaster_method(device_t dev, device_t child) 2927 { 2928 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2929 return (0); 2930 } 2931 2932 int 2933 pci_disable_busmaster_method(device_t dev, device_t child) 2934 { 2935 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2936 return (0); 2937 } 2938 2939 int 2940 pci_enable_io_method(device_t dev, device_t child, int space) 2941 { 2942 uint16_t bit; 2943 2944 switch(space) { 2945 case SYS_RES_IOPORT: 2946 bit = PCIM_CMD_PORTEN; 2947 break; 2948 case SYS_RES_MEMORY: 2949 bit = PCIM_CMD_MEMEN; 2950 break; 2951 default: 2952 return (EINVAL); 2953 } 2954 pci_set_command_bit(dev, child, bit); 2955 return (0); 2956 } 2957 2958 int 2959 pci_disable_io_method(device_t dev, device_t child, int space) 2960 { 2961 uint16_t bit; 2962 2963 switch(space) { 2964 case SYS_RES_IOPORT: 2965 bit = PCIM_CMD_PORTEN; 2966 break; 2967 case SYS_RES_MEMORY: 2968 bit = PCIM_CMD_MEMEN; 2969 break; 2970 default: 2971 return (EINVAL); 2972 } 2973 pci_clear_command_bit(dev, child, bit); 2974 return (0); 2975 } 2976 2977 /* 2978 * New style pci driver. Parent device is either a pci-host-bridge or a 2979 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2980 */ 2981 2982 void 2983 pci_print_verbose(struct pci_devinfo *dinfo) 2984 { 2985 2986 if (bootverbose) { 2987 pcicfgregs *cfg = &dinfo->cfg; 2988 2989 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2990 cfg->vendor, cfg->device, cfg->revid); 2991 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2992 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2993 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2994 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2995 cfg->mfdev); 2996 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2997 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2998 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2999 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3000 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3001 if (cfg->intpin > 0) 3002 printf("\tintpin=%c, irq=%d\n", 3003 cfg->intpin +'a' -1, cfg->intline); 3004 if (cfg->pp.pp_cap) { 3005 uint16_t status; 3006 3007 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 3008 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3009 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3010 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3011 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3012 status & PCIM_PSTAT_DMASK); 3013 } 3014 if (cfg->msi.msi_location) { 3015 int ctrl; 3016 3017 ctrl = cfg->msi.msi_ctrl; 3018 printf("\tMSI supports %d message%s%s%s\n", 3019 cfg->msi.msi_msgnum, 3020 (cfg->msi.msi_msgnum == 1) ? "" : "s", 3021 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3022 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3023 } 3024 if (cfg->msix.msix_location) { 3025 printf("\tMSI-X supports %d message%s ", 3026 cfg->msix.msix_msgnum, 3027 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 3028 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3029 printf("in map 0x%x\n", 3030 cfg->msix.msix_table_bar); 3031 else 3032 printf("in maps 0x%x and 0x%x\n", 3033 cfg->msix.msix_table_bar, 3034 cfg->msix.msix_pba_bar); 3035 } 3036 } 3037 } 3038 3039 static int 3040 pci_porten(device_t dev) 3041 { 3042 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3043 } 3044 3045 static int 3046 pci_memen(device_t dev) 3047 { 3048 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3049 } 3050 3051 void 3052 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3053 int *bar64) 3054 { 3055 struct pci_devinfo *dinfo; 3056 pci_addr_t map, testval; 3057 int ln2range; 3058 uint16_t cmd; 3059 3060 /* 3061 * The device ROM BAR is special. It is always a 32-bit 3062 * memory BAR. Bit 0 is special and should not be set when 3063 * sizing the BAR. 3064 */ 3065 dinfo = device_get_ivars(dev); 3066 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3067 map = pci_read_config(dev, reg, 4); 3068 pci_write_config(dev, reg, 0xfffffffe, 4); 3069 testval = pci_read_config(dev, reg, 4); 3070 pci_write_config(dev, reg, map, 4); 3071 *mapp = map; 3072 *testvalp = testval; 3073 if (bar64 != NULL) 3074 *bar64 = 0; 3075 return; 3076 } 3077 3078 map = pci_read_config(dev, reg, 4); 3079 ln2range = pci_maprange(map); 3080 if (ln2range == 64) 3081 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3082 3083 /* 3084 * Disable decoding via the command register before 3085 * determining the BAR's length since we will be placing it in 3086 * a weird state. 3087 */ 3088 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3089 pci_write_config(dev, PCIR_COMMAND, 3090 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3091 3092 /* 3093 * Determine the BAR's length by writing all 1's. The bottom 3094 * log_2(size) bits of the BAR will stick as 0 when we read 3095 * the value back. 3096 * 3097 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3098 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3099 * and combines the result into a 64-bit value." (section 6.2.5.1) 3100 * 3101 * Writes to both registers must be performed before attempting to 3102 * read back the size value. 3103 */ 3104 testval = 0; 3105 pci_write_config(dev, reg, 0xffffffff, 4); 3106 if (ln2range == 64) { 3107 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3108 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3109 } 3110 testval |= pci_read_config(dev, reg, 4); 3111 3112 /* 3113 * Restore the original value of the BAR. We may have reprogrammed 3114 * the BAR of the low-level console device and when booting verbose, 3115 * we need the console device addressable. 3116 */ 3117 pci_write_config(dev, reg, map, 4); 3118 if (ln2range == 64) 3119 pci_write_config(dev, reg + 4, map >> 32, 4); 3120 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3121 3122 *mapp = map; 3123 *testvalp = testval; 3124 if (bar64 != NULL) 3125 *bar64 = (ln2range == 64); 3126 } 3127 3128 static void 3129 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3130 { 3131 struct pci_devinfo *dinfo; 3132 int ln2range; 3133 3134 /* The device ROM BAR is always a 32-bit memory BAR. */ 3135 dinfo = device_get_ivars(dev); 3136 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3137 ln2range = 32; 3138 else 3139 ln2range = pci_maprange(pm->pm_value); 3140 pci_write_config(dev, pm->pm_reg, base, 4); 3141 if (ln2range == 64) 3142 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3143 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3144 if (ln2range == 64) 3145 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3146 pm->pm_reg + 4, 4) << 32; 3147 } 3148 3149 struct pci_map * 3150 pci_find_bar(device_t dev, int reg) 3151 { 3152 struct pci_devinfo *dinfo; 3153 struct pci_map *pm; 3154 3155 dinfo = device_get_ivars(dev); 3156 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3157 if (pm->pm_reg == reg) 3158 return (pm); 3159 } 3160 return (NULL); 3161 } 3162 3163 struct pci_map * 3164 pci_first_bar(device_t dev) 3165 { 3166 struct pci_devinfo *dinfo; 3167 3168 dinfo = device_get_ivars(dev); 3169 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3170 } 3171 3172 struct pci_map * 3173 pci_next_bar(struct pci_map *pm) 3174 { 3175 return (STAILQ_NEXT(pm, pm_link)); 3176 } 3177 3178 int 3179 pci_bar_enabled(device_t dev, struct pci_map *pm) 3180 { 3181 struct pci_devinfo *dinfo; 3182 uint16_t cmd; 3183 3184 dinfo = device_get_ivars(dev); 3185 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3186 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3187 return (0); 3188 #ifdef PCI_IOV 3189 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3190 struct pcicfg_iov *iov; 3191 3192 iov = dinfo->cfg.iov; 3193 cmd = pci_read_config(iov->iov_pf, 3194 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3195 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3196 } 3197 #endif 3198 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3199 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3200 return ((cmd & PCIM_CMD_MEMEN) != 0); 3201 else 3202 return ((cmd & PCIM_CMD_PORTEN) != 0); 3203 } 3204 3205 struct pci_map * 3206 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3207 { 3208 struct pci_devinfo *dinfo; 3209 struct pci_map *pm, *prev; 3210 3211 dinfo = device_get_ivars(dev); 3212 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3213 pm->pm_reg = reg; 3214 pm->pm_value = value; 3215 pm->pm_size = size; 3216 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3217 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3218 reg)); 3219 if (STAILQ_NEXT(prev, pm_link) == NULL || 3220 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3221 break; 3222 } 3223 if (prev != NULL) 3224 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3225 else 3226 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3227 return (pm); 3228 } 3229 3230 static void 3231 pci_restore_bars(device_t dev) 3232 { 3233 struct pci_devinfo *dinfo; 3234 struct pci_map *pm; 3235 int ln2range; 3236 3237 dinfo = device_get_ivars(dev); 3238 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3239 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3240 ln2range = 32; 3241 else 3242 ln2range = pci_maprange(pm->pm_value); 3243 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3244 if (ln2range == 64) 3245 pci_write_config(dev, pm->pm_reg + 4, 3246 pm->pm_value >> 32, 4); 3247 } 3248 } 3249 3250 /* 3251 * Add a resource based on a pci map register. Return 1 if the map 3252 * register is a 32bit map register or 2 if it is a 64bit register. 3253 */ 3254 static int 3255 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3256 int force, int prefetch) 3257 { 3258 struct pci_map *pm; 3259 pci_addr_t base, map, testval; 3260 pci_addr_t start, end, count; 3261 int barlen, basezero, flags, maprange, mapsize, type; 3262 uint16_t cmd; 3263 struct resource *res; 3264 3265 /* 3266 * The BAR may already exist if the device is a CardBus card 3267 * whose CIS is stored in this BAR. 3268 */ 3269 pm = pci_find_bar(dev, reg); 3270 if (pm != NULL) { 3271 maprange = pci_maprange(pm->pm_value); 3272 barlen = maprange == 64 ? 2 : 1; 3273 return (barlen); 3274 } 3275 3276 pci_read_bar(dev, reg, &map, &testval, NULL); 3277 if (PCI_BAR_MEM(map)) { 3278 type = SYS_RES_MEMORY; 3279 if (map & PCIM_BAR_MEM_PREFETCH) 3280 prefetch = 1; 3281 } else 3282 type = SYS_RES_IOPORT; 3283 mapsize = pci_mapsize(testval); 3284 base = pci_mapbase(map); 3285 #ifdef __PCI_BAR_ZERO_VALID 3286 basezero = 0; 3287 #else 3288 basezero = base == 0; 3289 #endif 3290 maprange = pci_maprange(map); 3291 barlen = maprange == 64 ? 2 : 1; 3292 3293 /* 3294 * For I/O registers, if bottom bit is set, and the next bit up 3295 * isn't clear, we know we have a BAR that doesn't conform to the 3296 * spec, so ignore it. Also, sanity check the size of the data 3297 * areas to the type of memory involved. Memory must be at least 3298 * 16 bytes in size, while I/O ranges must be at least 4. 3299 */ 3300 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3301 return (barlen); 3302 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3303 (type == SYS_RES_IOPORT && mapsize < 2)) 3304 return (barlen); 3305 3306 /* Save a record of this BAR. */ 3307 pm = pci_add_bar(dev, reg, map, mapsize); 3308 if (bootverbose) { 3309 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3310 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3311 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3312 printf(", port disabled\n"); 3313 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3314 printf(", memory disabled\n"); 3315 else 3316 printf(", enabled\n"); 3317 } 3318 3319 /* 3320 * If base is 0, then we have problems if this architecture does 3321 * not allow that. It is best to ignore such entries for the 3322 * moment. These will be allocated later if the driver specifically 3323 * requests them. However, some removable buses look better when 3324 * all resources are allocated, so allow '0' to be overridden. 3325 * 3326 * Similarly treat maps whose values is the same as the test value 3327 * read back. These maps have had all f's written to them by the 3328 * BIOS in an attempt to disable the resources. 3329 */ 3330 if (!force && (basezero || map == testval)) 3331 return (barlen); 3332 if ((u_long)base != base) { 3333 device_printf(bus, 3334 "pci%d:%d:%d:%d bar %#x too many address bits", 3335 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3336 pci_get_function(dev), reg); 3337 return (barlen); 3338 } 3339 3340 /* 3341 * This code theoretically does the right thing, but has 3342 * undesirable side effects in some cases where peripherals 3343 * respond oddly to having these bits enabled. Let the user 3344 * be able to turn them off (since pci_enable_io_modes is 1 by 3345 * default). 3346 */ 3347 if (pci_enable_io_modes) { 3348 /* Turn on resources that have been left off by a lazy BIOS */ 3349 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3350 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3351 cmd |= PCIM_CMD_PORTEN; 3352 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3353 } 3354 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3355 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3356 cmd |= PCIM_CMD_MEMEN; 3357 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3358 } 3359 } else { 3360 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3361 return (barlen); 3362 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3363 return (barlen); 3364 } 3365 3366 count = (pci_addr_t)1 << mapsize; 3367 flags = RF_ALIGNMENT_LOG2(mapsize); 3368 if (prefetch) 3369 flags |= RF_PREFETCHABLE; 3370 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3371 start = 0; /* Let the parent decide. */ 3372 end = ~0; 3373 } else { 3374 start = base; 3375 end = base + count - 1; 3376 } 3377 resource_list_add(rl, type, reg, start, end, count); 3378 3379 /* 3380 * Try to allocate the resource for this BAR from our parent 3381 * so that this resource range is already reserved. The 3382 * driver for this device will later inherit this resource in 3383 * pci_alloc_resource(). 3384 */ 3385 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3386 flags); 3387 if ((pci_do_realloc_bars 3388 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3389 && res == NULL && (start != 0 || end != ~0)) { 3390 /* 3391 * If the allocation fails, try to allocate a resource for 3392 * this BAR using any available range. The firmware felt 3393 * it was important enough to assign a resource, so don't 3394 * disable decoding if we can help it. 3395 */ 3396 resource_list_delete(rl, type, reg); 3397 resource_list_add(rl, type, reg, 0, ~0, count); 3398 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3399 count, flags); 3400 } 3401 if (res == NULL) { 3402 /* 3403 * If the allocation fails, delete the resource list entry 3404 * and disable decoding for this device. 3405 * 3406 * If the driver requests this resource in the future, 3407 * pci_reserve_map() will try to allocate a fresh 3408 * resource range. 3409 */ 3410 resource_list_delete(rl, type, reg); 3411 pci_disable_io(dev, type); 3412 if (bootverbose) 3413 device_printf(bus, 3414 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3415 pci_get_domain(dev), pci_get_bus(dev), 3416 pci_get_slot(dev), pci_get_function(dev), reg); 3417 } else { 3418 start = rman_get_start(res); 3419 pci_write_bar(dev, pm, start); 3420 } 3421 return (barlen); 3422 } 3423 3424 /* 3425 * For ATA devices we need to decide early what addressing mode to use. 3426 * Legacy demands that the primary and secondary ATA ports sits on the 3427 * same addresses that old ISA hardware did. This dictates that we use 3428 * those addresses and ignore the BAR's if we cannot set PCI native 3429 * addressing mode. 3430 */ 3431 static void 3432 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3433 uint32_t prefetchmask) 3434 { 3435 int rid, type, progif; 3436 #if 0 3437 /* if this device supports PCI native addressing use it */ 3438 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3439 if ((progif & 0x8a) == 0x8a) { 3440 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3441 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3442 printf("Trying ATA native PCI addressing mode\n"); 3443 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3444 } 3445 } 3446 #endif 3447 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3448 type = SYS_RES_IOPORT; 3449 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3450 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3451 prefetchmask & (1 << 0)); 3452 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3453 prefetchmask & (1 << 1)); 3454 } else { 3455 rid = PCIR_BAR(0); 3456 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3457 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3458 0x1f7, 8, 0); 3459 rid = PCIR_BAR(1); 3460 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3461 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3462 0x3f6, 1, 0); 3463 } 3464 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3465 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3466 prefetchmask & (1 << 2)); 3467 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3468 prefetchmask & (1 << 3)); 3469 } else { 3470 rid = PCIR_BAR(2); 3471 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3472 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3473 0x177, 8, 0); 3474 rid = PCIR_BAR(3); 3475 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3476 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3477 0x376, 1, 0); 3478 } 3479 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3480 prefetchmask & (1 << 4)); 3481 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3482 prefetchmask & (1 << 5)); 3483 } 3484 3485 static void 3486 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3487 { 3488 struct pci_devinfo *dinfo = device_get_ivars(dev); 3489 pcicfgregs *cfg = &dinfo->cfg; 3490 char tunable_name[64]; 3491 int irq; 3492 3493 /* Has to have an intpin to have an interrupt. */ 3494 if (cfg->intpin == 0) 3495 return; 3496 3497 /* Let the user override the IRQ with a tunable. */ 3498 irq = PCI_INVALID_IRQ; 3499 snprintf(tunable_name, sizeof(tunable_name), 3500 "hw.pci%d.%d.%d.INT%c.irq", 3501 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3502 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3503 irq = PCI_INVALID_IRQ; 3504 3505 /* 3506 * If we didn't get an IRQ via the tunable, then we either use the 3507 * IRQ value in the intline register or we ask the bus to route an 3508 * interrupt for us. If force_route is true, then we only use the 3509 * value in the intline register if the bus was unable to assign an 3510 * IRQ. 3511 */ 3512 if (!PCI_INTERRUPT_VALID(irq)) { 3513 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3514 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3515 if (!PCI_INTERRUPT_VALID(irq)) 3516 irq = cfg->intline; 3517 } 3518 3519 /* If after all that we don't have an IRQ, just bail. */ 3520 if (!PCI_INTERRUPT_VALID(irq)) 3521 return; 3522 3523 /* Update the config register if it changed. */ 3524 if (irq != cfg->intline) { 3525 cfg->intline = irq; 3526 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3527 } 3528 3529 /* Add this IRQ as rid 0 interrupt resource. */ 3530 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3531 } 3532 3533 /* Perform early OHCI takeover from SMM. */ 3534 static void 3535 ohci_early_takeover(device_t self) 3536 { 3537 struct resource *res; 3538 uint32_t ctl; 3539 int rid; 3540 int i; 3541 3542 rid = PCIR_BAR(0); 3543 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3544 if (res == NULL) 3545 return; 3546 3547 ctl = bus_read_4(res, OHCI_CONTROL); 3548 if (ctl & OHCI_IR) { 3549 if (bootverbose) 3550 printf("ohci early: " 3551 "SMM active, request owner change\n"); 3552 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3553 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3554 DELAY(1000); 3555 ctl = bus_read_4(res, OHCI_CONTROL); 3556 } 3557 if (ctl & OHCI_IR) { 3558 if (bootverbose) 3559 printf("ohci early: " 3560 "SMM does not respond, resetting\n"); 3561 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3562 } 3563 /* Disable interrupts */ 3564 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3565 } 3566 3567 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3568 } 3569 3570 /* Perform early UHCI takeover from SMM. */ 3571 static void 3572 uhci_early_takeover(device_t self) 3573 { 3574 struct resource *res; 3575 int rid; 3576 3577 /* 3578 * Set the PIRQD enable bit and switch off all the others. We don't 3579 * want legacy support to interfere with us XXX Does this also mean 3580 * that the BIOS won't touch the keyboard anymore if it is connected 3581 * to the ports of the root hub? 3582 */ 3583 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3584 3585 /* Disable interrupts */ 3586 rid = PCI_UHCI_BASE_REG; 3587 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3588 if (res != NULL) { 3589 bus_write_2(res, UHCI_INTR, 0); 3590 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3591 } 3592 } 3593 3594 /* Perform early EHCI takeover from SMM. */ 3595 static void 3596 ehci_early_takeover(device_t self) 3597 { 3598 struct resource *res; 3599 uint32_t cparams; 3600 uint32_t eec; 3601 uint8_t eecp; 3602 uint8_t bios_sem; 3603 uint8_t offs; 3604 int rid; 3605 int i; 3606 3607 rid = PCIR_BAR(0); 3608 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3609 if (res == NULL) 3610 return; 3611 3612 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3613 3614 /* Synchronise with the BIOS if it owns the controller. */ 3615 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3616 eecp = EHCI_EECP_NEXT(eec)) { 3617 eec = pci_read_config(self, eecp, 4); 3618 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3619 continue; 3620 } 3621 bios_sem = pci_read_config(self, eecp + 3622 EHCI_LEGSUP_BIOS_SEM, 1); 3623 if (bios_sem == 0) { 3624 continue; 3625 } 3626 if (bootverbose) 3627 printf("ehci early: " 3628 "SMM active, request owner change\n"); 3629 3630 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3631 3632 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3633 DELAY(1000); 3634 bios_sem = pci_read_config(self, eecp + 3635 EHCI_LEGSUP_BIOS_SEM, 1); 3636 } 3637 3638 if (bios_sem != 0) { 3639 if (bootverbose) 3640 printf("ehci early: " 3641 "SMM does not respond\n"); 3642 } 3643 /* Disable interrupts */ 3644 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3645 bus_write_4(res, offs + EHCI_USBINTR, 0); 3646 } 3647 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3648 } 3649 3650 /* Perform early XHCI takeover from SMM. */ 3651 static void 3652 xhci_early_takeover(device_t self) 3653 { 3654 struct resource *res; 3655 uint32_t cparams; 3656 uint32_t eec; 3657 uint8_t eecp; 3658 uint8_t bios_sem; 3659 uint8_t offs; 3660 int rid; 3661 int i; 3662 3663 rid = PCIR_BAR(0); 3664 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3665 if (res == NULL) 3666 return; 3667 3668 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3669 3670 eec = -1; 3671 3672 /* Synchronise with the BIOS if it owns the controller. */ 3673 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3674 eecp += XHCI_XECP_NEXT(eec) << 2) { 3675 eec = bus_read_4(res, eecp); 3676 3677 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3678 continue; 3679 3680 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3681 if (bios_sem == 0) 3682 continue; 3683 3684 if (bootverbose) 3685 printf("xhci early: " 3686 "SMM active, request owner change\n"); 3687 3688 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3689 3690 /* wait a maximum of 5 second */ 3691 3692 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3693 DELAY(1000); 3694 bios_sem = bus_read_1(res, eecp + 3695 XHCI_XECP_BIOS_SEM); 3696 } 3697 3698 if (bios_sem != 0) { 3699 if (bootverbose) 3700 printf("xhci early: " 3701 "SMM does not respond\n"); 3702 } 3703 3704 /* Disable interrupts */ 3705 offs = bus_read_1(res, XHCI_CAPLENGTH); 3706 bus_write_4(res, offs + XHCI_USBCMD, 0); 3707 bus_read_4(res, offs + XHCI_USBSTS); 3708 } 3709 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3710 } 3711 3712 static void 3713 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3714 struct resource_list *rl) 3715 { 3716 struct resource *res; 3717 char *cp; 3718 rman_res_t start, end, count; 3719 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3720 3721 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3722 case PCIM_HDRTYPE_BRIDGE: 3723 sec_reg = PCIR_SECBUS_1; 3724 sub_reg = PCIR_SUBBUS_1; 3725 break; 3726 case PCIM_HDRTYPE_CARDBUS: 3727 sec_reg = PCIR_SECBUS_2; 3728 sub_reg = PCIR_SUBBUS_2; 3729 break; 3730 default: 3731 return; 3732 } 3733 3734 /* 3735 * If the existing bus range is valid, attempt to reserve it 3736 * from our parent. If this fails for any reason, clear the 3737 * secbus and subbus registers. 3738 * 3739 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3740 * This would at least preserve the existing sec_bus if it is 3741 * valid. 3742 */ 3743 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3744 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3745 3746 /* Quirk handling. */ 3747 switch (pci_get_devid(dev)) { 3748 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3749 sup_bus = pci_read_config(dev, 0x41, 1); 3750 if (sup_bus != 0xff) { 3751 sec_bus = sup_bus + 1; 3752 sub_bus = sup_bus + 1; 3753 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3754 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3755 } 3756 break; 3757 3758 case 0x00dd10de: 3759 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3760 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3761 break; 3762 if (strncmp(cp, "Compal", 6) != 0) { 3763 freeenv(cp); 3764 break; 3765 } 3766 freeenv(cp); 3767 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3768 break; 3769 if (strncmp(cp, "08A0", 4) != 0) { 3770 freeenv(cp); 3771 break; 3772 } 3773 freeenv(cp); 3774 if (sub_bus < 0xa) { 3775 sub_bus = 0xa; 3776 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3777 } 3778 break; 3779 } 3780 3781 if (bootverbose) 3782 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3783 if (sec_bus > 0 && sub_bus >= sec_bus) { 3784 start = sec_bus; 3785 end = sub_bus; 3786 count = end - start + 1; 3787 3788 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3789 3790 /* 3791 * If requested, clear secondary bus registers in 3792 * bridge devices to force a complete renumbering 3793 * rather than reserving the existing range. However, 3794 * preserve the existing size. 3795 */ 3796 if (pci_clear_buses) 3797 goto clear; 3798 3799 rid = 0; 3800 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3801 start, end, count, 0); 3802 if (res != NULL) 3803 return; 3804 3805 if (bootverbose) 3806 device_printf(bus, 3807 "pci%d:%d:%d:%d secbus failed to allocate\n", 3808 pci_get_domain(dev), pci_get_bus(dev), 3809 pci_get_slot(dev), pci_get_function(dev)); 3810 } 3811 3812 clear: 3813 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3814 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3815 } 3816 3817 static struct resource * 3818 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3819 rman_res_t end, rman_res_t count, u_int flags) 3820 { 3821 struct pci_devinfo *dinfo; 3822 pcicfgregs *cfg; 3823 struct resource_list *rl; 3824 struct resource *res; 3825 int sec_reg, sub_reg; 3826 3827 dinfo = device_get_ivars(child); 3828 cfg = &dinfo->cfg; 3829 rl = &dinfo->resources; 3830 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3831 case PCIM_HDRTYPE_BRIDGE: 3832 sec_reg = PCIR_SECBUS_1; 3833 sub_reg = PCIR_SUBBUS_1; 3834 break; 3835 case PCIM_HDRTYPE_CARDBUS: 3836 sec_reg = PCIR_SECBUS_2; 3837 sub_reg = PCIR_SUBBUS_2; 3838 break; 3839 default: 3840 return (NULL); 3841 } 3842 3843 if (*rid != 0) 3844 return (NULL); 3845 3846 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3847 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3848 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3849 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3850 start, end, count, flags & ~RF_ACTIVE); 3851 if (res == NULL) { 3852 resource_list_delete(rl, PCI_RES_BUS, *rid); 3853 device_printf(child, "allocating %ju bus%s failed\n", 3854 count, count == 1 ? "" : "es"); 3855 return (NULL); 3856 } 3857 if (bootverbose) 3858 device_printf(child, 3859 "Lazy allocation of %ju bus%s at %ju\n", count, 3860 count == 1 ? "" : "es", rman_get_start(res)); 3861 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3862 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3863 } 3864 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3865 end, count, flags)); 3866 } 3867 3868 static int 3869 pci_ea_bei_to_rid(device_t dev, int bei) 3870 { 3871 #ifdef PCI_IOV 3872 struct pci_devinfo *dinfo; 3873 int iov_pos; 3874 struct pcicfg_iov *iov; 3875 3876 dinfo = device_get_ivars(dev); 3877 iov = dinfo->cfg.iov; 3878 if (iov != NULL) 3879 iov_pos = iov->iov_pos; 3880 else 3881 iov_pos = 0; 3882 #endif 3883 3884 /* Check if matches BAR */ 3885 if ((bei >= PCIM_EA_BEI_BAR_0) && 3886 (bei <= PCIM_EA_BEI_BAR_5)) 3887 return (PCIR_BAR(bei)); 3888 3889 /* Check ROM */ 3890 if (bei == PCIM_EA_BEI_ROM) 3891 return (PCIR_BIOS); 3892 3893 #ifdef PCI_IOV 3894 /* Check if matches VF_BAR */ 3895 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3896 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3897 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3898 iov_pos); 3899 #endif 3900 3901 return (-1); 3902 } 3903 3904 int 3905 pci_ea_is_enabled(device_t dev, int rid) 3906 { 3907 struct pci_ea_entry *ea; 3908 struct pci_devinfo *dinfo; 3909 3910 dinfo = device_get_ivars(dev); 3911 3912 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3913 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3914 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3915 } 3916 3917 return (0); 3918 } 3919 3920 void 3921 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3922 { 3923 struct pci_ea_entry *ea; 3924 struct pci_devinfo *dinfo; 3925 pci_addr_t start, end, count; 3926 struct resource_list *rl; 3927 int type, flags, rid; 3928 struct resource *res; 3929 uint32_t tmp; 3930 #ifdef PCI_IOV 3931 struct pcicfg_iov *iov; 3932 #endif 3933 3934 dinfo = device_get_ivars(dev); 3935 rl = &dinfo->resources; 3936 flags = 0; 3937 3938 #ifdef PCI_IOV 3939 iov = dinfo->cfg.iov; 3940 #endif 3941 3942 if (dinfo->cfg.ea.ea_location == 0) 3943 return; 3944 3945 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3946 /* 3947 * TODO: Ignore EA-BAR if is not enabled. 3948 * Currently the EA implementation supports 3949 * only situation, where EA structure contains 3950 * predefined entries. In case they are not enabled 3951 * leave them unallocated and proceed with 3952 * a legacy-BAR mechanism. 3953 */ 3954 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3955 continue; 3956 3957 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3958 case PCIM_EA_P_MEM_PREFETCH: 3959 case PCIM_EA_P_VF_MEM_PREFETCH: 3960 flags = RF_PREFETCHABLE; 3961 /* FALLTHROUGH */ 3962 case PCIM_EA_P_VF_MEM: 3963 case PCIM_EA_P_MEM: 3964 type = SYS_RES_MEMORY; 3965 break; 3966 case PCIM_EA_P_IO: 3967 type = SYS_RES_IOPORT; 3968 break; 3969 default: 3970 continue; 3971 } 3972 3973 if (alloc_iov != 0) { 3974 #ifdef PCI_IOV 3975 /* Allocating IOV, confirm BEI matches */ 3976 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3977 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3978 continue; 3979 #else 3980 continue; 3981 #endif 3982 } else { 3983 /* Allocating BAR, confirm BEI matches */ 3984 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3985 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3986 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3987 continue; 3988 } 3989 3990 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3991 if (rid < 0) 3992 continue; 3993 3994 /* Skip resources already allocated by EA */ 3995 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3996 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3997 continue; 3998 3999 start = ea->eae_base; 4000 count = ea->eae_max_offset + 1; 4001 #ifdef PCI_IOV 4002 if (iov != NULL) 4003 count = count * iov->iov_num_vfs; 4004 #endif 4005 end = start + count - 1; 4006 if (count == 0) 4007 continue; 4008 4009 resource_list_add(rl, type, rid, start, end, count); 4010 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4011 flags); 4012 if (res == NULL) { 4013 resource_list_delete(rl, type, rid); 4014 4015 /* 4016 * Failed to allocate using EA, disable entry. 4017 * Another attempt to allocation will be performed 4018 * further, but this time using legacy BAR registers 4019 */ 4020 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4021 tmp &= ~PCIM_EA_ENABLE; 4022 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4023 4024 /* 4025 * Disabling entry might fail in case it is hardwired. 4026 * Read flags again to match current status. 4027 */ 4028 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4029 4030 continue; 4031 } 4032 4033 /* As per specification, fill BAR with zeros */ 4034 pci_write_config(dev, rid, 0, 4); 4035 } 4036 } 4037 4038 void 4039 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4040 { 4041 struct pci_devinfo *dinfo; 4042 pcicfgregs *cfg; 4043 struct resource_list *rl; 4044 const struct pci_quirk *q; 4045 uint32_t devid; 4046 int i; 4047 4048 dinfo = device_get_ivars(dev); 4049 cfg = &dinfo->cfg; 4050 rl = &dinfo->resources; 4051 devid = (cfg->device << 16) | cfg->vendor; 4052 4053 /* Allocate resources using Enhanced Allocation */ 4054 pci_add_resources_ea(bus, dev, 0); 4055 4056 /* ATA devices needs special map treatment */ 4057 if ((pci_get_class(dev) == PCIC_STORAGE) && 4058 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4059 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4060 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4061 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4062 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4063 else 4064 for (i = 0; i < cfg->nummaps;) { 4065 /* Skip resources already managed by EA */ 4066 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4067 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4068 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4069 i++; 4070 continue; 4071 } 4072 4073 /* 4074 * Skip quirked resources. 4075 */ 4076 for (q = &pci_quirks[0]; q->devid != 0; q++) 4077 if (q->devid == devid && 4078 q->type == PCI_QUIRK_UNMAP_REG && 4079 q->arg1 == PCIR_BAR(i)) 4080 break; 4081 if (q->devid != 0) { 4082 i++; 4083 continue; 4084 } 4085 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4086 prefetchmask & (1 << i)); 4087 } 4088 4089 /* 4090 * Add additional, quirked resources. 4091 */ 4092 for (q = &pci_quirks[0]; q->devid != 0; q++) 4093 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4094 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4095 4096 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4097 /* 4098 * Try to re-route interrupts. Sometimes the BIOS or 4099 * firmware may leave bogus values in these registers. 4100 * If the re-route fails, then just stick with what we 4101 * have. 4102 */ 4103 pci_assign_interrupt(bus, dev, 1); 4104 } 4105 4106 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4107 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4108 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4109 xhci_early_takeover(dev); 4110 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4111 ehci_early_takeover(dev); 4112 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4113 ohci_early_takeover(dev); 4114 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4115 uhci_early_takeover(dev); 4116 } 4117 4118 /* 4119 * Reserve resources for secondary bus ranges behind bridge 4120 * devices. 4121 */ 4122 pci_reserve_secbus(bus, dev, cfg, rl); 4123 } 4124 4125 static struct pci_devinfo * 4126 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4127 int slot, int func) 4128 { 4129 struct pci_devinfo *dinfo; 4130 4131 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4132 if (dinfo != NULL) 4133 pci_add_child(dev, dinfo); 4134 4135 return (dinfo); 4136 } 4137 4138 void 4139 pci_add_children(device_t dev, int domain, int busno) 4140 { 4141 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4142 device_t pcib = device_get_parent(dev); 4143 struct pci_devinfo *dinfo; 4144 int maxslots; 4145 int s, f, pcifunchigh; 4146 uint8_t hdrtype; 4147 int first_func; 4148 4149 /* 4150 * Try to detect a device at slot 0, function 0. If it exists, try to 4151 * enable ARI. We must enable ARI before detecting the rest of the 4152 * functions on this bus as ARI changes the set of slots and functions 4153 * that are legal on this bus. 4154 */ 4155 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4156 if (dinfo != NULL && pci_enable_ari) 4157 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4158 4159 /* 4160 * Start looking for new devices on slot 0 at function 1 because we 4161 * just identified the device at slot 0, function 0. 4162 */ 4163 first_func = 1; 4164 4165 maxslots = PCIB_MAXSLOTS(pcib); 4166 for (s = 0; s <= maxslots; s++, first_func = 0) { 4167 pcifunchigh = 0; 4168 f = 0; 4169 DELAY(1); 4170 4171 /* If function 0 is not present, skip to the next slot. */ 4172 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4173 continue; 4174 hdrtype = REG(PCIR_HDRTYPE, 1); 4175 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4176 continue; 4177 if (hdrtype & PCIM_MFDEV) 4178 pcifunchigh = PCIB_MAXFUNCS(pcib); 4179 for (f = first_func; f <= pcifunchigh; f++) 4180 pci_identify_function(pcib, dev, domain, busno, s, f); 4181 } 4182 #undef REG 4183 } 4184 4185 int 4186 pci_rescan_method(device_t dev) 4187 { 4188 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4189 device_t pcib = device_get_parent(dev); 4190 device_t child, *devlist, *unchanged; 4191 int devcount, error, i, j, maxslots, oldcount; 4192 int busno, domain, s, f, pcifunchigh; 4193 uint8_t hdrtype; 4194 4195 /* No need to check for ARI on a rescan. */ 4196 error = device_get_children(dev, &devlist, &devcount); 4197 if (error) 4198 return (error); 4199 if (devcount != 0) { 4200 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4201 M_NOWAIT | M_ZERO); 4202 if (unchanged == NULL) { 4203 free(devlist, M_TEMP); 4204 return (ENOMEM); 4205 } 4206 } else 4207 unchanged = NULL; 4208 4209 domain = pcib_get_domain(dev); 4210 busno = pcib_get_bus(dev); 4211 maxslots = PCIB_MAXSLOTS(pcib); 4212 for (s = 0; s <= maxslots; s++) { 4213 /* If function 0 is not present, skip to the next slot. */ 4214 f = 0; 4215 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4216 continue; 4217 pcifunchigh = 0; 4218 hdrtype = REG(PCIR_HDRTYPE, 1); 4219 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4220 continue; 4221 if (hdrtype & PCIM_MFDEV) 4222 pcifunchigh = PCIB_MAXFUNCS(pcib); 4223 for (f = 0; f <= pcifunchigh; f++) { 4224 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4225 continue; 4226 4227 /* 4228 * Found a valid function. Check if a 4229 * device_t for this device already exists. 4230 */ 4231 for (i = 0; i < devcount; i++) { 4232 child = devlist[i]; 4233 if (child == NULL) 4234 continue; 4235 if (pci_get_slot(child) == s && 4236 pci_get_function(child) == f) { 4237 unchanged[i] = child; 4238 goto next_func; 4239 } 4240 } 4241 4242 pci_identify_function(pcib, dev, domain, busno, s, f); 4243 next_func:; 4244 } 4245 } 4246 4247 /* Remove devices that are no longer present. */ 4248 for (i = 0; i < devcount; i++) { 4249 if (unchanged[i] != NULL) 4250 continue; 4251 device_delete_child(dev, devlist[i]); 4252 } 4253 4254 free(devlist, M_TEMP); 4255 oldcount = devcount; 4256 4257 /* Try to attach the devices just added. */ 4258 error = device_get_children(dev, &devlist, &devcount); 4259 if (error) { 4260 free(unchanged, M_TEMP); 4261 return (error); 4262 } 4263 4264 for (i = 0; i < devcount; i++) { 4265 for (j = 0; j < oldcount; j++) { 4266 if (devlist[i] == unchanged[j]) 4267 goto next_device; 4268 } 4269 4270 device_probe_and_attach(devlist[i]); 4271 next_device:; 4272 } 4273 4274 free(unchanged, M_TEMP); 4275 free(devlist, M_TEMP); 4276 return (0); 4277 #undef REG 4278 } 4279 4280 #ifdef PCI_IOV 4281 device_t 4282 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4283 uint16_t did) 4284 { 4285 struct pci_devinfo *vf_dinfo; 4286 device_t pcib; 4287 int busno, slot, func; 4288 4289 pcib = device_get_parent(bus); 4290 4291 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4292 4293 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4294 slot, func, vid, did); 4295 4296 vf_dinfo->cfg.flags |= PCICFG_VF; 4297 pci_add_child(bus, vf_dinfo); 4298 4299 return (vf_dinfo->cfg.dev); 4300 } 4301 4302 device_t 4303 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4304 uint16_t vid, uint16_t did) 4305 { 4306 4307 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4308 } 4309 #endif 4310 4311 /* 4312 * For PCIe device set Max_Payload_Size to match PCIe root's. 4313 */ 4314 static void 4315 pcie_setup_mps(device_t dev) 4316 { 4317 struct pci_devinfo *dinfo = device_get_ivars(dev); 4318 device_t root; 4319 uint16_t rmps, mmps, mps; 4320 4321 if (dinfo->cfg.pcie.pcie_location == 0) 4322 return; 4323 root = pci_find_pcie_root_port(dev); 4324 if (root == NULL) 4325 return; 4326 /* Check whether the MPS is already configured. */ 4327 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4328 PCIEM_CTL_MAX_PAYLOAD; 4329 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4330 PCIEM_CTL_MAX_PAYLOAD; 4331 if (mps == rmps) 4332 return; 4333 /* Check whether the device is capable of the root's MPS. */ 4334 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4335 PCIEM_CAP_MAX_PAYLOAD) << 5; 4336 if (rmps > mmps) { 4337 /* 4338 * The device is unable to handle root's MPS. Limit root. 4339 * XXX: We should traverse through all the tree, applying 4340 * it to all the devices. 4341 */ 4342 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4343 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4344 } else { 4345 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4346 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4347 } 4348 } 4349 4350 static void 4351 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4352 { 4353 int aer; 4354 uint32_t r; 4355 uint16_t r2; 4356 4357 if (dinfo->cfg.pcie.pcie_location != 0 && 4358 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4359 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4360 PCIER_ROOT_CTL, 2); 4361 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4362 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4363 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4364 PCIER_ROOT_CTL, r2, 2); 4365 } 4366 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4367 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4368 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4369 if (r != 0 && bootverbose) { 4370 pci_printf(&dinfo->cfg, 4371 "clearing AER UC 0x%08x -> 0x%08x\n", 4372 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4373 4)); 4374 } 4375 4376 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4377 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4378 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4379 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4380 PCIM_AER_UC_POISONED_TLP | 4381 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4382 PCIM_AER_UC_COMPLETION_TIMEOUT | 4383 PCIM_AER_UC_COMPLETER_ABORT | 4384 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4385 PCIM_AER_UC_RECEIVER_OVERFLOW | 4386 PCIM_AER_UC_MALFORMED_TLP | 4387 PCIM_AER_UC_ECRC_ERROR | 4388 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4389 PCIM_AER_UC_ACS_VIOLATION | 4390 PCIM_AER_UC_INTERNAL_ERROR | 4391 PCIM_AER_UC_MC_BLOCKED_TLP | 4392 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4393 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4394 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4395 4396 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4397 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4398 if (r != 0 && bootverbose) { 4399 pci_printf(&dinfo->cfg, 4400 "clearing AER COR 0x%08x -> 0x%08x\n", 4401 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4402 4)); 4403 } 4404 4405 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4406 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4407 PCIM_AER_COR_BAD_TLP | 4408 PCIM_AER_COR_BAD_DLLP | 4409 PCIM_AER_COR_REPLAY_ROLLOVER | 4410 PCIM_AER_COR_REPLAY_TIMEOUT | 4411 PCIM_AER_COR_ADVISORY_NF_ERROR | 4412 PCIM_AER_COR_INTERNAL_ERROR | 4413 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4414 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4415 4416 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4417 PCIER_DEVICE_CTL, 2); 4418 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4419 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4420 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4421 PCIER_DEVICE_CTL, r, 2); 4422 } 4423 } 4424 4425 void 4426 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4427 { 4428 device_t dev; 4429 4430 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4431 device_set_ivars(dev, dinfo); 4432 resource_list_init(&dinfo->resources); 4433 pci_cfg_save(dev, dinfo, 0); 4434 pci_cfg_restore(dev, dinfo); 4435 pci_print_verbose(dinfo); 4436 pci_add_resources(bus, dev, 0, 0); 4437 if (pci_enable_mps_tune) 4438 pcie_setup_mps(dev); 4439 pci_child_added(dinfo->cfg.dev); 4440 4441 if (pci_clear_aer_on_attach) 4442 pci_add_child_clear_aer(dev, dinfo); 4443 4444 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4445 } 4446 4447 void 4448 pci_child_added_method(device_t dev, device_t child) 4449 { 4450 4451 } 4452 4453 static int 4454 pci_probe(device_t dev) 4455 { 4456 4457 device_set_desc(dev, "PCI bus"); 4458 4459 /* Allow other subclasses to override this driver. */ 4460 return (BUS_PROBE_GENERIC); 4461 } 4462 4463 int 4464 pci_attach_common(device_t dev) 4465 { 4466 struct pci_softc *sc; 4467 int busno, domain; 4468 int rid; 4469 4470 sc = device_get_softc(dev); 4471 domain = pcib_get_domain(dev); 4472 busno = pcib_get_bus(dev); 4473 rid = 0; 4474 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4475 1, 0); 4476 if (sc->sc_bus == NULL) { 4477 device_printf(dev, "failed to allocate bus number\n"); 4478 return (ENXIO); 4479 } 4480 if (bootverbose) 4481 device_printf(dev, "domain=%d, physical bus=%d\n", 4482 domain, busno); 4483 sc->sc_dma_tag = bus_get_dma_tag(dev); 4484 return (0); 4485 } 4486 4487 int 4488 pci_attach(device_t dev) 4489 { 4490 int busno, domain, error; 4491 4492 error = pci_attach_common(dev); 4493 if (error) 4494 return (error); 4495 4496 /* 4497 * Since there can be multiple independently numbered PCI 4498 * buses on systems with multiple PCI domains, we can't use 4499 * the unit number to decide which bus we are probing. We ask 4500 * the parent pcib what our domain and bus numbers are. 4501 */ 4502 domain = pcib_get_domain(dev); 4503 busno = pcib_get_bus(dev); 4504 pci_add_children(dev, domain, busno); 4505 bus_attach_children(dev); 4506 return (0); 4507 } 4508 4509 int 4510 pci_detach(device_t dev) 4511 { 4512 struct pci_softc *sc; 4513 int error; 4514 4515 error = bus_generic_detach(dev); 4516 if (error) 4517 return (error); 4518 sc = device_get_softc(dev); 4519 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4520 return (error); 4521 } 4522 4523 static void 4524 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4525 { 4526 int line, unit; 4527 const char *at; 4528 char me1[24], me2[32]; 4529 uint8_t b, s, f; 4530 uint32_t d; 4531 device_location_cache_t *cache; 4532 4533 d = pci_get_domain(child); 4534 b = pci_get_bus(child); 4535 s = pci_get_slot(child); 4536 f = pci_get_function(child); 4537 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4538 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4539 line = 0; 4540 cache = dev_wired_cache_init(); 4541 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4542 resource_string_value(name, unit, "at", &at); 4543 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4544 *unitp = unit; 4545 break; 4546 } 4547 if (dev_wired_cache_match(cache, child, at)) { 4548 *unitp = unit; 4549 break; 4550 } 4551 } 4552 dev_wired_cache_fini(cache); 4553 } 4554 4555 static void 4556 pci_set_power_child(device_t dev, device_t child, int state) 4557 { 4558 device_t pcib; 4559 int dstate; 4560 4561 /* 4562 * Set the device to the given state. If the firmware suggests 4563 * a different power state, use it instead. If power management 4564 * is not present, the firmware is responsible for managing 4565 * device power. Skip children who aren't attached since they 4566 * are handled separately. 4567 */ 4568 pcib = device_get_parent(dev); 4569 dstate = state; 4570 if (device_is_attached(child) && 4571 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4572 pci_set_powerstate(child, dstate); 4573 } 4574 4575 int 4576 pci_suspend_child(device_t dev, device_t child) 4577 { 4578 struct pci_devinfo *dinfo; 4579 struct resource_list_entry *rle; 4580 int error; 4581 4582 dinfo = device_get_ivars(child); 4583 4584 /* 4585 * Save the PCI configuration space for the child and set the 4586 * device in the appropriate power state for this sleep state. 4587 */ 4588 pci_cfg_save(child, dinfo, 0); 4589 4590 /* Suspend devices before potentially powering them down. */ 4591 error = bus_generic_suspend_child(dev, child); 4592 4593 if (error) 4594 return (error); 4595 4596 if (pci_do_power_suspend) { 4597 /* 4598 * Make sure this device's interrupt handler is not invoked 4599 * in the case the device uses a shared interrupt that can 4600 * be raised by some other device. 4601 * This is applicable only to regular (legacy) PCI interrupts 4602 * as MSI/MSI-X interrupts are never shared. 4603 */ 4604 rle = resource_list_find(&dinfo->resources, 4605 SYS_RES_IRQ, 0); 4606 if (rle != NULL && rle->res != NULL) 4607 (void)bus_suspend_intr(child, rle->res); 4608 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4609 } 4610 4611 return (0); 4612 } 4613 4614 int 4615 pci_resume_child(device_t dev, device_t child) 4616 { 4617 struct pci_devinfo *dinfo; 4618 struct resource_list_entry *rle; 4619 4620 if (pci_do_power_resume) 4621 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4622 4623 dinfo = device_get_ivars(child); 4624 pci_cfg_restore(child, dinfo); 4625 if (!device_is_attached(child)) 4626 pci_cfg_save(child, dinfo, 1); 4627 4628 bus_generic_resume_child(dev, child); 4629 4630 /* 4631 * Allow interrupts only after fully resuming the driver and hardware. 4632 */ 4633 if (pci_do_power_suspend) { 4634 /* See pci_suspend_child for details. */ 4635 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4636 if (rle != NULL && rle->res != NULL) 4637 (void)bus_resume_intr(child, rle->res); 4638 } 4639 4640 return (0); 4641 } 4642 4643 int 4644 pci_resume(device_t dev) 4645 { 4646 device_t child, *devlist; 4647 int error, i, numdevs; 4648 4649 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4650 return (error); 4651 4652 /* 4653 * Resume critical devices first, then everything else later. 4654 */ 4655 for (i = 0; i < numdevs; i++) { 4656 child = devlist[i]; 4657 switch (pci_get_class(child)) { 4658 case PCIC_DISPLAY: 4659 case PCIC_MEMORY: 4660 case PCIC_BRIDGE: 4661 case PCIC_BASEPERIPH: 4662 BUS_RESUME_CHILD(dev, child); 4663 break; 4664 } 4665 } 4666 for (i = 0; i < numdevs; i++) { 4667 child = devlist[i]; 4668 switch (pci_get_class(child)) { 4669 case PCIC_DISPLAY: 4670 case PCIC_MEMORY: 4671 case PCIC_BRIDGE: 4672 case PCIC_BASEPERIPH: 4673 break; 4674 default: 4675 BUS_RESUME_CHILD(dev, child); 4676 } 4677 } 4678 free(devlist, M_TEMP); 4679 return (0); 4680 } 4681 4682 static void 4683 pci_load_vendor_data(void) 4684 { 4685 caddr_t data; 4686 void *ptr; 4687 size_t sz; 4688 4689 data = preload_search_by_type("pci_vendor_data"); 4690 if (data != NULL) { 4691 ptr = preload_fetch_addr(data); 4692 sz = preload_fetch_size(data); 4693 if (ptr != NULL && sz != 0) { 4694 pci_vendordata = ptr; 4695 pci_vendordata_size = sz; 4696 /* terminate the database */ 4697 pci_vendordata[pci_vendordata_size] = '\n'; 4698 } 4699 } 4700 } 4701 4702 void 4703 pci_driver_added(device_t dev, driver_t *driver) 4704 { 4705 int numdevs; 4706 device_t *devlist; 4707 device_t child; 4708 struct pci_devinfo *dinfo; 4709 int i; 4710 4711 if (bootverbose) 4712 device_printf(dev, "driver added\n"); 4713 DEVICE_IDENTIFY(driver, dev); 4714 if (device_get_children(dev, &devlist, &numdevs) != 0) 4715 return; 4716 for (i = 0; i < numdevs; i++) { 4717 child = devlist[i]; 4718 if (device_get_state(child) != DS_NOTPRESENT) 4719 continue; 4720 dinfo = device_get_ivars(child); 4721 pci_print_verbose(dinfo); 4722 if (bootverbose) 4723 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4724 pci_cfg_restore(child, dinfo); 4725 if (device_probe_and_attach(child) != 0) 4726 pci_child_detached(dev, child); 4727 } 4728 free(devlist, M_TEMP); 4729 } 4730 4731 int 4732 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4733 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4734 { 4735 struct pci_devinfo *dinfo; 4736 struct msix_table_entry *mte; 4737 struct msix_vector *mv; 4738 uint64_t addr; 4739 uint32_t data; 4740 void *cookie; 4741 int error, rid; 4742 4743 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4744 arg, &cookie); 4745 if (error) 4746 return (error); 4747 4748 /* If this is not a direct child, just bail out. */ 4749 if (device_get_parent(child) != dev) { 4750 *cookiep = cookie; 4751 return(0); 4752 } 4753 4754 rid = rman_get_rid(irq); 4755 if (rid == 0) { 4756 /* Make sure that INTx is enabled */ 4757 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4758 } else { 4759 /* 4760 * Check to see if the interrupt is MSI or MSI-X. 4761 * Ask our parent to map the MSI and give 4762 * us the address and data register values. 4763 * If we fail for some reason, teardown the 4764 * interrupt handler. 4765 */ 4766 dinfo = device_get_ivars(child); 4767 if (dinfo->cfg.msi.msi_alloc > 0) { 4768 if (dinfo->cfg.msi.msi_addr == 0) { 4769 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4770 ("MSI has handlers, but vectors not mapped")); 4771 error = PCIB_MAP_MSI(device_get_parent(dev), 4772 child, rman_get_start(irq), &addr, &data); 4773 if (error) 4774 goto bad; 4775 dinfo->cfg.msi.msi_addr = addr; 4776 dinfo->cfg.msi.msi_data = data; 4777 } 4778 if (dinfo->cfg.msi.msi_handlers == 0) 4779 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4780 dinfo->cfg.msi.msi_data); 4781 dinfo->cfg.msi.msi_handlers++; 4782 } else { 4783 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4784 ("No MSI or MSI-X interrupts allocated")); 4785 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4786 ("MSI-X index too high")); 4787 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4788 KASSERT(mte->mte_vector != 0, ("no message vector")); 4789 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4790 KASSERT(mv->mv_irq == rman_get_start(irq), 4791 ("IRQ mismatch")); 4792 if (mv->mv_address == 0) { 4793 KASSERT(mte->mte_handlers == 0, 4794 ("MSI-X table entry has handlers, but vector not mapped")); 4795 error = PCIB_MAP_MSI(device_get_parent(dev), 4796 child, rman_get_start(irq), &addr, &data); 4797 if (error) 4798 goto bad; 4799 mv->mv_address = addr; 4800 mv->mv_data = data; 4801 } 4802 4803 /* 4804 * The MSIX table entry must be made valid by 4805 * incrementing the mte_handlers before 4806 * calling pci_enable_msix() and 4807 * pci_resume_msix(). Else the MSIX rewrite 4808 * table quirk will not work as expected. 4809 */ 4810 mte->mte_handlers++; 4811 if (mte->mte_handlers == 1) { 4812 pci_enable_msix(child, rid - 1, mv->mv_address, 4813 mv->mv_data); 4814 pci_unmask_msix(child, rid - 1); 4815 } 4816 } 4817 4818 /* 4819 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4820 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4821 * in which case we "enable" INTx so MSI/MSI-X actually works. 4822 */ 4823 if (!pci_has_quirk(pci_get_devid(child), 4824 PCI_QUIRK_MSI_INTX_BUG)) 4825 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4826 else 4827 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4828 bad: 4829 if (error) { 4830 (void)bus_generic_teardown_intr(dev, child, irq, 4831 cookie); 4832 return (error); 4833 } 4834 } 4835 *cookiep = cookie; 4836 return (0); 4837 } 4838 4839 int 4840 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4841 void *cookie) 4842 { 4843 struct msix_table_entry *mte; 4844 struct resource_list_entry *rle; 4845 struct pci_devinfo *dinfo; 4846 int error, rid; 4847 4848 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4849 return (EINVAL); 4850 4851 /* If this isn't a direct child, just bail out */ 4852 if (device_get_parent(child) != dev) 4853 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4854 4855 rid = rman_get_rid(irq); 4856 if (rid == 0) { 4857 /* Mask INTx */ 4858 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4859 } else { 4860 /* 4861 * Check to see if the interrupt is MSI or MSI-X. If so, 4862 * decrement the appropriate handlers count and mask the 4863 * MSI-X message, or disable MSI messages if the count 4864 * drops to 0. 4865 */ 4866 dinfo = device_get_ivars(child); 4867 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4868 if (rle->res != irq) 4869 return (EINVAL); 4870 if (dinfo->cfg.msi.msi_alloc > 0) { 4871 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4872 ("MSI-X index too high")); 4873 if (dinfo->cfg.msi.msi_handlers == 0) 4874 return (EINVAL); 4875 dinfo->cfg.msi.msi_handlers--; 4876 if (dinfo->cfg.msi.msi_handlers == 0) 4877 pci_disable_msi(child); 4878 } else { 4879 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4880 ("No MSI or MSI-X interrupts allocated")); 4881 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4882 ("MSI-X index too high")); 4883 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4884 if (mte->mte_handlers == 0) 4885 return (EINVAL); 4886 mte->mte_handlers--; 4887 if (mte->mte_handlers == 0) 4888 pci_mask_msix(child, rid - 1); 4889 } 4890 } 4891 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4892 if (rid > 0) 4893 KASSERT(error == 0, 4894 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4895 return (error); 4896 } 4897 4898 int 4899 pci_print_child(device_t dev, device_t child) 4900 { 4901 struct pci_devinfo *dinfo; 4902 struct resource_list *rl; 4903 int retval = 0; 4904 4905 dinfo = device_get_ivars(child); 4906 rl = &dinfo->resources; 4907 4908 retval += bus_print_child_header(dev, child); 4909 4910 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4911 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4912 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4913 if (device_get_flags(dev)) 4914 retval += printf(" flags %#x", device_get_flags(dev)); 4915 4916 retval += printf(" at device %d.%d", pci_get_slot(child), 4917 pci_get_function(child)); 4918 4919 retval += bus_print_child_domain(dev, child); 4920 retval += bus_print_child_footer(dev, child); 4921 4922 return (retval); 4923 } 4924 4925 static const struct 4926 { 4927 int class; 4928 int subclass; 4929 int report; /* 0 = bootverbose, 1 = always */ 4930 const char *desc; 4931 } pci_nomatch_tab[] = { 4932 {PCIC_OLD, -1, 1, "old"}, 4933 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4934 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4935 {PCIC_STORAGE, -1, 1, "mass storage"}, 4936 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4937 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4938 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4939 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4940 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4941 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4942 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4943 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4944 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4945 {PCIC_NETWORK, -1, 1, "network"}, 4946 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4947 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4948 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4949 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4950 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4951 {PCIC_DISPLAY, -1, 1, "display"}, 4952 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4953 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4954 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4955 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4956 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4957 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4958 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4959 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4960 {PCIC_MEMORY, -1, 1, "memory"}, 4961 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4962 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4963 {PCIC_BRIDGE, -1, 1, "bridge"}, 4964 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4965 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4966 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4967 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4968 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4969 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4970 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4971 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4972 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4973 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4974 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4975 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4976 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4977 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4978 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4979 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4980 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4981 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4982 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4983 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4984 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4985 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4986 {PCIC_INPUTDEV, -1, 1, "input device"}, 4987 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4988 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4989 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4990 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4991 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4992 {PCIC_DOCKING, -1, 1, "docking station"}, 4993 {PCIC_PROCESSOR, -1, 1, "processor"}, 4994 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4995 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4996 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4997 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4998 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4999 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5000 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5001 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5002 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5003 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5004 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5005 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5006 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5007 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5008 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5009 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5010 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5011 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5012 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5013 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5014 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5015 {PCIC_DASP, -1, 0, "dasp"}, 5016 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5017 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5018 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5019 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5020 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5021 {0, 0, 0, NULL} 5022 }; 5023 5024 void 5025 pci_probe_nomatch(device_t dev, device_t child) 5026 { 5027 int i, report; 5028 const char *cp, *scp; 5029 char *device; 5030 5031 /* 5032 * Look for a listing for this device in a loaded device database. 5033 */ 5034 report = 1; 5035 if ((device = pci_describe_device(child)) != NULL) { 5036 device_printf(dev, "<%s>", device); 5037 free(device, M_DEVBUF); 5038 } else { 5039 /* 5040 * Scan the class/subclass descriptions for a general 5041 * description. 5042 */ 5043 cp = "unknown"; 5044 scp = NULL; 5045 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5046 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5047 if (pci_nomatch_tab[i].subclass == -1) { 5048 cp = pci_nomatch_tab[i].desc; 5049 report = pci_nomatch_tab[i].report; 5050 } else if (pci_nomatch_tab[i].subclass == 5051 pci_get_subclass(child)) { 5052 scp = pci_nomatch_tab[i].desc; 5053 report = pci_nomatch_tab[i].report; 5054 } 5055 } 5056 } 5057 if (report || bootverbose) { 5058 device_printf(dev, "<%s%s%s>", 5059 cp ? cp : "", 5060 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5061 scp ? scp : ""); 5062 } 5063 } 5064 if (report || bootverbose) { 5065 printf(" at device %d.%d (no driver attached)\n", 5066 pci_get_slot(child), pci_get_function(child)); 5067 } 5068 pci_cfg_save(child, device_get_ivars(child), 1); 5069 } 5070 5071 void 5072 pci_child_detached(device_t dev, device_t child) 5073 { 5074 struct pci_devinfo *dinfo; 5075 struct resource_list *rl; 5076 5077 dinfo = device_get_ivars(child); 5078 rl = &dinfo->resources; 5079 5080 /* 5081 * Have to deallocate IRQs before releasing any MSI messages and 5082 * have to release MSI messages before deallocating any memory 5083 * BARs. 5084 */ 5085 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5086 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5087 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5088 if (dinfo->cfg.msi.msi_alloc != 0) 5089 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5090 "vectors\n", dinfo->cfg.msi.msi_alloc); 5091 else 5092 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5093 "vectors\n", dinfo->cfg.msix.msix_alloc); 5094 (void)pci_release_msi(child); 5095 } 5096 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5097 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5098 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5099 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5100 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5101 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5102 5103 pci_cfg_save(child, dinfo, 1); 5104 } 5105 5106 /* 5107 * Parse the PCI device database, if loaded, and return a pointer to a 5108 * description of the device. 5109 * 5110 * The database is flat text formatted as follows: 5111 * 5112 * Any line not in a valid format is ignored. 5113 * Lines are terminated with newline '\n' characters. 5114 * 5115 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5116 * the vendor name. 5117 * 5118 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5119 * - devices cannot be listed without a corresponding VENDOR line. 5120 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5121 * another TAB, then the device name. 5122 */ 5123 5124 /* 5125 * Assuming (ptr) points to the beginning of a line in the database, 5126 * return the vendor or device and description of the next entry. 5127 * The value of (vendor) or (device) inappropriate for the entry type 5128 * is set to -1. Returns nonzero at the end of the database. 5129 * 5130 * Note that this is slightly unrobust in the face of corrupt data; 5131 * we attempt to safeguard against this by spamming the end of the 5132 * database with a newline when we initialise. 5133 */ 5134 static int 5135 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5136 { 5137 char *cp = *ptr; 5138 int left; 5139 5140 *device = -1; 5141 *vendor = -1; 5142 **desc = '\0'; 5143 for (;;) { 5144 left = pci_vendordata_size - (cp - pci_vendordata); 5145 if (left <= 0) { 5146 *ptr = cp; 5147 return(1); 5148 } 5149 5150 /* vendor entry? */ 5151 if (*cp != '\t' && 5152 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5153 break; 5154 /* device entry? */ 5155 if (*cp == '\t' && 5156 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5157 break; 5158 5159 /* skip to next line */ 5160 while (*cp != '\n' && left > 0) { 5161 cp++; 5162 left--; 5163 } 5164 if (*cp == '\n') { 5165 cp++; 5166 left--; 5167 } 5168 } 5169 /* skip to next line */ 5170 while (*cp != '\n' && left > 0) { 5171 cp++; 5172 left--; 5173 } 5174 if (*cp == '\n' && left > 0) 5175 cp++; 5176 *ptr = cp; 5177 return(0); 5178 } 5179 5180 static char * 5181 pci_describe_device(device_t dev) 5182 { 5183 int vendor, device; 5184 char *desc, *vp, *dp, *line; 5185 5186 desc = vp = dp = NULL; 5187 5188 /* 5189 * If we have no vendor data, we can't do anything. 5190 */ 5191 if (pci_vendordata == NULL) 5192 goto out; 5193 5194 /* 5195 * Scan the vendor data looking for this device 5196 */ 5197 line = pci_vendordata; 5198 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5199 goto out; 5200 for (;;) { 5201 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5202 goto out; 5203 if (vendor == pci_get_vendor(dev)) 5204 break; 5205 } 5206 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5207 goto out; 5208 for (;;) { 5209 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5210 *dp = 0; 5211 break; 5212 } 5213 if (vendor != -1) { 5214 *dp = 0; 5215 break; 5216 } 5217 if (device == pci_get_device(dev)) 5218 break; 5219 } 5220 if (dp[0] == '\0') 5221 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5222 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5223 NULL) 5224 sprintf(desc, "%s, %s", vp, dp); 5225 out: 5226 if (vp != NULL) 5227 free(vp, M_DEVBUF); 5228 if (dp != NULL) 5229 free(dp, M_DEVBUF); 5230 return(desc); 5231 } 5232 5233 int 5234 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5235 { 5236 struct pci_devinfo *dinfo; 5237 pcicfgregs *cfg; 5238 5239 dinfo = device_get_ivars(child); 5240 cfg = &dinfo->cfg; 5241 5242 switch (which) { 5243 case PCI_IVAR_ETHADDR: 5244 /* 5245 * The generic accessor doesn't deal with failure, so 5246 * we set the return value, then return an error. 5247 */ 5248 *((uint8_t **) result) = NULL; 5249 return (EINVAL); 5250 case PCI_IVAR_SUBVENDOR: 5251 *result = cfg->subvendor; 5252 break; 5253 case PCI_IVAR_SUBDEVICE: 5254 *result = cfg->subdevice; 5255 break; 5256 case PCI_IVAR_VENDOR: 5257 *result = cfg->vendor; 5258 break; 5259 case PCI_IVAR_DEVICE: 5260 *result = cfg->device; 5261 break; 5262 case PCI_IVAR_DEVID: 5263 *result = (cfg->device << 16) | cfg->vendor; 5264 break; 5265 case PCI_IVAR_CLASS: 5266 *result = cfg->baseclass; 5267 break; 5268 case PCI_IVAR_SUBCLASS: 5269 *result = cfg->subclass; 5270 break; 5271 case PCI_IVAR_PROGIF: 5272 *result = cfg->progif; 5273 break; 5274 case PCI_IVAR_REVID: 5275 *result = cfg->revid; 5276 break; 5277 case PCI_IVAR_INTPIN: 5278 *result = cfg->intpin; 5279 break; 5280 case PCI_IVAR_IRQ: 5281 *result = cfg->intline; 5282 break; 5283 case PCI_IVAR_DOMAIN: 5284 *result = cfg->domain; 5285 break; 5286 case PCI_IVAR_BUS: 5287 *result = cfg->bus; 5288 break; 5289 case PCI_IVAR_SLOT: 5290 *result = cfg->slot; 5291 break; 5292 case PCI_IVAR_FUNCTION: 5293 *result = cfg->func; 5294 break; 5295 case PCI_IVAR_CMDREG: 5296 *result = cfg->cmdreg; 5297 break; 5298 case PCI_IVAR_CACHELNSZ: 5299 *result = cfg->cachelnsz; 5300 break; 5301 case PCI_IVAR_MINGNT: 5302 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5303 *result = -1; 5304 return (EINVAL); 5305 } 5306 *result = cfg->mingnt; 5307 break; 5308 case PCI_IVAR_MAXLAT: 5309 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5310 *result = -1; 5311 return (EINVAL); 5312 } 5313 *result = cfg->maxlat; 5314 break; 5315 case PCI_IVAR_LATTIMER: 5316 *result = cfg->lattimer; 5317 break; 5318 default: 5319 return (ENOENT); 5320 } 5321 return (0); 5322 } 5323 5324 int 5325 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5326 { 5327 struct pci_devinfo *dinfo; 5328 5329 dinfo = device_get_ivars(child); 5330 5331 switch (which) { 5332 case PCI_IVAR_INTPIN: 5333 dinfo->cfg.intpin = value; 5334 return (0); 5335 case PCI_IVAR_ETHADDR: 5336 case PCI_IVAR_SUBVENDOR: 5337 case PCI_IVAR_SUBDEVICE: 5338 case PCI_IVAR_VENDOR: 5339 case PCI_IVAR_DEVICE: 5340 case PCI_IVAR_DEVID: 5341 case PCI_IVAR_CLASS: 5342 case PCI_IVAR_SUBCLASS: 5343 case PCI_IVAR_PROGIF: 5344 case PCI_IVAR_REVID: 5345 case PCI_IVAR_IRQ: 5346 case PCI_IVAR_DOMAIN: 5347 case PCI_IVAR_BUS: 5348 case PCI_IVAR_SLOT: 5349 case PCI_IVAR_FUNCTION: 5350 return (EINVAL); /* disallow for now */ 5351 5352 default: 5353 return (ENOENT); 5354 } 5355 } 5356 5357 #include "opt_ddb.h" 5358 #ifdef DDB 5359 #include <ddb/ddb.h> 5360 #include <sys/cons.h> 5361 5362 /* 5363 * List resources based on pci map registers, used for within ddb 5364 */ 5365 5366 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5367 { 5368 struct pci_devinfo *dinfo; 5369 struct devlist *devlist_head; 5370 struct pci_conf *p; 5371 const char *name; 5372 int i, error, none_count; 5373 5374 none_count = 0; 5375 /* get the head of the device queue */ 5376 devlist_head = &pci_devq; 5377 5378 /* 5379 * Go through the list of devices and print out devices 5380 */ 5381 for (error = 0, i = 0, 5382 dinfo = STAILQ_FIRST(devlist_head); 5383 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5384 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5385 /* Populate pd_name and pd_unit */ 5386 name = NULL; 5387 if (dinfo->cfg.dev) 5388 name = device_get_name(dinfo->cfg.dev); 5389 5390 p = &dinfo->conf; 5391 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5392 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5393 (name && *name) ? name : "none", 5394 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5395 none_count++, 5396 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5397 p->pc_sel.pc_func, (p->pc_class << 16) | 5398 (p->pc_subclass << 8) | p->pc_progif, 5399 (p->pc_subdevice << 16) | p->pc_subvendor, 5400 (p->pc_device << 16) | p->pc_vendor, 5401 p->pc_revid, p->pc_hdr); 5402 } 5403 } 5404 #endif /* DDB */ 5405 5406 struct resource * 5407 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5408 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5409 u_int flags) 5410 { 5411 struct pci_devinfo *dinfo = device_get_ivars(child); 5412 struct resource_list *rl = &dinfo->resources; 5413 struct resource *res; 5414 struct pci_map *pm; 5415 uint16_t cmd; 5416 pci_addr_t map, testval; 5417 int mapsize; 5418 5419 res = NULL; 5420 5421 /* If rid is managed by EA, ignore it */ 5422 if (pci_ea_is_enabled(child, *rid)) 5423 goto out; 5424 5425 pm = pci_find_bar(child, *rid); 5426 if (pm != NULL) { 5427 /* This is a BAR that we failed to allocate earlier. */ 5428 mapsize = pm->pm_size; 5429 map = pm->pm_value; 5430 } else { 5431 /* 5432 * Weed out the bogons, and figure out how large the 5433 * BAR/map is. BARs that read back 0 here are bogus 5434 * and unimplemented. Note: atapci in legacy mode are 5435 * special and handled elsewhere in the code. If you 5436 * have a atapci device in legacy mode and it fails 5437 * here, that other code is broken. 5438 */ 5439 pci_read_bar(child, *rid, &map, &testval, NULL); 5440 5441 /* 5442 * Determine the size of the BAR and ignore BARs with a size 5443 * of 0. Device ROM BARs use a different mask value. 5444 */ 5445 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5446 mapsize = pci_romsize(testval); 5447 else 5448 mapsize = pci_mapsize(testval); 5449 if (mapsize == 0) 5450 goto out; 5451 pm = pci_add_bar(child, *rid, map, mapsize); 5452 } 5453 5454 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5455 if (type != SYS_RES_MEMORY) { 5456 if (bootverbose) 5457 device_printf(dev, 5458 "child %s requested type %d for rid %#x," 5459 " but the BAR says it is an memio\n", 5460 device_get_nameunit(child), type, *rid); 5461 goto out; 5462 } 5463 } else { 5464 if (type != SYS_RES_IOPORT) { 5465 if (bootverbose) 5466 device_printf(dev, 5467 "child %s requested type %d for rid %#x," 5468 " but the BAR says it is an ioport\n", 5469 device_get_nameunit(child), type, *rid); 5470 goto out; 5471 } 5472 } 5473 5474 /* 5475 * For real BARs, we need to override the size that 5476 * the driver requests, because that's what the BAR 5477 * actually uses and we would otherwise have a 5478 * situation where we might allocate the excess to 5479 * another driver, which won't work. 5480 */ 5481 count = ((pci_addr_t)1 << mapsize) * num; 5482 if (RF_ALIGNMENT(flags) < mapsize) 5483 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5484 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5485 flags |= RF_PREFETCHABLE; 5486 5487 /* 5488 * Allocate enough resource, and then write back the 5489 * appropriate BAR for that resource. 5490 */ 5491 resource_list_add(rl, type, *rid, start, end, count); 5492 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5493 count, flags & ~RF_ACTIVE); 5494 if (res == NULL) { 5495 resource_list_delete(rl, type, *rid); 5496 device_printf(child, 5497 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5498 count, *rid, type, start, end); 5499 goto out; 5500 } 5501 if (bootverbose) 5502 device_printf(child, 5503 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5504 count, *rid, type, rman_get_start(res)); 5505 5506 /* Disable decoding via the CMD register before updating the BAR */ 5507 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5508 pci_write_config(child, PCIR_COMMAND, 5509 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5510 5511 map = rman_get_start(res); 5512 pci_write_bar(child, pm, map); 5513 5514 /* Restore the original value of the CMD register */ 5515 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5516 out: 5517 return (res); 5518 } 5519 5520 struct resource * 5521 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5522 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5523 u_int flags) 5524 { 5525 struct pci_devinfo *dinfo; 5526 struct resource_list *rl; 5527 struct resource_list_entry *rle; 5528 struct resource *res; 5529 pcicfgregs *cfg; 5530 5531 /* 5532 * Perform lazy resource allocation 5533 */ 5534 dinfo = device_get_ivars(child); 5535 rl = &dinfo->resources; 5536 cfg = &dinfo->cfg; 5537 switch (type) { 5538 case PCI_RES_BUS: 5539 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5540 flags)); 5541 case SYS_RES_IRQ: 5542 /* 5543 * Can't alloc legacy interrupt once MSI messages have 5544 * been allocated. 5545 */ 5546 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5547 cfg->msix.msix_alloc > 0)) 5548 return (NULL); 5549 5550 /* 5551 * If the child device doesn't have an interrupt 5552 * routed and is deserving of an interrupt, try to 5553 * assign it one. 5554 */ 5555 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5556 (cfg->intpin != 0)) 5557 pci_assign_interrupt(dev, child, 0); 5558 break; 5559 case SYS_RES_IOPORT: 5560 case SYS_RES_MEMORY: 5561 /* 5562 * PCI-PCI bridge I/O window resources are not BARs. 5563 * For those allocations just pass the request up the 5564 * tree. 5565 */ 5566 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5567 switch (*rid) { 5568 case PCIR_IOBASEL_1: 5569 case PCIR_MEMBASE_1: 5570 case PCIR_PMBASEL_1: 5571 /* 5572 * XXX: Should we bother creating a resource 5573 * list entry? 5574 */ 5575 return (bus_generic_alloc_resource(dev, child, 5576 type, rid, start, end, count, flags)); 5577 } 5578 } 5579 /* Reserve resources for this BAR if needed. */ 5580 rle = resource_list_find(rl, type, *rid); 5581 if (rle == NULL) { 5582 res = pci_reserve_map(dev, child, type, rid, start, end, 5583 count, num, flags); 5584 if (res == NULL) 5585 return (NULL); 5586 } 5587 } 5588 return (resource_list_alloc(rl, dev, child, type, rid, 5589 start, end, count, flags)); 5590 } 5591 5592 struct resource * 5593 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5594 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5595 { 5596 #ifdef PCI_IOV 5597 struct pci_devinfo *dinfo; 5598 #endif 5599 5600 if (device_get_parent(child) != dev) 5601 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5602 type, rid, start, end, count, flags)); 5603 5604 #ifdef PCI_IOV 5605 dinfo = device_get_ivars(child); 5606 if (dinfo->cfg.flags & PCICFG_VF) { 5607 switch (type) { 5608 /* VFs can't have I/O BARs. */ 5609 case SYS_RES_IOPORT: 5610 return (NULL); 5611 case SYS_RES_MEMORY: 5612 return (pci_vf_alloc_mem_resource(dev, child, rid, 5613 start, end, count, flags)); 5614 } 5615 5616 /* Fall through for other types of resource allocations. */ 5617 } 5618 #endif 5619 5620 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5621 count, 1, flags)); 5622 } 5623 5624 int 5625 pci_release_resource(device_t dev, device_t child, struct resource *r) 5626 { 5627 struct pci_devinfo *dinfo; 5628 struct resource_list *rl; 5629 pcicfgregs *cfg __unused; 5630 5631 if (device_get_parent(child) != dev) 5632 return (bus_generic_release_resource(dev, child, r)); 5633 5634 dinfo = device_get_ivars(child); 5635 cfg = &dinfo->cfg; 5636 5637 #ifdef PCI_IOV 5638 if (cfg->flags & PCICFG_VF) { 5639 switch (rman_get_type(r)) { 5640 /* VFs can't have I/O BARs. */ 5641 case SYS_RES_IOPORT: 5642 return (EDOOFUS); 5643 case SYS_RES_MEMORY: 5644 return (pci_vf_release_mem_resource(dev, child, r)); 5645 } 5646 5647 /* Fall through for other types of resource allocations. */ 5648 } 5649 #endif 5650 5651 /* 5652 * PCI-PCI bridge I/O window resources are not BARs. For 5653 * those allocations just pass the request up the tree. 5654 */ 5655 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5656 (rman_get_type(r) == SYS_RES_IOPORT || 5657 rman_get_type(r) == SYS_RES_MEMORY)) { 5658 switch (rman_get_rid(r)) { 5659 case PCIR_IOBASEL_1: 5660 case PCIR_MEMBASE_1: 5661 case PCIR_PMBASEL_1: 5662 return (bus_generic_release_resource(dev, child, r)); 5663 } 5664 } 5665 5666 rl = &dinfo->resources; 5667 return (resource_list_release(rl, dev, child, r)); 5668 } 5669 5670 int 5671 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5672 { 5673 struct pci_devinfo *dinfo; 5674 int error, rid, type; 5675 5676 if (device_get_parent(child) != dev) 5677 return (bus_generic_activate_resource(dev, child, r)); 5678 5679 dinfo = device_get_ivars(child); 5680 #ifdef PCI_IOV 5681 if (dinfo->cfg.flags & PCICFG_VF) { 5682 switch (rman_get_type(r)) { 5683 /* VFs can't have I/O BARs. */ 5684 case SYS_RES_IOPORT: 5685 error = EINVAL; 5686 break; 5687 case SYS_RES_MEMORY: 5688 error = pci_vf_activate_mem_resource(dev, child, r); 5689 break; 5690 default: 5691 error = bus_generic_activate_resource(dev, child, r); 5692 break; 5693 } 5694 } else 5695 #endif 5696 error = bus_generic_activate_resource(dev, child, r); 5697 if (error) 5698 return (error); 5699 5700 rid = rman_get_rid(r); 5701 type = rman_get_type(r); 5702 5703 /* Device ROMs need their decoding explicitly enabled. */ 5704 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5705 pci_write_bar(child, pci_find_bar(child, rid), 5706 rman_get_start(r) | PCIM_BIOS_ENABLE); 5707 5708 /* Enable decoding in the command register when activating BARs. */ 5709 switch (type) { 5710 case SYS_RES_IOPORT: 5711 case SYS_RES_MEMORY: 5712 error = PCI_ENABLE_IO(dev, child, type); 5713 break; 5714 } 5715 return (error); 5716 } 5717 5718 int 5719 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5720 { 5721 struct pci_devinfo *dinfo; 5722 int error, rid, type; 5723 5724 if (device_get_parent(child) != dev) 5725 return (bus_generic_deactivate_resource(dev, child, r)); 5726 5727 dinfo = device_get_ivars(child); 5728 #ifdef PCI_IOV 5729 if (dinfo->cfg.flags & PCICFG_VF) { 5730 switch (rman_get_type(r)) { 5731 /* VFs can't have I/O BARs. */ 5732 case SYS_RES_IOPORT: 5733 error = EINVAL; 5734 break; 5735 case SYS_RES_MEMORY: 5736 error = pci_vf_deactivate_mem_resource(dev, child, r); 5737 break; 5738 default: 5739 error = bus_generic_deactivate_resource(dev, child, r); 5740 break; 5741 } 5742 } else 5743 #endif 5744 error = bus_generic_deactivate_resource(dev, child, r); 5745 if (error) 5746 return (error); 5747 5748 /* Disable decoding for device ROMs. */ 5749 rid = rman_get_rid(r); 5750 type = rman_get_type(r); 5751 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5752 pci_write_bar(child, pci_find_bar(child, rid), 5753 rman_get_start(r)); 5754 return (0); 5755 } 5756 5757 int 5758 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5759 rman_res_t start, rman_res_t end) 5760 { 5761 #ifdef PCI_IOV 5762 struct pci_devinfo *dinfo; 5763 5764 if (device_get_parent(child) != dev) 5765 return (bus_generic_adjust_resource(dev, child, r, start, 5766 end)); 5767 5768 dinfo = device_get_ivars(child); 5769 if (dinfo->cfg.flags & PCICFG_VF) { 5770 switch (rman_get_type(r)) { 5771 /* VFs can't have I/O BARs. */ 5772 case SYS_RES_IOPORT: 5773 return (EINVAL); 5774 case SYS_RES_MEMORY: 5775 return (pci_vf_adjust_mem_resource(dev, child, r, 5776 start, end)); 5777 } 5778 5779 /* Fall through for other types of resource allocations. */ 5780 } 5781 #endif 5782 5783 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5784 } 5785 5786 int 5787 pci_map_resource(device_t dev, device_t child, struct resource *r, 5788 struct resource_map_request *argsp, struct resource_map *map) 5789 { 5790 #ifdef PCI_IOV 5791 struct pci_devinfo *dinfo; 5792 5793 if (device_get_parent(child) != dev) 5794 return (bus_generic_map_resource(dev, child, r, argsp, 5795 map)); 5796 5797 dinfo = device_get_ivars(child); 5798 if (dinfo->cfg.flags & PCICFG_VF) { 5799 switch (rman_get_type(r)) { 5800 /* VFs can't have I/O BARs. */ 5801 case SYS_RES_IOPORT: 5802 return (EINVAL); 5803 case SYS_RES_MEMORY: 5804 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5805 map)); 5806 } 5807 5808 /* Fall through for other types of resource allocations. */ 5809 } 5810 #endif 5811 5812 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5813 } 5814 5815 int 5816 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5817 struct resource_map *map) 5818 { 5819 #ifdef PCI_IOV 5820 struct pci_devinfo *dinfo; 5821 5822 if (device_get_parent(child) != dev) 5823 return (bus_generic_unmap_resource(dev, child, r, map)); 5824 5825 dinfo = device_get_ivars(child); 5826 if (dinfo->cfg.flags & PCICFG_VF) { 5827 switch (rman_get_type(r)) { 5828 /* VFs can't have I/O BARs. */ 5829 case SYS_RES_IOPORT: 5830 return (EINVAL); 5831 case SYS_RES_MEMORY: 5832 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5833 } 5834 5835 /* Fall through for other types of resource allocations. */ 5836 } 5837 #endif 5838 5839 return (bus_generic_unmap_resource(dev, child, r, map)); 5840 } 5841 5842 void 5843 pci_child_deleted(device_t dev, device_t child) 5844 { 5845 struct resource_list_entry *rle; 5846 struct resource_list *rl; 5847 struct pci_devinfo *dinfo; 5848 5849 dinfo = device_get_ivars(child); 5850 rl = &dinfo->resources; 5851 5852 EVENTHANDLER_INVOKE(pci_delete_device, child); 5853 5854 /* Turn off access to resources we're about to free */ 5855 if (bus_child_present(child) != 0) { 5856 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5857 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5858 5859 pci_disable_busmaster(child); 5860 } 5861 5862 /* Free all allocated resources */ 5863 STAILQ_FOREACH(rle, rl, link) { 5864 if (rle->res) { 5865 if (rman_get_flags(rle->res) & RF_ACTIVE || 5866 resource_list_busy(rl, rle->type, rle->rid)) { 5867 pci_printf(&dinfo->cfg, 5868 "Resource still owned, oops. " 5869 "(type=%d, rid=%d, addr=%lx)\n", 5870 rle->type, rle->rid, 5871 rman_get_start(rle->res)); 5872 bus_release_resource(child, rle->type, rle->rid, 5873 rle->res); 5874 } 5875 resource_list_unreserve(rl, dev, child, rle->type, 5876 rle->rid); 5877 } 5878 } 5879 resource_list_free(rl); 5880 5881 pci_freecfg(dinfo); 5882 } 5883 5884 void 5885 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5886 { 5887 struct pci_devinfo *dinfo; 5888 struct resource_list *rl; 5889 struct resource_list_entry *rle; 5890 5891 if (device_get_parent(child) != dev) 5892 return; 5893 5894 dinfo = device_get_ivars(child); 5895 rl = &dinfo->resources; 5896 rle = resource_list_find(rl, type, rid); 5897 if (rle == NULL) 5898 return; 5899 5900 if (rle->res) { 5901 if (rman_get_flags(rle->res) & RF_ACTIVE || 5902 resource_list_busy(rl, type, rid)) { 5903 device_printf(dev, "delete_resource: " 5904 "Resource still owned by child, oops. " 5905 "(type=%d, rid=%d, addr=%jx)\n", 5906 type, rid, rman_get_start(rle->res)); 5907 return; 5908 } 5909 resource_list_unreserve(rl, dev, child, type, rid); 5910 } 5911 resource_list_delete(rl, type, rid); 5912 } 5913 5914 struct resource_list * 5915 pci_get_resource_list (device_t dev, device_t child) 5916 { 5917 struct pci_devinfo *dinfo = device_get_ivars(child); 5918 5919 return (&dinfo->resources); 5920 } 5921 5922 #ifdef IOMMU 5923 bus_dma_tag_t 5924 pci_get_dma_tag(device_t bus, device_t dev) 5925 { 5926 bus_dma_tag_t tag; 5927 struct pci_softc *sc; 5928 5929 if (device_get_parent(dev) == bus) { 5930 /* try iommu and return if it works */ 5931 tag = iommu_get_dma_tag(bus, dev); 5932 } else 5933 tag = NULL; 5934 if (tag == NULL) { 5935 sc = device_get_softc(bus); 5936 tag = sc->sc_dma_tag; 5937 } 5938 return (tag); 5939 } 5940 #else 5941 bus_dma_tag_t 5942 pci_get_dma_tag(device_t bus, device_t dev) 5943 { 5944 struct pci_softc *sc = device_get_softc(bus); 5945 5946 return (sc->sc_dma_tag); 5947 } 5948 #endif 5949 5950 uint32_t 5951 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5952 { 5953 struct pci_devinfo *dinfo = device_get_ivars(child); 5954 pcicfgregs *cfg = &dinfo->cfg; 5955 5956 #ifdef PCI_IOV 5957 /* 5958 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5959 * emulate them here. 5960 */ 5961 if (cfg->flags & PCICFG_VF) { 5962 if (reg == PCIR_VENDOR) { 5963 switch (width) { 5964 case 4: 5965 return (cfg->device << 16 | cfg->vendor); 5966 case 2: 5967 return (cfg->vendor); 5968 case 1: 5969 return (cfg->vendor & 0xff); 5970 default: 5971 return (0xffffffff); 5972 } 5973 } else if (reg == PCIR_DEVICE) { 5974 switch (width) { 5975 /* Note that an unaligned 4-byte read is an error. */ 5976 case 2: 5977 return (cfg->device); 5978 case 1: 5979 return (cfg->device & 0xff); 5980 default: 5981 return (0xffffffff); 5982 } 5983 } 5984 } 5985 #endif 5986 5987 return (PCIB_READ_CONFIG(device_get_parent(dev), 5988 cfg->bus, cfg->slot, cfg->func, reg, width)); 5989 } 5990 5991 void 5992 pci_write_config_method(device_t dev, device_t child, int reg, 5993 uint32_t val, int width) 5994 { 5995 struct pci_devinfo *dinfo = device_get_ivars(child); 5996 pcicfgregs *cfg = &dinfo->cfg; 5997 5998 PCIB_WRITE_CONFIG(device_get_parent(dev), 5999 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6000 } 6001 6002 int 6003 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6004 { 6005 6006 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6007 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6008 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6009 return (0); 6010 } 6011 6012 int 6013 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6014 { 6015 struct pci_devinfo *dinfo; 6016 pcicfgregs *cfg; 6017 6018 dinfo = device_get_ivars(child); 6019 cfg = &dinfo->cfg; 6020 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6021 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6022 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6023 cfg->progif); 6024 return (0); 6025 } 6026 6027 int 6028 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6029 struct sbuf *sb) 6030 { 6031 device_t parent = device_get_parent(bus); 6032 int rv; 6033 6034 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6035 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6036 if (rv == 0) { 6037 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6038 pci_get_function(child)); 6039 } 6040 return (0); 6041 } 6042 return (bus_generic_get_device_path(bus, child, locator, sb)); 6043 } 6044 6045 int 6046 pci_assign_interrupt_method(device_t dev, device_t child) 6047 { 6048 struct pci_devinfo *dinfo = device_get_ivars(child); 6049 pcicfgregs *cfg = &dinfo->cfg; 6050 6051 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6052 cfg->intpin)); 6053 } 6054 6055 static void 6056 pci_lookup(void *arg, const char *name, device_t *dev) 6057 { 6058 long val; 6059 char *end; 6060 int domain, bus, slot, func; 6061 6062 if (*dev != NULL) 6063 return; 6064 6065 /* 6066 * Accept pciconf-style selectors of either pciD:B:S:F or 6067 * pciB:S:F. In the latter case, the domain is assumed to 6068 * be zero. 6069 */ 6070 if (strncmp(name, "pci", 3) != 0) 6071 return; 6072 val = strtol(name + 3, &end, 10); 6073 if (val < 0 || val > INT_MAX || *end != ':') 6074 return; 6075 domain = val; 6076 val = strtol(end + 1, &end, 10); 6077 if (val < 0 || val > INT_MAX || *end != ':') 6078 return; 6079 bus = val; 6080 val = strtol(end + 1, &end, 10); 6081 if (val < 0 || val > INT_MAX) 6082 return; 6083 slot = val; 6084 if (*end == ':') { 6085 val = strtol(end + 1, &end, 10); 6086 if (val < 0 || val > INT_MAX || *end != '\0') 6087 return; 6088 func = val; 6089 } else if (*end == '\0') { 6090 func = slot; 6091 slot = bus; 6092 bus = domain; 6093 domain = 0; 6094 } else 6095 return; 6096 6097 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6098 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6099 return; 6100 6101 *dev = pci_find_dbsf(domain, bus, slot, func); 6102 } 6103 6104 static int 6105 pci_modevent(module_t mod, int what, void *arg) 6106 { 6107 static struct cdev *pci_cdev; 6108 static eventhandler_tag tag; 6109 6110 switch (what) { 6111 case MOD_LOAD: 6112 STAILQ_INIT(&pci_devq); 6113 pci_generation = 0; 6114 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6115 "pci"); 6116 pci_load_vendor_data(); 6117 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6118 1000); 6119 break; 6120 6121 case MOD_UNLOAD: 6122 if (tag != NULL) 6123 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6124 destroy_dev(pci_cdev); 6125 break; 6126 } 6127 6128 return (0); 6129 } 6130 6131 static void 6132 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6133 { 6134 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6135 struct pcicfg_pcie *cfg; 6136 int version, pos; 6137 6138 cfg = &dinfo->cfg.pcie; 6139 pos = cfg->pcie_location; 6140 6141 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6142 6143 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6144 6145 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6146 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6147 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6148 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6149 6150 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6151 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6152 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6153 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6154 6155 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6156 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6157 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6158 6159 if (version > 1) { 6160 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6161 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6162 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6163 } 6164 #undef WREG 6165 } 6166 6167 static void 6168 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6169 { 6170 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6171 dinfo->cfg.pcix.pcix_command, 2); 6172 } 6173 6174 void 6175 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6176 { 6177 6178 /* 6179 * Restore the device to full power mode. We must do this 6180 * before we restore the registers because moving from D3 to 6181 * D0 will cause the chip's BARs and some other registers to 6182 * be reset to some unknown power on reset values. Cut down 6183 * the noise on boot by doing nothing if we are already in 6184 * state D0. 6185 */ 6186 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6187 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6188 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6189 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6190 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6191 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6192 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6193 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6194 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6195 case PCIM_HDRTYPE_NORMAL: 6196 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6197 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6198 break; 6199 case PCIM_HDRTYPE_BRIDGE: 6200 pci_write_config(dev, PCIR_SECLAT_1, 6201 dinfo->cfg.bridge.br_seclat, 1); 6202 pci_write_config(dev, PCIR_SUBBUS_1, 6203 dinfo->cfg.bridge.br_subbus, 1); 6204 pci_write_config(dev, PCIR_SECBUS_1, 6205 dinfo->cfg.bridge.br_secbus, 1); 6206 pci_write_config(dev, PCIR_PRIBUS_1, 6207 dinfo->cfg.bridge.br_pribus, 1); 6208 pci_write_config(dev, PCIR_BRIDGECTL_1, 6209 dinfo->cfg.bridge.br_control, 2); 6210 break; 6211 case PCIM_HDRTYPE_CARDBUS: 6212 pci_write_config(dev, PCIR_SECLAT_2, 6213 dinfo->cfg.bridge.br_seclat, 1); 6214 pci_write_config(dev, PCIR_SUBBUS_2, 6215 dinfo->cfg.bridge.br_subbus, 1); 6216 pci_write_config(dev, PCIR_SECBUS_2, 6217 dinfo->cfg.bridge.br_secbus, 1); 6218 pci_write_config(dev, PCIR_PRIBUS_2, 6219 dinfo->cfg.bridge.br_pribus, 1); 6220 pci_write_config(dev, PCIR_BRIDGECTL_2, 6221 dinfo->cfg.bridge.br_control, 2); 6222 break; 6223 } 6224 pci_restore_bars(dev); 6225 6226 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6227 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6228 6229 /* 6230 * Restore extended capabilities for PCI-Express and PCI-X 6231 */ 6232 if (dinfo->cfg.pcie.pcie_location != 0) 6233 pci_cfg_restore_pcie(dev, dinfo); 6234 if (dinfo->cfg.pcix.pcix_location != 0) 6235 pci_cfg_restore_pcix(dev, dinfo); 6236 6237 /* Restore MSI and MSI-X configurations if they are present. */ 6238 if (dinfo->cfg.msi.msi_location != 0) 6239 pci_resume_msi(dev); 6240 if (dinfo->cfg.msix.msix_location != 0) 6241 pci_resume_msix(dev); 6242 6243 #ifdef PCI_IOV 6244 if (dinfo->cfg.iov != NULL) 6245 pci_iov_cfg_restore(dev, dinfo); 6246 #endif 6247 } 6248 6249 static void 6250 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6251 { 6252 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6253 struct pcicfg_pcie *cfg; 6254 int version, pos; 6255 6256 cfg = &dinfo->cfg.pcie; 6257 pos = cfg->pcie_location; 6258 6259 cfg->pcie_flags = RREG(PCIER_FLAGS); 6260 6261 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6262 6263 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6264 6265 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6266 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6267 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6268 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6269 6270 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6271 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6272 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6273 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6274 6275 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6276 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6277 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6278 6279 if (version > 1) { 6280 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6281 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6282 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6283 } 6284 #undef RREG 6285 } 6286 6287 static void 6288 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6289 { 6290 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6291 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6292 } 6293 6294 void 6295 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6296 { 6297 uint32_t cls; 6298 int ps; 6299 6300 /* 6301 * Some drivers apparently write to these registers w/o updating our 6302 * cached copy. No harm happens if we update the copy, so do so here 6303 * so we can restore them. The COMMAND register is modified by the 6304 * bus w/o updating the cache. This should represent the normally 6305 * writable portion of the 'defined' part of type 0/1/2 headers. 6306 */ 6307 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6308 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6309 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6310 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6311 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6312 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6313 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6314 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6315 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6316 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6317 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6318 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6319 case PCIM_HDRTYPE_NORMAL: 6320 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6321 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6322 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6323 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6324 break; 6325 case PCIM_HDRTYPE_BRIDGE: 6326 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6327 PCIR_SECLAT_1, 1); 6328 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6329 PCIR_SUBBUS_1, 1); 6330 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6331 PCIR_SECBUS_1, 1); 6332 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6333 PCIR_PRIBUS_1, 1); 6334 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6335 PCIR_BRIDGECTL_1, 2); 6336 break; 6337 case PCIM_HDRTYPE_CARDBUS: 6338 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6339 PCIR_SECLAT_2, 1); 6340 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6341 PCIR_SUBBUS_2, 1); 6342 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6343 PCIR_SECBUS_2, 1); 6344 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6345 PCIR_PRIBUS_2, 1); 6346 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6347 PCIR_BRIDGECTL_2, 2); 6348 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6349 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6350 break; 6351 } 6352 6353 if (dinfo->cfg.pcie.pcie_location != 0) 6354 pci_cfg_save_pcie(dev, dinfo); 6355 6356 if (dinfo->cfg.pcix.pcix_location != 0) 6357 pci_cfg_save_pcix(dev, dinfo); 6358 6359 #ifdef PCI_IOV 6360 if (dinfo->cfg.iov != NULL) 6361 pci_iov_cfg_save(dev, dinfo); 6362 #endif 6363 6364 /* 6365 * don't set the state for display devices, base peripherals and 6366 * memory devices since bad things happen when they are powered down. 6367 * We should (a) have drivers that can easily detach and (b) use 6368 * generic drivers for these devices so that some device actually 6369 * attaches. We need to make sure that when we implement (a) we don't 6370 * power the device down on a reattach. 6371 */ 6372 cls = pci_get_class(dev); 6373 if (!setstate) 6374 return; 6375 switch (pci_do_power_nodriver) 6376 { 6377 case 0: /* NO powerdown at all */ 6378 return; 6379 case 1: /* Conservative about what to power down */ 6380 if (cls == PCIC_STORAGE) 6381 return; 6382 /*FALLTHROUGH*/ 6383 case 2: /* Aggressive about what to power down */ 6384 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6385 cls == PCIC_BASEPERIPH) 6386 return; 6387 /*FALLTHROUGH*/ 6388 case 3: /* Power down everything */ 6389 break; 6390 } 6391 /* 6392 * PCI spec says we can only go into D3 state from D0 state. 6393 * Transition from D[12] into D0 before going to D3 state. 6394 */ 6395 ps = pci_get_powerstate(dev); 6396 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6397 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6398 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6399 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6400 } 6401 6402 /* Wrapper APIs suitable for device driver use. */ 6403 void 6404 pci_save_state(device_t dev) 6405 { 6406 struct pci_devinfo *dinfo; 6407 6408 dinfo = device_get_ivars(dev); 6409 pci_cfg_save(dev, dinfo, 0); 6410 } 6411 6412 void 6413 pci_restore_state(device_t dev) 6414 { 6415 struct pci_devinfo *dinfo; 6416 6417 dinfo = device_get_ivars(dev); 6418 pci_cfg_restore(dev, dinfo); 6419 } 6420 6421 static int 6422 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6423 uintptr_t *id) 6424 { 6425 6426 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6427 } 6428 6429 /* Find the upstream port of a given PCI device in a root complex. */ 6430 device_t 6431 pci_find_pcie_root_port(device_t dev) 6432 { 6433 struct pci_devinfo *dinfo; 6434 devclass_t pci_class; 6435 device_t pcib, bus; 6436 6437 pci_class = devclass_find("pci"); 6438 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6439 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6440 6441 /* 6442 * Walk the bridge hierarchy until we find a PCI-e root 6443 * port or a non-PCI device. 6444 */ 6445 for (;;) { 6446 bus = device_get_parent(dev); 6447 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6448 device_get_nameunit(dev))); 6449 6450 pcib = device_get_parent(bus); 6451 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6452 device_get_nameunit(bus))); 6453 6454 /* 6455 * pcib's parent must be a PCI bus for this to be a 6456 * PCI-PCI bridge. 6457 */ 6458 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6459 return (NULL); 6460 6461 dinfo = device_get_ivars(pcib); 6462 if (dinfo->cfg.pcie.pcie_location != 0 && 6463 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6464 return (pcib); 6465 6466 dev = pcib; 6467 } 6468 } 6469 6470 /* 6471 * Wait for pending transactions to complete on a PCI-express function. 6472 * 6473 * The maximum delay is specified in milliseconds in max_delay. Note 6474 * that this function may sleep. 6475 * 6476 * Returns true if the function is idle and false if the timeout is 6477 * exceeded. If dev is not a PCI-express function, this returns true. 6478 */ 6479 bool 6480 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6481 { 6482 struct pci_devinfo *dinfo = device_get_ivars(dev); 6483 uint16_t sta; 6484 int cap; 6485 6486 cap = dinfo->cfg.pcie.pcie_location; 6487 if (cap == 0) 6488 return (true); 6489 6490 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6491 while (sta & PCIEM_STA_TRANSACTION_PND) { 6492 if (max_delay == 0) 6493 return (false); 6494 6495 /* Poll once every 100 milliseconds up to the timeout. */ 6496 if (max_delay > 100) { 6497 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6498 max_delay -= 100; 6499 } else { 6500 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6501 C_HARDCLOCK); 6502 max_delay = 0; 6503 } 6504 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6505 } 6506 6507 return (true); 6508 } 6509 6510 /* 6511 * Determine the maximum Completion Timeout in microseconds. 6512 * 6513 * For non-PCI-express functions this returns 0. 6514 */ 6515 int 6516 pcie_get_max_completion_timeout(device_t dev) 6517 { 6518 struct pci_devinfo *dinfo = device_get_ivars(dev); 6519 int cap; 6520 6521 cap = dinfo->cfg.pcie.pcie_location; 6522 if (cap == 0) 6523 return (0); 6524 6525 /* 6526 * Functions using the 1.x spec use the default timeout range of 6527 * 50 microseconds to 50 milliseconds. Functions that do not 6528 * support programmable timeouts also use this range. 6529 */ 6530 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6531 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6532 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6533 return (50 * 1000); 6534 6535 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6536 PCIEM_CTL2_COMP_TIMO_VAL) { 6537 case PCIEM_CTL2_COMP_TIMO_100US: 6538 return (100); 6539 case PCIEM_CTL2_COMP_TIMO_10MS: 6540 return (10 * 1000); 6541 case PCIEM_CTL2_COMP_TIMO_55MS: 6542 return (55 * 1000); 6543 case PCIEM_CTL2_COMP_TIMO_210MS: 6544 return (210 * 1000); 6545 case PCIEM_CTL2_COMP_TIMO_900MS: 6546 return (900 * 1000); 6547 case PCIEM_CTL2_COMP_TIMO_3500MS: 6548 return (3500 * 1000); 6549 case PCIEM_CTL2_COMP_TIMO_13S: 6550 return (13 * 1000 * 1000); 6551 case PCIEM_CTL2_COMP_TIMO_64S: 6552 return (64 * 1000 * 1000); 6553 default: 6554 return (50 * 1000); 6555 } 6556 } 6557 6558 void 6559 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6560 { 6561 struct pci_devinfo *dinfo = device_get_ivars(dev); 6562 const char *s; 6563 int aer; 6564 uint32_t r, r1; 6565 uint16_t rs; 6566 6567 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6568 s = "Correctable"; 6569 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6570 s = "Uncorrectable (Non-Fatal)"; 6571 else 6572 s = "Uncorrectable (Fatal)"; 6573 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6574 if (aerp) { 6575 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6576 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6577 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6578 } else { 6579 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6580 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6581 } 6582 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6583 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6584 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6585 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6586 printf(" severity 0x%08x first %d\n", 6587 r, rs & 0x1f); 6588 } else 6589 printf("\n"); 6590 } 6591 6592 /* As kind of recovery just report and clear the error statuses. */ 6593 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6594 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6595 if (r != 0) { 6596 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6597 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6598 } 6599 6600 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6601 if (r != 0) { 6602 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6603 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6604 } 6605 } 6606 if (dinfo->cfg.pcie.pcie_location != 0) { 6607 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6608 PCIER_DEVICE_STA, 2); 6609 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6610 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6611 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6612 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6613 PCIER_DEVICE_STA, rs, 2); 6614 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6615 } 6616 } 6617 } 6618 6619 /* 6620 * Perform a Function Level Reset (FLR) on a device. 6621 * 6622 * This function first waits for any pending transactions to complete 6623 * within the timeout specified by max_delay. If transactions are 6624 * still pending, the function will return false without attempting a 6625 * reset. 6626 * 6627 * If dev is not a PCI-express function or does not support FLR, this 6628 * function returns false. 6629 * 6630 * Note that no registers are saved or restored. The caller is 6631 * responsible for saving and restoring any registers including 6632 * PCI-standard registers via pci_save_state() and 6633 * pci_restore_state(). 6634 */ 6635 bool 6636 pcie_flr(device_t dev, u_int max_delay, bool force) 6637 { 6638 struct pci_devinfo *dinfo = device_get_ivars(dev); 6639 uint16_t cmd, ctl; 6640 int compl_delay; 6641 int cap; 6642 6643 cap = dinfo->cfg.pcie.pcie_location; 6644 if (cap == 0) 6645 return (false); 6646 6647 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6648 return (false); 6649 6650 /* 6651 * Disable busmastering to prevent generation of new 6652 * transactions while waiting for the device to go idle. If 6653 * the idle timeout fails, the command register is restored 6654 * which will re-enable busmastering. 6655 */ 6656 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6657 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6658 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6659 if (!force) { 6660 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6661 return (false); 6662 } 6663 pci_printf(&dinfo->cfg, 6664 "Resetting with transactions pending after %d ms\n", 6665 max_delay); 6666 6667 /* 6668 * Extend the post-FLR delay to cover the maximum 6669 * Completion Timeout delay of anything in flight 6670 * during the FLR delay. Enforce a minimum delay of 6671 * at least 10ms. 6672 */ 6673 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6674 if (compl_delay < 10) 6675 compl_delay = 10; 6676 } else 6677 compl_delay = 0; 6678 6679 /* Initiate the reset. */ 6680 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6681 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6682 PCIEM_CTL_INITIATE_FLR, 2); 6683 6684 /* Wait for 100ms. */ 6685 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6686 6687 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6688 PCIEM_STA_TRANSACTION_PND) 6689 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6690 return (true); 6691 } 6692 6693 /* 6694 * Attempt a power-management reset by cycling the device in/out of D3 6695 * state. PCI spec says we can only go into D3 state from D0 state. 6696 * Transition from D[12] into D0 before going to D3 state. 6697 */ 6698 int 6699 pci_power_reset(device_t dev) 6700 { 6701 int ps; 6702 6703 ps = pci_get_powerstate(dev); 6704 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6705 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6706 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6707 pci_set_powerstate(dev, ps); 6708 return (0); 6709 } 6710 6711 /* 6712 * Try link drop and retrain of the downstream port of upstream 6713 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6714 * cause Conventional Hot reset of the device in the slot. 6715 * Alternative, for PCIe, could be the secondary bus reset initiatied 6716 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6717 */ 6718 int 6719 pcie_link_reset(device_t port, int pcie_location) 6720 { 6721 uint16_t v; 6722 6723 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6724 v |= PCIEM_LINK_CTL_LINK_DIS; 6725 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6726 pause_sbt("pcier1", mstosbt(20), 0, 0); 6727 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6728 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6729 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6730 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6731 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6732 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6733 } 6734 6735 static int 6736 pci_reset_post(device_t dev, device_t child) 6737 { 6738 6739 if (dev == device_get_parent(child)) 6740 pci_restore_state(child); 6741 return (0); 6742 } 6743 6744 static int 6745 pci_reset_prepare(device_t dev, device_t child) 6746 { 6747 6748 if (dev == device_get_parent(child)) 6749 pci_save_state(child); 6750 return (0); 6751 } 6752 6753 static int 6754 pci_reset_child(device_t dev, device_t child, int flags) 6755 { 6756 int error; 6757 6758 if (dev == NULL || device_get_parent(child) != dev) 6759 return (0); 6760 if ((flags & DEVF_RESET_DETACH) != 0) { 6761 error = device_get_state(child) == DS_ATTACHED ? 6762 device_detach(child) : 0; 6763 } else { 6764 error = BUS_SUSPEND_CHILD(dev, child); 6765 } 6766 if (error == 0) { 6767 if (!pcie_flr(child, 1000, false)) { 6768 error = BUS_RESET_PREPARE(dev, child); 6769 if (error == 0) 6770 pci_power_reset(child); 6771 BUS_RESET_POST(dev, child); 6772 } 6773 if ((flags & DEVF_RESET_DETACH) != 0) 6774 device_probe_and_attach(child); 6775 else 6776 BUS_RESUME_CHILD(dev, child); 6777 } 6778 return (error); 6779 } 6780 6781 const struct pci_device_table * 6782 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6783 { 6784 bool match; 6785 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6786 6787 vendor = pci_get_vendor(child); 6788 device = pci_get_device(child); 6789 subvendor = pci_get_subvendor(child); 6790 subdevice = pci_get_subdevice(child); 6791 class = pci_get_class(child); 6792 subclass = pci_get_subclass(child); 6793 revid = pci_get_revid(child); 6794 while (nelt-- > 0) { 6795 match = true; 6796 if (id->match_flag_vendor) 6797 match &= vendor == id->vendor; 6798 if (id->match_flag_device) 6799 match &= device == id->device; 6800 if (id->match_flag_subvendor) 6801 match &= subvendor == id->subvendor; 6802 if (id->match_flag_subdevice) 6803 match &= subdevice == id->subdevice; 6804 if (id->match_flag_class) 6805 match &= class == id->class_id; 6806 if (id->match_flag_subclass) 6807 match &= subclass == id->subclass; 6808 if (id->match_flag_revid) 6809 match &= revid == id->revid; 6810 if (match) 6811 return (id); 6812 id++; 6813 } 6814 return (NULL); 6815 } 6816 6817 static void 6818 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6819 { 6820 const char *dev_name; 6821 device_t dev; 6822 6823 dev = dinfo->cfg.dev; 6824 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6825 dinfo->cfg.slot, dinfo->cfg.func); 6826 dev_name = device_get_name(dev); 6827 if (dev_name != NULL) 6828 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6829 } 6830 6831 void 6832 pci_print_faulted_dev(void) 6833 { 6834 struct pci_devinfo *dinfo; 6835 device_t dev; 6836 int aer, i; 6837 uint32_t r1, r2; 6838 uint16_t status; 6839 6840 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6841 dev = dinfo->cfg.dev; 6842 status = pci_read_config(dev, PCIR_STATUS, 2); 6843 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6844 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6845 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6846 if (status != 0) { 6847 pci_print_faulted_dev_name(dinfo); 6848 printf(" error 0x%04x\n", status); 6849 } 6850 if (dinfo->cfg.pcie.pcie_location != 0) { 6851 status = pci_read_config(dev, 6852 dinfo->cfg.pcie.pcie_location + 6853 PCIER_DEVICE_STA, 2); 6854 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6855 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6856 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6857 pci_print_faulted_dev_name(dinfo); 6858 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6859 pci_read_config(dev, 6860 dinfo->cfg.pcie.pcie_location + 6861 PCIER_DEVICE_CTL, 2), 6862 status); 6863 } 6864 } 6865 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6866 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6867 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6868 if (r1 != 0 || r2 != 0) { 6869 pci_print_faulted_dev_name(dinfo); 6870 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6871 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6872 r1, pci_read_config(dev, aer + 6873 PCIR_AER_UC_MASK, 4), 6874 pci_read_config(dev, aer + 6875 PCIR_AER_UC_SEVERITY, 4), 6876 r2, pci_read_config(dev, aer + 6877 PCIR_AER_COR_MASK, 4), 6878 pci_read_config(dev, aer + 6879 PCIR_AER_CAP_CONTROL, 4)); 6880 for (i = 0; i < 4; i++) { 6881 r1 = pci_read_config(dev, aer + 6882 PCIR_AER_HEADER_LOG + i * 4, 4); 6883 printf(" HL%d: 0x%08x\n", i, r1); 6884 } 6885 } 6886 } 6887 } 6888 } 6889 6890 #ifdef DDB 6891 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6892 { 6893 6894 pci_print_faulted_dev(); 6895 } 6896 6897 static void 6898 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6899 { 6900 device_t dev; 6901 int aer; 6902 uint32_t r; 6903 6904 dev = dinfo->cfg.dev; 6905 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6906 PCIER_DEVICE_STA, 2); 6907 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6908 PCIER_DEVICE_STA, r, 2); 6909 6910 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6911 return; 6912 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6913 if (r != 0) 6914 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6915 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6916 if (r != 0) 6917 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6918 } 6919 6920 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 6921 { 6922 struct pci_devinfo *dinfo; 6923 device_t dev; 6924 uint16_t status, status1; 6925 6926 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6927 dev = dinfo->cfg.dev; 6928 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6929 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6930 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6931 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6932 if (status1 != 0) { 6933 status &= ~status1; 6934 pci_write_config(dev, PCIR_STATUS, status, 2); 6935 } 6936 if (dinfo->cfg.pcie.pcie_location != 0) 6937 db_clear_pcie_errors(dinfo); 6938 } 6939 } 6940 #endif 6941