1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 static u_int32_t pci_mapbase(unsigned mapreg); 64 static int pci_maptype(unsigned mapreg); 65 static int pci_mapsize(unsigned testval); 66 static int pci_maprange(unsigned mapreg); 67 static void pci_fixancient(pcicfgregs *cfg); 68 69 static int pci_porten(device_t pcib, int b, int s, int f); 70 static int pci_memen(device_t pcib, int b, int s, int f); 71 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73 static void pci_add_resources(device_t pcib, device_t dev); 74 static int pci_probe(device_t dev); 75 static int pci_attach(device_t dev); 76 static void pci_load_vendor_data(void); 77 static int pci_describe_parse_line(char **ptr, int *vendor, 78 int *device, char **desc); 79 static char *pci_describe_device(device_t dev); 80 static int pci_modevent(module_t mod, int what, void *arg); 81 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 82 pcicfgregs *cfg); 83 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 84 85 static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, pci_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 111 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 112 113 /* PCI interface */ 114 DEVMETHOD(pci_read_config, pci_read_config_method), 115 DEVMETHOD(pci_write_config, pci_write_config_method), 116 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 117 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 118 DEVMETHOD(pci_enable_io, pci_enable_io_method), 119 DEVMETHOD(pci_disable_io, pci_disable_io_method), 120 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 121 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 122 123 { 0, 0 } 124 }; 125 126 static driver_t pci_driver = { 127 "pci", 128 pci_methods, 129 0, /* no softc */ 130 }; 131 132 devclass_t pci_devclass; 133 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 134 MODULE_VERSION(pci, 1); 135 136 static char *pci_vendordata; 137 static size_t pci_vendordata_size; 138 139 140 struct pci_quirk { 141 u_int32_t devid; /* Vendor/device of the card */ 142 int type; 143 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 144 int arg1; 145 int arg2; 146 }; 147 148 struct pci_quirk pci_quirks[] = { 149 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 150 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 153 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 155 { 0 } 156 }; 157 158 /* map register information */ 159 #define PCI_MAPMEM 0x01 /* memory map */ 160 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 161 #define PCI_MAPPORT 0x04 /* port map */ 162 163 struct devlist pci_devq; 164 u_int32_t pci_generation; 165 u_int32_t pci_numdevs = 0; 166 167 /* sysctl vars */ 168 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 169 170 static int pci_enable_io_modes = 1; 171 TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 172 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 173 &pci_enable_io_modes, 1, 174 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 175 enable these bits correctly. We'd like to do this all the time, but there\n\ 176 are some peripherals that this causes problems with."); 177 178 /* Find a device_t by bus/slot/function */ 179 180 device_t 181 pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 182 { 183 struct pci_devinfo *dinfo; 184 185 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 186 if ((dinfo->cfg.bus == bus) && 187 (dinfo->cfg.slot == slot) && 188 (dinfo->cfg.func == func)) { 189 return (dinfo->cfg.dev); 190 } 191 } 192 193 return (NULL); 194 } 195 196 /* Find a device_t by vendor/device ID */ 197 198 device_t 199 pci_find_device(u_int16_t vendor, u_int16_t device) 200 { 201 struct pci_devinfo *dinfo; 202 203 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 204 if ((dinfo->cfg.vendor == vendor) && 205 (dinfo->cfg.device == device)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211 } 212 213 /* return base address of memory or port map */ 214 215 static u_int32_t 216 pci_mapbase(unsigned mapreg) 217 { 218 int mask = 0x03; 219 if ((mapreg & 0x01) == 0) 220 mask = 0x0f; 221 return (mapreg & ~mask); 222 } 223 224 /* return map type of memory or port map */ 225 226 static int 227 pci_maptype(unsigned mapreg) 228 { 229 static u_int8_t maptype[0x10] = { 230 PCI_MAPMEM, PCI_MAPPORT, 231 PCI_MAPMEM, 0, 232 PCI_MAPMEM, PCI_MAPPORT, 233 0, 0, 234 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 235 PCI_MAPMEM|PCI_MAPMEMP, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 0, 0, 238 }; 239 240 return maptype[mapreg & 0x0f]; 241 } 242 243 /* return log2 of map size decoded for memory or port map */ 244 245 static int 246 pci_mapsize(unsigned testval) 247 { 248 int ln2size; 249 250 testval = pci_mapbase(testval); 251 ln2size = 0; 252 if (testval != 0) { 253 while ((testval & 1) == 0) 254 { 255 ln2size++; 256 testval >>= 1; 257 } 258 } 259 return (ln2size); 260 } 261 262 /* return log2 of address range supported by map register */ 263 264 static int 265 pci_maprange(unsigned mapreg) 266 { 267 int ln2range = 0; 268 switch (mapreg & 0x07) { 269 case 0x00: 270 case 0x01: 271 case 0x05: 272 ln2range = 32; 273 break; 274 case 0x02: 275 ln2range = 20; 276 break; 277 case 0x04: 278 ln2range = 64; 279 break; 280 } 281 return (ln2range); 282 } 283 284 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 285 286 static void 287 pci_fixancient(pcicfgregs *cfg) 288 { 289 if (cfg->hdrtype != 0) 290 return; 291 292 /* PCI to PCI bridges use header type 1 */ 293 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 294 cfg->hdrtype = 1; 295 } 296 297 /* extract header type specific config data */ 298 299 static void 300 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 301 { 302 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 303 switch (cfg->hdrtype) { 304 case 0: 305 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 307 cfg->nummaps = PCI_MAXMAPS_0; 308 break; 309 case 1: 310 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 312 cfg->nummaps = PCI_MAXMAPS_1; 313 break; 314 case 2: 315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 break; 319 } 320 #undef REG 321 } 322 323 /* read configuration header into pcicfgregs structure */ 324 325 struct pci_devinfo * 326 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 327 { 328 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 329 pcicfgregs *cfg = NULL; 330 struct pci_devinfo *devlist_entry; 331 struct devlist *devlist_head; 332 333 devlist_head = &pci_devq; 334 335 devlist_entry = NULL; 336 337 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 338 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 cfg = &devlist_entry->cfg; 343 344 cfg->bus = b; 345 cfg->slot = s; 346 cfg->func = f; 347 cfg->vendor = REG(PCIR_VENDOR, 2); 348 cfg->device = REG(PCIR_DEVICE, 2); 349 cfg->cmdreg = REG(PCIR_COMMAND, 2); 350 cfg->statreg = REG(PCIR_STATUS, 2); 351 cfg->baseclass = REG(PCIR_CLASS, 1); 352 cfg->subclass = REG(PCIR_SUBCLASS, 1); 353 cfg->progif = REG(PCIR_PROGIF, 1); 354 cfg->revid = REG(PCIR_REVID, 1); 355 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 357 cfg->lattimer = REG(PCIR_LATTIMER, 1); 358 cfg->intpin = REG(PCIR_INTPIN, 1); 359 cfg->intline = REG(PCIR_INTLINE, 1); 360 361 cfg->mingnt = REG(PCIR_MINGNT, 1); 362 cfg->maxlat = REG(PCIR_MAXLAT, 1); 363 364 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 365 cfg->hdrtype &= ~PCIM_MFDEV; 366 367 pci_fixancient(cfg); 368 pci_hdrtypedata(pcib, b, s, f, cfg); 369 370 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 371 pci_read_extcap(pcib, cfg); 372 373 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 374 375 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 376 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 377 devlist_entry->conf.pc_sel.pc_func = cfg->func; 378 devlist_entry->conf.pc_hdr = cfg->hdrtype; 379 380 devlist_entry->conf.pc_subvendor = cfg->subvendor; 381 devlist_entry->conf.pc_subdevice = cfg->subdevice; 382 devlist_entry->conf.pc_vendor = cfg->vendor; 383 devlist_entry->conf.pc_device = cfg->device; 384 385 devlist_entry->conf.pc_class = cfg->baseclass; 386 devlist_entry->conf.pc_subclass = cfg->subclass; 387 devlist_entry->conf.pc_progif = cfg->progif; 388 devlist_entry->conf.pc_revid = cfg->revid; 389 390 pci_numdevs++; 391 pci_generation++; 392 } 393 return (devlist_entry); 394 #undef REG 395 } 396 397 static void 398 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 399 { 400 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 401 int ptr, nextptr, ptrptr; 402 403 switch (cfg->hdrtype) { 404 case 0: 405 ptrptr = 0x34; 406 break; 407 case 2: 408 ptrptr = 0x14; 409 break; 410 default: 411 return; /* no extended capabilities support */ 412 } 413 nextptr = REG(ptrptr, 1); /* sanity check? */ 414 415 /* 416 * Read capability entries. 417 */ 418 while (nextptr != 0) { 419 /* Sanity check */ 420 if (nextptr > 255) { 421 printf("illegal PCI extended capability offset %d\n", 422 nextptr); 423 return; 424 } 425 /* Find the next entry */ 426 ptr = nextptr; 427 nextptr = REG(ptr + 1, 1); 428 429 /* Process this entry */ 430 switch (REG(ptr, 1)) { 431 case 0x01: /* PCI power management */ 432 if (cfg->pp_cap == 0) { 433 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 434 cfg->pp_status = ptr + PCIR_POWER_STATUS; 435 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 436 if ((nextptr - ptr) > PCIR_POWER_DATA) 437 cfg->pp_data = ptr + PCIR_POWER_DATA; 438 } 439 break; 440 default: 441 break; 442 } 443 } 444 #undef REG 445 } 446 447 /* free pcicfgregs structure and all depending data structures */ 448 449 int 450 pci_freecfg(struct pci_devinfo *dinfo) 451 { 452 struct devlist *devlist_head; 453 454 devlist_head = &pci_devq; 455 456 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 457 free(dinfo, M_DEVBUF); 458 459 /* increment the generation count */ 460 pci_generation++; 461 462 /* we're losing one device */ 463 pci_numdevs--; 464 return (0); 465 } 466 467 /* 468 * PCI power manangement 469 */ 470 int 471 pci_set_powerstate_method(device_t dev, device_t child, int state) 472 { 473 struct pci_devinfo *dinfo = device_get_ivars(child); 474 pcicfgregs *cfg = &dinfo->cfg; 475 u_int16_t status; 476 int result; 477 478 if (cfg->pp_cap != 0) { 479 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 480 result = 0; 481 switch (state) { 482 case PCI_POWERSTATE_D0: 483 status |= PCIM_PSTAT_D0; 484 break; 485 case PCI_POWERSTATE_D1: 486 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 487 status |= PCIM_PSTAT_D1; 488 } else { 489 result = EOPNOTSUPP; 490 } 491 break; 492 case PCI_POWERSTATE_D2: 493 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 494 status |= PCIM_PSTAT_D2; 495 } else { 496 result = EOPNOTSUPP; 497 } 498 break; 499 case PCI_POWERSTATE_D3: 500 status |= PCIM_PSTAT_D3; 501 break; 502 default: 503 result = EINVAL; 504 } 505 if (result == 0) 506 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 507 } else { 508 result = ENXIO; 509 } 510 return(result); 511 } 512 513 int 514 pci_get_powerstate_method(device_t dev, device_t child) 515 { 516 struct pci_devinfo *dinfo = device_get_ivars(child); 517 pcicfgregs *cfg = &dinfo->cfg; 518 u_int16_t status; 519 int result; 520 521 if (cfg->pp_cap != 0) { 522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 523 switch (status & PCIM_PSTAT_DMASK) { 524 case PCIM_PSTAT_D0: 525 result = PCI_POWERSTATE_D0; 526 break; 527 case PCIM_PSTAT_D1: 528 result = PCI_POWERSTATE_D1; 529 break; 530 case PCIM_PSTAT_D2: 531 result = PCI_POWERSTATE_D2; 532 break; 533 case PCIM_PSTAT_D3: 534 result = PCI_POWERSTATE_D3; 535 break; 536 default: 537 result = PCI_POWERSTATE_UNKNOWN; 538 break; 539 } 540 } else { 541 /* No support, device is always at D0 */ 542 result = PCI_POWERSTATE_D0; 543 } 544 return(result); 545 } 546 547 /* 548 * Some convenience functions for PCI device drivers. 549 */ 550 551 static __inline void 552 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 553 { 554 u_int16_t command; 555 556 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 557 command |= bit; 558 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 559 } 560 561 static __inline void 562 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 563 { 564 u_int16_t command; 565 566 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 567 command &= ~bit; 568 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 569 } 570 571 int 572 pci_enable_busmaster_method(device_t dev, device_t child) 573 { 574 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 575 return (0); 576 } 577 578 int 579 pci_disable_busmaster_method(device_t dev, device_t child) 580 { 581 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 582 return (0); 583 } 584 585 int 586 pci_enable_io_method(device_t dev, device_t child, int space) 587 { 588 u_int16_t command; 589 u_int16_t bit; 590 char *error; 591 592 bit = 0; 593 error = NULL; 594 595 switch(space) { 596 case SYS_RES_IOPORT: 597 bit = PCIM_CMD_PORTEN; 598 error = "port"; 599 break; 600 case SYS_RES_MEMORY: 601 bit = PCIM_CMD_MEMEN; 602 error = "memory"; 603 break; 604 default: 605 return (EINVAL); 606 } 607 pci_set_command_bit(dev, child, bit); 608 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 609 if (command & bit) 610 return (0); 611 device_printf(child, "failed to enable %s mapping!\n", error); 612 return (ENXIO); 613 } 614 615 int 616 pci_disable_io_method(device_t dev, device_t child, int space) 617 { 618 u_int16_t command; 619 u_int16_t bit; 620 char *error; 621 622 bit = 0; 623 error = NULL; 624 625 switch(space) { 626 case SYS_RES_IOPORT: 627 bit = PCIM_CMD_PORTEN; 628 error = "port"; 629 break; 630 case SYS_RES_MEMORY: 631 bit = PCIM_CMD_MEMEN; 632 error = "memory"; 633 break; 634 default: 635 return (EINVAL); 636 } 637 pci_clear_command_bit(dev, child, bit); 638 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 639 if (command & bit) { 640 device_printf(child, "failed to disable %s mapping!\n", error); 641 return (ENXIO); 642 } 643 return (0); 644 } 645 646 /* 647 * New style pci driver. Parent device is either a pci-host-bridge or a 648 * pci-pci-bridge. Both kinds are represented by instances of pcib. 649 */ 650 651 void 652 pci_print_verbose(struct pci_devinfo *dinfo) 653 { 654 if (bootverbose) { 655 pcicfgregs *cfg = &dinfo->cfg; 656 657 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 658 cfg->vendor, cfg->device, cfg->revid); 659 printf("\tbus=%d, slot=%d, func=%d\n", 660 cfg->bus, cfg->slot, cfg->func); 661 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 662 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 663 cfg->mfdev); 664 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 665 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 666 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 667 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 668 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 669 if (cfg->intpin > 0) 670 printf("\tintpin=%c, irq=%d\n", 671 cfg->intpin +'a' -1, cfg->intline); 672 if (cfg->pp_cap) { 673 u_int16_t status; 674 675 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 676 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 677 cfg->pp_cap & PCIM_PCAP_SPEC, 678 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 679 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 680 status & PCIM_PSTAT_DMASK); 681 } 682 } 683 } 684 685 static int 686 pci_porten(device_t pcib, int b, int s, int f) 687 { 688 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 689 & PCIM_CMD_PORTEN) != 0; 690 } 691 692 static int 693 pci_memen(device_t pcib, int b, int s, int f) 694 { 695 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 696 & PCIM_CMD_MEMEN) != 0; 697 } 698 699 /* 700 * Add a resource based on a pci map register. Return 1 if the map 701 * register is a 32bit map register or 2 if it is a 64bit register. 702 */ 703 static int 704 pci_add_map(device_t pcib, int b, int s, int f, int reg, 705 struct resource_list *rl) 706 { 707 u_int32_t map; 708 u_int64_t base; 709 u_int8_t ln2size; 710 u_int8_t ln2range; 711 u_int32_t testval; 712 u_int16_t cmd; 713 int type; 714 715 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 716 717 if (map == 0 || map == 0xffffffff) 718 return (1); /* skip invalid entry */ 719 720 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 721 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 722 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 723 724 base = pci_mapbase(map); 725 if (pci_maptype(map) & PCI_MAPMEM) 726 type = SYS_RES_MEMORY; 727 else 728 type = SYS_RES_IOPORT; 729 ln2size = pci_mapsize(testval); 730 ln2range = pci_maprange(testval); 731 if (ln2range == 64) { 732 /* Read the other half of a 64bit map register */ 733 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 734 } 735 736 if (bootverbose) { 737 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 738 reg, pci_maptype(map), ln2range, 739 (unsigned int) base, ln2size); 740 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 741 printf(", port disabled\n"); 742 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 743 printf(", memory disabled\n"); 744 else 745 printf(", enabled\n"); 746 } 747 748 /* 749 * This code theoretically does the right thing, but has 750 * undesirable side effects in some cases where 751 * peripherals respond oddly to having these bits 752 * enabled. Leave them alone by default. 753 */ 754 if (pci_enable_io_modes) { 755 /* Turn on resources that have been left off by a lazy BIOS */ 756 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 757 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 758 cmd |= PCIM_CMD_PORTEN; 759 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 760 } 761 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 762 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 763 cmd |= PCIM_CMD_MEMEN; 764 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 765 } 766 } else { 767 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 768 return (1); 769 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 770 return (1); 771 } 772 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 773 (1 << ln2size)); 774 775 return ((ln2range == 64) ? 2 : 1); 776 } 777 778 static void 779 pci_add_resources(device_t pcib, device_t dev) 780 { 781 struct pci_devinfo *dinfo = device_get_ivars(dev); 782 pcicfgregs *cfg = &dinfo->cfg; 783 struct resource_list *rl = &dinfo->resources; 784 struct pci_quirk *q; 785 int b, i, f, s; 786 787 b = cfg->bus; 788 s = cfg->slot; 789 f = cfg->func; 790 for (i = 0; i < cfg->nummaps;) { 791 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 792 } 793 794 for (q = &pci_quirks[0]; q->devid; q++) { 795 if (q->devid == ((cfg->device << 16) | cfg->vendor) 796 && q->type == PCI_QUIRK_MAP_REG) 797 pci_add_map(pcib, b, s, f, q->arg1, rl); 798 } 799 800 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 801 #ifdef __ia64__ 802 /* 803 * Re-route interrupts on ia64 so that we can get the 804 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 805 * PIC interrupt numbers in the intline registers). 806 */ 807 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 808 #endif 809 resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline, 810 cfg->intline, 1); 811 } 812 } 813 814 void 815 pci_add_children(device_t dev, int busno, size_t dinfo_size) 816 { 817 device_t pcib = device_get_parent(dev); 818 struct pci_devinfo *dinfo; 819 int maxslots; 820 int s, f, pcifunchigh; 821 822 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 823 ("dinfo_size too small")); 824 maxslots = PCIB_MAXSLOTS(pcib); 825 for (s = 0; s <= maxslots; s++) { 826 pcifunchigh = 0; 827 for (f = 0; f <= pcifunchigh; f++) { 828 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 829 if (dinfo != NULL) { 830 if (dinfo->cfg.mfdev) 831 pcifunchigh = PCI_FUNCMAX; 832 pci_add_child(dev, dinfo); 833 } 834 } 835 } 836 } 837 838 void 839 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 840 { 841 device_t pcib; 842 843 pcib = device_get_parent(bus); 844 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 845 device_set_ivars(dinfo->cfg.dev, dinfo); 846 pci_add_resources(pcib, dinfo->cfg.dev); 847 pci_print_verbose(dinfo); 848 } 849 850 static int 851 pci_probe(device_t dev) 852 { 853 854 device_set_desc(dev, "PCI bus"); 855 856 /* Allow other subclasses to override this driver. */ 857 return (-1000); 858 } 859 860 static int 861 pci_attach(device_t dev) 862 { 863 int busno; 864 865 /* 866 * Since there can be multiple independantly numbered PCI 867 * busses on some large alpha systems, we can't use the unit 868 * number to decide what bus we are probing. We ask the parent 869 * pcib what our bus number is. 870 */ 871 busno = pcib_get_bus(dev); 872 if (bootverbose) 873 device_printf(dev, "physical bus=%d\n", busno); 874 875 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 876 877 return (bus_generic_attach(dev)); 878 } 879 880 static void 881 pci_load_vendor_data(void) 882 { 883 caddr_t vendordata, info; 884 885 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 886 info = preload_search_info(vendordata, MODINFO_ADDR); 887 pci_vendordata = *(char **)info; 888 info = preload_search_info(vendordata, MODINFO_SIZE); 889 pci_vendordata_size = *(size_t *)info; 890 /* terminate the database */ 891 pci_vendordata[pci_vendordata_size] = '\n'; 892 } 893 } 894 895 int 896 pci_print_child(device_t dev, device_t child) 897 { 898 struct pci_devinfo *dinfo; 899 struct resource_list *rl; 900 int retval = 0; 901 902 dinfo = device_get_ivars(child); 903 rl = &dinfo->resources; 904 905 retval += bus_print_child_header(dev, child); 906 907 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 908 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 909 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 910 if (device_get_flags(dev)) 911 retval += printf(" flags %#x", device_get_flags(dev)); 912 913 retval += printf(" at device %d.%d", pci_get_slot(child), 914 pci_get_function(child)); 915 916 retval += bus_print_child_footer(dev, child); 917 918 return (retval); 919 } 920 921 static struct 922 { 923 int class; 924 int subclass; 925 char *desc; 926 } pci_nomatch_tab[] = { 927 {PCIC_OLD, -1, "old"}, 928 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 929 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 930 {PCIC_STORAGE, -1, "mass storage"}, 931 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 932 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 933 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 934 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 935 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 936 {PCIC_NETWORK, -1, "network"}, 937 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 938 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 939 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 940 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 941 {PCIC_DISPLAY, -1, "display"}, 942 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 943 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 944 {PCIC_MULTIMEDIA, -1, "multimedia"}, 945 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 946 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 947 {PCIC_MEMORY, -1, "memory"}, 948 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 949 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 950 {PCIC_BRIDGE, -1, "bridge"}, 951 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 952 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 953 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 954 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 955 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 956 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 957 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 958 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 959 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 960 {PCIC_SIMPLECOMM, -1, "simple comms"}, 961 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 962 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 963 {PCIC_BASEPERIPH, -1, "base peripheral"}, 964 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 965 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 966 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 967 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 968 {PCIC_INPUTDEV, -1, "input device"}, 969 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 970 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 971 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 972 {PCIC_DOCKING, -1, "docking station"}, 973 {PCIC_PROCESSOR, -1, "processor"}, 974 {PCIC_SERIALBUS, -1, "serial bus"}, 975 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 976 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 977 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 978 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 979 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 980 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 981 {0, 0, NULL} 982 }; 983 984 void 985 pci_probe_nomatch(device_t dev, device_t child) 986 { 987 int i; 988 char *cp, *scp, *device; 989 990 /* 991 * Look for a listing for this device in a loaded device database. 992 */ 993 if ((device = pci_describe_device(child)) != NULL) { 994 device_printf(dev, "<%s>", device); 995 free(device, M_DEVBUF); 996 } else { 997 /* 998 * Scan the class/subclass descriptions for a general 999 * description. 1000 */ 1001 cp = "unknown"; 1002 scp = NULL; 1003 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1004 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1005 if (pci_nomatch_tab[i].subclass == -1) { 1006 cp = pci_nomatch_tab[i].desc; 1007 } else if (pci_nomatch_tab[i].subclass == 1008 pci_get_subclass(child)) { 1009 scp = pci_nomatch_tab[i].desc; 1010 } 1011 } 1012 } 1013 device_printf(dev, "<%s%s%s>", 1014 cp ? cp : "", 1015 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1016 scp ? scp : ""); 1017 } 1018 printf(" at device %d.%d (no driver attached)\n", 1019 pci_get_slot(child), pci_get_function(child)); 1020 return; 1021 } 1022 1023 /* 1024 * Parse the PCI device database, if loaded, and return a pointer to a 1025 * description of the device. 1026 * 1027 * The database is flat text formatted as follows: 1028 * 1029 * Any line not in a valid format is ignored. 1030 * Lines are terminated with newline '\n' characters. 1031 * 1032 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1033 * the vendor name. 1034 * 1035 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1036 * - devices cannot be listed without a corresponding VENDOR line. 1037 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1038 * another TAB, then the device name. 1039 */ 1040 1041 /* 1042 * Assuming (ptr) points to the beginning of a line in the database, 1043 * return the vendor or device and description of the next entry. 1044 * The value of (vendor) or (device) inappropriate for the entry type 1045 * is set to -1. Returns nonzero at the end of the database. 1046 * 1047 * Note that this is slightly unrobust in the face of corrupt data; 1048 * we attempt to safeguard against this by spamming the end of the 1049 * database with a newline when we initialise. 1050 */ 1051 static int 1052 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1053 { 1054 char *cp = *ptr; 1055 int left; 1056 1057 *device = -1; 1058 *vendor = -1; 1059 **desc = '\0'; 1060 for (;;) { 1061 left = pci_vendordata_size - (cp - pci_vendordata); 1062 if (left <= 0) { 1063 *ptr = cp; 1064 return(1); 1065 } 1066 1067 /* vendor entry? */ 1068 if (*cp != '\t' && 1069 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1070 break; 1071 /* device entry? */ 1072 if (*cp == '\t' && 1073 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1074 break; 1075 1076 /* skip to next line */ 1077 while (*cp != '\n' && left > 0) { 1078 cp++; 1079 left--; 1080 } 1081 if (*cp == '\n') { 1082 cp++; 1083 left--; 1084 } 1085 } 1086 /* skip to next line */ 1087 while (*cp != '\n' && left > 0) { 1088 cp++; 1089 left--; 1090 } 1091 if (*cp == '\n' && left > 0) 1092 cp++; 1093 *ptr = cp; 1094 return(0); 1095 } 1096 1097 static char * 1098 pci_describe_device(device_t dev) 1099 { 1100 int vendor, device; 1101 char *desc, *vp, *dp, *line; 1102 1103 desc = vp = dp = NULL; 1104 1105 /* 1106 * If we have no vendor data, we can't do anything. 1107 */ 1108 if (pci_vendordata == NULL) 1109 goto out; 1110 1111 /* 1112 * Scan the vendor data looking for this device 1113 */ 1114 line = pci_vendordata; 1115 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1116 goto out; 1117 for (;;) { 1118 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1119 goto out; 1120 if (vendor == pci_get_vendor(dev)) 1121 break; 1122 } 1123 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1124 goto out; 1125 for (;;) { 1126 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1127 *dp = 0; 1128 break; 1129 } 1130 if (vendor != -1) { 1131 *dp = 0; 1132 break; 1133 } 1134 if (device == pci_get_device(dev)) 1135 break; 1136 } 1137 if (dp[0] == '\0') 1138 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1139 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1140 NULL) 1141 sprintf(desc, "%s, %s", vp, dp); 1142 out: 1143 if (vp != NULL) 1144 free(vp, M_DEVBUF); 1145 if (dp != NULL) 1146 free(dp, M_DEVBUF); 1147 return(desc); 1148 } 1149 1150 int 1151 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1152 { 1153 struct pci_devinfo *dinfo; 1154 pcicfgregs *cfg; 1155 1156 dinfo = device_get_ivars(child); 1157 cfg = &dinfo->cfg; 1158 1159 switch (which) { 1160 case PCI_IVAR_ETHADDR: 1161 /* 1162 * The generic accessor doesn't deal with failure, so 1163 * we set the return value, then return an error. 1164 */ 1165 *((u_int8_t **) result) = NULL; 1166 return (EINVAL); 1167 case PCI_IVAR_SUBVENDOR: 1168 *result = cfg->subvendor; 1169 break; 1170 case PCI_IVAR_SUBDEVICE: 1171 *result = cfg->subdevice; 1172 break; 1173 case PCI_IVAR_VENDOR: 1174 *result = cfg->vendor; 1175 break; 1176 case PCI_IVAR_DEVICE: 1177 *result = cfg->device; 1178 break; 1179 case PCI_IVAR_DEVID: 1180 *result = (cfg->device << 16) | cfg->vendor; 1181 break; 1182 case PCI_IVAR_CLASS: 1183 *result = cfg->baseclass; 1184 break; 1185 case PCI_IVAR_SUBCLASS: 1186 *result = cfg->subclass; 1187 break; 1188 case PCI_IVAR_PROGIF: 1189 *result = cfg->progif; 1190 break; 1191 case PCI_IVAR_REVID: 1192 *result = cfg->revid; 1193 break; 1194 case PCI_IVAR_INTPIN: 1195 *result = cfg->intpin; 1196 break; 1197 case PCI_IVAR_IRQ: 1198 *result = cfg->intline; 1199 break; 1200 case PCI_IVAR_BUS: 1201 *result = cfg->bus; 1202 break; 1203 case PCI_IVAR_SLOT: 1204 *result = cfg->slot; 1205 break; 1206 case PCI_IVAR_FUNCTION: 1207 *result = cfg->func; 1208 break; 1209 default: 1210 return (ENOENT); 1211 } 1212 return (0); 1213 } 1214 1215 int 1216 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1217 { 1218 struct pci_devinfo *dinfo; 1219 1220 dinfo = device_get_ivars(child); 1221 1222 switch (which) { 1223 case PCI_IVAR_ETHADDR: 1224 case PCI_IVAR_SUBVENDOR: 1225 case PCI_IVAR_SUBDEVICE: 1226 case PCI_IVAR_VENDOR: 1227 case PCI_IVAR_DEVICE: 1228 case PCI_IVAR_DEVID: 1229 case PCI_IVAR_CLASS: 1230 case PCI_IVAR_SUBCLASS: 1231 case PCI_IVAR_PROGIF: 1232 case PCI_IVAR_REVID: 1233 case PCI_IVAR_INTPIN: 1234 case PCI_IVAR_IRQ: 1235 case PCI_IVAR_BUS: 1236 case PCI_IVAR_SLOT: 1237 case PCI_IVAR_FUNCTION: 1238 return (EINVAL); /* disallow for now */ 1239 1240 default: 1241 return (ENOENT); 1242 } 1243 } 1244 1245 1246 #include "opt_ddb.h" 1247 #ifdef DDB 1248 #include <ddb/ddb.h> 1249 #include <sys/cons.h> 1250 1251 /* 1252 * List resources based on pci map registers, used for within ddb 1253 */ 1254 1255 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1256 { 1257 struct pci_devinfo *dinfo; 1258 struct devlist *devlist_head; 1259 struct pci_conf *p; 1260 const char *name; 1261 int i, error, none_count, nl; 1262 1263 none_count = 0; 1264 nl = 0; 1265 /* get the head of the device queue */ 1266 devlist_head = &pci_devq; 1267 1268 /* 1269 * Go through the list of devices and print out devices 1270 */ 1271 for (error = 0, i = 0, 1272 dinfo = STAILQ_FIRST(devlist_head); 1273 (dinfo != NULL) && (error == 0) && (i < pci_numdevs); 1274 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1275 1276 /* Populate pd_name and pd_unit */ 1277 name = NULL; 1278 if (dinfo->cfg.dev) 1279 name = device_get_name(dinfo->cfg.dev); 1280 1281 p = &dinfo->conf; 1282 /* 1283 * XXX just take 20 for now... 1284 */ 1285 if (nl++ == 20) { 1286 int c; 1287 1288 db_printf("--More--"); 1289 c = cngetc(); 1290 db_printf("\r"); 1291 /* 1292 * A whole screenfull or just one line? 1293 */ 1294 switch (c) { 1295 case '\n': /* just one line */ 1296 nl = 20; 1297 break; 1298 case ' ': 1299 nl = 0; /* another screenfull */ 1300 break; 1301 default: /* exit */ 1302 db_printf("\n"); 1303 return; 1304 } 1305 } 1306 1307 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1308 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1309 (name && *name) ? name : "none", 1310 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1311 none_count++, 1312 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1313 p->pc_sel.pc_func, (p->pc_class << 16) | 1314 (p->pc_subclass << 8) | p->pc_progif, 1315 (p->pc_subdevice << 16) | p->pc_subvendor, 1316 (p->pc_device << 16) | p->pc_vendor, 1317 p->pc_revid, p->pc_hdr); 1318 } 1319 } 1320 #endif /* DDB */ 1321 1322 struct resource * 1323 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1324 u_long start, u_long end, u_long count, u_int flags) 1325 { 1326 struct pci_devinfo *dinfo = device_get_ivars(child); 1327 struct resource_list *rl = &dinfo->resources; 1328 pcicfgregs *cfg = &dinfo->cfg; 1329 1330 /* 1331 * Perform lazy resource allocation 1332 * 1333 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1334 */ 1335 if (device_get_parent(child) == dev) { 1336 switch (type) { 1337 case SYS_RES_IRQ: 1338 /* 1339 * If the child device doesn't have an 1340 * interrupt routed and is deserving of an 1341 * interrupt, try to assign it one. 1342 */ 1343 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1344 (cfg->intpin != 0)) { 1345 cfg->intline = PCIB_ROUTE_INTERRUPT( 1346 device_get_parent(dev), child, cfg->intpin); 1347 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1348 pci_write_config(child, PCIR_INTLINE, 1349 cfg->intline, 1); 1350 resource_list_add(rl, SYS_RES_IRQ, 0, 1351 cfg->intline, cfg->intline, 1); 1352 } 1353 } 1354 break; 1355 case SYS_RES_IOPORT: 1356 case SYS_RES_MEMORY: 1357 /* 1358 * Enable the I/O mode. We should also be allocating 1359 * resources too. XXX 1360 */ 1361 if (PCI_ENABLE_IO(dev, child, type)) 1362 return (NULL); 1363 break; 1364 } 1365 } 1366 1367 return (resource_list_alloc(rl, dev, child, type, rid, 1368 start, end, count, flags)); 1369 } 1370 1371 void 1372 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1373 { 1374 struct pci_devinfo *dinfo; 1375 struct resource_list *rl; 1376 struct resource_list_entry *rle; 1377 1378 if (device_get_parent(child) != dev) 1379 return; 1380 1381 dinfo = device_get_ivars(child); 1382 rl = &dinfo->resources; 1383 rle = resource_list_find(rl, type, rid); 1384 if (rle) { 1385 if (rle->res) { 1386 if (rman_get_device(rle->res) != dev || 1387 rman_get_flags(rle->res) & RF_ACTIVE) { 1388 device_printf(dev, "delete_resource: " 1389 "Resource still owned by child, oops. " 1390 "(type=%d, rid=%d, addr=%lx)\n", 1391 rle->type, rle->rid, 1392 rman_get_start(rle->res)); 1393 return; 1394 } 1395 bus_release_resource(dev, type, rid, rle->res); 1396 } 1397 resource_list_delete(rl, type, rid); 1398 } 1399 /* 1400 * Why do we turn off the PCI configuration BAR when we delete a 1401 * resource? -- imp 1402 */ 1403 pci_write_config(child, rid, 0, 4); 1404 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1405 } 1406 1407 struct resource_list * 1408 pci_get_resource_list (device_t dev, device_t child) 1409 { 1410 struct pci_devinfo * dinfo = device_get_ivars(child); 1411 struct resource_list * rl = &dinfo->resources; 1412 1413 if (!rl) 1414 return (NULL); 1415 1416 return (rl); 1417 } 1418 1419 u_int32_t 1420 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1421 { 1422 struct pci_devinfo *dinfo = device_get_ivars(child); 1423 pcicfgregs *cfg = &dinfo->cfg; 1424 1425 return (PCIB_READ_CONFIG(device_get_parent(dev), 1426 cfg->bus, cfg->slot, cfg->func, reg, width)); 1427 } 1428 1429 void 1430 pci_write_config_method(device_t dev, device_t child, int reg, 1431 u_int32_t val, int width) 1432 { 1433 struct pci_devinfo *dinfo = device_get_ivars(child); 1434 pcicfgregs *cfg = &dinfo->cfg; 1435 1436 PCIB_WRITE_CONFIG(device_get_parent(dev), 1437 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1438 } 1439 1440 int 1441 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1442 size_t buflen) 1443 { 1444 struct pci_devinfo *dinfo; 1445 1446 dinfo = device_get_ivars(child); 1447 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1448 pci_get_function(child)); 1449 return (0); 1450 } 1451 1452 int 1453 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1454 size_t buflen) 1455 { 1456 struct pci_devinfo *dinfo; 1457 pcicfgregs *cfg; 1458 1459 dinfo = device_get_ivars(child); 1460 cfg = &dinfo->cfg; 1461 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1462 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1463 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1464 cfg->progif); 1465 return (0); 1466 } 1467 1468 static int 1469 pci_modevent(module_t mod, int what, void *arg) 1470 { 1471 static dev_t pci_cdev; 1472 1473 switch (what) { 1474 case MOD_LOAD: 1475 STAILQ_INIT(&pci_devq); 1476 pci_generation = 0; 1477 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1478 "pci"); 1479 pci_load_vendor_data(); 1480 break; 1481 1482 case MOD_UNLOAD: 1483 destroy_dev(pci_cdev); 1484 break; 1485 } 1486 1487 return (0); 1488 } 1489