1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_iommu.h" 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/endian.h> 41 #include <sys/eventhandler.h> 42 #include <sys/fcntl.h> 43 #include <sys/kernel.h> 44 #include <sys/limits.h> 45 #include <sys/linker.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/queue.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 #include <vm/vm_extern.h> 57 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <sys/rman.h> 61 #include <machine/resource.h> 62 #include <machine/stdarg.h> 63 64 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 65 #include <machine/intr_machdep.h> 66 #endif 67 68 #include <sys/pciio.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pci_private.h> 72 73 #ifdef PCI_IOV 74 #include <sys/nv.h> 75 #include <dev/pci/pci_iov_private.h> 76 #endif 77 78 #include <dev/usb/controller/xhcireg.h> 79 #include <dev/usb/controller/ehcireg.h> 80 #include <dev/usb/controller/ohcireg.h> 81 #include <dev/usb/controller/uhcireg.h> 82 83 #include <dev/iommu/iommu.h> 84 85 #include "pcib_if.h" 86 #include "pci_if.h" 87 88 #define PCIR_IS_BIOS(cfg, reg) \ 89 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 90 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 91 92 static int pci_has_quirk(uint32_t devid, int quirk); 93 static pci_addr_t pci_mapbase(uint64_t mapreg); 94 static const char *pci_maptype(uint64_t mapreg); 95 static int pci_maprange(uint64_t mapreg); 96 static pci_addr_t pci_rombase(uint64_t mapreg); 97 static int pci_romsize(uint64_t testval); 98 static void pci_fixancient(pcicfgregs *cfg); 99 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 100 101 static int pci_porten(device_t dev); 102 static int pci_memen(device_t dev); 103 static void pci_assign_interrupt(device_t bus, device_t dev, 104 int force_route); 105 static int pci_add_map(device_t bus, device_t dev, int reg, 106 struct resource_list *rl, int force, int prefetch); 107 static int pci_probe(device_t dev); 108 static void pci_load_vendor_data(void); 109 static int pci_describe_parse_line(char **ptr, int *vendor, 110 int *device, char **desc); 111 static char *pci_describe_device(device_t dev); 112 static int pci_modevent(module_t mod, int what, void *arg); 113 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 114 pcicfgregs *cfg); 115 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 116 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 117 int reg, uint32_t *data); 118 #if 0 119 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 120 int reg, uint32_t data); 121 #endif 122 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 123 static void pci_mask_msix(device_t dev, u_int index); 124 static void pci_unmask_msix(device_t dev, u_int index); 125 static int pci_msi_blacklisted(void); 126 static int pci_msix_blacklisted(void); 127 static void pci_resume_msi(device_t dev); 128 static void pci_resume_msix(device_t dev); 129 static int pci_remap_intr_method(device_t bus, device_t dev, 130 u_int irq); 131 static void pci_hint_device_unit(device_t acdev, device_t child, 132 const char *name, int *unitp); 133 static int pci_reset_post(device_t dev, device_t child); 134 static int pci_reset_prepare(device_t dev, device_t child); 135 static int pci_reset_child(device_t dev, device_t child, 136 int flags); 137 138 static int pci_get_id_method(device_t dev, device_t child, 139 enum pci_id_type type, uintptr_t *rid); 140 141 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 142 int b, int s, int f, uint16_t vid, uint16_t did); 143 144 static device_method_t pci_methods[] = { 145 /* Device interface */ 146 DEVMETHOD(device_probe, pci_probe), 147 DEVMETHOD(device_attach, pci_attach), 148 DEVMETHOD(device_detach, pci_detach), 149 DEVMETHOD(device_shutdown, bus_generic_shutdown), 150 DEVMETHOD(device_suspend, bus_generic_suspend), 151 DEVMETHOD(device_resume, pci_resume), 152 153 /* Bus interface */ 154 DEVMETHOD(bus_print_child, pci_print_child), 155 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 156 DEVMETHOD(bus_read_ivar, pci_read_ivar), 157 DEVMETHOD(bus_write_ivar, pci_write_ivar), 158 DEVMETHOD(bus_driver_added, pci_driver_added), 159 DEVMETHOD(bus_setup_intr, pci_setup_intr), 160 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 161 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 162 DEVMETHOD(bus_reset_post, pci_reset_post), 163 DEVMETHOD(bus_reset_child, pci_reset_child), 164 165 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 166 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 167 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 168 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 169 DEVMETHOD(bus_delete_resource, pci_delete_resource), 170 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 171 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 172 DEVMETHOD(bus_release_resource, pci_release_resource), 173 DEVMETHOD(bus_activate_resource, pci_activate_resource), 174 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 175 DEVMETHOD(bus_child_deleted, pci_child_deleted), 176 DEVMETHOD(bus_child_detached, pci_child_detached), 177 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 178 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 179 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 180 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 181 DEVMETHOD(bus_suspend_child, pci_suspend_child), 182 DEVMETHOD(bus_resume_child, pci_resume_child), 183 DEVMETHOD(bus_rescan, pci_rescan_method), 184 185 /* PCI interface */ 186 DEVMETHOD(pci_read_config, pci_read_config_method), 187 DEVMETHOD(pci_write_config, pci_write_config_method), 188 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 189 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 190 DEVMETHOD(pci_enable_io, pci_enable_io_method), 191 DEVMETHOD(pci_disable_io, pci_disable_io_method), 192 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 193 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 194 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 195 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 196 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 197 DEVMETHOD(pci_find_cap, pci_find_cap_method), 198 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 199 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 200 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 201 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 202 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 203 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 204 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 205 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 206 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 207 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 208 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 209 DEVMETHOD(pci_release_msi, pci_release_msi_method), 210 DEVMETHOD(pci_msi_count, pci_msi_count_method), 211 DEVMETHOD(pci_msix_count, pci_msix_count_method), 212 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 213 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 214 DEVMETHOD(pci_get_id, pci_get_id_method), 215 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 216 DEVMETHOD(pci_child_added, pci_child_added_method), 217 #ifdef PCI_IOV 218 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 219 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 220 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 221 #endif 222 223 DEVMETHOD_END 224 }; 225 226 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 227 228 static devclass_t pci_devclass; 229 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 230 BUS_PASS_BUS); 231 MODULE_VERSION(pci, 1); 232 233 static char *pci_vendordata; 234 static size_t pci_vendordata_size; 235 236 struct pci_quirk { 237 uint32_t devid; /* Vendor/device of the card */ 238 int type; 239 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 240 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 241 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 242 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 243 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 244 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 245 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 246 int arg1; 247 int arg2; 248 }; 249 250 static const struct pci_quirk pci_quirks[] = { 251 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 252 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 255 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 256 257 /* 258 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 259 * or the CMIC-SL (AKA ServerWorks GC_LE). 260 */ 261 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 262 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 263 264 /* 265 * MSI doesn't work on earlier Intel chipsets including 266 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 267 */ 268 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 274 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 275 276 /* 277 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 278 * bridge. 279 */ 280 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 281 282 /* 283 * Some virtualization environments emulate an older chipset 284 * but support MSI just fine. QEMU uses the Intel 82440. 285 */ 286 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 287 288 /* 289 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 290 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 291 * It prevents us from attaching hpet(4) when the bit is unset. 292 * Note this quirk only affects SB600 revision A13 and earlier. 293 * For SB600 A21 and later, firmware must set the bit to hide it. 294 * For SB700 and later, it is unused and hardcoded to zero. 295 */ 296 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 297 298 /* 299 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 300 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 301 * of the command register is set. 302 */ 303 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 309 /* 310 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 311 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 312 */ 313 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 314 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 315 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 316 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 317 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 318 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 319 320 /* 321 * HPE Gen 10 VGA has a memory range that can't be allocated in the 322 * expected place. 323 */ 324 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 325 { 0 } 326 }; 327 328 /* map register information */ 329 #define PCI_MAPMEM 0x01 /* memory map */ 330 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 331 #define PCI_MAPPORT 0x04 /* port map */ 332 333 struct devlist pci_devq; 334 uint32_t pci_generation; 335 uint32_t pci_numdevs = 0; 336 static int pcie_chipset, pcix_chipset; 337 338 /* sysctl vars */ 339 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 340 "PCI bus tuning parameters"); 341 342 static int pci_enable_io_modes = 1; 343 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 344 &pci_enable_io_modes, 1, 345 "Enable I/O and memory bits in the config register. Some BIOSes do not" 346 " enable these bits correctly. We'd like to do this all the time, but" 347 " there are some peripherals that this causes problems with."); 348 349 static int pci_do_realloc_bars = 1; 350 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 351 &pci_do_realloc_bars, 0, 352 "Attempt to allocate a new range for any BARs whose original " 353 "firmware-assigned ranges fail to allocate during the initial device scan."); 354 355 static int pci_do_power_nodriver = 0; 356 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 357 &pci_do_power_nodriver, 0, 358 "Place a function into D3 state when no driver attaches to it. 0 means" 359 " disable. 1 means conservatively place devices into D3 state. 2 means" 360 " aggressively place devices into D3 state. 3 means put absolutely" 361 " everything in D3 state."); 362 363 int pci_do_power_resume = 1; 364 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 365 &pci_do_power_resume, 1, 366 "Transition from D3 -> D0 on resume."); 367 368 int pci_do_power_suspend = 1; 369 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 370 &pci_do_power_suspend, 1, 371 "Transition from D0 -> D3 on suspend."); 372 373 static int pci_do_msi = 1; 374 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 375 "Enable support for MSI interrupts"); 376 377 static int pci_do_msix = 1; 378 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 379 "Enable support for MSI-X interrupts"); 380 381 static int pci_msix_rewrite_table = 0; 382 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 383 &pci_msix_rewrite_table, 0, 384 "Rewrite entire MSI-X table when updating MSI-X entries"); 385 386 static int pci_honor_msi_blacklist = 1; 387 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 388 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 389 390 #if defined(__i386__) || defined(__amd64__) 391 static int pci_usb_takeover = 1; 392 #else 393 static int pci_usb_takeover = 0; 394 #endif 395 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 396 &pci_usb_takeover, 1, 397 "Enable early takeover of USB controllers. Disable this if you depend on" 398 " BIOS emulation of USB devices, that is you use USB devices (like" 399 " keyboard or mouse) but do not load USB drivers"); 400 401 static int pci_clear_bars; 402 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 403 "Ignore firmware-assigned resources for BARs."); 404 405 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 406 static int pci_clear_buses; 407 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 408 "Ignore firmware-assigned bus numbers."); 409 #endif 410 411 static int pci_enable_ari = 1; 412 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 413 0, "Enable support for PCIe Alternative RID Interpretation"); 414 415 int pci_enable_aspm = 1; 416 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 417 0, "Enable support for PCIe Active State Power Management"); 418 419 static int pci_clear_aer_on_attach = 0; 420 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 421 &pci_clear_aer_on_attach, 0, 422 "Clear port and device AER state on driver attach"); 423 424 static int 425 pci_has_quirk(uint32_t devid, int quirk) 426 { 427 const struct pci_quirk *q; 428 429 for (q = &pci_quirks[0]; q->devid; q++) { 430 if (q->devid == devid && q->type == quirk) 431 return (1); 432 } 433 return (0); 434 } 435 436 /* Find a device_t by bus/slot/function in domain 0 */ 437 438 device_t 439 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 440 { 441 442 return (pci_find_dbsf(0, bus, slot, func)); 443 } 444 445 /* Find a device_t by domain/bus/slot/function */ 446 447 device_t 448 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 449 { 450 struct pci_devinfo *dinfo = NULL; 451 452 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 453 if ((dinfo->cfg.domain == domain) && 454 (dinfo->cfg.bus == bus) && 455 (dinfo->cfg.slot == slot) && 456 (dinfo->cfg.func == func)) { 457 break; 458 } 459 } 460 461 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 462 } 463 464 /* Find a device_t by vendor/device ID */ 465 466 device_t 467 pci_find_device(uint16_t vendor, uint16_t device) 468 { 469 struct pci_devinfo *dinfo; 470 471 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 472 if ((dinfo->cfg.vendor == vendor) && 473 (dinfo->cfg.device == device)) { 474 return (dinfo->cfg.dev); 475 } 476 } 477 478 return (NULL); 479 } 480 481 device_t 482 pci_find_class(uint8_t class, uint8_t subclass) 483 { 484 struct pci_devinfo *dinfo; 485 486 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 487 if (dinfo->cfg.baseclass == class && 488 dinfo->cfg.subclass == subclass) { 489 return (dinfo->cfg.dev); 490 } 491 } 492 493 return (NULL); 494 } 495 496 static int 497 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 498 { 499 va_list ap; 500 int retval; 501 502 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 503 cfg->func); 504 va_start(ap, fmt); 505 retval += vprintf(fmt, ap); 506 va_end(ap); 507 return (retval); 508 } 509 510 /* return base address of memory or port map */ 511 512 static pci_addr_t 513 pci_mapbase(uint64_t mapreg) 514 { 515 516 if (PCI_BAR_MEM(mapreg)) 517 return (mapreg & PCIM_BAR_MEM_BASE); 518 else 519 return (mapreg & PCIM_BAR_IO_BASE); 520 } 521 522 /* return map type of memory or port map */ 523 524 static const char * 525 pci_maptype(uint64_t mapreg) 526 { 527 528 if (PCI_BAR_IO(mapreg)) 529 return ("I/O Port"); 530 if (mapreg & PCIM_BAR_MEM_PREFETCH) 531 return ("Prefetchable Memory"); 532 return ("Memory"); 533 } 534 535 /* return log2 of map size decoded for memory or port map */ 536 537 int 538 pci_mapsize(uint64_t testval) 539 { 540 int ln2size; 541 542 testval = pci_mapbase(testval); 543 ln2size = 0; 544 if (testval != 0) { 545 while ((testval & 1) == 0) 546 { 547 ln2size++; 548 testval >>= 1; 549 } 550 } 551 return (ln2size); 552 } 553 554 /* return base address of device ROM */ 555 556 static pci_addr_t 557 pci_rombase(uint64_t mapreg) 558 { 559 560 return (mapreg & PCIM_BIOS_ADDR_MASK); 561 } 562 563 /* return log2 of map size decided for device ROM */ 564 565 static int 566 pci_romsize(uint64_t testval) 567 { 568 int ln2size; 569 570 testval = pci_rombase(testval); 571 ln2size = 0; 572 if (testval != 0) { 573 while ((testval & 1) == 0) 574 { 575 ln2size++; 576 testval >>= 1; 577 } 578 } 579 return (ln2size); 580 } 581 582 /* return log2 of address range supported by map register */ 583 584 static int 585 pci_maprange(uint64_t mapreg) 586 { 587 int ln2range = 0; 588 589 if (PCI_BAR_IO(mapreg)) 590 ln2range = 32; 591 else 592 switch (mapreg & PCIM_BAR_MEM_TYPE) { 593 case PCIM_BAR_MEM_32: 594 ln2range = 32; 595 break; 596 case PCIM_BAR_MEM_1MB: 597 ln2range = 20; 598 break; 599 case PCIM_BAR_MEM_64: 600 ln2range = 64; 601 break; 602 } 603 return (ln2range); 604 } 605 606 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 607 608 static void 609 pci_fixancient(pcicfgregs *cfg) 610 { 611 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 612 return; 613 614 /* PCI to PCI bridges use header type 1 */ 615 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 616 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 617 } 618 619 /* extract header type specific config data */ 620 621 static void 622 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 623 { 624 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 625 switch (cfg->hdrtype & PCIM_HDRTYPE) { 626 case PCIM_HDRTYPE_NORMAL: 627 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 628 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 629 cfg->mingnt = REG(PCIR_MINGNT, 1); 630 cfg->maxlat = REG(PCIR_MAXLAT, 1); 631 cfg->nummaps = PCI_MAXMAPS_0; 632 break; 633 case PCIM_HDRTYPE_BRIDGE: 634 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 635 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 636 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 637 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 638 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 639 cfg->nummaps = PCI_MAXMAPS_1; 640 break; 641 case PCIM_HDRTYPE_CARDBUS: 642 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 643 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 644 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 645 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 646 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 647 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 648 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 649 cfg->nummaps = PCI_MAXMAPS_2; 650 break; 651 } 652 #undef REG 653 } 654 655 /* read configuration header into pcicfgregs structure */ 656 struct pci_devinfo * 657 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 658 { 659 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 660 uint16_t vid, did; 661 662 vid = REG(PCIR_VENDOR, 2); 663 did = REG(PCIR_DEVICE, 2); 664 if (vid != 0xffff) 665 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 666 667 return (NULL); 668 } 669 670 struct pci_devinfo * 671 pci_alloc_devinfo_method(device_t dev) 672 { 673 674 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 675 M_WAITOK | M_ZERO)); 676 } 677 678 static struct pci_devinfo * 679 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 680 uint16_t vid, uint16_t did) 681 { 682 struct pci_devinfo *devlist_entry; 683 pcicfgregs *cfg; 684 685 devlist_entry = PCI_ALLOC_DEVINFO(bus); 686 687 cfg = &devlist_entry->cfg; 688 689 cfg->domain = d; 690 cfg->bus = b; 691 cfg->slot = s; 692 cfg->func = f; 693 cfg->vendor = vid; 694 cfg->device = did; 695 cfg->cmdreg = REG(PCIR_COMMAND, 2); 696 cfg->statreg = REG(PCIR_STATUS, 2); 697 cfg->baseclass = REG(PCIR_CLASS, 1); 698 cfg->subclass = REG(PCIR_SUBCLASS, 1); 699 cfg->progif = REG(PCIR_PROGIF, 1); 700 cfg->revid = REG(PCIR_REVID, 1); 701 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 702 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 703 cfg->lattimer = REG(PCIR_LATTIMER, 1); 704 cfg->intpin = REG(PCIR_INTPIN, 1); 705 cfg->intline = REG(PCIR_INTLINE, 1); 706 707 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 708 cfg->hdrtype &= ~PCIM_MFDEV; 709 STAILQ_INIT(&cfg->maps); 710 711 cfg->iov = NULL; 712 713 pci_fixancient(cfg); 714 pci_hdrtypedata(pcib, b, s, f, cfg); 715 716 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 717 pci_read_cap(pcib, cfg); 718 719 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 720 721 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 722 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 723 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 724 devlist_entry->conf.pc_sel.pc_func = cfg->func; 725 devlist_entry->conf.pc_hdr = cfg->hdrtype; 726 727 devlist_entry->conf.pc_subvendor = cfg->subvendor; 728 devlist_entry->conf.pc_subdevice = cfg->subdevice; 729 devlist_entry->conf.pc_vendor = cfg->vendor; 730 devlist_entry->conf.pc_device = cfg->device; 731 732 devlist_entry->conf.pc_class = cfg->baseclass; 733 devlist_entry->conf.pc_subclass = cfg->subclass; 734 devlist_entry->conf.pc_progif = cfg->progif; 735 devlist_entry->conf.pc_revid = cfg->revid; 736 737 pci_numdevs++; 738 pci_generation++; 739 740 return (devlist_entry); 741 } 742 #undef REG 743 744 static void 745 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 746 { 747 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 748 cfg->ea.ea_location + (n), w) 749 int num_ent; 750 int ptr; 751 int a, b; 752 uint32_t val; 753 int ent_size; 754 uint32_t dw[4]; 755 uint64_t base, max_offset; 756 struct pci_ea_entry *eae; 757 758 if (cfg->ea.ea_location == 0) 759 return; 760 761 STAILQ_INIT(&cfg->ea.ea_entries); 762 763 /* Determine the number of entries */ 764 num_ent = REG(PCIR_EA_NUM_ENT, 2); 765 num_ent &= PCIM_EA_NUM_ENT_MASK; 766 767 /* Find the first entry to care of */ 768 ptr = PCIR_EA_FIRST_ENT; 769 770 /* Skip DWORD 2 for type 1 functions */ 771 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 772 ptr += 4; 773 774 for (a = 0; a < num_ent; a++) { 775 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 776 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 777 778 /* Read a number of dwords in the entry */ 779 val = REG(ptr, 4); 780 ptr += 4; 781 ent_size = (val & PCIM_EA_ES); 782 783 for (b = 0; b < ent_size; b++) { 784 dw[b] = REG(ptr, 4); 785 ptr += 4; 786 } 787 788 eae->eae_flags = val; 789 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 790 791 base = dw[0] & PCIM_EA_FIELD_MASK; 792 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 793 b = 2; 794 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 795 base |= (uint64_t)dw[b] << 32UL; 796 b++; 797 } 798 if (((dw[1] & PCIM_EA_IS_64) != 0) 799 && (b < ent_size)) { 800 max_offset |= (uint64_t)dw[b] << 32UL; 801 b++; 802 } 803 804 eae->eae_base = base; 805 eae->eae_max_offset = max_offset; 806 807 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 808 809 if (bootverbose) { 810 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 811 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 812 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 813 } 814 } 815 } 816 #undef REG 817 818 static void 819 pci_read_cap(device_t pcib, pcicfgregs *cfg) 820 { 821 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 822 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 823 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 824 uint64_t addr; 825 #endif 826 uint32_t val; 827 int ptr, nextptr, ptrptr; 828 829 switch (cfg->hdrtype & PCIM_HDRTYPE) { 830 case PCIM_HDRTYPE_NORMAL: 831 case PCIM_HDRTYPE_BRIDGE: 832 ptrptr = PCIR_CAP_PTR; 833 break; 834 case PCIM_HDRTYPE_CARDBUS: 835 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 836 break; 837 default: 838 return; /* no extended capabilities support */ 839 } 840 nextptr = REG(ptrptr, 1); /* sanity check? */ 841 842 /* 843 * Read capability entries. 844 */ 845 while (nextptr != 0) { 846 /* Sanity check */ 847 if (nextptr > 255) { 848 printf("illegal PCI extended capability offset %d\n", 849 nextptr); 850 return; 851 } 852 /* Find the next entry */ 853 ptr = nextptr; 854 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 855 856 /* Process this entry */ 857 switch (REG(ptr + PCICAP_ID, 1)) { 858 case PCIY_PMG: /* PCI power management */ 859 if (cfg->pp.pp_cap == 0) { 860 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 861 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 862 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 863 if ((nextptr - ptr) > PCIR_POWER_DATA) 864 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 865 } 866 break; 867 case PCIY_HT: /* HyperTransport */ 868 /* Determine HT-specific capability type. */ 869 val = REG(ptr + PCIR_HT_COMMAND, 2); 870 871 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 872 cfg->ht.ht_slave = ptr; 873 874 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 875 switch (val & PCIM_HTCMD_CAP_MASK) { 876 case PCIM_HTCAP_MSI_MAPPING: 877 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 878 /* Sanity check the mapping window. */ 879 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 880 4); 881 addr <<= 32; 882 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 883 4); 884 if (addr != MSI_INTEL_ADDR_BASE) 885 device_printf(pcib, 886 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 887 cfg->domain, cfg->bus, 888 cfg->slot, cfg->func, 889 (long long)addr); 890 } else 891 addr = MSI_INTEL_ADDR_BASE; 892 893 cfg->ht.ht_msimap = ptr; 894 cfg->ht.ht_msictrl = val; 895 cfg->ht.ht_msiaddr = addr; 896 break; 897 } 898 #endif 899 break; 900 case PCIY_MSI: /* PCI MSI */ 901 cfg->msi.msi_location = ptr; 902 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 903 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 904 PCIM_MSICTRL_MMC_MASK)>>1); 905 break; 906 case PCIY_MSIX: /* PCI MSI-X */ 907 cfg->msix.msix_location = ptr; 908 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 909 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 910 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 911 val = REG(ptr + PCIR_MSIX_TABLE, 4); 912 cfg->msix.msix_table_bar = PCIR_BAR(val & 913 PCIM_MSIX_BIR_MASK); 914 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 915 val = REG(ptr + PCIR_MSIX_PBA, 4); 916 cfg->msix.msix_pba_bar = PCIR_BAR(val & 917 PCIM_MSIX_BIR_MASK); 918 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 919 break; 920 case PCIY_VPD: /* PCI Vital Product Data */ 921 cfg->vpd.vpd_reg = ptr; 922 break; 923 case PCIY_SUBVENDOR: 924 /* Should always be true. */ 925 if ((cfg->hdrtype & PCIM_HDRTYPE) == 926 PCIM_HDRTYPE_BRIDGE) { 927 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 928 cfg->subvendor = val & 0xffff; 929 cfg->subdevice = val >> 16; 930 } 931 break; 932 case PCIY_PCIX: /* PCI-X */ 933 /* 934 * Assume we have a PCI-X chipset if we have 935 * at least one PCI-PCI bridge with a PCI-X 936 * capability. Note that some systems with 937 * PCI-express or HT chipsets might match on 938 * this check as well. 939 */ 940 if ((cfg->hdrtype & PCIM_HDRTYPE) == 941 PCIM_HDRTYPE_BRIDGE) 942 pcix_chipset = 1; 943 cfg->pcix.pcix_location = ptr; 944 break; 945 case PCIY_EXPRESS: /* PCI-express */ 946 /* 947 * Assume we have a PCI-express chipset if we have 948 * at least one PCI-express device. 949 */ 950 pcie_chipset = 1; 951 cfg->pcie.pcie_location = ptr; 952 val = REG(ptr + PCIER_FLAGS, 2); 953 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 954 break; 955 case PCIY_EA: /* Enhanced Allocation */ 956 cfg->ea.ea_location = ptr; 957 pci_ea_fill_info(pcib, cfg); 958 break; 959 default: 960 break; 961 } 962 } 963 964 #if defined(__powerpc__) 965 /* 966 * Enable the MSI mapping window for all HyperTransport 967 * slaves. PCI-PCI bridges have their windows enabled via 968 * PCIB_MAP_MSI(). 969 */ 970 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 971 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 972 device_printf(pcib, 973 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 974 cfg->domain, cfg->bus, cfg->slot, cfg->func); 975 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 976 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 977 2); 978 } 979 #endif 980 /* REG and WREG use carry through to next functions */ 981 } 982 983 /* 984 * PCI Vital Product Data 985 */ 986 987 #define PCI_VPD_TIMEOUT 1000000 988 989 static int 990 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 991 { 992 int count = PCI_VPD_TIMEOUT; 993 994 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 995 996 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 997 998 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 999 if (--count < 0) 1000 return (ENXIO); 1001 DELAY(1); /* limit looping */ 1002 } 1003 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1004 1005 return (0); 1006 } 1007 1008 #if 0 1009 static int 1010 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1011 { 1012 int count = PCI_VPD_TIMEOUT; 1013 1014 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1015 1016 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1017 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1018 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1019 if (--count < 0) 1020 return (ENXIO); 1021 DELAY(1); /* limit looping */ 1022 } 1023 1024 return (0); 1025 } 1026 #endif 1027 1028 #undef PCI_VPD_TIMEOUT 1029 1030 struct vpd_readstate { 1031 device_t pcib; 1032 pcicfgregs *cfg; 1033 uint32_t val; 1034 int bytesinval; 1035 int off; 1036 uint8_t cksum; 1037 }; 1038 1039 static int 1040 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1041 { 1042 uint32_t reg; 1043 uint8_t byte; 1044 1045 if (vrs->bytesinval == 0) { 1046 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1047 return (ENXIO); 1048 vrs->val = le32toh(reg); 1049 vrs->off += 4; 1050 byte = vrs->val & 0xff; 1051 vrs->bytesinval = 3; 1052 } else { 1053 vrs->val = vrs->val >> 8; 1054 byte = vrs->val & 0xff; 1055 vrs->bytesinval--; 1056 } 1057 1058 vrs->cksum += byte; 1059 *data = byte; 1060 return (0); 1061 } 1062 1063 static void 1064 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1065 { 1066 struct vpd_readstate vrs; 1067 int state; 1068 int name; 1069 int remain; 1070 int i; 1071 int alloc, off; /* alloc/off for RO/W arrays */ 1072 int cksumvalid; 1073 int dflen; 1074 uint8_t byte; 1075 uint8_t byte2; 1076 1077 /* init vpd reader */ 1078 vrs.bytesinval = 0; 1079 vrs.off = 0; 1080 vrs.pcib = pcib; 1081 vrs.cfg = cfg; 1082 vrs.cksum = 0; 1083 1084 state = 0; 1085 name = remain = i = 0; /* shut up stupid gcc */ 1086 alloc = off = 0; /* shut up stupid gcc */ 1087 dflen = 0; /* shut up stupid gcc */ 1088 cksumvalid = -1; 1089 while (state >= 0) { 1090 if (vpd_nextbyte(&vrs, &byte)) { 1091 state = -2; 1092 break; 1093 } 1094 #if 0 1095 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1096 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1097 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1098 #endif 1099 switch (state) { 1100 case 0: /* item name */ 1101 if (byte & 0x80) { 1102 if (vpd_nextbyte(&vrs, &byte2)) { 1103 state = -2; 1104 break; 1105 } 1106 remain = byte2; 1107 if (vpd_nextbyte(&vrs, &byte2)) { 1108 state = -2; 1109 break; 1110 } 1111 remain |= byte2 << 8; 1112 name = byte & 0x7f; 1113 } else { 1114 remain = byte & 0x7; 1115 name = (byte >> 3) & 0xf; 1116 } 1117 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1118 pci_printf(cfg, 1119 "VPD data overflow, remain %#x\n", remain); 1120 state = -1; 1121 break; 1122 } 1123 switch (name) { 1124 case 0x2: /* String */ 1125 cfg->vpd.vpd_ident = malloc(remain + 1, 1126 M_DEVBUF, M_WAITOK); 1127 i = 0; 1128 state = 1; 1129 break; 1130 case 0xf: /* End */ 1131 state = -1; 1132 break; 1133 case 0x10: /* VPD-R */ 1134 alloc = 8; 1135 off = 0; 1136 cfg->vpd.vpd_ros = malloc(alloc * 1137 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1138 M_WAITOK | M_ZERO); 1139 state = 2; 1140 break; 1141 case 0x11: /* VPD-W */ 1142 alloc = 8; 1143 off = 0; 1144 cfg->vpd.vpd_w = malloc(alloc * 1145 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1146 M_WAITOK | M_ZERO); 1147 state = 5; 1148 break; 1149 default: /* Invalid data, abort */ 1150 state = -1; 1151 break; 1152 } 1153 break; 1154 1155 case 1: /* Identifier String */ 1156 cfg->vpd.vpd_ident[i++] = byte; 1157 remain--; 1158 if (remain == 0) { 1159 cfg->vpd.vpd_ident[i] = '\0'; 1160 state = 0; 1161 } 1162 break; 1163 1164 case 2: /* VPD-R Keyword Header */ 1165 if (off == alloc) { 1166 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1167 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1168 M_DEVBUF, M_WAITOK | M_ZERO); 1169 } 1170 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1171 if (vpd_nextbyte(&vrs, &byte2)) { 1172 state = -2; 1173 break; 1174 } 1175 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1176 if (vpd_nextbyte(&vrs, &byte2)) { 1177 state = -2; 1178 break; 1179 } 1180 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1181 if (dflen == 0 && 1182 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1183 2) == 0) { 1184 /* 1185 * if this happens, we can't trust the rest 1186 * of the VPD. 1187 */ 1188 pci_printf(cfg, "bad keyword length: %d\n", 1189 dflen); 1190 cksumvalid = 0; 1191 state = -1; 1192 break; 1193 } else if (dflen == 0) { 1194 cfg->vpd.vpd_ros[off].value = malloc(1 * 1195 sizeof(*cfg->vpd.vpd_ros[off].value), 1196 M_DEVBUF, M_WAITOK); 1197 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1198 } else 1199 cfg->vpd.vpd_ros[off].value = malloc( 1200 (dflen + 1) * 1201 sizeof(*cfg->vpd.vpd_ros[off].value), 1202 M_DEVBUF, M_WAITOK); 1203 remain -= 3; 1204 i = 0; 1205 /* keep in sync w/ state 3's transistions */ 1206 if (dflen == 0 && remain == 0) 1207 state = 0; 1208 else if (dflen == 0) 1209 state = 2; 1210 else 1211 state = 3; 1212 break; 1213 1214 case 3: /* VPD-R Keyword Value */ 1215 cfg->vpd.vpd_ros[off].value[i++] = byte; 1216 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1217 "RV", 2) == 0 && cksumvalid == -1) { 1218 if (vrs.cksum == 0) 1219 cksumvalid = 1; 1220 else { 1221 if (bootverbose) 1222 pci_printf(cfg, 1223 "bad VPD cksum, remain %hhu\n", 1224 vrs.cksum); 1225 cksumvalid = 0; 1226 state = -1; 1227 break; 1228 } 1229 } 1230 dflen--; 1231 remain--; 1232 /* keep in sync w/ state 2's transistions */ 1233 if (dflen == 0) 1234 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1235 if (dflen == 0 && remain == 0) { 1236 cfg->vpd.vpd_rocnt = off; 1237 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1238 off * sizeof(*cfg->vpd.vpd_ros), 1239 M_DEVBUF, M_WAITOK | M_ZERO); 1240 state = 0; 1241 } else if (dflen == 0) 1242 state = 2; 1243 break; 1244 1245 case 4: 1246 remain--; 1247 if (remain == 0) 1248 state = 0; 1249 break; 1250 1251 case 5: /* VPD-W Keyword Header */ 1252 if (off == alloc) { 1253 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1254 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1255 M_DEVBUF, M_WAITOK | M_ZERO); 1256 } 1257 cfg->vpd.vpd_w[off].keyword[0] = byte; 1258 if (vpd_nextbyte(&vrs, &byte2)) { 1259 state = -2; 1260 break; 1261 } 1262 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1263 if (vpd_nextbyte(&vrs, &byte2)) { 1264 state = -2; 1265 break; 1266 } 1267 cfg->vpd.vpd_w[off].len = dflen = byte2; 1268 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1269 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1270 sizeof(*cfg->vpd.vpd_w[off].value), 1271 M_DEVBUF, M_WAITOK); 1272 remain -= 3; 1273 i = 0; 1274 /* keep in sync w/ state 6's transistions */ 1275 if (dflen == 0 && remain == 0) 1276 state = 0; 1277 else if (dflen == 0) 1278 state = 5; 1279 else 1280 state = 6; 1281 break; 1282 1283 case 6: /* VPD-W Keyword Value */ 1284 cfg->vpd.vpd_w[off].value[i++] = byte; 1285 dflen--; 1286 remain--; 1287 /* keep in sync w/ state 5's transistions */ 1288 if (dflen == 0) 1289 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1290 if (dflen == 0 && remain == 0) { 1291 cfg->vpd.vpd_wcnt = off; 1292 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1293 off * sizeof(*cfg->vpd.vpd_w), 1294 M_DEVBUF, M_WAITOK | M_ZERO); 1295 state = 0; 1296 } else if (dflen == 0) 1297 state = 5; 1298 break; 1299 1300 default: 1301 pci_printf(cfg, "invalid state: %d\n", state); 1302 state = -1; 1303 break; 1304 } 1305 } 1306 1307 if (cksumvalid == 0 || state < -1) { 1308 /* read-only data bad, clean up */ 1309 if (cfg->vpd.vpd_ros != NULL) { 1310 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1311 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1312 free(cfg->vpd.vpd_ros, M_DEVBUF); 1313 cfg->vpd.vpd_ros = NULL; 1314 } 1315 } 1316 if (state < -1) { 1317 /* I/O error, clean up */ 1318 pci_printf(cfg, "failed to read VPD data.\n"); 1319 if (cfg->vpd.vpd_ident != NULL) { 1320 free(cfg->vpd.vpd_ident, M_DEVBUF); 1321 cfg->vpd.vpd_ident = NULL; 1322 } 1323 if (cfg->vpd.vpd_w != NULL) { 1324 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1325 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1326 free(cfg->vpd.vpd_w, M_DEVBUF); 1327 cfg->vpd.vpd_w = NULL; 1328 } 1329 } 1330 cfg->vpd.vpd_cached = 1; 1331 #undef REG 1332 #undef WREG 1333 } 1334 1335 int 1336 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1337 { 1338 struct pci_devinfo *dinfo = device_get_ivars(child); 1339 pcicfgregs *cfg = &dinfo->cfg; 1340 1341 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1342 pci_read_vpd(device_get_parent(dev), cfg); 1343 1344 *identptr = cfg->vpd.vpd_ident; 1345 1346 if (*identptr == NULL) 1347 return (ENXIO); 1348 1349 return (0); 1350 } 1351 1352 int 1353 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1354 const char **vptr) 1355 { 1356 struct pci_devinfo *dinfo = device_get_ivars(child); 1357 pcicfgregs *cfg = &dinfo->cfg; 1358 int i; 1359 1360 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1361 pci_read_vpd(device_get_parent(dev), cfg); 1362 1363 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1364 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1365 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1366 *vptr = cfg->vpd.vpd_ros[i].value; 1367 return (0); 1368 } 1369 1370 *vptr = NULL; 1371 return (ENXIO); 1372 } 1373 1374 struct pcicfg_vpd * 1375 pci_fetch_vpd_list(device_t dev) 1376 { 1377 struct pci_devinfo *dinfo = device_get_ivars(dev); 1378 pcicfgregs *cfg = &dinfo->cfg; 1379 1380 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1381 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1382 return (&cfg->vpd); 1383 } 1384 1385 /* 1386 * Find the requested HyperTransport capability and return the offset 1387 * in configuration space via the pointer provided. The function 1388 * returns 0 on success and an error code otherwise. 1389 */ 1390 int 1391 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1392 { 1393 int ptr, error; 1394 uint16_t val; 1395 1396 error = pci_find_cap(child, PCIY_HT, &ptr); 1397 if (error) 1398 return (error); 1399 1400 /* 1401 * Traverse the capabilities list checking each HT capability 1402 * to see if it matches the requested HT capability. 1403 */ 1404 for (;;) { 1405 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1406 if (capability == PCIM_HTCAP_SLAVE || 1407 capability == PCIM_HTCAP_HOST) 1408 val &= 0xe000; 1409 else 1410 val &= PCIM_HTCMD_CAP_MASK; 1411 if (val == capability) { 1412 if (capreg != NULL) 1413 *capreg = ptr; 1414 return (0); 1415 } 1416 1417 /* Skip to the next HT capability. */ 1418 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1419 break; 1420 } 1421 1422 return (ENOENT); 1423 } 1424 1425 /* 1426 * Find the next requested HyperTransport capability after start and return 1427 * the offset in configuration space via the pointer provided. The function 1428 * returns 0 on success and an error code otherwise. 1429 */ 1430 int 1431 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1432 int start, int *capreg) 1433 { 1434 int ptr; 1435 uint16_t val; 1436 1437 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1438 ("start capability is not HyperTransport capability")); 1439 ptr = start; 1440 1441 /* 1442 * Traverse the capabilities list checking each HT capability 1443 * to see if it matches the requested HT capability. 1444 */ 1445 for (;;) { 1446 /* Skip to the next HT capability. */ 1447 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1448 break; 1449 1450 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1451 if (capability == PCIM_HTCAP_SLAVE || 1452 capability == PCIM_HTCAP_HOST) 1453 val &= 0xe000; 1454 else 1455 val &= PCIM_HTCMD_CAP_MASK; 1456 if (val == capability) { 1457 if (capreg != NULL) 1458 *capreg = ptr; 1459 return (0); 1460 } 1461 } 1462 1463 return (ENOENT); 1464 } 1465 1466 /* 1467 * Find the requested capability and return the offset in 1468 * configuration space via the pointer provided. The function returns 1469 * 0 on success and an error code otherwise. 1470 */ 1471 int 1472 pci_find_cap_method(device_t dev, device_t child, int capability, 1473 int *capreg) 1474 { 1475 struct pci_devinfo *dinfo = device_get_ivars(child); 1476 pcicfgregs *cfg = &dinfo->cfg; 1477 uint32_t status; 1478 uint8_t ptr; 1479 1480 /* 1481 * Check the CAP_LIST bit of the PCI status register first. 1482 */ 1483 status = pci_read_config(child, PCIR_STATUS, 2); 1484 if (!(status & PCIM_STATUS_CAPPRESENT)) 1485 return (ENXIO); 1486 1487 /* 1488 * Determine the start pointer of the capabilities list. 1489 */ 1490 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1491 case PCIM_HDRTYPE_NORMAL: 1492 case PCIM_HDRTYPE_BRIDGE: 1493 ptr = PCIR_CAP_PTR; 1494 break; 1495 case PCIM_HDRTYPE_CARDBUS: 1496 ptr = PCIR_CAP_PTR_2; 1497 break; 1498 default: 1499 /* XXX: panic? */ 1500 return (ENXIO); /* no extended capabilities support */ 1501 } 1502 ptr = pci_read_config(child, ptr, 1); 1503 1504 /* 1505 * Traverse the capabilities list. 1506 */ 1507 while (ptr != 0) { 1508 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1509 if (capreg != NULL) 1510 *capreg = ptr; 1511 return (0); 1512 } 1513 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1514 } 1515 1516 return (ENOENT); 1517 } 1518 1519 /* 1520 * Find the next requested capability after start and return the offset in 1521 * configuration space via the pointer provided. The function returns 1522 * 0 on success and an error code otherwise. 1523 */ 1524 int 1525 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1526 int start, int *capreg) 1527 { 1528 uint8_t ptr; 1529 1530 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1531 ("start capability is not expected capability")); 1532 1533 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1534 while (ptr != 0) { 1535 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1536 if (capreg != NULL) 1537 *capreg = ptr; 1538 return (0); 1539 } 1540 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1541 } 1542 1543 return (ENOENT); 1544 } 1545 1546 /* 1547 * Find the requested extended capability and return the offset in 1548 * configuration space via the pointer provided. The function returns 1549 * 0 on success and an error code otherwise. 1550 */ 1551 int 1552 pci_find_extcap_method(device_t dev, device_t child, int capability, 1553 int *capreg) 1554 { 1555 struct pci_devinfo *dinfo = device_get_ivars(child); 1556 pcicfgregs *cfg = &dinfo->cfg; 1557 uint32_t ecap; 1558 uint16_t ptr; 1559 1560 /* Only supported for PCI-express devices. */ 1561 if (cfg->pcie.pcie_location == 0) 1562 return (ENXIO); 1563 1564 ptr = PCIR_EXTCAP; 1565 ecap = pci_read_config(child, ptr, 4); 1566 if (ecap == 0xffffffff || ecap == 0) 1567 return (ENOENT); 1568 for (;;) { 1569 if (PCI_EXTCAP_ID(ecap) == capability) { 1570 if (capreg != NULL) 1571 *capreg = ptr; 1572 return (0); 1573 } 1574 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1575 if (ptr == 0) 1576 break; 1577 ecap = pci_read_config(child, ptr, 4); 1578 } 1579 1580 return (ENOENT); 1581 } 1582 1583 /* 1584 * Find the next requested extended capability after start and return the 1585 * offset in configuration space via the pointer provided. The function 1586 * returns 0 on success and an error code otherwise. 1587 */ 1588 int 1589 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1590 int start, int *capreg) 1591 { 1592 struct pci_devinfo *dinfo = device_get_ivars(child); 1593 pcicfgregs *cfg = &dinfo->cfg; 1594 uint32_t ecap; 1595 uint16_t ptr; 1596 1597 /* Only supported for PCI-express devices. */ 1598 if (cfg->pcie.pcie_location == 0) 1599 return (ENXIO); 1600 1601 ecap = pci_read_config(child, start, 4); 1602 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1603 ("start extended capability is not expected capability")); 1604 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1605 while (ptr != 0) { 1606 ecap = pci_read_config(child, ptr, 4); 1607 if (PCI_EXTCAP_ID(ecap) == capability) { 1608 if (capreg != NULL) 1609 *capreg = ptr; 1610 return (0); 1611 } 1612 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1613 } 1614 1615 return (ENOENT); 1616 } 1617 1618 /* 1619 * Support for MSI-X message interrupts. 1620 */ 1621 static void 1622 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1623 { 1624 struct pci_devinfo *dinfo = device_get_ivars(dev); 1625 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1626 uint32_t offset; 1627 1628 KASSERT(msix->msix_table_len > index, ("bogus index")); 1629 offset = msix->msix_table_offset + index * 16; 1630 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1631 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1632 bus_write_4(msix->msix_table_res, offset + 8, data); 1633 } 1634 1635 void 1636 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1637 uint64_t address, uint32_t data) 1638 { 1639 1640 if (pci_msix_rewrite_table) { 1641 struct pci_devinfo *dinfo = device_get_ivars(child); 1642 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1643 1644 /* 1645 * Some VM hosts require MSIX to be disabled in the 1646 * control register before updating the MSIX table 1647 * entries are allowed. It is not enough to only 1648 * disable MSIX while updating a single entry. MSIX 1649 * must be disabled while updating all entries in the 1650 * table. 1651 */ 1652 pci_write_config(child, 1653 msix->msix_location + PCIR_MSIX_CTRL, 1654 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1655 pci_resume_msix(child); 1656 } else 1657 pci_write_msix_entry(child, index, address, data); 1658 1659 /* Enable MSI -> HT mapping. */ 1660 pci_ht_map_msi(child, address); 1661 } 1662 1663 void 1664 pci_mask_msix(device_t dev, u_int index) 1665 { 1666 struct pci_devinfo *dinfo = device_get_ivars(dev); 1667 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1668 uint32_t offset, val; 1669 1670 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1671 offset = msix->msix_table_offset + index * 16 + 12; 1672 val = bus_read_4(msix->msix_table_res, offset); 1673 val |= PCIM_MSIX_VCTRL_MASK; 1674 1675 /* 1676 * Some devices (e.g. Samsung PM961) do not support reads of this 1677 * register, so always write the new value. 1678 */ 1679 bus_write_4(msix->msix_table_res, offset, val); 1680 } 1681 1682 void 1683 pci_unmask_msix(device_t dev, u_int index) 1684 { 1685 struct pci_devinfo *dinfo = device_get_ivars(dev); 1686 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1687 uint32_t offset, val; 1688 1689 KASSERT(msix->msix_table_len > index, ("bogus index")); 1690 offset = msix->msix_table_offset + index * 16 + 12; 1691 val = bus_read_4(msix->msix_table_res, offset); 1692 val &= ~PCIM_MSIX_VCTRL_MASK; 1693 1694 /* 1695 * Some devices (e.g. Samsung PM961) do not support reads of this 1696 * register, so always write the new value. 1697 */ 1698 bus_write_4(msix->msix_table_res, offset, val); 1699 } 1700 1701 int 1702 pci_pending_msix(device_t dev, u_int index) 1703 { 1704 struct pci_devinfo *dinfo = device_get_ivars(dev); 1705 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1706 uint32_t offset, bit; 1707 1708 KASSERT(msix->msix_table_len > index, ("bogus index")); 1709 offset = msix->msix_pba_offset + (index / 32) * 4; 1710 bit = 1 << index % 32; 1711 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1712 } 1713 1714 /* 1715 * Restore MSI-X registers and table during resume. If MSI-X is 1716 * enabled then walk the virtual table to restore the actual MSI-X 1717 * table. 1718 */ 1719 static void 1720 pci_resume_msix(device_t dev) 1721 { 1722 struct pci_devinfo *dinfo = device_get_ivars(dev); 1723 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1724 struct msix_table_entry *mte; 1725 struct msix_vector *mv; 1726 int i; 1727 1728 if (msix->msix_alloc > 0) { 1729 /* First, mask all vectors. */ 1730 for (i = 0; i < msix->msix_msgnum; i++) 1731 pci_mask_msix(dev, i); 1732 1733 /* Second, program any messages with at least one handler. */ 1734 for (i = 0; i < msix->msix_table_len; i++) { 1735 mte = &msix->msix_table[i]; 1736 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1737 continue; 1738 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1739 pci_write_msix_entry(dev, i, mv->mv_address, 1740 mv->mv_data); 1741 pci_unmask_msix(dev, i); 1742 } 1743 } 1744 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1745 msix->msix_ctrl, 2); 1746 } 1747 1748 /* 1749 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1750 * returned in *count. After this function returns, each message will be 1751 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1752 */ 1753 int 1754 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1755 { 1756 struct pci_devinfo *dinfo = device_get_ivars(child); 1757 pcicfgregs *cfg = &dinfo->cfg; 1758 struct resource_list_entry *rle; 1759 int actual, error, i, irq, max; 1760 1761 /* Don't let count == 0 get us into trouble. */ 1762 if (*count == 0) 1763 return (EINVAL); 1764 1765 /* If rid 0 is allocated, then fail. */ 1766 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1767 if (rle != NULL && rle->res != NULL) 1768 return (ENXIO); 1769 1770 /* Already have allocated messages? */ 1771 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1772 return (ENXIO); 1773 1774 /* If MSI-X is blacklisted for this system, fail. */ 1775 if (pci_msix_blacklisted()) 1776 return (ENXIO); 1777 1778 /* MSI-X capability present? */ 1779 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1780 return (ENODEV); 1781 1782 /* Make sure the appropriate BARs are mapped. */ 1783 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1784 cfg->msix.msix_table_bar); 1785 if (rle == NULL || rle->res == NULL || 1786 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1787 return (ENXIO); 1788 cfg->msix.msix_table_res = rle->res; 1789 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1790 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1791 cfg->msix.msix_pba_bar); 1792 if (rle == NULL || rle->res == NULL || 1793 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1794 return (ENXIO); 1795 } 1796 cfg->msix.msix_pba_res = rle->res; 1797 1798 if (bootverbose) 1799 device_printf(child, 1800 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1801 *count, cfg->msix.msix_msgnum); 1802 max = min(*count, cfg->msix.msix_msgnum); 1803 for (i = 0; i < max; i++) { 1804 /* Allocate a message. */ 1805 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1806 if (error) { 1807 if (i == 0) 1808 return (error); 1809 break; 1810 } 1811 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1812 irq, 1); 1813 } 1814 actual = i; 1815 1816 if (bootverbose) { 1817 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1818 if (actual == 1) 1819 device_printf(child, "using IRQ %ju for MSI-X\n", 1820 rle->start); 1821 else { 1822 int run; 1823 1824 /* 1825 * Be fancy and try to print contiguous runs of 1826 * IRQ values as ranges. 'irq' is the previous IRQ. 1827 * 'run' is true if we are in a range. 1828 */ 1829 device_printf(child, "using IRQs %ju", rle->start); 1830 irq = rle->start; 1831 run = 0; 1832 for (i = 1; i < actual; i++) { 1833 rle = resource_list_find(&dinfo->resources, 1834 SYS_RES_IRQ, i + 1); 1835 1836 /* Still in a run? */ 1837 if (rle->start == irq + 1) { 1838 run = 1; 1839 irq++; 1840 continue; 1841 } 1842 1843 /* Finish previous range. */ 1844 if (run) { 1845 printf("-%d", irq); 1846 run = 0; 1847 } 1848 1849 /* Start new range. */ 1850 printf(",%ju", rle->start); 1851 irq = rle->start; 1852 } 1853 1854 /* Unfinished range? */ 1855 if (run) 1856 printf("-%d", irq); 1857 printf(" for MSI-X\n"); 1858 } 1859 } 1860 1861 /* Mask all vectors. */ 1862 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1863 pci_mask_msix(child, i); 1864 1865 /* Allocate and initialize vector data and virtual table. */ 1866 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1867 M_DEVBUF, M_WAITOK | M_ZERO); 1868 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1869 M_DEVBUF, M_WAITOK | M_ZERO); 1870 for (i = 0; i < actual; i++) { 1871 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1872 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1873 cfg->msix.msix_table[i].mte_vector = i + 1; 1874 } 1875 1876 /* Update control register to enable MSI-X. */ 1877 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1878 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1879 cfg->msix.msix_ctrl, 2); 1880 1881 /* Update counts of alloc'd messages. */ 1882 cfg->msix.msix_alloc = actual; 1883 cfg->msix.msix_table_len = actual; 1884 *count = actual; 1885 return (0); 1886 } 1887 1888 /* 1889 * By default, pci_alloc_msix() will assign the allocated IRQ 1890 * resources consecutively to the first N messages in the MSI-X table. 1891 * However, device drivers may want to use different layouts if they 1892 * either receive fewer messages than they asked for, or they wish to 1893 * populate the MSI-X table sparsely. This method allows the driver 1894 * to specify what layout it wants. It must be called after a 1895 * successful pci_alloc_msix() but before any of the associated 1896 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1897 * 1898 * The 'vectors' array contains 'count' message vectors. The array 1899 * maps directly to the MSI-X table in that index 0 in the array 1900 * specifies the vector for the first message in the MSI-X table, etc. 1901 * The vector value in each array index can either be 0 to indicate 1902 * that no vector should be assigned to a message slot, or it can be a 1903 * number from 1 to N (where N is the count returned from a 1904 * succcessful call to pci_alloc_msix()) to indicate which message 1905 * vector (IRQ) to be used for the corresponding message. 1906 * 1907 * On successful return, each message with a non-zero vector will have 1908 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1909 * 1. Additionally, if any of the IRQs allocated via the previous 1910 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1911 * will be freed back to the system automatically. 1912 * 1913 * For example, suppose a driver has a MSI-X table with 6 messages and 1914 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1915 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1916 * C. After the call to pci_alloc_msix(), the device will be setup to 1917 * have an MSI-X table of ABC--- (where - means no vector assigned). 1918 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1919 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1920 * be freed back to the system. This device will also have valid 1921 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1922 * 1923 * In any case, the SYS_RES_IRQ rid X will always map to the message 1924 * at MSI-X table index X - 1 and will only be valid if a vector is 1925 * assigned to that table entry. 1926 */ 1927 int 1928 pci_remap_msix_method(device_t dev, device_t child, int count, 1929 const u_int *vectors) 1930 { 1931 struct pci_devinfo *dinfo = device_get_ivars(child); 1932 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1933 struct resource_list_entry *rle; 1934 int i, irq, j, *used; 1935 1936 /* 1937 * Have to have at least one message in the table but the 1938 * table can't be bigger than the actual MSI-X table in the 1939 * device. 1940 */ 1941 if (count == 0 || count > msix->msix_msgnum) 1942 return (EINVAL); 1943 1944 /* Sanity check the vectors. */ 1945 for (i = 0; i < count; i++) 1946 if (vectors[i] > msix->msix_alloc) 1947 return (EINVAL); 1948 1949 /* 1950 * Make sure there aren't any holes in the vectors to be used. 1951 * It's a big pain to support it, and it doesn't really make 1952 * sense anyway. Also, at least one vector must be used. 1953 */ 1954 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1955 M_ZERO); 1956 for (i = 0; i < count; i++) 1957 if (vectors[i] != 0) 1958 used[vectors[i] - 1] = 1; 1959 for (i = 0; i < msix->msix_alloc - 1; i++) 1960 if (used[i] == 0 && used[i + 1] == 1) { 1961 free(used, M_DEVBUF); 1962 return (EINVAL); 1963 } 1964 if (used[0] != 1) { 1965 free(used, M_DEVBUF); 1966 return (EINVAL); 1967 } 1968 1969 /* Make sure none of the resources are allocated. */ 1970 for (i = 0; i < msix->msix_table_len; i++) { 1971 if (msix->msix_table[i].mte_vector == 0) 1972 continue; 1973 if (msix->msix_table[i].mte_handlers > 0) { 1974 free(used, M_DEVBUF); 1975 return (EBUSY); 1976 } 1977 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1978 KASSERT(rle != NULL, ("missing resource")); 1979 if (rle->res != NULL) { 1980 free(used, M_DEVBUF); 1981 return (EBUSY); 1982 } 1983 } 1984 1985 /* Free the existing resource list entries. */ 1986 for (i = 0; i < msix->msix_table_len; i++) { 1987 if (msix->msix_table[i].mte_vector == 0) 1988 continue; 1989 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1990 } 1991 1992 /* 1993 * Build the new virtual table keeping track of which vectors are 1994 * used. 1995 */ 1996 free(msix->msix_table, M_DEVBUF); 1997 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1998 M_DEVBUF, M_WAITOK | M_ZERO); 1999 for (i = 0; i < count; i++) 2000 msix->msix_table[i].mte_vector = vectors[i]; 2001 msix->msix_table_len = count; 2002 2003 /* Free any unused IRQs and resize the vectors array if necessary. */ 2004 j = msix->msix_alloc - 1; 2005 if (used[j] == 0) { 2006 struct msix_vector *vec; 2007 2008 while (used[j] == 0) { 2009 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2010 msix->msix_vectors[j].mv_irq); 2011 j--; 2012 } 2013 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2014 M_WAITOK); 2015 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2016 (j + 1)); 2017 free(msix->msix_vectors, M_DEVBUF); 2018 msix->msix_vectors = vec; 2019 msix->msix_alloc = j + 1; 2020 } 2021 free(used, M_DEVBUF); 2022 2023 /* Map the IRQs onto the rids. */ 2024 for (i = 0; i < count; i++) { 2025 if (vectors[i] == 0) 2026 continue; 2027 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2028 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2029 irq, 1); 2030 } 2031 2032 if (bootverbose) { 2033 device_printf(child, "Remapped MSI-X IRQs as: "); 2034 for (i = 0; i < count; i++) { 2035 if (i != 0) 2036 printf(", "); 2037 if (vectors[i] == 0) 2038 printf("---"); 2039 else 2040 printf("%d", 2041 msix->msix_vectors[vectors[i] - 1].mv_irq); 2042 } 2043 printf("\n"); 2044 } 2045 2046 return (0); 2047 } 2048 2049 static int 2050 pci_release_msix(device_t dev, device_t child) 2051 { 2052 struct pci_devinfo *dinfo = device_get_ivars(child); 2053 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2054 struct resource_list_entry *rle; 2055 int i; 2056 2057 /* Do we have any messages to release? */ 2058 if (msix->msix_alloc == 0) 2059 return (ENODEV); 2060 2061 /* Make sure none of the resources are allocated. */ 2062 for (i = 0; i < msix->msix_table_len; i++) { 2063 if (msix->msix_table[i].mte_vector == 0) 2064 continue; 2065 if (msix->msix_table[i].mte_handlers > 0) 2066 return (EBUSY); 2067 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2068 KASSERT(rle != NULL, ("missing resource")); 2069 if (rle->res != NULL) 2070 return (EBUSY); 2071 } 2072 2073 /* Update control register to disable MSI-X. */ 2074 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2075 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2076 msix->msix_ctrl, 2); 2077 2078 /* Free the resource list entries. */ 2079 for (i = 0; i < msix->msix_table_len; i++) { 2080 if (msix->msix_table[i].mte_vector == 0) 2081 continue; 2082 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2083 } 2084 free(msix->msix_table, M_DEVBUF); 2085 msix->msix_table_len = 0; 2086 2087 /* Release the IRQs. */ 2088 for (i = 0; i < msix->msix_alloc; i++) 2089 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2090 msix->msix_vectors[i].mv_irq); 2091 free(msix->msix_vectors, M_DEVBUF); 2092 msix->msix_alloc = 0; 2093 return (0); 2094 } 2095 2096 /* 2097 * Return the max supported MSI-X messages this device supports. 2098 * Basically, assuming the MD code can alloc messages, this function 2099 * should return the maximum value that pci_alloc_msix() can return. 2100 * Thus, it is subject to the tunables, etc. 2101 */ 2102 int 2103 pci_msix_count_method(device_t dev, device_t child) 2104 { 2105 struct pci_devinfo *dinfo = device_get_ivars(child); 2106 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2107 2108 if (pci_do_msix && msix->msix_location != 0) 2109 return (msix->msix_msgnum); 2110 return (0); 2111 } 2112 2113 int 2114 pci_msix_pba_bar_method(device_t dev, device_t child) 2115 { 2116 struct pci_devinfo *dinfo = device_get_ivars(child); 2117 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2118 2119 if (pci_do_msix && msix->msix_location != 0) 2120 return (msix->msix_pba_bar); 2121 return (-1); 2122 } 2123 2124 int 2125 pci_msix_table_bar_method(device_t dev, device_t child) 2126 { 2127 struct pci_devinfo *dinfo = device_get_ivars(child); 2128 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2129 2130 if (pci_do_msix && msix->msix_location != 0) 2131 return (msix->msix_table_bar); 2132 return (-1); 2133 } 2134 2135 /* 2136 * HyperTransport MSI mapping control 2137 */ 2138 void 2139 pci_ht_map_msi(device_t dev, uint64_t addr) 2140 { 2141 struct pci_devinfo *dinfo = device_get_ivars(dev); 2142 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2143 2144 if (!ht->ht_msimap) 2145 return; 2146 2147 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2148 ht->ht_msiaddr >> 20 == addr >> 20) { 2149 /* Enable MSI -> HT mapping. */ 2150 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2151 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2152 ht->ht_msictrl, 2); 2153 } 2154 2155 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2156 /* Disable MSI -> HT mapping. */ 2157 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2158 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2159 ht->ht_msictrl, 2); 2160 } 2161 } 2162 2163 int 2164 pci_get_max_payload(device_t dev) 2165 { 2166 struct pci_devinfo *dinfo = device_get_ivars(dev); 2167 int cap; 2168 uint16_t val; 2169 2170 cap = dinfo->cfg.pcie.pcie_location; 2171 if (cap == 0) 2172 return (0); 2173 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2174 val &= PCIEM_CTL_MAX_PAYLOAD; 2175 val >>= 5; 2176 return (1 << (val + 7)); 2177 } 2178 2179 int 2180 pci_get_max_read_req(device_t dev) 2181 { 2182 struct pci_devinfo *dinfo = device_get_ivars(dev); 2183 int cap; 2184 uint16_t val; 2185 2186 cap = dinfo->cfg.pcie.pcie_location; 2187 if (cap == 0) 2188 return (0); 2189 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2190 val &= PCIEM_CTL_MAX_READ_REQUEST; 2191 val >>= 12; 2192 return (1 << (val + 7)); 2193 } 2194 2195 int 2196 pci_set_max_read_req(device_t dev, int size) 2197 { 2198 struct pci_devinfo *dinfo = device_get_ivars(dev); 2199 int cap; 2200 uint16_t val; 2201 2202 cap = dinfo->cfg.pcie.pcie_location; 2203 if (cap == 0) 2204 return (0); 2205 if (size < 128) 2206 size = 128; 2207 if (size > 4096) 2208 size = 4096; 2209 size = (1 << (fls(size) - 1)); 2210 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2211 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2212 val |= (fls(size) - 8) << 12; 2213 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2214 return (size); 2215 } 2216 2217 uint32_t 2218 pcie_read_config(device_t dev, int reg, int width) 2219 { 2220 struct pci_devinfo *dinfo = device_get_ivars(dev); 2221 int cap; 2222 2223 cap = dinfo->cfg.pcie.pcie_location; 2224 if (cap == 0) { 2225 if (width == 2) 2226 return (0xffff); 2227 return (0xffffffff); 2228 } 2229 2230 return (pci_read_config(dev, cap + reg, width)); 2231 } 2232 2233 void 2234 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2235 { 2236 struct pci_devinfo *dinfo = device_get_ivars(dev); 2237 int cap; 2238 2239 cap = dinfo->cfg.pcie.pcie_location; 2240 if (cap == 0) 2241 return; 2242 pci_write_config(dev, cap + reg, value, width); 2243 } 2244 2245 /* 2246 * Adjusts a PCI-e capability register by clearing the bits in mask 2247 * and setting the bits in (value & mask). Bits not set in mask are 2248 * not adjusted. 2249 * 2250 * Returns the old value on success or all ones on failure. 2251 */ 2252 uint32_t 2253 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2254 int width) 2255 { 2256 struct pci_devinfo *dinfo = device_get_ivars(dev); 2257 uint32_t old, new; 2258 int cap; 2259 2260 cap = dinfo->cfg.pcie.pcie_location; 2261 if (cap == 0) { 2262 if (width == 2) 2263 return (0xffff); 2264 return (0xffffffff); 2265 } 2266 2267 old = pci_read_config(dev, cap + reg, width); 2268 new = old & ~mask; 2269 new |= (value & mask); 2270 pci_write_config(dev, cap + reg, new, width); 2271 return (old); 2272 } 2273 2274 /* 2275 * Support for MSI message signalled interrupts. 2276 */ 2277 void 2278 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2279 uint16_t data) 2280 { 2281 struct pci_devinfo *dinfo = device_get_ivars(child); 2282 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2283 2284 /* Write data and address values. */ 2285 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2286 address & 0xffffffff, 4); 2287 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2288 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2289 address >> 32, 4); 2290 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2291 data, 2); 2292 } else 2293 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2294 2); 2295 2296 /* Enable MSI in the control register. */ 2297 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2298 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2299 msi->msi_ctrl, 2); 2300 2301 /* Enable MSI -> HT mapping. */ 2302 pci_ht_map_msi(child, address); 2303 } 2304 2305 void 2306 pci_disable_msi_method(device_t dev, device_t child) 2307 { 2308 struct pci_devinfo *dinfo = device_get_ivars(child); 2309 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2310 2311 /* Disable MSI -> HT mapping. */ 2312 pci_ht_map_msi(child, 0); 2313 2314 /* Disable MSI in the control register. */ 2315 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2316 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2317 msi->msi_ctrl, 2); 2318 } 2319 2320 /* 2321 * Restore MSI registers during resume. If MSI is enabled then 2322 * restore the data and address registers in addition to the control 2323 * register. 2324 */ 2325 static void 2326 pci_resume_msi(device_t dev) 2327 { 2328 struct pci_devinfo *dinfo = device_get_ivars(dev); 2329 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2330 uint64_t address; 2331 uint16_t data; 2332 2333 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2334 address = msi->msi_addr; 2335 data = msi->msi_data; 2336 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2337 address & 0xffffffff, 4); 2338 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2339 pci_write_config(dev, msi->msi_location + 2340 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2341 pci_write_config(dev, msi->msi_location + 2342 PCIR_MSI_DATA_64BIT, data, 2); 2343 } else 2344 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2345 data, 2); 2346 } 2347 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2348 2); 2349 } 2350 2351 static int 2352 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2353 { 2354 struct pci_devinfo *dinfo = device_get_ivars(dev); 2355 pcicfgregs *cfg = &dinfo->cfg; 2356 struct resource_list_entry *rle; 2357 struct msix_table_entry *mte; 2358 struct msix_vector *mv; 2359 uint64_t addr; 2360 uint32_t data; 2361 int error, i, j; 2362 2363 /* 2364 * Handle MSI first. We try to find this IRQ among our list 2365 * of MSI IRQs. If we find it, we request updated address and 2366 * data registers and apply the results. 2367 */ 2368 if (cfg->msi.msi_alloc > 0) { 2369 /* If we don't have any active handlers, nothing to do. */ 2370 if (cfg->msi.msi_handlers == 0) 2371 return (0); 2372 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2373 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2374 i + 1); 2375 if (rle->start == irq) { 2376 error = PCIB_MAP_MSI(device_get_parent(bus), 2377 dev, irq, &addr, &data); 2378 if (error) 2379 return (error); 2380 pci_disable_msi(dev); 2381 dinfo->cfg.msi.msi_addr = addr; 2382 dinfo->cfg.msi.msi_data = data; 2383 pci_enable_msi(dev, addr, data); 2384 return (0); 2385 } 2386 } 2387 return (ENOENT); 2388 } 2389 2390 /* 2391 * For MSI-X, we check to see if we have this IRQ. If we do, 2392 * we request the updated mapping info. If that works, we go 2393 * through all the slots that use this IRQ and update them. 2394 */ 2395 if (cfg->msix.msix_alloc > 0) { 2396 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2397 mv = &cfg->msix.msix_vectors[i]; 2398 if (mv->mv_irq == irq) { 2399 error = PCIB_MAP_MSI(device_get_parent(bus), 2400 dev, irq, &addr, &data); 2401 if (error) 2402 return (error); 2403 mv->mv_address = addr; 2404 mv->mv_data = data; 2405 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2406 mte = &cfg->msix.msix_table[j]; 2407 if (mte->mte_vector != i + 1) 2408 continue; 2409 if (mte->mte_handlers == 0) 2410 continue; 2411 pci_mask_msix(dev, j); 2412 pci_enable_msix(dev, j, addr, data); 2413 pci_unmask_msix(dev, j); 2414 } 2415 } 2416 } 2417 return (ENOENT); 2418 } 2419 2420 return (ENOENT); 2421 } 2422 2423 /* 2424 * Returns true if the specified device is blacklisted because MSI 2425 * doesn't work. 2426 */ 2427 int 2428 pci_msi_device_blacklisted(device_t dev) 2429 { 2430 2431 if (!pci_honor_msi_blacklist) 2432 return (0); 2433 2434 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2435 } 2436 2437 /* 2438 * Determine if MSI is blacklisted globally on this system. Currently, 2439 * we just check for blacklisted chipsets as represented by the 2440 * host-PCI bridge at device 0:0:0. In the future, it may become 2441 * necessary to check other system attributes, such as the kenv values 2442 * that give the motherboard manufacturer and model number. 2443 */ 2444 static int 2445 pci_msi_blacklisted(void) 2446 { 2447 device_t dev; 2448 2449 if (!pci_honor_msi_blacklist) 2450 return (0); 2451 2452 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2453 if (!(pcie_chipset || pcix_chipset)) { 2454 if (vm_guest != VM_GUEST_NO) { 2455 /* 2456 * Whitelist older chipsets in virtual 2457 * machines known to support MSI. 2458 */ 2459 dev = pci_find_bsf(0, 0, 0); 2460 if (dev != NULL) 2461 return (!pci_has_quirk(pci_get_devid(dev), 2462 PCI_QUIRK_ENABLE_MSI_VM)); 2463 } 2464 return (1); 2465 } 2466 2467 dev = pci_find_bsf(0, 0, 0); 2468 if (dev != NULL) 2469 return (pci_msi_device_blacklisted(dev)); 2470 return (0); 2471 } 2472 2473 /* 2474 * Returns true if the specified device is blacklisted because MSI-X 2475 * doesn't work. Note that this assumes that if MSI doesn't work, 2476 * MSI-X doesn't either. 2477 */ 2478 int 2479 pci_msix_device_blacklisted(device_t dev) 2480 { 2481 2482 if (!pci_honor_msi_blacklist) 2483 return (0); 2484 2485 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2486 return (1); 2487 2488 return (pci_msi_device_blacklisted(dev)); 2489 } 2490 2491 /* 2492 * Determine if MSI-X is blacklisted globally on this system. If MSI 2493 * is blacklisted, assume that MSI-X is as well. Check for additional 2494 * chipsets where MSI works but MSI-X does not. 2495 */ 2496 static int 2497 pci_msix_blacklisted(void) 2498 { 2499 device_t dev; 2500 2501 if (!pci_honor_msi_blacklist) 2502 return (0); 2503 2504 dev = pci_find_bsf(0, 0, 0); 2505 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2506 PCI_QUIRK_DISABLE_MSIX)) 2507 return (1); 2508 2509 return (pci_msi_blacklisted()); 2510 } 2511 2512 /* 2513 * Attempt to allocate *count MSI messages. The actual number allocated is 2514 * returned in *count. After this function returns, each message will be 2515 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2516 */ 2517 int 2518 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2519 { 2520 struct pci_devinfo *dinfo = device_get_ivars(child); 2521 pcicfgregs *cfg = &dinfo->cfg; 2522 struct resource_list_entry *rle; 2523 int actual, error, i, irqs[32]; 2524 uint16_t ctrl; 2525 2526 /* Don't let count == 0 get us into trouble. */ 2527 if (*count == 0) 2528 return (EINVAL); 2529 2530 /* If rid 0 is allocated, then fail. */ 2531 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2532 if (rle != NULL && rle->res != NULL) 2533 return (ENXIO); 2534 2535 /* Already have allocated messages? */ 2536 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2537 return (ENXIO); 2538 2539 /* If MSI is blacklisted for this system, fail. */ 2540 if (pci_msi_blacklisted()) 2541 return (ENXIO); 2542 2543 /* MSI capability present? */ 2544 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2545 return (ENODEV); 2546 2547 if (bootverbose) 2548 device_printf(child, 2549 "attempting to allocate %d MSI vectors (%d supported)\n", 2550 *count, cfg->msi.msi_msgnum); 2551 2552 /* Don't ask for more than the device supports. */ 2553 actual = min(*count, cfg->msi.msi_msgnum); 2554 2555 /* Don't ask for more than 32 messages. */ 2556 actual = min(actual, 32); 2557 2558 /* MSI requires power of 2 number of messages. */ 2559 if (!powerof2(actual)) 2560 return (EINVAL); 2561 2562 for (;;) { 2563 /* Try to allocate N messages. */ 2564 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2565 actual, irqs); 2566 if (error == 0) 2567 break; 2568 if (actual == 1) 2569 return (error); 2570 2571 /* Try N / 2. */ 2572 actual >>= 1; 2573 } 2574 2575 /* 2576 * We now have N actual messages mapped onto SYS_RES_IRQ 2577 * resources in the irqs[] array, so add new resources 2578 * starting at rid 1. 2579 */ 2580 for (i = 0; i < actual; i++) 2581 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2582 irqs[i], irqs[i], 1); 2583 2584 if (bootverbose) { 2585 if (actual == 1) 2586 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2587 else { 2588 int run; 2589 2590 /* 2591 * Be fancy and try to print contiguous runs 2592 * of IRQ values as ranges. 'run' is true if 2593 * we are in a range. 2594 */ 2595 device_printf(child, "using IRQs %d", irqs[0]); 2596 run = 0; 2597 for (i = 1; i < actual; i++) { 2598 /* Still in a run? */ 2599 if (irqs[i] == irqs[i - 1] + 1) { 2600 run = 1; 2601 continue; 2602 } 2603 2604 /* Finish previous range. */ 2605 if (run) { 2606 printf("-%d", irqs[i - 1]); 2607 run = 0; 2608 } 2609 2610 /* Start new range. */ 2611 printf(",%d", irqs[i]); 2612 } 2613 2614 /* Unfinished range? */ 2615 if (run) 2616 printf("-%d", irqs[actual - 1]); 2617 printf(" for MSI\n"); 2618 } 2619 } 2620 2621 /* Update control register with actual count. */ 2622 ctrl = cfg->msi.msi_ctrl; 2623 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2624 ctrl |= (ffs(actual) - 1) << 4; 2625 cfg->msi.msi_ctrl = ctrl; 2626 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2627 2628 /* Update counts of alloc'd messages. */ 2629 cfg->msi.msi_alloc = actual; 2630 cfg->msi.msi_handlers = 0; 2631 *count = actual; 2632 return (0); 2633 } 2634 2635 /* Release the MSI messages associated with this device. */ 2636 int 2637 pci_release_msi_method(device_t dev, device_t child) 2638 { 2639 struct pci_devinfo *dinfo = device_get_ivars(child); 2640 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2641 struct resource_list_entry *rle; 2642 int error, i, irqs[32]; 2643 2644 /* Try MSI-X first. */ 2645 error = pci_release_msix(dev, child); 2646 if (error != ENODEV) 2647 return (error); 2648 2649 /* Do we have any messages to release? */ 2650 if (msi->msi_alloc == 0) 2651 return (ENODEV); 2652 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2653 2654 /* Make sure none of the resources are allocated. */ 2655 if (msi->msi_handlers > 0) 2656 return (EBUSY); 2657 for (i = 0; i < msi->msi_alloc; i++) { 2658 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2659 KASSERT(rle != NULL, ("missing MSI resource")); 2660 if (rle->res != NULL) 2661 return (EBUSY); 2662 irqs[i] = rle->start; 2663 } 2664 2665 /* Update control register with 0 count. */ 2666 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2667 ("%s: MSI still enabled", __func__)); 2668 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2669 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2670 msi->msi_ctrl, 2); 2671 2672 /* Release the messages. */ 2673 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2674 for (i = 0; i < msi->msi_alloc; i++) 2675 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2676 2677 /* Update alloc count. */ 2678 msi->msi_alloc = 0; 2679 msi->msi_addr = 0; 2680 msi->msi_data = 0; 2681 return (0); 2682 } 2683 2684 /* 2685 * Return the max supported MSI messages this device supports. 2686 * Basically, assuming the MD code can alloc messages, this function 2687 * should return the maximum value that pci_alloc_msi() can return. 2688 * Thus, it is subject to the tunables, etc. 2689 */ 2690 int 2691 pci_msi_count_method(device_t dev, device_t child) 2692 { 2693 struct pci_devinfo *dinfo = device_get_ivars(child); 2694 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2695 2696 if (pci_do_msi && msi->msi_location != 0) 2697 return (msi->msi_msgnum); 2698 return (0); 2699 } 2700 2701 /* free pcicfgregs structure and all depending data structures */ 2702 2703 int 2704 pci_freecfg(struct pci_devinfo *dinfo) 2705 { 2706 struct devlist *devlist_head; 2707 struct pci_map *pm, *next; 2708 int i; 2709 2710 devlist_head = &pci_devq; 2711 2712 if (dinfo->cfg.vpd.vpd_reg) { 2713 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2714 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2715 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2716 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2717 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2718 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2719 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2720 } 2721 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2722 free(pm, M_DEVBUF); 2723 } 2724 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2725 free(dinfo, M_DEVBUF); 2726 2727 /* increment the generation count */ 2728 pci_generation++; 2729 2730 /* we're losing one device */ 2731 pci_numdevs--; 2732 return (0); 2733 } 2734 2735 /* 2736 * PCI power manangement 2737 */ 2738 int 2739 pci_set_powerstate_method(device_t dev, device_t child, int state) 2740 { 2741 struct pci_devinfo *dinfo = device_get_ivars(child); 2742 pcicfgregs *cfg = &dinfo->cfg; 2743 uint16_t status; 2744 int oldstate, highest, delay; 2745 2746 if (cfg->pp.pp_cap == 0) 2747 return (EOPNOTSUPP); 2748 2749 /* 2750 * Optimize a no state change request away. While it would be OK to 2751 * write to the hardware in theory, some devices have shown odd 2752 * behavior when going from D3 -> D3. 2753 */ 2754 oldstate = pci_get_powerstate(child); 2755 if (oldstate == state) 2756 return (0); 2757 2758 /* 2759 * The PCI power management specification states that after a state 2760 * transition between PCI power states, system software must 2761 * guarantee a minimal delay before the function accesses the device. 2762 * Compute the worst case delay that we need to guarantee before we 2763 * access the device. Many devices will be responsive much more 2764 * quickly than this delay, but there are some that don't respond 2765 * instantly to state changes. Transitions to/from D3 state require 2766 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2767 * is done below with DELAY rather than a sleeper function because 2768 * this function can be called from contexts where we cannot sleep. 2769 */ 2770 highest = (oldstate > state) ? oldstate : state; 2771 if (highest == PCI_POWERSTATE_D3) 2772 delay = 10000; 2773 else if (highest == PCI_POWERSTATE_D2) 2774 delay = 200; 2775 else 2776 delay = 0; 2777 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2778 & ~PCIM_PSTAT_DMASK; 2779 switch (state) { 2780 case PCI_POWERSTATE_D0: 2781 status |= PCIM_PSTAT_D0; 2782 break; 2783 case PCI_POWERSTATE_D1: 2784 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2785 return (EOPNOTSUPP); 2786 status |= PCIM_PSTAT_D1; 2787 break; 2788 case PCI_POWERSTATE_D2: 2789 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2790 return (EOPNOTSUPP); 2791 status |= PCIM_PSTAT_D2; 2792 break; 2793 case PCI_POWERSTATE_D3: 2794 status |= PCIM_PSTAT_D3; 2795 break; 2796 default: 2797 return (EINVAL); 2798 } 2799 2800 if (bootverbose) 2801 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2802 state); 2803 2804 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2805 if (delay) 2806 DELAY(delay); 2807 return (0); 2808 } 2809 2810 int 2811 pci_get_powerstate_method(device_t dev, device_t child) 2812 { 2813 struct pci_devinfo *dinfo = device_get_ivars(child); 2814 pcicfgregs *cfg = &dinfo->cfg; 2815 uint16_t status; 2816 int result; 2817 2818 if (cfg->pp.pp_cap != 0) { 2819 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2820 switch (status & PCIM_PSTAT_DMASK) { 2821 case PCIM_PSTAT_D0: 2822 result = PCI_POWERSTATE_D0; 2823 break; 2824 case PCIM_PSTAT_D1: 2825 result = PCI_POWERSTATE_D1; 2826 break; 2827 case PCIM_PSTAT_D2: 2828 result = PCI_POWERSTATE_D2; 2829 break; 2830 case PCIM_PSTAT_D3: 2831 result = PCI_POWERSTATE_D3; 2832 break; 2833 default: 2834 result = PCI_POWERSTATE_UNKNOWN; 2835 break; 2836 } 2837 } else { 2838 /* No support, device is always at D0 */ 2839 result = PCI_POWERSTATE_D0; 2840 } 2841 return (result); 2842 } 2843 2844 /* 2845 * Some convenience functions for PCI device drivers. 2846 */ 2847 2848 static __inline void 2849 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2850 { 2851 uint16_t command; 2852 2853 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2854 command |= bit; 2855 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2856 } 2857 2858 static __inline void 2859 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2860 { 2861 uint16_t command; 2862 2863 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2864 command &= ~bit; 2865 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2866 } 2867 2868 int 2869 pci_enable_busmaster_method(device_t dev, device_t child) 2870 { 2871 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2872 return (0); 2873 } 2874 2875 int 2876 pci_disable_busmaster_method(device_t dev, device_t child) 2877 { 2878 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2879 return (0); 2880 } 2881 2882 int 2883 pci_enable_io_method(device_t dev, device_t child, int space) 2884 { 2885 uint16_t bit; 2886 2887 switch(space) { 2888 case SYS_RES_IOPORT: 2889 bit = PCIM_CMD_PORTEN; 2890 break; 2891 case SYS_RES_MEMORY: 2892 bit = PCIM_CMD_MEMEN; 2893 break; 2894 default: 2895 return (EINVAL); 2896 } 2897 pci_set_command_bit(dev, child, bit); 2898 return (0); 2899 } 2900 2901 int 2902 pci_disable_io_method(device_t dev, device_t child, int space) 2903 { 2904 uint16_t bit; 2905 2906 switch(space) { 2907 case SYS_RES_IOPORT: 2908 bit = PCIM_CMD_PORTEN; 2909 break; 2910 case SYS_RES_MEMORY: 2911 bit = PCIM_CMD_MEMEN; 2912 break; 2913 default: 2914 return (EINVAL); 2915 } 2916 pci_clear_command_bit(dev, child, bit); 2917 return (0); 2918 } 2919 2920 /* 2921 * New style pci driver. Parent device is either a pci-host-bridge or a 2922 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2923 */ 2924 2925 void 2926 pci_print_verbose(struct pci_devinfo *dinfo) 2927 { 2928 2929 if (bootverbose) { 2930 pcicfgregs *cfg = &dinfo->cfg; 2931 2932 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2933 cfg->vendor, cfg->device, cfg->revid); 2934 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2935 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2936 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2937 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2938 cfg->mfdev); 2939 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2940 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2941 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2942 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2943 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2944 if (cfg->intpin > 0) 2945 printf("\tintpin=%c, irq=%d\n", 2946 cfg->intpin +'a' -1, cfg->intline); 2947 if (cfg->pp.pp_cap) { 2948 uint16_t status; 2949 2950 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2951 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2952 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2953 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2954 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2955 status & PCIM_PSTAT_DMASK); 2956 } 2957 if (cfg->msi.msi_location) { 2958 int ctrl; 2959 2960 ctrl = cfg->msi.msi_ctrl; 2961 printf("\tMSI supports %d message%s%s%s\n", 2962 cfg->msi.msi_msgnum, 2963 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2964 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2965 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2966 } 2967 if (cfg->msix.msix_location) { 2968 printf("\tMSI-X supports %d message%s ", 2969 cfg->msix.msix_msgnum, 2970 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2971 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2972 printf("in map 0x%x\n", 2973 cfg->msix.msix_table_bar); 2974 else 2975 printf("in maps 0x%x and 0x%x\n", 2976 cfg->msix.msix_table_bar, 2977 cfg->msix.msix_pba_bar); 2978 } 2979 } 2980 } 2981 2982 static int 2983 pci_porten(device_t dev) 2984 { 2985 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2986 } 2987 2988 static int 2989 pci_memen(device_t dev) 2990 { 2991 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2992 } 2993 2994 void 2995 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 2996 int *bar64) 2997 { 2998 struct pci_devinfo *dinfo; 2999 pci_addr_t map, testval; 3000 int ln2range; 3001 uint16_t cmd; 3002 3003 /* 3004 * The device ROM BAR is special. It is always a 32-bit 3005 * memory BAR. Bit 0 is special and should not be set when 3006 * sizing the BAR. 3007 */ 3008 dinfo = device_get_ivars(dev); 3009 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3010 map = pci_read_config(dev, reg, 4); 3011 pci_write_config(dev, reg, 0xfffffffe, 4); 3012 testval = pci_read_config(dev, reg, 4); 3013 pci_write_config(dev, reg, map, 4); 3014 *mapp = map; 3015 *testvalp = testval; 3016 if (bar64 != NULL) 3017 *bar64 = 0; 3018 return; 3019 } 3020 3021 map = pci_read_config(dev, reg, 4); 3022 ln2range = pci_maprange(map); 3023 if (ln2range == 64) 3024 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3025 3026 /* 3027 * Disable decoding via the command register before 3028 * determining the BAR's length since we will be placing it in 3029 * a weird state. 3030 */ 3031 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3032 pci_write_config(dev, PCIR_COMMAND, 3033 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3034 3035 /* 3036 * Determine the BAR's length by writing all 1's. The bottom 3037 * log_2(size) bits of the BAR will stick as 0 when we read 3038 * the value back. 3039 * 3040 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3041 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3042 * and combines the result into a 64-bit value." (section 6.2.5.1) 3043 * 3044 * Writes to both registers must be performed before attempting to 3045 * read back the size value. 3046 */ 3047 testval = 0; 3048 pci_write_config(dev, reg, 0xffffffff, 4); 3049 if (ln2range == 64) { 3050 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3051 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3052 } 3053 testval |= pci_read_config(dev, reg, 4); 3054 3055 /* 3056 * Restore the original value of the BAR. We may have reprogrammed 3057 * the BAR of the low-level console device and when booting verbose, 3058 * we need the console device addressable. 3059 */ 3060 pci_write_config(dev, reg, map, 4); 3061 if (ln2range == 64) 3062 pci_write_config(dev, reg + 4, map >> 32, 4); 3063 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3064 3065 *mapp = map; 3066 *testvalp = testval; 3067 if (bar64 != NULL) 3068 *bar64 = (ln2range == 64); 3069 } 3070 3071 static void 3072 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3073 { 3074 struct pci_devinfo *dinfo; 3075 int ln2range; 3076 3077 /* The device ROM BAR is always a 32-bit memory BAR. */ 3078 dinfo = device_get_ivars(dev); 3079 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3080 ln2range = 32; 3081 else 3082 ln2range = pci_maprange(pm->pm_value); 3083 pci_write_config(dev, pm->pm_reg, base, 4); 3084 if (ln2range == 64) 3085 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3086 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3087 if (ln2range == 64) 3088 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3089 pm->pm_reg + 4, 4) << 32; 3090 } 3091 3092 struct pci_map * 3093 pci_find_bar(device_t dev, int reg) 3094 { 3095 struct pci_devinfo *dinfo; 3096 struct pci_map *pm; 3097 3098 dinfo = device_get_ivars(dev); 3099 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3100 if (pm->pm_reg == reg) 3101 return (pm); 3102 } 3103 return (NULL); 3104 } 3105 3106 int 3107 pci_bar_enabled(device_t dev, struct pci_map *pm) 3108 { 3109 struct pci_devinfo *dinfo; 3110 uint16_t cmd; 3111 3112 dinfo = device_get_ivars(dev); 3113 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3114 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3115 return (0); 3116 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3117 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3118 return ((cmd & PCIM_CMD_MEMEN) != 0); 3119 else 3120 return ((cmd & PCIM_CMD_PORTEN) != 0); 3121 } 3122 3123 struct pci_map * 3124 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3125 { 3126 struct pci_devinfo *dinfo; 3127 struct pci_map *pm, *prev; 3128 3129 dinfo = device_get_ivars(dev); 3130 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3131 pm->pm_reg = reg; 3132 pm->pm_value = value; 3133 pm->pm_size = size; 3134 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3135 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3136 reg)); 3137 if (STAILQ_NEXT(prev, pm_link) == NULL || 3138 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3139 break; 3140 } 3141 if (prev != NULL) 3142 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3143 else 3144 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3145 return (pm); 3146 } 3147 3148 static void 3149 pci_restore_bars(device_t dev) 3150 { 3151 struct pci_devinfo *dinfo; 3152 struct pci_map *pm; 3153 int ln2range; 3154 3155 dinfo = device_get_ivars(dev); 3156 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3157 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3158 ln2range = 32; 3159 else 3160 ln2range = pci_maprange(pm->pm_value); 3161 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3162 if (ln2range == 64) 3163 pci_write_config(dev, pm->pm_reg + 4, 3164 pm->pm_value >> 32, 4); 3165 } 3166 } 3167 3168 /* 3169 * Add a resource based on a pci map register. Return 1 if the map 3170 * register is a 32bit map register or 2 if it is a 64bit register. 3171 */ 3172 static int 3173 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3174 int force, int prefetch) 3175 { 3176 struct pci_map *pm; 3177 pci_addr_t base, map, testval; 3178 pci_addr_t start, end, count; 3179 int barlen, basezero, flags, maprange, mapsize, type; 3180 uint16_t cmd; 3181 struct resource *res; 3182 3183 /* 3184 * The BAR may already exist if the device is a CardBus card 3185 * whose CIS is stored in this BAR. 3186 */ 3187 pm = pci_find_bar(dev, reg); 3188 if (pm != NULL) { 3189 maprange = pci_maprange(pm->pm_value); 3190 barlen = maprange == 64 ? 2 : 1; 3191 return (barlen); 3192 } 3193 3194 pci_read_bar(dev, reg, &map, &testval, NULL); 3195 if (PCI_BAR_MEM(map)) { 3196 type = SYS_RES_MEMORY; 3197 if (map & PCIM_BAR_MEM_PREFETCH) 3198 prefetch = 1; 3199 } else 3200 type = SYS_RES_IOPORT; 3201 mapsize = pci_mapsize(testval); 3202 base = pci_mapbase(map); 3203 #ifdef __PCI_BAR_ZERO_VALID 3204 basezero = 0; 3205 #else 3206 basezero = base == 0; 3207 #endif 3208 maprange = pci_maprange(map); 3209 barlen = maprange == 64 ? 2 : 1; 3210 3211 /* 3212 * For I/O registers, if bottom bit is set, and the next bit up 3213 * isn't clear, we know we have a BAR that doesn't conform to the 3214 * spec, so ignore it. Also, sanity check the size of the data 3215 * areas to the type of memory involved. Memory must be at least 3216 * 16 bytes in size, while I/O ranges must be at least 4. 3217 */ 3218 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3219 return (barlen); 3220 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3221 (type == SYS_RES_IOPORT && mapsize < 2)) 3222 return (barlen); 3223 3224 /* Save a record of this BAR. */ 3225 pm = pci_add_bar(dev, reg, map, mapsize); 3226 if (bootverbose) { 3227 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3228 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3229 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3230 printf(", port disabled\n"); 3231 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3232 printf(", memory disabled\n"); 3233 else 3234 printf(", enabled\n"); 3235 } 3236 3237 /* 3238 * If base is 0, then we have problems if this architecture does 3239 * not allow that. It is best to ignore such entries for the 3240 * moment. These will be allocated later if the driver specifically 3241 * requests them. However, some removable buses look better when 3242 * all resources are allocated, so allow '0' to be overriden. 3243 * 3244 * Similarly treat maps whose values is the same as the test value 3245 * read back. These maps have had all f's written to them by the 3246 * BIOS in an attempt to disable the resources. 3247 */ 3248 if (!force && (basezero || map == testval)) 3249 return (barlen); 3250 if ((u_long)base != base) { 3251 device_printf(bus, 3252 "pci%d:%d:%d:%d bar %#x too many address bits", 3253 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3254 pci_get_function(dev), reg); 3255 return (barlen); 3256 } 3257 3258 /* 3259 * This code theoretically does the right thing, but has 3260 * undesirable side effects in some cases where peripherals 3261 * respond oddly to having these bits enabled. Let the user 3262 * be able to turn them off (since pci_enable_io_modes is 1 by 3263 * default). 3264 */ 3265 if (pci_enable_io_modes) { 3266 /* Turn on resources that have been left off by a lazy BIOS */ 3267 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3268 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3269 cmd |= PCIM_CMD_PORTEN; 3270 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3271 } 3272 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3273 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3274 cmd |= PCIM_CMD_MEMEN; 3275 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3276 } 3277 } else { 3278 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3279 return (barlen); 3280 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3281 return (barlen); 3282 } 3283 3284 count = (pci_addr_t)1 << mapsize; 3285 flags = RF_ALIGNMENT_LOG2(mapsize); 3286 if (prefetch) 3287 flags |= RF_PREFETCHABLE; 3288 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3289 start = 0; /* Let the parent decide. */ 3290 end = ~0; 3291 } else { 3292 start = base; 3293 end = base + count - 1; 3294 } 3295 resource_list_add(rl, type, reg, start, end, count); 3296 3297 /* 3298 * Try to allocate the resource for this BAR from our parent 3299 * so that this resource range is already reserved. The 3300 * driver for this device will later inherit this resource in 3301 * pci_alloc_resource(). 3302 */ 3303 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3304 flags); 3305 if ((pci_do_realloc_bars 3306 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3307 && res == NULL && (start != 0 || end != ~0)) { 3308 /* 3309 * If the allocation fails, try to allocate a resource for 3310 * this BAR using any available range. The firmware felt 3311 * it was important enough to assign a resource, so don't 3312 * disable decoding if we can help it. 3313 */ 3314 resource_list_delete(rl, type, reg); 3315 resource_list_add(rl, type, reg, 0, ~0, count); 3316 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3317 count, flags); 3318 } 3319 if (res == NULL) { 3320 /* 3321 * If the allocation fails, delete the resource list entry 3322 * and disable decoding for this device. 3323 * 3324 * If the driver requests this resource in the future, 3325 * pci_reserve_map() will try to allocate a fresh 3326 * resource range. 3327 */ 3328 resource_list_delete(rl, type, reg); 3329 pci_disable_io(dev, type); 3330 if (bootverbose) 3331 device_printf(bus, 3332 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3333 pci_get_domain(dev), pci_get_bus(dev), 3334 pci_get_slot(dev), pci_get_function(dev), reg); 3335 } else { 3336 start = rman_get_start(res); 3337 pci_write_bar(dev, pm, start); 3338 } 3339 return (barlen); 3340 } 3341 3342 /* 3343 * For ATA devices we need to decide early what addressing mode to use. 3344 * Legacy demands that the primary and secondary ATA ports sits on the 3345 * same addresses that old ISA hardware did. This dictates that we use 3346 * those addresses and ignore the BAR's if we cannot set PCI native 3347 * addressing mode. 3348 */ 3349 static void 3350 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3351 uint32_t prefetchmask) 3352 { 3353 int rid, type, progif; 3354 #if 0 3355 /* if this device supports PCI native addressing use it */ 3356 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3357 if ((progif & 0x8a) == 0x8a) { 3358 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3359 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3360 printf("Trying ATA native PCI addressing mode\n"); 3361 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3362 } 3363 } 3364 #endif 3365 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3366 type = SYS_RES_IOPORT; 3367 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3368 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3369 prefetchmask & (1 << 0)); 3370 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3371 prefetchmask & (1 << 1)); 3372 } else { 3373 rid = PCIR_BAR(0); 3374 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3375 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3376 0x1f7, 8, 0); 3377 rid = PCIR_BAR(1); 3378 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3379 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3380 0x3f6, 1, 0); 3381 } 3382 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3383 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3384 prefetchmask & (1 << 2)); 3385 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3386 prefetchmask & (1 << 3)); 3387 } else { 3388 rid = PCIR_BAR(2); 3389 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3390 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3391 0x177, 8, 0); 3392 rid = PCIR_BAR(3); 3393 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3394 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3395 0x376, 1, 0); 3396 } 3397 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3398 prefetchmask & (1 << 4)); 3399 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3400 prefetchmask & (1 << 5)); 3401 } 3402 3403 static void 3404 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3405 { 3406 struct pci_devinfo *dinfo = device_get_ivars(dev); 3407 pcicfgregs *cfg = &dinfo->cfg; 3408 char tunable_name[64]; 3409 int irq; 3410 3411 /* Has to have an intpin to have an interrupt. */ 3412 if (cfg->intpin == 0) 3413 return; 3414 3415 /* Let the user override the IRQ with a tunable. */ 3416 irq = PCI_INVALID_IRQ; 3417 snprintf(tunable_name, sizeof(tunable_name), 3418 "hw.pci%d.%d.%d.INT%c.irq", 3419 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3420 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3421 irq = PCI_INVALID_IRQ; 3422 3423 /* 3424 * If we didn't get an IRQ via the tunable, then we either use the 3425 * IRQ value in the intline register or we ask the bus to route an 3426 * interrupt for us. If force_route is true, then we only use the 3427 * value in the intline register if the bus was unable to assign an 3428 * IRQ. 3429 */ 3430 if (!PCI_INTERRUPT_VALID(irq)) { 3431 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3432 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3433 if (!PCI_INTERRUPT_VALID(irq)) 3434 irq = cfg->intline; 3435 } 3436 3437 /* If after all that we don't have an IRQ, just bail. */ 3438 if (!PCI_INTERRUPT_VALID(irq)) 3439 return; 3440 3441 /* Update the config register if it changed. */ 3442 if (irq != cfg->intline) { 3443 cfg->intline = irq; 3444 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3445 } 3446 3447 /* Add this IRQ as rid 0 interrupt resource. */ 3448 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3449 } 3450 3451 /* Perform early OHCI takeover from SMM. */ 3452 static void 3453 ohci_early_takeover(device_t self) 3454 { 3455 struct resource *res; 3456 uint32_t ctl; 3457 int rid; 3458 int i; 3459 3460 rid = PCIR_BAR(0); 3461 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3462 if (res == NULL) 3463 return; 3464 3465 ctl = bus_read_4(res, OHCI_CONTROL); 3466 if (ctl & OHCI_IR) { 3467 if (bootverbose) 3468 printf("ohci early: " 3469 "SMM active, request owner change\n"); 3470 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3471 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3472 DELAY(1000); 3473 ctl = bus_read_4(res, OHCI_CONTROL); 3474 } 3475 if (ctl & OHCI_IR) { 3476 if (bootverbose) 3477 printf("ohci early: " 3478 "SMM does not respond, resetting\n"); 3479 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3480 } 3481 /* Disable interrupts */ 3482 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3483 } 3484 3485 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3486 } 3487 3488 /* Perform early UHCI takeover from SMM. */ 3489 static void 3490 uhci_early_takeover(device_t self) 3491 { 3492 struct resource *res; 3493 int rid; 3494 3495 /* 3496 * Set the PIRQD enable bit and switch off all the others. We don't 3497 * want legacy support to interfere with us XXX Does this also mean 3498 * that the BIOS won't touch the keyboard anymore if it is connected 3499 * to the ports of the root hub? 3500 */ 3501 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3502 3503 /* Disable interrupts */ 3504 rid = PCI_UHCI_BASE_REG; 3505 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3506 if (res != NULL) { 3507 bus_write_2(res, UHCI_INTR, 0); 3508 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3509 } 3510 } 3511 3512 /* Perform early EHCI takeover from SMM. */ 3513 static void 3514 ehci_early_takeover(device_t self) 3515 { 3516 struct resource *res; 3517 uint32_t cparams; 3518 uint32_t eec; 3519 uint8_t eecp; 3520 uint8_t bios_sem; 3521 uint8_t offs; 3522 int rid; 3523 int i; 3524 3525 rid = PCIR_BAR(0); 3526 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3527 if (res == NULL) 3528 return; 3529 3530 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3531 3532 /* Synchronise with the BIOS if it owns the controller. */ 3533 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3534 eecp = EHCI_EECP_NEXT(eec)) { 3535 eec = pci_read_config(self, eecp, 4); 3536 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3537 continue; 3538 } 3539 bios_sem = pci_read_config(self, eecp + 3540 EHCI_LEGSUP_BIOS_SEM, 1); 3541 if (bios_sem == 0) { 3542 continue; 3543 } 3544 if (bootverbose) 3545 printf("ehci early: " 3546 "SMM active, request owner change\n"); 3547 3548 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3549 3550 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3551 DELAY(1000); 3552 bios_sem = pci_read_config(self, eecp + 3553 EHCI_LEGSUP_BIOS_SEM, 1); 3554 } 3555 3556 if (bios_sem != 0) { 3557 if (bootverbose) 3558 printf("ehci early: " 3559 "SMM does not respond\n"); 3560 } 3561 /* Disable interrupts */ 3562 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3563 bus_write_4(res, offs + EHCI_USBINTR, 0); 3564 } 3565 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3566 } 3567 3568 /* Perform early XHCI takeover from SMM. */ 3569 static void 3570 xhci_early_takeover(device_t self) 3571 { 3572 struct resource *res; 3573 uint32_t cparams; 3574 uint32_t eec; 3575 uint8_t eecp; 3576 uint8_t bios_sem; 3577 uint8_t offs; 3578 int rid; 3579 int i; 3580 3581 rid = PCIR_BAR(0); 3582 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3583 if (res == NULL) 3584 return; 3585 3586 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3587 3588 eec = -1; 3589 3590 /* Synchronise with the BIOS if it owns the controller. */ 3591 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3592 eecp += XHCI_XECP_NEXT(eec) << 2) { 3593 eec = bus_read_4(res, eecp); 3594 3595 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3596 continue; 3597 3598 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3599 if (bios_sem == 0) 3600 continue; 3601 3602 if (bootverbose) 3603 printf("xhci early: " 3604 "SMM active, request owner change\n"); 3605 3606 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3607 3608 /* wait a maximum of 5 second */ 3609 3610 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3611 DELAY(1000); 3612 bios_sem = bus_read_1(res, eecp + 3613 XHCI_XECP_BIOS_SEM); 3614 } 3615 3616 if (bios_sem != 0) { 3617 if (bootverbose) 3618 printf("xhci early: " 3619 "SMM does not respond\n"); 3620 } 3621 3622 /* Disable interrupts */ 3623 offs = bus_read_1(res, XHCI_CAPLENGTH); 3624 bus_write_4(res, offs + XHCI_USBCMD, 0); 3625 bus_read_4(res, offs + XHCI_USBSTS); 3626 } 3627 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3628 } 3629 3630 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3631 static void 3632 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3633 struct resource_list *rl) 3634 { 3635 struct resource *res; 3636 char *cp; 3637 rman_res_t start, end, count; 3638 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3639 3640 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3641 case PCIM_HDRTYPE_BRIDGE: 3642 sec_reg = PCIR_SECBUS_1; 3643 sub_reg = PCIR_SUBBUS_1; 3644 break; 3645 case PCIM_HDRTYPE_CARDBUS: 3646 sec_reg = PCIR_SECBUS_2; 3647 sub_reg = PCIR_SUBBUS_2; 3648 break; 3649 default: 3650 return; 3651 } 3652 3653 /* 3654 * If the existing bus range is valid, attempt to reserve it 3655 * from our parent. If this fails for any reason, clear the 3656 * secbus and subbus registers. 3657 * 3658 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3659 * This would at least preserve the existing sec_bus if it is 3660 * valid. 3661 */ 3662 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3663 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3664 3665 /* Quirk handling. */ 3666 switch (pci_get_devid(dev)) { 3667 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3668 sup_bus = pci_read_config(dev, 0x41, 1); 3669 if (sup_bus != 0xff) { 3670 sec_bus = sup_bus + 1; 3671 sub_bus = sup_bus + 1; 3672 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3673 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3674 } 3675 break; 3676 3677 case 0x00dd10de: 3678 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3679 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3680 break; 3681 if (strncmp(cp, "Compal", 6) != 0) { 3682 freeenv(cp); 3683 break; 3684 } 3685 freeenv(cp); 3686 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3687 break; 3688 if (strncmp(cp, "08A0", 4) != 0) { 3689 freeenv(cp); 3690 break; 3691 } 3692 freeenv(cp); 3693 if (sub_bus < 0xa) { 3694 sub_bus = 0xa; 3695 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3696 } 3697 break; 3698 } 3699 3700 if (bootverbose) 3701 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3702 if (sec_bus > 0 && sub_bus >= sec_bus) { 3703 start = sec_bus; 3704 end = sub_bus; 3705 count = end - start + 1; 3706 3707 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3708 3709 /* 3710 * If requested, clear secondary bus registers in 3711 * bridge devices to force a complete renumbering 3712 * rather than reserving the existing range. However, 3713 * preserve the existing size. 3714 */ 3715 if (pci_clear_buses) 3716 goto clear; 3717 3718 rid = 0; 3719 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3720 start, end, count, 0); 3721 if (res != NULL) 3722 return; 3723 3724 if (bootverbose) 3725 device_printf(bus, 3726 "pci%d:%d:%d:%d secbus failed to allocate\n", 3727 pci_get_domain(dev), pci_get_bus(dev), 3728 pci_get_slot(dev), pci_get_function(dev)); 3729 } 3730 3731 clear: 3732 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3733 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3734 } 3735 3736 static struct resource * 3737 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3738 rman_res_t end, rman_res_t count, u_int flags) 3739 { 3740 struct pci_devinfo *dinfo; 3741 pcicfgregs *cfg; 3742 struct resource_list *rl; 3743 struct resource *res; 3744 int sec_reg, sub_reg; 3745 3746 dinfo = device_get_ivars(child); 3747 cfg = &dinfo->cfg; 3748 rl = &dinfo->resources; 3749 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3750 case PCIM_HDRTYPE_BRIDGE: 3751 sec_reg = PCIR_SECBUS_1; 3752 sub_reg = PCIR_SUBBUS_1; 3753 break; 3754 case PCIM_HDRTYPE_CARDBUS: 3755 sec_reg = PCIR_SECBUS_2; 3756 sub_reg = PCIR_SUBBUS_2; 3757 break; 3758 default: 3759 return (NULL); 3760 } 3761 3762 if (*rid != 0) 3763 return (NULL); 3764 3765 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3766 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3767 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3768 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3769 start, end, count, flags & ~RF_ACTIVE); 3770 if (res == NULL) { 3771 resource_list_delete(rl, PCI_RES_BUS, *rid); 3772 device_printf(child, "allocating %ju bus%s failed\n", 3773 count, count == 1 ? "" : "es"); 3774 return (NULL); 3775 } 3776 if (bootverbose) 3777 device_printf(child, 3778 "Lazy allocation of %ju bus%s at %ju\n", count, 3779 count == 1 ? "" : "es", rman_get_start(res)); 3780 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3781 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3782 } 3783 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3784 end, count, flags)); 3785 } 3786 #endif 3787 3788 static int 3789 pci_ea_bei_to_rid(device_t dev, int bei) 3790 { 3791 #ifdef PCI_IOV 3792 struct pci_devinfo *dinfo; 3793 int iov_pos; 3794 struct pcicfg_iov *iov; 3795 3796 dinfo = device_get_ivars(dev); 3797 iov = dinfo->cfg.iov; 3798 if (iov != NULL) 3799 iov_pos = iov->iov_pos; 3800 else 3801 iov_pos = 0; 3802 #endif 3803 3804 /* Check if matches BAR */ 3805 if ((bei >= PCIM_EA_BEI_BAR_0) && 3806 (bei <= PCIM_EA_BEI_BAR_5)) 3807 return (PCIR_BAR(bei)); 3808 3809 /* Check ROM */ 3810 if (bei == PCIM_EA_BEI_ROM) 3811 return (PCIR_BIOS); 3812 3813 #ifdef PCI_IOV 3814 /* Check if matches VF_BAR */ 3815 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3816 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3817 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3818 iov_pos); 3819 #endif 3820 3821 return (-1); 3822 } 3823 3824 int 3825 pci_ea_is_enabled(device_t dev, int rid) 3826 { 3827 struct pci_ea_entry *ea; 3828 struct pci_devinfo *dinfo; 3829 3830 dinfo = device_get_ivars(dev); 3831 3832 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3833 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3834 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3835 } 3836 3837 return (0); 3838 } 3839 3840 void 3841 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3842 { 3843 struct pci_ea_entry *ea; 3844 struct pci_devinfo *dinfo; 3845 pci_addr_t start, end, count; 3846 struct resource_list *rl; 3847 int type, flags, rid; 3848 struct resource *res; 3849 uint32_t tmp; 3850 #ifdef PCI_IOV 3851 struct pcicfg_iov *iov; 3852 #endif 3853 3854 dinfo = device_get_ivars(dev); 3855 rl = &dinfo->resources; 3856 flags = 0; 3857 3858 #ifdef PCI_IOV 3859 iov = dinfo->cfg.iov; 3860 #endif 3861 3862 if (dinfo->cfg.ea.ea_location == 0) 3863 return; 3864 3865 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3866 /* 3867 * TODO: Ignore EA-BAR if is not enabled. 3868 * Currently the EA implementation supports 3869 * only situation, where EA structure contains 3870 * predefined entries. In case they are not enabled 3871 * leave them unallocated and proceed with 3872 * a legacy-BAR mechanism. 3873 */ 3874 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3875 continue; 3876 3877 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3878 case PCIM_EA_P_MEM_PREFETCH: 3879 case PCIM_EA_P_VF_MEM_PREFETCH: 3880 flags = RF_PREFETCHABLE; 3881 /* FALLTHROUGH */ 3882 case PCIM_EA_P_VF_MEM: 3883 case PCIM_EA_P_MEM: 3884 type = SYS_RES_MEMORY; 3885 break; 3886 case PCIM_EA_P_IO: 3887 type = SYS_RES_IOPORT; 3888 break; 3889 default: 3890 continue; 3891 } 3892 3893 if (alloc_iov != 0) { 3894 #ifdef PCI_IOV 3895 /* Allocating IOV, confirm BEI matches */ 3896 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3897 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3898 continue; 3899 #else 3900 continue; 3901 #endif 3902 } else { 3903 /* Allocating BAR, confirm BEI matches */ 3904 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3905 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3906 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3907 continue; 3908 } 3909 3910 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3911 if (rid < 0) 3912 continue; 3913 3914 /* Skip resources already allocated by EA */ 3915 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3916 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3917 continue; 3918 3919 start = ea->eae_base; 3920 count = ea->eae_max_offset + 1; 3921 #ifdef PCI_IOV 3922 if (iov != NULL) 3923 count = count * iov->iov_num_vfs; 3924 #endif 3925 end = start + count - 1; 3926 if (count == 0) 3927 continue; 3928 3929 resource_list_add(rl, type, rid, start, end, count); 3930 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3931 flags); 3932 if (res == NULL) { 3933 resource_list_delete(rl, type, rid); 3934 3935 /* 3936 * Failed to allocate using EA, disable entry. 3937 * Another attempt to allocation will be performed 3938 * further, but this time using legacy BAR registers 3939 */ 3940 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3941 tmp &= ~PCIM_EA_ENABLE; 3942 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3943 3944 /* 3945 * Disabling entry might fail in case it is hardwired. 3946 * Read flags again to match current status. 3947 */ 3948 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3949 3950 continue; 3951 } 3952 3953 /* As per specification, fill BAR with zeros */ 3954 pci_write_config(dev, rid, 0, 4); 3955 } 3956 } 3957 3958 void 3959 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3960 { 3961 struct pci_devinfo *dinfo; 3962 pcicfgregs *cfg; 3963 struct resource_list *rl; 3964 const struct pci_quirk *q; 3965 uint32_t devid; 3966 int i; 3967 3968 dinfo = device_get_ivars(dev); 3969 cfg = &dinfo->cfg; 3970 rl = &dinfo->resources; 3971 devid = (cfg->device << 16) | cfg->vendor; 3972 3973 /* Allocate resources using Enhanced Allocation */ 3974 pci_add_resources_ea(bus, dev, 0); 3975 3976 /* ATA devices needs special map treatment */ 3977 if ((pci_get_class(dev) == PCIC_STORAGE) && 3978 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3979 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3980 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3981 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3982 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3983 else 3984 for (i = 0; i < cfg->nummaps;) { 3985 /* Skip resources already managed by EA */ 3986 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 3987 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 3988 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 3989 i++; 3990 continue; 3991 } 3992 3993 /* 3994 * Skip quirked resources. 3995 */ 3996 for (q = &pci_quirks[0]; q->devid != 0; q++) 3997 if (q->devid == devid && 3998 q->type == PCI_QUIRK_UNMAP_REG && 3999 q->arg1 == PCIR_BAR(i)) 4000 break; 4001 if (q->devid != 0) { 4002 i++; 4003 continue; 4004 } 4005 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4006 prefetchmask & (1 << i)); 4007 } 4008 4009 /* 4010 * Add additional, quirked resources. 4011 */ 4012 for (q = &pci_quirks[0]; q->devid != 0; q++) 4013 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4014 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4015 4016 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4017 #ifdef __PCI_REROUTE_INTERRUPT 4018 /* 4019 * Try to re-route interrupts. Sometimes the BIOS or 4020 * firmware may leave bogus values in these registers. 4021 * If the re-route fails, then just stick with what we 4022 * have. 4023 */ 4024 pci_assign_interrupt(bus, dev, 1); 4025 #else 4026 pci_assign_interrupt(bus, dev, 0); 4027 #endif 4028 } 4029 4030 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4031 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4032 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4033 xhci_early_takeover(dev); 4034 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4035 ehci_early_takeover(dev); 4036 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4037 ohci_early_takeover(dev); 4038 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4039 uhci_early_takeover(dev); 4040 } 4041 4042 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4043 /* 4044 * Reserve resources for secondary bus ranges behind bridge 4045 * devices. 4046 */ 4047 pci_reserve_secbus(bus, dev, cfg, rl); 4048 #endif 4049 } 4050 4051 static struct pci_devinfo * 4052 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4053 int slot, int func) 4054 { 4055 struct pci_devinfo *dinfo; 4056 4057 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4058 if (dinfo != NULL) 4059 pci_add_child(dev, dinfo); 4060 4061 return (dinfo); 4062 } 4063 4064 void 4065 pci_add_children(device_t dev, int domain, int busno) 4066 { 4067 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4068 device_t pcib = device_get_parent(dev); 4069 struct pci_devinfo *dinfo; 4070 int maxslots; 4071 int s, f, pcifunchigh; 4072 uint8_t hdrtype; 4073 int first_func; 4074 4075 /* 4076 * Try to detect a device at slot 0, function 0. If it exists, try to 4077 * enable ARI. We must enable ARI before detecting the rest of the 4078 * functions on this bus as ARI changes the set of slots and functions 4079 * that are legal on this bus. 4080 */ 4081 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4082 if (dinfo != NULL && pci_enable_ari) 4083 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4084 4085 /* 4086 * Start looking for new devices on slot 0 at function 1 because we 4087 * just identified the device at slot 0, function 0. 4088 */ 4089 first_func = 1; 4090 4091 maxslots = PCIB_MAXSLOTS(pcib); 4092 for (s = 0; s <= maxslots; s++, first_func = 0) { 4093 pcifunchigh = 0; 4094 f = 0; 4095 DELAY(1); 4096 hdrtype = REG(PCIR_HDRTYPE, 1); 4097 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4098 continue; 4099 if (hdrtype & PCIM_MFDEV) 4100 pcifunchigh = PCIB_MAXFUNCS(pcib); 4101 for (f = first_func; f <= pcifunchigh; f++) 4102 pci_identify_function(pcib, dev, domain, busno, s, f); 4103 } 4104 #undef REG 4105 } 4106 4107 int 4108 pci_rescan_method(device_t dev) 4109 { 4110 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4111 device_t pcib = device_get_parent(dev); 4112 device_t child, *devlist, *unchanged; 4113 int devcount, error, i, j, maxslots, oldcount; 4114 int busno, domain, s, f, pcifunchigh; 4115 uint8_t hdrtype; 4116 4117 /* No need to check for ARI on a rescan. */ 4118 error = device_get_children(dev, &devlist, &devcount); 4119 if (error) 4120 return (error); 4121 if (devcount != 0) { 4122 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4123 M_NOWAIT | M_ZERO); 4124 if (unchanged == NULL) { 4125 free(devlist, M_TEMP); 4126 return (ENOMEM); 4127 } 4128 } else 4129 unchanged = NULL; 4130 4131 domain = pcib_get_domain(dev); 4132 busno = pcib_get_bus(dev); 4133 maxslots = PCIB_MAXSLOTS(pcib); 4134 for (s = 0; s <= maxslots; s++) { 4135 /* If function 0 is not present, skip to the next slot. */ 4136 f = 0; 4137 if (REG(PCIR_VENDOR, 2) == 0xffff) 4138 continue; 4139 pcifunchigh = 0; 4140 hdrtype = REG(PCIR_HDRTYPE, 1); 4141 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4142 continue; 4143 if (hdrtype & PCIM_MFDEV) 4144 pcifunchigh = PCIB_MAXFUNCS(pcib); 4145 for (f = 0; f <= pcifunchigh; f++) { 4146 if (REG(PCIR_VENDOR, 2) == 0xffff) 4147 continue; 4148 4149 /* 4150 * Found a valid function. Check if a 4151 * device_t for this device already exists. 4152 */ 4153 for (i = 0; i < devcount; i++) { 4154 child = devlist[i]; 4155 if (child == NULL) 4156 continue; 4157 if (pci_get_slot(child) == s && 4158 pci_get_function(child) == f) { 4159 unchanged[i] = child; 4160 goto next_func; 4161 } 4162 } 4163 4164 pci_identify_function(pcib, dev, domain, busno, s, f); 4165 next_func:; 4166 } 4167 } 4168 4169 /* Remove devices that are no longer present. */ 4170 for (i = 0; i < devcount; i++) { 4171 if (unchanged[i] != NULL) 4172 continue; 4173 device_delete_child(dev, devlist[i]); 4174 } 4175 4176 free(devlist, M_TEMP); 4177 oldcount = devcount; 4178 4179 /* Try to attach the devices just added. */ 4180 error = device_get_children(dev, &devlist, &devcount); 4181 if (error) { 4182 free(unchanged, M_TEMP); 4183 return (error); 4184 } 4185 4186 for (i = 0; i < devcount; i++) { 4187 for (j = 0; j < oldcount; j++) { 4188 if (devlist[i] == unchanged[j]) 4189 goto next_device; 4190 } 4191 4192 device_probe_and_attach(devlist[i]); 4193 next_device:; 4194 } 4195 4196 free(unchanged, M_TEMP); 4197 free(devlist, M_TEMP); 4198 return (0); 4199 #undef REG 4200 } 4201 4202 #ifdef PCI_IOV 4203 device_t 4204 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4205 uint16_t did) 4206 { 4207 struct pci_devinfo *vf_dinfo; 4208 device_t pcib; 4209 int busno, slot, func; 4210 4211 pcib = device_get_parent(bus); 4212 4213 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4214 4215 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4216 slot, func, vid, did); 4217 4218 vf_dinfo->cfg.flags |= PCICFG_VF; 4219 pci_add_child(bus, vf_dinfo); 4220 4221 return (vf_dinfo->cfg.dev); 4222 } 4223 4224 device_t 4225 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4226 uint16_t vid, uint16_t did) 4227 { 4228 4229 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4230 } 4231 #endif 4232 4233 static void 4234 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4235 { 4236 int aer; 4237 uint32_t r; 4238 uint16_t r2; 4239 4240 if (dinfo->cfg.pcie.pcie_location != 0 && 4241 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4242 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4243 PCIER_ROOT_CTL, 2); 4244 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4245 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4246 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4247 PCIER_ROOT_CTL, r2, 2); 4248 } 4249 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4250 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4251 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4252 if (r != 0 && bootverbose) { 4253 pci_printf(&dinfo->cfg, 4254 "clearing AER UC 0x%08x -> 0x%08x\n", 4255 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4256 4)); 4257 } 4258 4259 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4260 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4261 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4262 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4263 PCIM_AER_UC_POISONED_TLP | 4264 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4265 PCIM_AER_UC_COMPLETION_TIMEOUT | 4266 PCIM_AER_UC_COMPLETER_ABORT | 4267 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4268 PCIM_AER_UC_RECEIVER_OVERFLOW | 4269 PCIM_AER_UC_MALFORMED_TLP | 4270 PCIM_AER_UC_ECRC_ERROR | 4271 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4272 PCIM_AER_UC_ACS_VIOLATION | 4273 PCIM_AER_UC_INTERNAL_ERROR | 4274 PCIM_AER_UC_MC_BLOCKED_TLP | 4275 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4276 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4277 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4278 4279 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4280 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4281 if (r != 0 && bootverbose) { 4282 pci_printf(&dinfo->cfg, 4283 "clearing AER COR 0x%08x -> 0x%08x\n", 4284 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4285 4)); 4286 } 4287 4288 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4289 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4290 PCIM_AER_COR_BAD_TLP | 4291 PCIM_AER_COR_BAD_DLLP | 4292 PCIM_AER_COR_REPLAY_ROLLOVER | 4293 PCIM_AER_COR_REPLAY_TIMEOUT | 4294 PCIM_AER_COR_ADVISORY_NF_ERROR | 4295 PCIM_AER_COR_INTERNAL_ERROR | 4296 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4297 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4298 4299 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4300 PCIER_DEVICE_CTL, 2); 4301 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4302 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4303 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4304 PCIER_DEVICE_CTL, r, 2); 4305 } 4306 } 4307 4308 void 4309 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4310 { 4311 device_t dev; 4312 4313 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4314 device_set_ivars(dev, dinfo); 4315 resource_list_init(&dinfo->resources); 4316 pci_cfg_save(dev, dinfo, 0); 4317 pci_cfg_restore(dev, dinfo); 4318 pci_print_verbose(dinfo); 4319 pci_add_resources(bus, dev, 0, 0); 4320 pci_child_added(dinfo->cfg.dev); 4321 4322 if (pci_clear_aer_on_attach) 4323 pci_add_child_clear_aer(dev, dinfo); 4324 4325 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4326 } 4327 4328 void 4329 pci_child_added_method(device_t dev, device_t child) 4330 { 4331 4332 } 4333 4334 static int 4335 pci_probe(device_t dev) 4336 { 4337 4338 device_set_desc(dev, "PCI bus"); 4339 4340 /* Allow other subclasses to override this driver. */ 4341 return (BUS_PROBE_GENERIC); 4342 } 4343 4344 int 4345 pci_attach_common(device_t dev) 4346 { 4347 struct pci_softc *sc; 4348 int busno, domain; 4349 #ifdef PCI_RES_BUS 4350 int rid; 4351 #endif 4352 4353 sc = device_get_softc(dev); 4354 domain = pcib_get_domain(dev); 4355 busno = pcib_get_bus(dev); 4356 #ifdef PCI_RES_BUS 4357 rid = 0; 4358 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4359 1, 0); 4360 if (sc->sc_bus == NULL) { 4361 device_printf(dev, "failed to allocate bus number\n"); 4362 return (ENXIO); 4363 } 4364 #endif 4365 if (bootverbose) 4366 device_printf(dev, "domain=%d, physical bus=%d\n", 4367 domain, busno); 4368 sc->sc_dma_tag = bus_get_dma_tag(dev); 4369 return (0); 4370 } 4371 4372 int 4373 pci_attach(device_t dev) 4374 { 4375 int busno, domain, error; 4376 4377 error = pci_attach_common(dev); 4378 if (error) 4379 return (error); 4380 4381 /* 4382 * Since there can be multiple independently numbered PCI 4383 * buses on systems with multiple PCI domains, we can't use 4384 * the unit number to decide which bus we are probing. We ask 4385 * the parent pcib what our domain and bus numbers are. 4386 */ 4387 domain = pcib_get_domain(dev); 4388 busno = pcib_get_bus(dev); 4389 pci_add_children(dev, domain, busno); 4390 return (bus_generic_attach(dev)); 4391 } 4392 4393 int 4394 pci_detach(device_t dev) 4395 { 4396 #ifdef PCI_RES_BUS 4397 struct pci_softc *sc; 4398 #endif 4399 int error; 4400 4401 error = bus_generic_detach(dev); 4402 if (error) 4403 return (error); 4404 #ifdef PCI_RES_BUS 4405 sc = device_get_softc(dev); 4406 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4407 if (error) 4408 return (error); 4409 #endif 4410 return (device_delete_children(dev)); 4411 } 4412 4413 static void 4414 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4415 { 4416 int line, unit; 4417 const char *at; 4418 char me1[24], me2[32]; 4419 uint8_t b, s, f; 4420 uint32_t d; 4421 4422 d = pci_get_domain(child); 4423 b = pci_get_bus(child); 4424 s = pci_get_slot(child); 4425 f = pci_get_function(child); 4426 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4427 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4428 line = 0; 4429 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4430 resource_string_value(name, unit, "at", &at); 4431 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4432 continue; /* No match, try next candidate */ 4433 *unitp = unit; 4434 return; 4435 } 4436 } 4437 4438 static void 4439 pci_set_power_child(device_t dev, device_t child, int state) 4440 { 4441 device_t pcib; 4442 int dstate; 4443 4444 /* 4445 * Set the device to the given state. If the firmware suggests 4446 * a different power state, use it instead. If power management 4447 * is not present, the firmware is responsible for managing 4448 * device power. Skip children who aren't attached since they 4449 * are handled separately. 4450 */ 4451 pcib = device_get_parent(dev); 4452 dstate = state; 4453 if (device_is_attached(child) && 4454 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4455 pci_set_powerstate(child, dstate); 4456 } 4457 4458 int 4459 pci_suspend_child(device_t dev, device_t child) 4460 { 4461 struct pci_devinfo *dinfo; 4462 struct resource_list_entry *rle; 4463 int error; 4464 4465 dinfo = device_get_ivars(child); 4466 4467 /* 4468 * Save the PCI configuration space for the child and set the 4469 * device in the appropriate power state for this sleep state. 4470 */ 4471 pci_cfg_save(child, dinfo, 0); 4472 4473 /* Suspend devices before potentially powering them down. */ 4474 error = bus_generic_suspend_child(dev, child); 4475 4476 if (error) 4477 return (error); 4478 4479 if (pci_do_power_suspend) { 4480 /* 4481 * Make sure this device's interrupt handler is not invoked 4482 * in the case the device uses a shared interrupt that can 4483 * be raised by some other device. 4484 * This is applicable only to regular (legacy) PCI interrupts 4485 * as MSI/MSI-X interrupts are never shared. 4486 */ 4487 rle = resource_list_find(&dinfo->resources, 4488 SYS_RES_IRQ, 0); 4489 if (rle != NULL && rle->res != NULL) 4490 (void)bus_suspend_intr(child, rle->res); 4491 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4492 } 4493 4494 return (0); 4495 } 4496 4497 int 4498 pci_resume_child(device_t dev, device_t child) 4499 { 4500 struct pci_devinfo *dinfo; 4501 struct resource_list_entry *rle; 4502 4503 if (pci_do_power_resume) 4504 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4505 4506 dinfo = device_get_ivars(child); 4507 pci_cfg_restore(child, dinfo); 4508 if (!device_is_attached(child)) 4509 pci_cfg_save(child, dinfo, 1); 4510 4511 bus_generic_resume_child(dev, child); 4512 4513 /* 4514 * Allow interrupts only after fully resuming the driver and hardware. 4515 */ 4516 if (pci_do_power_suspend) { 4517 /* See pci_suspend_child for details. */ 4518 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4519 if (rle != NULL && rle->res != NULL) 4520 (void)bus_resume_intr(child, rle->res); 4521 } 4522 4523 return (0); 4524 } 4525 4526 int 4527 pci_resume(device_t dev) 4528 { 4529 device_t child, *devlist; 4530 int error, i, numdevs; 4531 4532 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4533 return (error); 4534 4535 /* 4536 * Resume critical devices first, then everything else later. 4537 */ 4538 for (i = 0; i < numdevs; i++) { 4539 child = devlist[i]; 4540 switch (pci_get_class(child)) { 4541 case PCIC_DISPLAY: 4542 case PCIC_MEMORY: 4543 case PCIC_BRIDGE: 4544 case PCIC_BASEPERIPH: 4545 BUS_RESUME_CHILD(dev, child); 4546 break; 4547 } 4548 } 4549 for (i = 0; i < numdevs; i++) { 4550 child = devlist[i]; 4551 switch (pci_get_class(child)) { 4552 case PCIC_DISPLAY: 4553 case PCIC_MEMORY: 4554 case PCIC_BRIDGE: 4555 case PCIC_BASEPERIPH: 4556 break; 4557 default: 4558 BUS_RESUME_CHILD(dev, child); 4559 } 4560 } 4561 free(devlist, M_TEMP); 4562 return (0); 4563 } 4564 4565 static void 4566 pci_load_vendor_data(void) 4567 { 4568 caddr_t data; 4569 void *ptr; 4570 size_t sz; 4571 4572 data = preload_search_by_type("pci_vendor_data"); 4573 if (data != NULL) { 4574 ptr = preload_fetch_addr(data); 4575 sz = preload_fetch_size(data); 4576 if (ptr != NULL && sz != 0) { 4577 pci_vendordata = ptr; 4578 pci_vendordata_size = sz; 4579 /* terminate the database */ 4580 pci_vendordata[pci_vendordata_size] = '\n'; 4581 } 4582 } 4583 } 4584 4585 void 4586 pci_driver_added(device_t dev, driver_t *driver) 4587 { 4588 int numdevs; 4589 device_t *devlist; 4590 device_t child; 4591 struct pci_devinfo *dinfo; 4592 int i; 4593 4594 if (bootverbose) 4595 device_printf(dev, "driver added\n"); 4596 DEVICE_IDENTIFY(driver, dev); 4597 if (device_get_children(dev, &devlist, &numdevs) != 0) 4598 return; 4599 for (i = 0; i < numdevs; i++) { 4600 child = devlist[i]; 4601 if (device_get_state(child) != DS_NOTPRESENT) 4602 continue; 4603 dinfo = device_get_ivars(child); 4604 pci_print_verbose(dinfo); 4605 if (bootverbose) 4606 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4607 pci_cfg_restore(child, dinfo); 4608 if (device_probe_and_attach(child) != 0) 4609 pci_child_detached(dev, child); 4610 } 4611 free(devlist, M_TEMP); 4612 } 4613 4614 int 4615 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4616 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4617 { 4618 struct pci_devinfo *dinfo; 4619 struct msix_table_entry *mte; 4620 struct msix_vector *mv; 4621 uint64_t addr; 4622 uint32_t data; 4623 void *cookie; 4624 int error, rid; 4625 4626 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4627 arg, &cookie); 4628 if (error) 4629 return (error); 4630 4631 /* If this is not a direct child, just bail out. */ 4632 if (device_get_parent(child) != dev) { 4633 *cookiep = cookie; 4634 return(0); 4635 } 4636 4637 rid = rman_get_rid(irq); 4638 if (rid == 0) { 4639 /* Make sure that INTx is enabled */ 4640 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4641 } else { 4642 /* 4643 * Check to see if the interrupt is MSI or MSI-X. 4644 * Ask our parent to map the MSI and give 4645 * us the address and data register values. 4646 * If we fail for some reason, teardown the 4647 * interrupt handler. 4648 */ 4649 dinfo = device_get_ivars(child); 4650 if (dinfo->cfg.msi.msi_alloc > 0) { 4651 if (dinfo->cfg.msi.msi_addr == 0) { 4652 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4653 ("MSI has handlers, but vectors not mapped")); 4654 error = PCIB_MAP_MSI(device_get_parent(dev), 4655 child, rman_get_start(irq), &addr, &data); 4656 if (error) 4657 goto bad; 4658 dinfo->cfg.msi.msi_addr = addr; 4659 dinfo->cfg.msi.msi_data = data; 4660 } 4661 if (dinfo->cfg.msi.msi_handlers == 0) 4662 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4663 dinfo->cfg.msi.msi_data); 4664 dinfo->cfg.msi.msi_handlers++; 4665 } else { 4666 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4667 ("No MSI or MSI-X interrupts allocated")); 4668 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4669 ("MSI-X index too high")); 4670 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4671 KASSERT(mte->mte_vector != 0, ("no message vector")); 4672 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4673 KASSERT(mv->mv_irq == rman_get_start(irq), 4674 ("IRQ mismatch")); 4675 if (mv->mv_address == 0) { 4676 KASSERT(mte->mte_handlers == 0, 4677 ("MSI-X table entry has handlers, but vector not mapped")); 4678 error = PCIB_MAP_MSI(device_get_parent(dev), 4679 child, rman_get_start(irq), &addr, &data); 4680 if (error) 4681 goto bad; 4682 mv->mv_address = addr; 4683 mv->mv_data = data; 4684 } 4685 4686 /* 4687 * The MSIX table entry must be made valid by 4688 * incrementing the mte_handlers before 4689 * calling pci_enable_msix() and 4690 * pci_resume_msix(). Else the MSIX rewrite 4691 * table quirk will not work as expected. 4692 */ 4693 mte->mte_handlers++; 4694 if (mte->mte_handlers == 1) { 4695 pci_enable_msix(child, rid - 1, mv->mv_address, 4696 mv->mv_data); 4697 pci_unmask_msix(child, rid - 1); 4698 } 4699 } 4700 4701 /* 4702 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4703 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4704 * in which case we "enable" INTx so MSI/MSI-X actually works. 4705 */ 4706 if (!pci_has_quirk(pci_get_devid(child), 4707 PCI_QUIRK_MSI_INTX_BUG)) 4708 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4709 else 4710 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4711 bad: 4712 if (error) { 4713 (void)bus_generic_teardown_intr(dev, child, irq, 4714 cookie); 4715 return (error); 4716 } 4717 } 4718 *cookiep = cookie; 4719 return (0); 4720 } 4721 4722 int 4723 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4724 void *cookie) 4725 { 4726 struct msix_table_entry *mte; 4727 struct resource_list_entry *rle; 4728 struct pci_devinfo *dinfo; 4729 int error, rid; 4730 4731 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4732 return (EINVAL); 4733 4734 /* If this isn't a direct child, just bail out */ 4735 if (device_get_parent(child) != dev) 4736 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4737 4738 rid = rman_get_rid(irq); 4739 if (rid == 0) { 4740 /* Mask INTx */ 4741 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4742 } else { 4743 /* 4744 * Check to see if the interrupt is MSI or MSI-X. If so, 4745 * decrement the appropriate handlers count and mask the 4746 * MSI-X message, or disable MSI messages if the count 4747 * drops to 0. 4748 */ 4749 dinfo = device_get_ivars(child); 4750 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4751 if (rle->res != irq) 4752 return (EINVAL); 4753 if (dinfo->cfg.msi.msi_alloc > 0) { 4754 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4755 ("MSI-X index too high")); 4756 if (dinfo->cfg.msi.msi_handlers == 0) 4757 return (EINVAL); 4758 dinfo->cfg.msi.msi_handlers--; 4759 if (dinfo->cfg.msi.msi_handlers == 0) 4760 pci_disable_msi(child); 4761 } else { 4762 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4763 ("No MSI or MSI-X interrupts allocated")); 4764 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4765 ("MSI-X index too high")); 4766 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4767 if (mte->mte_handlers == 0) 4768 return (EINVAL); 4769 mte->mte_handlers--; 4770 if (mte->mte_handlers == 0) 4771 pci_mask_msix(child, rid - 1); 4772 } 4773 } 4774 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4775 if (rid > 0) 4776 KASSERT(error == 0, 4777 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4778 return (error); 4779 } 4780 4781 int 4782 pci_print_child(device_t dev, device_t child) 4783 { 4784 struct pci_devinfo *dinfo; 4785 struct resource_list *rl; 4786 int retval = 0; 4787 4788 dinfo = device_get_ivars(child); 4789 rl = &dinfo->resources; 4790 4791 retval += bus_print_child_header(dev, child); 4792 4793 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4794 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4795 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4796 if (device_get_flags(dev)) 4797 retval += printf(" flags %#x", device_get_flags(dev)); 4798 4799 retval += printf(" at device %d.%d", pci_get_slot(child), 4800 pci_get_function(child)); 4801 4802 retval += bus_print_child_domain(dev, child); 4803 retval += bus_print_child_footer(dev, child); 4804 4805 return (retval); 4806 } 4807 4808 static const struct 4809 { 4810 int class; 4811 int subclass; 4812 int report; /* 0 = bootverbose, 1 = always */ 4813 const char *desc; 4814 } pci_nomatch_tab[] = { 4815 {PCIC_OLD, -1, 1, "old"}, 4816 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4817 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4818 {PCIC_STORAGE, -1, 1, "mass storage"}, 4819 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4820 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4821 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4822 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4823 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4824 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4825 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4826 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4827 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4828 {PCIC_NETWORK, -1, 1, "network"}, 4829 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4830 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4831 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4832 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4833 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4834 {PCIC_DISPLAY, -1, 1, "display"}, 4835 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4836 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4837 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4838 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4839 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4840 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4841 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4842 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4843 {PCIC_MEMORY, -1, 1, "memory"}, 4844 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4845 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4846 {PCIC_BRIDGE, -1, 1, "bridge"}, 4847 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4848 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4849 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4850 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4851 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4852 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4853 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4854 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4855 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4856 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4857 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4858 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4859 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4860 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4861 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4862 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4863 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4864 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4865 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4866 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4867 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4868 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4869 {PCIC_INPUTDEV, -1, 1, "input device"}, 4870 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4871 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4872 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4873 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4874 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4875 {PCIC_DOCKING, -1, 1, "docking station"}, 4876 {PCIC_PROCESSOR, -1, 1, "processor"}, 4877 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4878 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4879 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4880 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4881 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4882 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4883 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4884 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4885 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4886 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4887 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4888 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4889 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4890 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4891 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4892 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4893 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4894 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4895 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4896 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4897 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4898 {PCIC_DASP, -1, 0, "dasp"}, 4899 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4900 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4901 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4902 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4903 {0, 0, 0, NULL} 4904 }; 4905 4906 void 4907 pci_probe_nomatch(device_t dev, device_t child) 4908 { 4909 int i, report; 4910 const char *cp, *scp; 4911 char *device; 4912 4913 /* 4914 * Look for a listing for this device in a loaded device database. 4915 */ 4916 report = 1; 4917 if ((device = pci_describe_device(child)) != NULL) { 4918 device_printf(dev, "<%s>", device); 4919 free(device, M_DEVBUF); 4920 } else { 4921 /* 4922 * Scan the class/subclass descriptions for a general 4923 * description. 4924 */ 4925 cp = "unknown"; 4926 scp = NULL; 4927 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4928 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4929 if (pci_nomatch_tab[i].subclass == -1) { 4930 cp = pci_nomatch_tab[i].desc; 4931 report = pci_nomatch_tab[i].report; 4932 } else if (pci_nomatch_tab[i].subclass == 4933 pci_get_subclass(child)) { 4934 scp = pci_nomatch_tab[i].desc; 4935 report = pci_nomatch_tab[i].report; 4936 } 4937 } 4938 } 4939 if (report || bootverbose) { 4940 device_printf(dev, "<%s%s%s>", 4941 cp ? cp : "", 4942 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4943 scp ? scp : ""); 4944 } 4945 } 4946 if (report || bootverbose) { 4947 printf(" at device %d.%d (no driver attached)\n", 4948 pci_get_slot(child), pci_get_function(child)); 4949 } 4950 pci_cfg_save(child, device_get_ivars(child), 1); 4951 } 4952 4953 void 4954 pci_child_detached(device_t dev, device_t child) 4955 { 4956 struct pci_devinfo *dinfo; 4957 struct resource_list *rl; 4958 4959 dinfo = device_get_ivars(child); 4960 rl = &dinfo->resources; 4961 4962 /* 4963 * Have to deallocate IRQs before releasing any MSI messages and 4964 * have to release MSI messages before deallocating any memory 4965 * BARs. 4966 */ 4967 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4968 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4969 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4970 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4971 (void)pci_release_msi(child); 4972 } 4973 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4974 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4975 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4976 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4977 #ifdef PCI_RES_BUS 4978 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4979 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4980 #endif 4981 4982 pci_cfg_save(child, dinfo, 1); 4983 } 4984 4985 /* 4986 * Parse the PCI device database, if loaded, and return a pointer to a 4987 * description of the device. 4988 * 4989 * The database is flat text formatted as follows: 4990 * 4991 * Any line not in a valid format is ignored. 4992 * Lines are terminated with newline '\n' characters. 4993 * 4994 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4995 * the vendor name. 4996 * 4997 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4998 * - devices cannot be listed without a corresponding VENDOR line. 4999 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5000 * another TAB, then the device name. 5001 */ 5002 5003 /* 5004 * Assuming (ptr) points to the beginning of a line in the database, 5005 * return the vendor or device and description of the next entry. 5006 * The value of (vendor) or (device) inappropriate for the entry type 5007 * is set to -1. Returns nonzero at the end of the database. 5008 * 5009 * Note that this is slightly unrobust in the face of corrupt data; 5010 * we attempt to safeguard against this by spamming the end of the 5011 * database with a newline when we initialise. 5012 */ 5013 static int 5014 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5015 { 5016 char *cp = *ptr; 5017 int left; 5018 5019 *device = -1; 5020 *vendor = -1; 5021 **desc = '\0'; 5022 for (;;) { 5023 left = pci_vendordata_size - (cp - pci_vendordata); 5024 if (left <= 0) { 5025 *ptr = cp; 5026 return(1); 5027 } 5028 5029 /* vendor entry? */ 5030 if (*cp != '\t' && 5031 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5032 break; 5033 /* device entry? */ 5034 if (*cp == '\t' && 5035 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5036 break; 5037 5038 /* skip to next line */ 5039 while (*cp != '\n' && left > 0) { 5040 cp++; 5041 left--; 5042 } 5043 if (*cp == '\n') { 5044 cp++; 5045 left--; 5046 } 5047 } 5048 /* skip to next line */ 5049 while (*cp != '\n' && left > 0) { 5050 cp++; 5051 left--; 5052 } 5053 if (*cp == '\n' && left > 0) 5054 cp++; 5055 *ptr = cp; 5056 return(0); 5057 } 5058 5059 static char * 5060 pci_describe_device(device_t dev) 5061 { 5062 int vendor, device; 5063 char *desc, *vp, *dp, *line; 5064 5065 desc = vp = dp = NULL; 5066 5067 /* 5068 * If we have no vendor data, we can't do anything. 5069 */ 5070 if (pci_vendordata == NULL) 5071 goto out; 5072 5073 /* 5074 * Scan the vendor data looking for this device 5075 */ 5076 line = pci_vendordata; 5077 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5078 goto out; 5079 for (;;) { 5080 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5081 goto out; 5082 if (vendor == pci_get_vendor(dev)) 5083 break; 5084 } 5085 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5086 goto out; 5087 for (;;) { 5088 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5089 *dp = 0; 5090 break; 5091 } 5092 if (vendor != -1) { 5093 *dp = 0; 5094 break; 5095 } 5096 if (device == pci_get_device(dev)) 5097 break; 5098 } 5099 if (dp[0] == '\0') 5100 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5101 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5102 NULL) 5103 sprintf(desc, "%s, %s", vp, dp); 5104 out: 5105 if (vp != NULL) 5106 free(vp, M_DEVBUF); 5107 if (dp != NULL) 5108 free(dp, M_DEVBUF); 5109 return(desc); 5110 } 5111 5112 int 5113 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5114 { 5115 struct pci_devinfo *dinfo; 5116 pcicfgregs *cfg; 5117 5118 dinfo = device_get_ivars(child); 5119 cfg = &dinfo->cfg; 5120 5121 switch (which) { 5122 case PCI_IVAR_ETHADDR: 5123 /* 5124 * The generic accessor doesn't deal with failure, so 5125 * we set the return value, then return an error. 5126 */ 5127 *((uint8_t **) result) = NULL; 5128 return (EINVAL); 5129 case PCI_IVAR_SUBVENDOR: 5130 *result = cfg->subvendor; 5131 break; 5132 case PCI_IVAR_SUBDEVICE: 5133 *result = cfg->subdevice; 5134 break; 5135 case PCI_IVAR_VENDOR: 5136 *result = cfg->vendor; 5137 break; 5138 case PCI_IVAR_DEVICE: 5139 *result = cfg->device; 5140 break; 5141 case PCI_IVAR_DEVID: 5142 *result = (cfg->device << 16) | cfg->vendor; 5143 break; 5144 case PCI_IVAR_CLASS: 5145 *result = cfg->baseclass; 5146 break; 5147 case PCI_IVAR_SUBCLASS: 5148 *result = cfg->subclass; 5149 break; 5150 case PCI_IVAR_PROGIF: 5151 *result = cfg->progif; 5152 break; 5153 case PCI_IVAR_REVID: 5154 *result = cfg->revid; 5155 break; 5156 case PCI_IVAR_INTPIN: 5157 *result = cfg->intpin; 5158 break; 5159 case PCI_IVAR_IRQ: 5160 *result = cfg->intline; 5161 break; 5162 case PCI_IVAR_DOMAIN: 5163 *result = cfg->domain; 5164 break; 5165 case PCI_IVAR_BUS: 5166 *result = cfg->bus; 5167 break; 5168 case PCI_IVAR_SLOT: 5169 *result = cfg->slot; 5170 break; 5171 case PCI_IVAR_FUNCTION: 5172 *result = cfg->func; 5173 break; 5174 case PCI_IVAR_CMDREG: 5175 *result = cfg->cmdreg; 5176 break; 5177 case PCI_IVAR_CACHELNSZ: 5178 *result = cfg->cachelnsz; 5179 break; 5180 case PCI_IVAR_MINGNT: 5181 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5182 *result = -1; 5183 return (EINVAL); 5184 } 5185 *result = cfg->mingnt; 5186 break; 5187 case PCI_IVAR_MAXLAT: 5188 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5189 *result = -1; 5190 return (EINVAL); 5191 } 5192 *result = cfg->maxlat; 5193 break; 5194 case PCI_IVAR_LATTIMER: 5195 *result = cfg->lattimer; 5196 break; 5197 default: 5198 return (ENOENT); 5199 } 5200 return (0); 5201 } 5202 5203 int 5204 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5205 { 5206 struct pci_devinfo *dinfo; 5207 5208 dinfo = device_get_ivars(child); 5209 5210 switch (which) { 5211 case PCI_IVAR_INTPIN: 5212 dinfo->cfg.intpin = value; 5213 return (0); 5214 case PCI_IVAR_ETHADDR: 5215 case PCI_IVAR_SUBVENDOR: 5216 case PCI_IVAR_SUBDEVICE: 5217 case PCI_IVAR_VENDOR: 5218 case PCI_IVAR_DEVICE: 5219 case PCI_IVAR_DEVID: 5220 case PCI_IVAR_CLASS: 5221 case PCI_IVAR_SUBCLASS: 5222 case PCI_IVAR_PROGIF: 5223 case PCI_IVAR_REVID: 5224 case PCI_IVAR_IRQ: 5225 case PCI_IVAR_DOMAIN: 5226 case PCI_IVAR_BUS: 5227 case PCI_IVAR_SLOT: 5228 case PCI_IVAR_FUNCTION: 5229 return (EINVAL); /* disallow for now */ 5230 5231 default: 5232 return (ENOENT); 5233 } 5234 } 5235 5236 #include "opt_ddb.h" 5237 #ifdef DDB 5238 #include <ddb/ddb.h> 5239 #include <sys/cons.h> 5240 5241 /* 5242 * List resources based on pci map registers, used for within ddb 5243 */ 5244 5245 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5246 { 5247 struct pci_devinfo *dinfo; 5248 struct devlist *devlist_head; 5249 struct pci_conf *p; 5250 const char *name; 5251 int i, error, none_count; 5252 5253 none_count = 0; 5254 /* get the head of the device queue */ 5255 devlist_head = &pci_devq; 5256 5257 /* 5258 * Go through the list of devices and print out devices 5259 */ 5260 for (error = 0, i = 0, 5261 dinfo = STAILQ_FIRST(devlist_head); 5262 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5263 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5264 /* Populate pd_name and pd_unit */ 5265 name = NULL; 5266 if (dinfo->cfg.dev) 5267 name = device_get_name(dinfo->cfg.dev); 5268 5269 p = &dinfo->conf; 5270 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5271 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5272 (name && *name) ? name : "none", 5273 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5274 none_count++, 5275 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5276 p->pc_sel.pc_func, (p->pc_class << 16) | 5277 (p->pc_subclass << 8) | p->pc_progif, 5278 (p->pc_subdevice << 16) | p->pc_subvendor, 5279 (p->pc_device << 16) | p->pc_vendor, 5280 p->pc_revid, p->pc_hdr); 5281 } 5282 } 5283 #endif /* DDB */ 5284 5285 static struct resource * 5286 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5287 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5288 u_int flags) 5289 { 5290 struct pci_devinfo *dinfo = device_get_ivars(child); 5291 struct resource_list *rl = &dinfo->resources; 5292 struct resource *res; 5293 struct pci_map *pm; 5294 uint16_t cmd; 5295 pci_addr_t map, testval; 5296 int mapsize; 5297 5298 res = NULL; 5299 5300 /* If rid is managed by EA, ignore it */ 5301 if (pci_ea_is_enabled(child, *rid)) 5302 goto out; 5303 5304 pm = pci_find_bar(child, *rid); 5305 if (pm != NULL) { 5306 /* This is a BAR that we failed to allocate earlier. */ 5307 mapsize = pm->pm_size; 5308 map = pm->pm_value; 5309 } else { 5310 /* 5311 * Weed out the bogons, and figure out how large the 5312 * BAR/map is. BARs that read back 0 here are bogus 5313 * and unimplemented. Note: atapci in legacy mode are 5314 * special and handled elsewhere in the code. If you 5315 * have a atapci device in legacy mode and it fails 5316 * here, that other code is broken. 5317 */ 5318 pci_read_bar(child, *rid, &map, &testval, NULL); 5319 5320 /* 5321 * Determine the size of the BAR and ignore BARs with a size 5322 * of 0. Device ROM BARs use a different mask value. 5323 */ 5324 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5325 mapsize = pci_romsize(testval); 5326 else 5327 mapsize = pci_mapsize(testval); 5328 if (mapsize == 0) 5329 goto out; 5330 pm = pci_add_bar(child, *rid, map, mapsize); 5331 } 5332 5333 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5334 if (type != SYS_RES_MEMORY) { 5335 if (bootverbose) 5336 device_printf(dev, 5337 "child %s requested type %d for rid %#x," 5338 " but the BAR says it is an memio\n", 5339 device_get_nameunit(child), type, *rid); 5340 goto out; 5341 } 5342 } else { 5343 if (type != SYS_RES_IOPORT) { 5344 if (bootverbose) 5345 device_printf(dev, 5346 "child %s requested type %d for rid %#x," 5347 " but the BAR says it is an ioport\n", 5348 device_get_nameunit(child), type, *rid); 5349 goto out; 5350 } 5351 } 5352 5353 /* 5354 * For real BARs, we need to override the size that 5355 * the driver requests, because that's what the BAR 5356 * actually uses and we would otherwise have a 5357 * situation where we might allocate the excess to 5358 * another driver, which won't work. 5359 */ 5360 count = ((pci_addr_t)1 << mapsize) * num; 5361 if (RF_ALIGNMENT(flags) < mapsize) 5362 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5363 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5364 flags |= RF_PREFETCHABLE; 5365 5366 /* 5367 * Allocate enough resource, and then write back the 5368 * appropriate BAR for that resource. 5369 */ 5370 resource_list_add(rl, type, *rid, start, end, count); 5371 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5372 count, flags & ~RF_ACTIVE); 5373 if (res == NULL) { 5374 resource_list_delete(rl, type, *rid); 5375 device_printf(child, 5376 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5377 count, *rid, type, start, end); 5378 goto out; 5379 } 5380 if (bootverbose) 5381 device_printf(child, 5382 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5383 count, *rid, type, rman_get_start(res)); 5384 5385 /* Disable decoding via the CMD register before updating the BAR */ 5386 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5387 pci_write_config(child, PCIR_COMMAND, 5388 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5389 5390 map = rman_get_start(res); 5391 pci_write_bar(child, pm, map); 5392 5393 /* Restore the original value of the CMD register */ 5394 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5395 out: 5396 return (res); 5397 } 5398 5399 struct resource * 5400 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5401 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5402 u_int flags) 5403 { 5404 struct pci_devinfo *dinfo; 5405 struct resource_list *rl; 5406 struct resource_list_entry *rle; 5407 struct resource *res; 5408 pcicfgregs *cfg; 5409 5410 /* 5411 * Perform lazy resource allocation 5412 */ 5413 dinfo = device_get_ivars(child); 5414 rl = &dinfo->resources; 5415 cfg = &dinfo->cfg; 5416 switch (type) { 5417 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5418 case PCI_RES_BUS: 5419 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5420 flags)); 5421 #endif 5422 case SYS_RES_IRQ: 5423 /* 5424 * Can't alloc legacy interrupt once MSI messages have 5425 * been allocated. 5426 */ 5427 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5428 cfg->msix.msix_alloc > 0)) 5429 return (NULL); 5430 5431 /* 5432 * If the child device doesn't have an interrupt 5433 * routed and is deserving of an interrupt, try to 5434 * assign it one. 5435 */ 5436 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5437 (cfg->intpin != 0)) 5438 pci_assign_interrupt(dev, child, 0); 5439 break; 5440 case SYS_RES_IOPORT: 5441 case SYS_RES_MEMORY: 5442 #ifdef NEW_PCIB 5443 /* 5444 * PCI-PCI bridge I/O window resources are not BARs. 5445 * For those allocations just pass the request up the 5446 * tree. 5447 */ 5448 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5449 switch (*rid) { 5450 case PCIR_IOBASEL_1: 5451 case PCIR_MEMBASE_1: 5452 case PCIR_PMBASEL_1: 5453 /* 5454 * XXX: Should we bother creating a resource 5455 * list entry? 5456 */ 5457 return (bus_generic_alloc_resource(dev, child, 5458 type, rid, start, end, count, flags)); 5459 } 5460 } 5461 #endif 5462 /* Reserve resources for this BAR if needed. */ 5463 rle = resource_list_find(rl, type, *rid); 5464 if (rle == NULL) { 5465 res = pci_reserve_map(dev, child, type, rid, start, end, 5466 count, num, flags); 5467 if (res == NULL) 5468 return (NULL); 5469 } 5470 } 5471 return (resource_list_alloc(rl, dev, child, type, rid, 5472 start, end, count, flags)); 5473 } 5474 5475 struct resource * 5476 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5477 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5478 { 5479 #ifdef PCI_IOV 5480 struct pci_devinfo *dinfo; 5481 #endif 5482 5483 if (device_get_parent(child) != dev) 5484 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5485 type, rid, start, end, count, flags)); 5486 5487 #ifdef PCI_IOV 5488 dinfo = device_get_ivars(child); 5489 if (dinfo->cfg.flags & PCICFG_VF) { 5490 switch (type) { 5491 /* VFs can't have I/O BARs. */ 5492 case SYS_RES_IOPORT: 5493 return (NULL); 5494 case SYS_RES_MEMORY: 5495 return (pci_vf_alloc_mem_resource(dev, child, rid, 5496 start, end, count, flags)); 5497 } 5498 5499 /* Fall through for other types of resource allocations. */ 5500 } 5501 #endif 5502 5503 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5504 count, 1, flags)); 5505 } 5506 5507 int 5508 pci_release_resource(device_t dev, device_t child, int type, int rid, 5509 struct resource *r) 5510 { 5511 struct pci_devinfo *dinfo; 5512 struct resource_list *rl; 5513 pcicfgregs *cfg; 5514 5515 if (device_get_parent(child) != dev) 5516 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5517 type, rid, r)); 5518 5519 dinfo = device_get_ivars(child); 5520 cfg = &dinfo->cfg; 5521 5522 #ifdef PCI_IOV 5523 if (dinfo->cfg.flags & PCICFG_VF) { 5524 switch (type) { 5525 /* VFs can't have I/O BARs. */ 5526 case SYS_RES_IOPORT: 5527 return (EDOOFUS); 5528 case SYS_RES_MEMORY: 5529 return (pci_vf_release_mem_resource(dev, child, rid, 5530 r)); 5531 } 5532 5533 /* Fall through for other types of resource allocations. */ 5534 } 5535 #endif 5536 5537 #ifdef NEW_PCIB 5538 /* 5539 * PCI-PCI bridge I/O window resources are not BARs. For 5540 * those allocations just pass the request up the tree. 5541 */ 5542 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5543 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5544 switch (rid) { 5545 case PCIR_IOBASEL_1: 5546 case PCIR_MEMBASE_1: 5547 case PCIR_PMBASEL_1: 5548 return (bus_generic_release_resource(dev, child, type, 5549 rid, r)); 5550 } 5551 } 5552 #endif 5553 5554 rl = &dinfo->resources; 5555 return (resource_list_release(rl, dev, child, type, rid, r)); 5556 } 5557 5558 int 5559 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5560 struct resource *r) 5561 { 5562 struct pci_devinfo *dinfo; 5563 int error; 5564 5565 error = bus_generic_activate_resource(dev, child, type, rid, r); 5566 if (error) 5567 return (error); 5568 5569 /* Enable decoding in the command register when activating BARs. */ 5570 if (device_get_parent(child) == dev) { 5571 /* Device ROMs need their decoding explicitly enabled. */ 5572 dinfo = device_get_ivars(child); 5573 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5574 pci_write_bar(child, pci_find_bar(child, rid), 5575 rman_get_start(r) | PCIM_BIOS_ENABLE); 5576 switch (type) { 5577 case SYS_RES_IOPORT: 5578 case SYS_RES_MEMORY: 5579 error = PCI_ENABLE_IO(dev, child, type); 5580 break; 5581 } 5582 } 5583 return (error); 5584 } 5585 5586 int 5587 pci_deactivate_resource(device_t dev, device_t child, int type, 5588 int rid, struct resource *r) 5589 { 5590 struct pci_devinfo *dinfo; 5591 int error; 5592 5593 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5594 if (error) 5595 return (error); 5596 5597 /* Disable decoding for device ROMs. */ 5598 if (device_get_parent(child) == dev) { 5599 dinfo = device_get_ivars(child); 5600 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5601 pci_write_bar(child, pci_find_bar(child, rid), 5602 rman_get_start(r)); 5603 } 5604 return (0); 5605 } 5606 5607 void 5608 pci_child_deleted(device_t dev, device_t child) 5609 { 5610 struct resource_list_entry *rle; 5611 struct resource_list *rl; 5612 struct pci_devinfo *dinfo; 5613 5614 dinfo = device_get_ivars(child); 5615 rl = &dinfo->resources; 5616 5617 EVENTHANDLER_INVOKE(pci_delete_device, child); 5618 5619 /* Turn off access to resources we're about to free */ 5620 if (bus_child_present(child) != 0) { 5621 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5622 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5623 5624 pci_disable_busmaster(child); 5625 } 5626 5627 /* Free all allocated resources */ 5628 STAILQ_FOREACH(rle, rl, link) { 5629 if (rle->res) { 5630 if (rman_get_flags(rle->res) & RF_ACTIVE || 5631 resource_list_busy(rl, rle->type, rle->rid)) { 5632 pci_printf(&dinfo->cfg, 5633 "Resource still owned, oops. " 5634 "(type=%d, rid=%d, addr=%lx)\n", 5635 rle->type, rle->rid, 5636 rman_get_start(rle->res)); 5637 bus_release_resource(child, rle->type, rle->rid, 5638 rle->res); 5639 } 5640 resource_list_unreserve(rl, dev, child, rle->type, 5641 rle->rid); 5642 } 5643 } 5644 resource_list_free(rl); 5645 5646 pci_freecfg(dinfo); 5647 } 5648 5649 void 5650 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5651 { 5652 struct pci_devinfo *dinfo; 5653 struct resource_list *rl; 5654 struct resource_list_entry *rle; 5655 5656 if (device_get_parent(child) != dev) 5657 return; 5658 5659 dinfo = device_get_ivars(child); 5660 rl = &dinfo->resources; 5661 rle = resource_list_find(rl, type, rid); 5662 if (rle == NULL) 5663 return; 5664 5665 if (rle->res) { 5666 if (rman_get_flags(rle->res) & RF_ACTIVE || 5667 resource_list_busy(rl, type, rid)) { 5668 device_printf(dev, "delete_resource: " 5669 "Resource still owned by child, oops. " 5670 "(type=%d, rid=%d, addr=%jx)\n", 5671 type, rid, rman_get_start(rle->res)); 5672 return; 5673 } 5674 resource_list_unreserve(rl, dev, child, type, rid); 5675 } 5676 resource_list_delete(rl, type, rid); 5677 } 5678 5679 struct resource_list * 5680 pci_get_resource_list (device_t dev, device_t child) 5681 { 5682 struct pci_devinfo *dinfo = device_get_ivars(child); 5683 5684 return (&dinfo->resources); 5685 } 5686 5687 #ifdef IOMMU 5688 bus_dma_tag_t 5689 pci_get_dma_tag(device_t bus, device_t dev) 5690 { 5691 bus_dma_tag_t tag; 5692 struct pci_softc *sc; 5693 5694 if (device_get_parent(dev) == bus) { 5695 /* try iommu and return if it works */ 5696 tag = iommu_get_dma_tag(bus, dev); 5697 } else 5698 tag = NULL; 5699 if (tag == NULL) { 5700 sc = device_get_softc(bus); 5701 tag = sc->sc_dma_tag; 5702 } 5703 return (tag); 5704 } 5705 #else 5706 bus_dma_tag_t 5707 pci_get_dma_tag(device_t bus, device_t dev) 5708 { 5709 struct pci_softc *sc = device_get_softc(bus); 5710 5711 return (sc->sc_dma_tag); 5712 } 5713 #endif 5714 5715 uint32_t 5716 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5717 { 5718 struct pci_devinfo *dinfo = device_get_ivars(child); 5719 pcicfgregs *cfg = &dinfo->cfg; 5720 5721 #ifdef PCI_IOV 5722 /* 5723 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5724 * emulate them here. 5725 */ 5726 if (cfg->flags & PCICFG_VF) { 5727 if (reg == PCIR_VENDOR) { 5728 switch (width) { 5729 case 4: 5730 return (cfg->device << 16 | cfg->vendor); 5731 case 2: 5732 return (cfg->vendor); 5733 case 1: 5734 return (cfg->vendor & 0xff); 5735 default: 5736 return (0xffffffff); 5737 } 5738 } else if (reg == PCIR_DEVICE) { 5739 switch (width) { 5740 /* Note that an unaligned 4-byte read is an error. */ 5741 case 2: 5742 return (cfg->device); 5743 case 1: 5744 return (cfg->device & 0xff); 5745 default: 5746 return (0xffffffff); 5747 } 5748 } 5749 } 5750 #endif 5751 5752 return (PCIB_READ_CONFIG(device_get_parent(dev), 5753 cfg->bus, cfg->slot, cfg->func, reg, width)); 5754 } 5755 5756 void 5757 pci_write_config_method(device_t dev, device_t child, int reg, 5758 uint32_t val, int width) 5759 { 5760 struct pci_devinfo *dinfo = device_get_ivars(child); 5761 pcicfgregs *cfg = &dinfo->cfg; 5762 5763 PCIB_WRITE_CONFIG(device_get_parent(dev), 5764 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5765 } 5766 5767 int 5768 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5769 size_t buflen) 5770 { 5771 5772 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5773 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5774 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5775 return (0); 5776 } 5777 5778 int 5779 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5780 size_t buflen) 5781 { 5782 struct pci_devinfo *dinfo; 5783 pcicfgregs *cfg; 5784 5785 dinfo = device_get_ivars(child); 5786 cfg = &dinfo->cfg; 5787 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5788 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5789 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5790 cfg->progif); 5791 return (0); 5792 } 5793 5794 int 5795 pci_assign_interrupt_method(device_t dev, device_t child) 5796 { 5797 struct pci_devinfo *dinfo = device_get_ivars(child); 5798 pcicfgregs *cfg = &dinfo->cfg; 5799 5800 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5801 cfg->intpin)); 5802 } 5803 5804 static void 5805 pci_lookup(void *arg, const char *name, device_t *dev) 5806 { 5807 long val; 5808 char *end; 5809 int domain, bus, slot, func; 5810 5811 if (*dev != NULL) 5812 return; 5813 5814 /* 5815 * Accept pciconf-style selectors of either pciD:B:S:F or 5816 * pciB:S:F. In the latter case, the domain is assumed to 5817 * be zero. 5818 */ 5819 if (strncmp(name, "pci", 3) != 0) 5820 return; 5821 val = strtol(name + 3, &end, 10); 5822 if (val < 0 || val > INT_MAX || *end != ':') 5823 return; 5824 domain = val; 5825 val = strtol(end + 1, &end, 10); 5826 if (val < 0 || val > INT_MAX || *end != ':') 5827 return; 5828 bus = val; 5829 val = strtol(end + 1, &end, 10); 5830 if (val < 0 || val > INT_MAX) 5831 return; 5832 slot = val; 5833 if (*end == ':') { 5834 val = strtol(end + 1, &end, 10); 5835 if (val < 0 || val > INT_MAX || *end != '\0') 5836 return; 5837 func = val; 5838 } else if (*end == '\0') { 5839 func = slot; 5840 slot = bus; 5841 bus = domain; 5842 domain = 0; 5843 } else 5844 return; 5845 5846 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5847 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5848 return; 5849 5850 *dev = pci_find_dbsf(domain, bus, slot, func); 5851 } 5852 5853 static int 5854 pci_modevent(module_t mod, int what, void *arg) 5855 { 5856 static struct cdev *pci_cdev; 5857 static eventhandler_tag tag; 5858 5859 switch (what) { 5860 case MOD_LOAD: 5861 STAILQ_INIT(&pci_devq); 5862 pci_generation = 0; 5863 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5864 "pci"); 5865 pci_load_vendor_data(); 5866 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5867 1000); 5868 break; 5869 5870 case MOD_UNLOAD: 5871 if (tag != NULL) 5872 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5873 destroy_dev(pci_cdev); 5874 break; 5875 } 5876 5877 return (0); 5878 } 5879 5880 static void 5881 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5882 { 5883 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5884 struct pcicfg_pcie *cfg; 5885 int version, pos; 5886 5887 cfg = &dinfo->cfg.pcie; 5888 pos = cfg->pcie_location; 5889 5890 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5891 5892 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5893 5894 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5895 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5896 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5897 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5898 5899 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5900 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5901 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5902 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5903 5904 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5905 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5906 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5907 5908 if (version > 1) { 5909 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5910 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5911 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5912 } 5913 #undef WREG 5914 } 5915 5916 static void 5917 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5918 { 5919 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5920 dinfo->cfg.pcix.pcix_command, 2); 5921 } 5922 5923 void 5924 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5925 { 5926 5927 /* 5928 * Restore the device to full power mode. We must do this 5929 * before we restore the registers because moving from D3 to 5930 * D0 will cause the chip's BARs and some other registers to 5931 * be reset to some unknown power on reset values. Cut down 5932 * the noise on boot by doing nothing if we are already in 5933 * state D0. 5934 */ 5935 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5936 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5937 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5938 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5939 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5940 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5941 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5942 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5943 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5944 case PCIM_HDRTYPE_NORMAL: 5945 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5946 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5947 break; 5948 case PCIM_HDRTYPE_BRIDGE: 5949 pci_write_config(dev, PCIR_SECLAT_1, 5950 dinfo->cfg.bridge.br_seclat, 1); 5951 pci_write_config(dev, PCIR_SUBBUS_1, 5952 dinfo->cfg.bridge.br_subbus, 1); 5953 pci_write_config(dev, PCIR_SECBUS_1, 5954 dinfo->cfg.bridge.br_secbus, 1); 5955 pci_write_config(dev, PCIR_PRIBUS_1, 5956 dinfo->cfg.bridge.br_pribus, 1); 5957 pci_write_config(dev, PCIR_BRIDGECTL_1, 5958 dinfo->cfg.bridge.br_control, 2); 5959 break; 5960 case PCIM_HDRTYPE_CARDBUS: 5961 pci_write_config(dev, PCIR_SECLAT_2, 5962 dinfo->cfg.bridge.br_seclat, 1); 5963 pci_write_config(dev, PCIR_SUBBUS_2, 5964 dinfo->cfg.bridge.br_subbus, 1); 5965 pci_write_config(dev, PCIR_SECBUS_2, 5966 dinfo->cfg.bridge.br_secbus, 1); 5967 pci_write_config(dev, PCIR_PRIBUS_2, 5968 dinfo->cfg.bridge.br_pribus, 1); 5969 pci_write_config(dev, PCIR_BRIDGECTL_2, 5970 dinfo->cfg.bridge.br_control, 2); 5971 break; 5972 } 5973 pci_restore_bars(dev); 5974 5975 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 5976 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5977 5978 /* 5979 * Restore extended capabilities for PCI-Express and PCI-X 5980 */ 5981 if (dinfo->cfg.pcie.pcie_location != 0) 5982 pci_cfg_restore_pcie(dev, dinfo); 5983 if (dinfo->cfg.pcix.pcix_location != 0) 5984 pci_cfg_restore_pcix(dev, dinfo); 5985 5986 /* Restore MSI and MSI-X configurations if they are present. */ 5987 if (dinfo->cfg.msi.msi_location != 0) 5988 pci_resume_msi(dev); 5989 if (dinfo->cfg.msix.msix_location != 0) 5990 pci_resume_msix(dev); 5991 5992 #ifdef PCI_IOV 5993 if (dinfo->cfg.iov != NULL) 5994 pci_iov_cfg_restore(dev, dinfo); 5995 #endif 5996 } 5997 5998 static void 5999 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6000 { 6001 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6002 struct pcicfg_pcie *cfg; 6003 int version, pos; 6004 6005 cfg = &dinfo->cfg.pcie; 6006 pos = cfg->pcie_location; 6007 6008 cfg->pcie_flags = RREG(PCIER_FLAGS); 6009 6010 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6011 6012 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6013 6014 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6015 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6016 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6017 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6018 6019 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6020 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6021 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6022 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6023 6024 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6025 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6026 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6027 6028 if (version > 1) { 6029 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6030 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6031 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6032 } 6033 #undef RREG 6034 } 6035 6036 static void 6037 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6038 { 6039 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6040 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6041 } 6042 6043 void 6044 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6045 { 6046 uint32_t cls; 6047 int ps; 6048 6049 /* 6050 * Some drivers apparently write to these registers w/o updating our 6051 * cached copy. No harm happens if we update the copy, so do so here 6052 * so we can restore them. The COMMAND register is modified by the 6053 * bus w/o updating the cache. This should represent the normally 6054 * writable portion of the 'defined' part of type 0/1/2 headers. 6055 */ 6056 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6057 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6058 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6059 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6060 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6061 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6062 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6063 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6064 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6065 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6066 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6067 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6068 case PCIM_HDRTYPE_NORMAL: 6069 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6070 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6071 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6072 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6073 break; 6074 case PCIM_HDRTYPE_BRIDGE: 6075 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6076 PCIR_SECLAT_1, 1); 6077 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6078 PCIR_SUBBUS_1, 1); 6079 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6080 PCIR_SECBUS_1, 1); 6081 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6082 PCIR_PRIBUS_1, 1); 6083 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6084 PCIR_BRIDGECTL_1, 2); 6085 break; 6086 case PCIM_HDRTYPE_CARDBUS: 6087 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6088 PCIR_SECLAT_2, 1); 6089 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6090 PCIR_SUBBUS_2, 1); 6091 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6092 PCIR_SECBUS_2, 1); 6093 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6094 PCIR_PRIBUS_2, 1); 6095 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6096 PCIR_BRIDGECTL_2, 2); 6097 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6098 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6099 break; 6100 } 6101 6102 if (dinfo->cfg.pcie.pcie_location != 0) 6103 pci_cfg_save_pcie(dev, dinfo); 6104 6105 if (dinfo->cfg.pcix.pcix_location != 0) 6106 pci_cfg_save_pcix(dev, dinfo); 6107 6108 #ifdef PCI_IOV 6109 if (dinfo->cfg.iov != NULL) 6110 pci_iov_cfg_save(dev, dinfo); 6111 #endif 6112 6113 /* 6114 * don't set the state for display devices, base peripherals and 6115 * memory devices since bad things happen when they are powered down. 6116 * We should (a) have drivers that can easily detach and (b) use 6117 * generic drivers for these devices so that some device actually 6118 * attaches. We need to make sure that when we implement (a) we don't 6119 * power the device down on a reattach. 6120 */ 6121 cls = pci_get_class(dev); 6122 if (!setstate) 6123 return; 6124 switch (pci_do_power_nodriver) 6125 { 6126 case 0: /* NO powerdown at all */ 6127 return; 6128 case 1: /* Conservative about what to power down */ 6129 if (cls == PCIC_STORAGE) 6130 return; 6131 /*FALLTHROUGH*/ 6132 case 2: /* Aggressive about what to power down */ 6133 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6134 cls == PCIC_BASEPERIPH) 6135 return; 6136 /*FALLTHROUGH*/ 6137 case 3: /* Power down everything */ 6138 break; 6139 } 6140 /* 6141 * PCI spec says we can only go into D3 state from D0 state. 6142 * Transition from D[12] into D0 before going to D3 state. 6143 */ 6144 ps = pci_get_powerstate(dev); 6145 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6146 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6147 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6148 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6149 } 6150 6151 /* Wrapper APIs suitable for device driver use. */ 6152 void 6153 pci_save_state(device_t dev) 6154 { 6155 struct pci_devinfo *dinfo; 6156 6157 dinfo = device_get_ivars(dev); 6158 pci_cfg_save(dev, dinfo, 0); 6159 } 6160 6161 void 6162 pci_restore_state(device_t dev) 6163 { 6164 struct pci_devinfo *dinfo; 6165 6166 dinfo = device_get_ivars(dev); 6167 pci_cfg_restore(dev, dinfo); 6168 } 6169 6170 static int 6171 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6172 uintptr_t *id) 6173 { 6174 6175 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6176 } 6177 6178 /* Find the upstream port of a given PCI device in a root complex. */ 6179 device_t 6180 pci_find_pcie_root_port(device_t dev) 6181 { 6182 struct pci_devinfo *dinfo; 6183 devclass_t pci_class; 6184 device_t pcib, bus; 6185 6186 pci_class = devclass_find("pci"); 6187 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6188 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6189 6190 /* 6191 * Walk the bridge hierarchy until we find a PCI-e root 6192 * port or a non-PCI device. 6193 */ 6194 for (;;) { 6195 bus = device_get_parent(dev); 6196 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6197 device_get_nameunit(dev))); 6198 6199 pcib = device_get_parent(bus); 6200 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6201 device_get_nameunit(bus))); 6202 6203 /* 6204 * pcib's parent must be a PCI bus for this to be a 6205 * PCI-PCI bridge. 6206 */ 6207 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6208 return (NULL); 6209 6210 dinfo = device_get_ivars(pcib); 6211 if (dinfo->cfg.pcie.pcie_location != 0 && 6212 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6213 return (pcib); 6214 6215 dev = pcib; 6216 } 6217 } 6218 6219 /* 6220 * Wait for pending transactions to complete on a PCI-express function. 6221 * 6222 * The maximum delay is specified in milliseconds in max_delay. Note 6223 * that this function may sleep. 6224 * 6225 * Returns true if the function is idle and false if the timeout is 6226 * exceeded. If dev is not a PCI-express function, this returns true. 6227 */ 6228 bool 6229 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6230 { 6231 struct pci_devinfo *dinfo = device_get_ivars(dev); 6232 uint16_t sta; 6233 int cap; 6234 6235 cap = dinfo->cfg.pcie.pcie_location; 6236 if (cap == 0) 6237 return (true); 6238 6239 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6240 while (sta & PCIEM_STA_TRANSACTION_PND) { 6241 if (max_delay == 0) 6242 return (false); 6243 6244 /* Poll once every 100 milliseconds up to the timeout. */ 6245 if (max_delay > 100) { 6246 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6247 max_delay -= 100; 6248 } else { 6249 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6250 C_HARDCLOCK); 6251 max_delay = 0; 6252 } 6253 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6254 } 6255 6256 return (true); 6257 } 6258 6259 /* 6260 * Determine the maximum Completion Timeout in microseconds. 6261 * 6262 * For non-PCI-express functions this returns 0. 6263 */ 6264 int 6265 pcie_get_max_completion_timeout(device_t dev) 6266 { 6267 struct pci_devinfo *dinfo = device_get_ivars(dev); 6268 int cap; 6269 6270 cap = dinfo->cfg.pcie.pcie_location; 6271 if (cap == 0) 6272 return (0); 6273 6274 /* 6275 * Functions using the 1.x spec use the default timeout range of 6276 * 50 microseconds to 50 milliseconds. Functions that do not 6277 * support programmable timeouts also use this range. 6278 */ 6279 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6280 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6281 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6282 return (50 * 1000); 6283 6284 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6285 PCIEM_CTL2_COMP_TIMO_VAL) { 6286 case PCIEM_CTL2_COMP_TIMO_100US: 6287 return (100); 6288 case PCIEM_CTL2_COMP_TIMO_10MS: 6289 return (10 * 1000); 6290 case PCIEM_CTL2_COMP_TIMO_55MS: 6291 return (55 * 1000); 6292 case PCIEM_CTL2_COMP_TIMO_210MS: 6293 return (210 * 1000); 6294 case PCIEM_CTL2_COMP_TIMO_900MS: 6295 return (900 * 1000); 6296 case PCIEM_CTL2_COMP_TIMO_3500MS: 6297 return (3500 * 1000); 6298 case PCIEM_CTL2_COMP_TIMO_13S: 6299 return (13 * 1000 * 1000); 6300 case PCIEM_CTL2_COMP_TIMO_64S: 6301 return (64 * 1000 * 1000); 6302 default: 6303 return (50 * 1000); 6304 } 6305 } 6306 6307 void 6308 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6309 { 6310 struct pci_devinfo *dinfo = device_get_ivars(dev); 6311 const char *s; 6312 int aer; 6313 uint32_t r, r1; 6314 uint16_t rs; 6315 6316 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6317 s = "Correctable"; 6318 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6319 s = "Uncorrectable (Non-Fatal)"; 6320 else 6321 s = "Uncorrectable (Fatal)"; 6322 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6323 if (aerp) { 6324 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6325 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6326 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6327 } else { 6328 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6329 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6330 } 6331 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6332 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6333 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6334 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6335 printf(" severity 0x%08x first %d\n", 6336 r, rs & 0x1f); 6337 } else 6338 printf("\n"); 6339 } 6340 6341 /* As kind of recovery just report and clear the error statuses. */ 6342 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6343 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6344 if (r != 0) { 6345 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6346 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6347 } 6348 6349 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6350 if (r != 0) { 6351 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6352 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6353 } 6354 } 6355 if (dinfo->cfg.pcie.pcie_location != 0) { 6356 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6357 PCIER_DEVICE_STA, 2); 6358 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6359 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6360 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6361 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6362 PCIER_DEVICE_STA, rs, 2); 6363 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6364 } 6365 } 6366 } 6367 6368 /* 6369 * Perform a Function Level Reset (FLR) on a device. 6370 * 6371 * This function first waits for any pending transactions to complete 6372 * within the timeout specified by max_delay. If transactions are 6373 * still pending, the function will return false without attempting a 6374 * reset. 6375 * 6376 * If dev is not a PCI-express function or does not support FLR, this 6377 * function returns false. 6378 * 6379 * Note that no registers are saved or restored. The caller is 6380 * responsible for saving and restoring any registers including 6381 * PCI-standard registers via pci_save_state() and 6382 * pci_restore_state(). 6383 */ 6384 bool 6385 pcie_flr(device_t dev, u_int max_delay, bool force) 6386 { 6387 struct pci_devinfo *dinfo = device_get_ivars(dev); 6388 uint16_t cmd, ctl; 6389 int compl_delay; 6390 int cap; 6391 6392 cap = dinfo->cfg.pcie.pcie_location; 6393 if (cap == 0) 6394 return (false); 6395 6396 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6397 return (false); 6398 6399 /* 6400 * Disable busmastering to prevent generation of new 6401 * transactions while waiting for the device to go idle. If 6402 * the idle timeout fails, the command register is restored 6403 * which will re-enable busmastering. 6404 */ 6405 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6406 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6407 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6408 if (!force) { 6409 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6410 return (false); 6411 } 6412 pci_printf(&dinfo->cfg, 6413 "Resetting with transactions pending after %d ms\n", 6414 max_delay); 6415 6416 /* 6417 * Extend the post-FLR delay to cover the maximum 6418 * Completion Timeout delay of anything in flight 6419 * during the FLR delay. Enforce a minimum delay of 6420 * at least 10ms. 6421 */ 6422 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6423 if (compl_delay < 10) 6424 compl_delay = 10; 6425 } else 6426 compl_delay = 0; 6427 6428 /* Initiate the reset. */ 6429 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6430 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6431 PCIEM_CTL_INITIATE_FLR, 2); 6432 6433 /* Wait for 100ms. */ 6434 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6435 6436 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6437 PCIEM_STA_TRANSACTION_PND) 6438 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6439 return (true); 6440 } 6441 6442 /* 6443 * Attempt a power-management reset by cycling the device in/out of D3 6444 * state. PCI spec says we can only go into D3 state from D0 state. 6445 * Transition from D[12] into D0 before going to D3 state. 6446 */ 6447 int 6448 pci_power_reset(device_t dev) 6449 { 6450 int ps; 6451 6452 ps = pci_get_powerstate(dev); 6453 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6454 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6455 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6456 pci_set_powerstate(dev, ps); 6457 return (0); 6458 } 6459 6460 /* 6461 * Try link drop and retrain of the downstream port of upstream 6462 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6463 * cause Conventional Hot reset of the device in the slot. 6464 * Alternative, for PCIe, could be the secondary bus reset initiatied 6465 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6466 */ 6467 int 6468 pcie_link_reset(device_t port, int pcie_location) 6469 { 6470 uint16_t v; 6471 6472 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6473 v |= PCIEM_LINK_CTL_LINK_DIS; 6474 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6475 pause_sbt("pcier1", mstosbt(20), 0, 0); 6476 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6477 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6478 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6479 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6480 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6481 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6482 } 6483 6484 static int 6485 pci_reset_post(device_t dev, device_t child) 6486 { 6487 6488 if (dev == device_get_parent(child)) 6489 pci_restore_state(child); 6490 return (0); 6491 } 6492 6493 static int 6494 pci_reset_prepare(device_t dev, device_t child) 6495 { 6496 6497 if (dev == device_get_parent(child)) 6498 pci_save_state(child); 6499 return (0); 6500 } 6501 6502 static int 6503 pci_reset_child(device_t dev, device_t child, int flags) 6504 { 6505 int error; 6506 6507 if (dev == NULL || device_get_parent(child) != dev) 6508 return (0); 6509 if ((flags & DEVF_RESET_DETACH) != 0) { 6510 error = device_get_state(child) == DS_ATTACHED ? 6511 device_detach(child) : 0; 6512 } else { 6513 error = BUS_SUSPEND_CHILD(dev, child); 6514 } 6515 if (error == 0) { 6516 if (!pcie_flr(child, 1000, false)) { 6517 error = BUS_RESET_PREPARE(dev, child); 6518 if (error == 0) 6519 pci_power_reset(child); 6520 BUS_RESET_POST(dev, child); 6521 } 6522 if ((flags & DEVF_RESET_DETACH) != 0) 6523 device_probe_and_attach(child); 6524 else 6525 BUS_RESUME_CHILD(dev, child); 6526 } 6527 return (error); 6528 } 6529 6530 const struct pci_device_table * 6531 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6532 { 6533 bool match; 6534 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6535 6536 vendor = pci_get_vendor(child); 6537 device = pci_get_device(child); 6538 subvendor = pci_get_subvendor(child); 6539 subdevice = pci_get_subdevice(child); 6540 class = pci_get_class(child); 6541 subclass = pci_get_subclass(child); 6542 revid = pci_get_revid(child); 6543 while (nelt-- > 0) { 6544 match = true; 6545 if (id->match_flag_vendor) 6546 match &= vendor == id->vendor; 6547 if (id->match_flag_device) 6548 match &= device == id->device; 6549 if (id->match_flag_subvendor) 6550 match &= subvendor == id->subvendor; 6551 if (id->match_flag_subdevice) 6552 match &= subdevice == id->subdevice; 6553 if (id->match_flag_class) 6554 match &= class == id->class_id; 6555 if (id->match_flag_subclass) 6556 match &= subclass == id->subclass; 6557 if (id->match_flag_revid) 6558 match &= revid == id->revid; 6559 if (match) 6560 return (id); 6561 id++; 6562 } 6563 return (NULL); 6564 } 6565 6566 static void 6567 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6568 { 6569 const char *dev_name; 6570 device_t dev; 6571 6572 dev = dinfo->cfg.dev; 6573 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6574 dinfo->cfg.slot, dinfo->cfg.func); 6575 dev_name = device_get_name(dev); 6576 if (dev_name != NULL) 6577 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6578 } 6579 6580 void 6581 pci_print_faulted_dev(void) 6582 { 6583 struct pci_devinfo *dinfo; 6584 device_t dev; 6585 int aer, i; 6586 uint32_t r1, r2; 6587 uint16_t status; 6588 6589 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6590 dev = dinfo->cfg.dev; 6591 status = pci_read_config(dev, PCIR_STATUS, 2); 6592 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6593 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6594 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6595 if (status != 0) { 6596 pci_print_faulted_dev_name(dinfo); 6597 printf(" error 0x%04x\n", status); 6598 } 6599 if (dinfo->cfg.pcie.pcie_location != 0) { 6600 status = pci_read_config(dev, 6601 dinfo->cfg.pcie.pcie_location + 6602 PCIER_DEVICE_STA, 2); 6603 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6604 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6605 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6606 pci_print_faulted_dev_name(dinfo); 6607 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6608 pci_read_config(dev, 6609 dinfo->cfg.pcie.pcie_location + 6610 PCIER_DEVICE_CTL, 2), 6611 status); 6612 } 6613 } 6614 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6615 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6616 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6617 if (r1 != 0 || r2 != 0) { 6618 pci_print_faulted_dev_name(dinfo); 6619 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6620 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6621 r1, pci_read_config(dev, aer + 6622 PCIR_AER_UC_MASK, 4), 6623 pci_read_config(dev, aer + 6624 PCIR_AER_UC_SEVERITY, 4), 6625 r2, pci_read_config(dev, aer + 6626 PCIR_AER_COR_MASK, 4), 6627 pci_read_config(dev, aer + 6628 PCIR_AER_CAP_CONTROL, 4)); 6629 for (i = 0; i < 4; i++) { 6630 r1 = pci_read_config(dev, aer + 6631 PCIR_AER_HEADER_LOG + i * 4, 4); 6632 printf(" HL%d: 0x%08x\n", i, r1); 6633 } 6634 } 6635 } 6636 } 6637 } 6638 6639 #ifdef DDB 6640 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6641 { 6642 6643 pci_print_faulted_dev(); 6644 } 6645 6646 static void 6647 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6648 { 6649 device_t dev; 6650 int aer; 6651 uint32_t r; 6652 6653 dev = dinfo->cfg.dev; 6654 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6655 PCIER_DEVICE_STA, 2); 6656 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6657 PCIER_DEVICE_STA, r, 2); 6658 6659 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6660 return; 6661 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6662 if (r != 0) 6663 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6664 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6665 if (r != 0) 6666 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6667 } 6668 6669 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6670 { 6671 struct pci_devinfo *dinfo; 6672 device_t dev; 6673 uint16_t status, status1; 6674 6675 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6676 dev = dinfo->cfg.dev; 6677 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6678 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6679 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6680 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6681 if (status1 != 0) { 6682 status &= ~status1; 6683 pci_write_config(dev, PCIR_STATUS, status, 2); 6684 } 6685 if (dinfo->cfg.pcie.pcie_location != 0) 6686 db_clear_pcie_errors(dinfo); 6687 } 6688 } 6689 #endif 6690