1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82 static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95 static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 135 { 0, 0 } 136 }; 137 138 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140 devclass_t pci_devclass; 141 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142 MODULE_VERSION(pci, 1); 143 144 static char *pci_vendordata; 145 static size_t pci_vendordata_size; 146 147 148 struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154 }; 155 156 struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164 }; 165 166 /* map register information */ 167 #define PCI_MAPMEM 0x01 /* memory map */ 168 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169 #define PCI_MAPPORT 0x04 /* port map */ 170 171 struct devlist pci_devq; 172 uint32_t pci_generation; 173 uint32_t pci_numdevs = 0; 174 175 /* sysctl vars */ 176 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178 static int pci_enable_io_modes = 1; 179 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183 enable these bits correctly. We'd like to do this all the time, but there\n\ 184 are some peripherals that this causes problems with."); 185 186 static int pci_do_powerstate = 1; 187 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 188 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 189 &pci_do_powerstate, 1, 190 "Controls the behvior of the pci driver when it encounters\n\ 191 devices which no driver claims. Set to 0 causes the pci to leave\n\ 192 the device in D0. Set to 1 causes pci to conservatively devices\n\ 193 into D3 state. These are devices which have had issues in the past.\n\ 194 Set to 2 causes the bus driver to agressively place devices into D3 state.\n\ 195 The only devices it excludes are devices for which no drivers generally\n\ 196 exist in FreeBSD. Set to 3 causes the bus driver to place all unattached\n\ 197 devices into D3 state."); 198 199 /* Find a device_t by bus/slot/function */ 200 201 device_t 202 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 203 { 204 struct pci_devinfo *dinfo; 205 206 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 207 if ((dinfo->cfg.bus == bus) && 208 (dinfo->cfg.slot == slot) && 209 (dinfo->cfg.func == func)) { 210 return (dinfo->cfg.dev); 211 } 212 } 213 214 return (NULL); 215 } 216 217 /* Find a device_t by vendor/device ID */ 218 219 device_t 220 pci_find_device(uint16_t vendor, uint16_t device) 221 { 222 struct pci_devinfo *dinfo; 223 224 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 225 if ((dinfo->cfg.vendor == vendor) && 226 (dinfo->cfg.device == device)) { 227 return (dinfo->cfg.dev); 228 } 229 } 230 231 return (NULL); 232 } 233 234 /* return base address of memory or port map */ 235 236 static uint32_t 237 pci_mapbase(unsigned mapreg) 238 { 239 int mask = 0x03; 240 if ((mapreg & 0x01) == 0) 241 mask = 0x0f; 242 return (mapreg & ~mask); 243 } 244 245 /* return map type of memory or port map */ 246 247 static int 248 pci_maptype(unsigned mapreg) 249 { 250 static uint8_t maptype[0x10] = { 251 PCI_MAPMEM, PCI_MAPPORT, 252 PCI_MAPMEM, 0, 253 PCI_MAPMEM, PCI_MAPPORT, 254 0, 0, 255 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 256 PCI_MAPMEM|PCI_MAPMEMP, 0, 257 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 258 0, 0, 259 }; 260 261 return maptype[mapreg & 0x0f]; 262 } 263 264 /* return log2 of map size decoded for memory or port map */ 265 266 static int 267 pci_mapsize(unsigned testval) 268 { 269 int ln2size; 270 271 testval = pci_mapbase(testval); 272 ln2size = 0; 273 if (testval != 0) { 274 while ((testval & 1) == 0) 275 { 276 ln2size++; 277 testval >>= 1; 278 } 279 } 280 return (ln2size); 281 } 282 283 /* return log2 of address range supported by map register */ 284 285 static int 286 pci_maprange(unsigned mapreg) 287 { 288 int ln2range = 0; 289 switch (mapreg & 0x07) { 290 case 0x00: 291 case 0x01: 292 case 0x05: 293 ln2range = 32; 294 break; 295 case 0x02: 296 ln2range = 20; 297 break; 298 case 0x04: 299 ln2range = 64; 300 break; 301 } 302 return (ln2range); 303 } 304 305 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 306 307 static void 308 pci_fixancient(pcicfgregs *cfg) 309 { 310 if (cfg->hdrtype != 0) 311 return; 312 313 /* PCI to PCI bridges use header type 1 */ 314 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 315 cfg->hdrtype = 1; 316 } 317 318 /* extract header type specific config data */ 319 320 static void 321 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 322 { 323 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 324 switch (cfg->hdrtype) { 325 case 0: 326 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 327 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 328 cfg->nummaps = PCI_MAXMAPS_0; 329 break; 330 case 1: 331 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 332 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 333 cfg->nummaps = PCI_MAXMAPS_1; 334 break; 335 case 2: 336 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 337 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 338 cfg->nummaps = PCI_MAXMAPS_2; 339 break; 340 } 341 #undef REG 342 } 343 344 /* read configuration header into pcicfgregs structure */ 345 346 struct pci_devinfo * 347 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 348 { 349 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 350 pcicfgregs *cfg = NULL; 351 struct pci_devinfo *devlist_entry; 352 struct devlist *devlist_head; 353 354 devlist_head = &pci_devq; 355 356 devlist_entry = NULL; 357 358 if (REG(PCIR_DEVVENDOR, 4) != -1) { 359 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 360 if (devlist_entry == NULL) 361 return (NULL); 362 363 cfg = &devlist_entry->cfg; 364 365 cfg->bus = b; 366 cfg->slot = s; 367 cfg->func = f; 368 cfg->vendor = REG(PCIR_VENDOR, 2); 369 cfg->device = REG(PCIR_DEVICE, 2); 370 cfg->cmdreg = REG(PCIR_COMMAND, 2); 371 cfg->statreg = REG(PCIR_STATUS, 2); 372 cfg->baseclass = REG(PCIR_CLASS, 1); 373 cfg->subclass = REG(PCIR_SUBCLASS, 1); 374 cfg->progif = REG(PCIR_PROGIF, 1); 375 cfg->revid = REG(PCIR_REVID, 1); 376 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 377 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 378 cfg->lattimer = REG(PCIR_LATTIMER, 1); 379 cfg->intpin = REG(PCIR_INTPIN, 1); 380 cfg->intline = REG(PCIR_INTLINE, 1); 381 382 cfg->mingnt = REG(PCIR_MINGNT, 1); 383 cfg->maxlat = REG(PCIR_MAXLAT, 1); 384 385 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 386 cfg->hdrtype &= ~PCIM_MFDEV; 387 388 pci_fixancient(cfg); 389 pci_hdrtypedata(pcib, b, s, f, cfg); 390 391 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 392 pci_read_extcap(pcib, cfg); 393 394 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 395 396 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 397 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 398 devlist_entry->conf.pc_sel.pc_func = cfg->func; 399 devlist_entry->conf.pc_hdr = cfg->hdrtype; 400 401 devlist_entry->conf.pc_subvendor = cfg->subvendor; 402 devlist_entry->conf.pc_subdevice = cfg->subdevice; 403 devlist_entry->conf.pc_vendor = cfg->vendor; 404 devlist_entry->conf.pc_device = cfg->device; 405 406 devlist_entry->conf.pc_class = cfg->baseclass; 407 devlist_entry->conf.pc_subclass = cfg->subclass; 408 devlist_entry->conf.pc_progif = cfg->progif; 409 devlist_entry->conf.pc_revid = cfg->revid; 410 411 pci_numdevs++; 412 pci_generation++; 413 } 414 return (devlist_entry); 415 #undef REG 416 } 417 418 static void 419 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 420 { 421 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 422 int ptr, nextptr, ptrptr; 423 424 switch (cfg->hdrtype & PCIM_HDRTYPE) { 425 case 0: 426 ptrptr = PCIR_CAP_PTR; 427 break; 428 case 2: 429 ptrptr = 0x14; 430 break; 431 default: 432 return; /* no extended capabilities support */ 433 } 434 nextptr = REG(ptrptr, 1); /* sanity check? */ 435 436 /* 437 * Read capability entries. 438 */ 439 while (nextptr != 0) { 440 /* Sanity check */ 441 if (nextptr > 255) { 442 printf("illegal PCI extended capability offset %d\n", 443 nextptr); 444 return; 445 } 446 /* Find the next entry */ 447 ptr = nextptr; 448 nextptr = REG(ptr + 1, 1); 449 450 /* Process this entry */ 451 switch (REG(ptr, 1)) { 452 case PCIY_PMG: /* PCI power management */ 453 if (cfg->pp.pp_cap == 0) { 454 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 455 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 456 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 457 if ((nextptr - ptr) > PCIR_POWER_DATA) 458 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 459 } 460 break; 461 case PCIY_MSI: /* PCI MSI */ 462 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 463 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 464 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 465 else 466 cfg->msi.msi_data = PCIR_MSI_DATA; 467 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 468 PCIM_MSICTRL_MMC_MASK)>>1); 469 default: 470 break; 471 } 472 } 473 #undef REG 474 } 475 476 /* free pcicfgregs structure and all depending data structures */ 477 478 int 479 pci_freecfg(struct pci_devinfo *dinfo) 480 { 481 struct devlist *devlist_head; 482 483 devlist_head = &pci_devq; 484 485 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 486 free(dinfo, M_DEVBUF); 487 488 /* increment the generation count */ 489 pci_generation++; 490 491 /* we're losing one device */ 492 pci_numdevs--; 493 return (0); 494 } 495 496 /* 497 * PCI power manangement 498 */ 499 int 500 pci_set_powerstate_method(device_t dev, device_t child, int state) 501 { 502 struct pci_devinfo *dinfo = device_get_ivars(child); 503 pcicfgregs *cfg = &dinfo->cfg; 504 uint16_t status; 505 int result, oldstate, highest, delay; 506 507 if (cfg->pp.pp_cap == 0) 508 return (EOPNOTSUPP); 509 510 /* 511 * Optimize a no state change request away. While it would be OK to 512 * write to the hardware in theory, some devices have shown odd 513 * behavior when going from D3 -> D3. 514 */ 515 oldstate = pci_get_powerstate(child); 516 if (oldstate == state) 517 return (0); 518 519 /* 520 * The PCI power management specification states that after a state 521 * transition between PCI power states, system software must 522 * guarantee a minimal delay before the function accesses the device. 523 * Compute the worst case delay that we need to guarantee before we 524 * access the device. Many devices will be responsive much more 525 * quickly than this delay, but there are some that don't respond 526 * instantly to state changes. Transitions to/from D3 state require 527 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 528 * is done below with DELAY rather than a sleeper function because 529 * this function can be called from contexts where we cannot sleep. 530 */ 531 highest = (oldstate > state) ? oldstate : state; 532 if (highest == PCI_POWERSTATE_D3) 533 delay = 10000; 534 else if (highest == PCI_POWERSTATE_D2) 535 delay = 200; 536 else 537 delay = 0; 538 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 539 & ~PCIM_PSTAT_DMASK; 540 result = 0; 541 switch (state) { 542 case PCI_POWERSTATE_D0: 543 status |= PCIM_PSTAT_D0; 544 break; 545 case PCI_POWERSTATE_D1: 546 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 547 return (EOPNOTSUPP); 548 status |= PCIM_PSTAT_D1; 549 break; 550 case PCI_POWERSTATE_D2: 551 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 552 return (EOPNOTSUPP); 553 status |= PCIM_PSTAT_D2; 554 break; 555 case PCI_POWERSTATE_D3: 556 status |= PCIM_PSTAT_D3; 557 break; 558 default: 559 return (EINVAL); 560 } 561 562 if (bootverbose) 563 printf( 564 "pci%d:%d:%d: Transition from D%d to D%d\n", 565 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 566 oldstate, state); 567 568 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 569 if (delay) 570 DELAY(delay); 571 return (0); 572 } 573 574 int 575 pci_get_powerstate_method(device_t dev, device_t child) 576 { 577 struct pci_devinfo *dinfo = device_get_ivars(child); 578 pcicfgregs *cfg = &dinfo->cfg; 579 uint16_t status; 580 int result; 581 582 if (cfg->pp.pp_cap != 0) { 583 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 584 switch (status & PCIM_PSTAT_DMASK) { 585 case PCIM_PSTAT_D0: 586 result = PCI_POWERSTATE_D0; 587 break; 588 case PCIM_PSTAT_D1: 589 result = PCI_POWERSTATE_D1; 590 break; 591 case PCIM_PSTAT_D2: 592 result = PCI_POWERSTATE_D2; 593 break; 594 case PCIM_PSTAT_D3: 595 result = PCI_POWERSTATE_D3; 596 break; 597 default: 598 result = PCI_POWERSTATE_UNKNOWN; 599 break; 600 } 601 } else { 602 /* No support, device is always at D0 */ 603 result = PCI_POWERSTATE_D0; 604 } 605 return (result); 606 } 607 608 /* 609 * Some convenience functions for PCI device drivers. 610 */ 611 612 static __inline void 613 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 614 { 615 uint16_t command; 616 617 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 618 command |= bit; 619 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 620 } 621 622 static __inline void 623 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 624 { 625 uint16_t command; 626 627 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 628 command &= ~bit; 629 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 630 } 631 632 int 633 pci_enable_busmaster_method(device_t dev, device_t child) 634 { 635 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 636 return (0); 637 } 638 639 int 640 pci_disable_busmaster_method(device_t dev, device_t child) 641 { 642 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 643 return (0); 644 } 645 646 int 647 pci_enable_io_method(device_t dev, device_t child, int space) 648 { 649 uint16_t command; 650 uint16_t bit; 651 char *error; 652 653 bit = 0; 654 error = NULL; 655 656 switch(space) { 657 case SYS_RES_IOPORT: 658 bit = PCIM_CMD_PORTEN; 659 error = "port"; 660 break; 661 case SYS_RES_MEMORY: 662 bit = PCIM_CMD_MEMEN; 663 error = "memory"; 664 break; 665 default: 666 return (EINVAL); 667 } 668 pci_set_command_bit(dev, child, bit); 669 /* Some devices seem to need a brief stall here, what do to? */ 670 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 671 if (command & bit) 672 return (0); 673 device_printf(child, "failed to enable %s mapping!\n", error); 674 return (ENXIO); 675 } 676 677 int 678 pci_disable_io_method(device_t dev, device_t child, int space) 679 { 680 uint16_t command; 681 uint16_t bit; 682 char *error; 683 684 bit = 0; 685 error = NULL; 686 687 switch(space) { 688 case SYS_RES_IOPORT: 689 bit = PCIM_CMD_PORTEN; 690 error = "port"; 691 break; 692 case SYS_RES_MEMORY: 693 bit = PCIM_CMD_MEMEN; 694 error = "memory"; 695 break; 696 default: 697 return (EINVAL); 698 } 699 pci_clear_command_bit(dev, child, bit); 700 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 701 if (command & bit) { 702 device_printf(child, "failed to disable %s mapping!\n", error); 703 return (ENXIO); 704 } 705 return (0); 706 } 707 708 /* 709 * New style pci driver. Parent device is either a pci-host-bridge or a 710 * pci-pci-bridge. Both kinds are represented by instances of pcib. 711 */ 712 713 void 714 pci_print_verbose(struct pci_devinfo *dinfo) 715 { 716 if (bootverbose) { 717 pcicfgregs *cfg = &dinfo->cfg; 718 719 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 720 cfg->vendor, cfg->device, cfg->revid); 721 printf("\tbus=%d, slot=%d, func=%d\n", 722 cfg->bus, cfg->slot, cfg->func); 723 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 724 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 725 cfg->mfdev); 726 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 727 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 728 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 729 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 730 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 731 if (cfg->intpin > 0) 732 printf("\tintpin=%c, irq=%d\n", 733 cfg->intpin +'a' -1, cfg->intline); 734 if (cfg->pp.pp_cap) { 735 uint16_t status; 736 737 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 738 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 739 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 740 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 741 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 742 status & PCIM_PSTAT_DMASK); 743 } 744 if (cfg->msi.msi_data) { 745 int ctrl; 746 747 ctrl = cfg->msi.msi_ctrl; 748 printf("\tMSI supports %d message%s%s%s\n", 749 cfg->msi.msi_msgnum, 750 (cfg->msi.msi_msgnum == 1) ? "" : "s", 751 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 752 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 753 } 754 } 755 } 756 757 static int 758 pci_porten(device_t pcib, int b, int s, int f) 759 { 760 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 761 & PCIM_CMD_PORTEN) != 0; 762 } 763 764 static int 765 pci_memen(device_t pcib, int b, int s, int f) 766 { 767 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 768 & PCIM_CMD_MEMEN) != 0; 769 } 770 771 /* 772 * Add a resource based on a pci map register. Return 1 if the map 773 * register is a 32bit map register or 2 if it is a 64bit register. 774 */ 775 static int 776 pci_add_map(device_t pcib, device_t bus, device_t dev, 777 int b, int s, int f, int reg, struct resource_list *rl) 778 { 779 uint32_t map; 780 uint64_t base; 781 uint64_t start, end, count; 782 uint8_t ln2size; 783 uint8_t ln2range; 784 uint32_t testval; 785 uint16_t cmd; 786 int type; 787 int barlen; 788 789 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 790 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 791 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 792 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 793 794 if (pci_maptype(map) & PCI_MAPMEM) 795 type = SYS_RES_MEMORY; 796 else 797 type = SYS_RES_IOPORT; 798 ln2size = pci_mapsize(testval); 799 ln2range = pci_maprange(testval); 800 base = pci_mapbase(map); 801 barlen = ln2range == 64 ? 2 : 1; 802 803 /* 804 * For I/O registers, if bottom bit is set, and the next bit up 805 * isn't clear, we know we have a BAR that doesn't conform to the 806 * spec, so ignore it. Also, sanity check the size of the data 807 * areas to the type of memory involved. Memory must be at least 808 * 32 bytes in size, while I/O ranges must be at least 4. 809 */ 810 if ((testval & 0x1) == 0x1 && 811 (testval & 0x2) != 0) 812 return (barlen); 813 if ((type == SYS_RES_MEMORY && ln2size < 5) || 814 (type == SYS_RES_IOPORT && ln2size < 2)) 815 return (barlen); 816 817 if (ln2range == 64) 818 /* Read the other half of a 64bit map register */ 819 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 820 821 if (bootverbose) { 822 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 823 reg, pci_maptype(map), ln2range, 824 (unsigned int) base, ln2size); 825 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 826 printf(", port disabled\n"); 827 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 828 printf(", memory disabled\n"); 829 else 830 printf(", enabled\n"); 831 } 832 833 /* 834 * If base is 0, then we have problems. It is best to ignore 835 * such entries for the moment. These will be allocated later if 836 * the driver specifically requests them. 837 * 838 * Similarly treat maps whose values is the same as the test value 839 * read back. These maps have had all f's written to them by the 840 * BIOS in an attempt to disable the resources. 841 */ 842 if (base == 0 || map == testval) 843 return (barlen); 844 845 /* 846 * This code theoretically does the right thing, but has 847 * undesirable side effects in some cases where peripherals 848 * respond oddly to having these bits enabled. Let the user 849 * be able to turn them off (since pci_enable_io_modes is 1 by 850 * default). 851 */ 852 if (pci_enable_io_modes) { 853 /* Turn on resources that have been left off by a lazy BIOS */ 854 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 855 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 856 cmd |= PCIM_CMD_PORTEN; 857 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 858 } 859 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 860 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 861 cmd |= PCIM_CMD_MEMEN; 862 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 863 } 864 } else { 865 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 866 return (barlen); 867 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 868 return (barlen); 869 } 870 871 start = base; 872 end = base + (1 << ln2size) - 1; 873 count = 1 << ln2size; 874 resource_list_add(rl, type, reg, start, end, count); 875 876 /* 877 * Not quite sure what to do on failure of allocating the resource 878 * since I can postulate several right answers. 879 */ 880 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 881 return (barlen); 882 } 883 884 /* 885 * For ATA devices we need to decide early what addressing mode to use. 886 * Legacy demands that the primary and secondary ATA ports sits on the 887 * same addresses that old ISA hardware did. This dictates that we use 888 * those addresses and ignore the BAR's if we cannot set PCI native 889 * addressing mode. 890 */ 891 static void 892 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 893 int s, int f, struct resource_list *rl) 894 { 895 int rid, type, progif; 896 #if 0 897 /* if this device supports PCI native addressing use it */ 898 progif = pci_read_config(dev, PCIR_PROGIF, 1); 899 if ((progif & 0x8a) == 0x8a) { 900 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 901 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 902 printf("Trying ATA native PCI addressing mode\n"); 903 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 904 } 905 } 906 #endif 907 progif = pci_read_config(dev, PCIR_PROGIF, 1); 908 type = SYS_RES_IOPORT; 909 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 910 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 911 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 912 } 913 else { 914 rid = PCIR_BAR(0); 915 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 916 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 917 rid = PCIR_BAR(1); 918 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 919 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 920 } 921 if (progif & PCIP_STORAGE_IDE_MODESEC) { 922 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 923 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 924 } 925 else { 926 rid = PCIR_BAR(2); 927 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 928 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 929 rid = PCIR_BAR(3); 930 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 931 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 932 } 933 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 934 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 935 } 936 937 static void 938 pci_add_resources(device_t pcib, device_t bus, device_t dev) 939 { 940 struct pci_devinfo *dinfo = device_get_ivars(dev); 941 pcicfgregs *cfg = &dinfo->cfg; 942 struct resource_list *rl = &dinfo->resources; 943 struct pci_quirk *q; 944 int b, i, irq, f, s; 945 946 b = cfg->bus; 947 s = cfg->slot; 948 f = cfg->func; 949 950 /* ATA devices needs special map treatment */ 951 if ((pci_get_class(dev) == PCIC_STORAGE) && 952 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 953 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 954 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 955 else 956 for (i = 0; i < cfg->nummaps;) 957 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 958 rl); 959 960 for (q = &pci_quirks[0]; q->devid; q++) { 961 if (q->devid == ((cfg->device << 16) | cfg->vendor) 962 && q->type == PCI_QUIRK_MAP_REG) 963 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 964 } 965 966 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 967 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 968 defined(__arm__) || defined(__alpha__) 969 /* 970 * Try to re-route interrupts. Sometimes the BIOS or 971 * firmware may leave bogus values in these registers. 972 * If the re-route fails, then just stick with what we 973 * have. 974 */ 975 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 976 if (PCI_INTERRUPT_VALID(irq)) { 977 pci_write_config(dev, PCIR_INTLINE, irq, 1); 978 cfg->intline = irq; 979 } else 980 #endif 981 irq = cfg->intline; 982 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 983 } 984 } 985 986 void 987 pci_add_children(device_t dev, int busno, size_t dinfo_size) 988 { 989 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 990 device_t pcib = device_get_parent(dev); 991 struct pci_devinfo *dinfo; 992 int maxslots; 993 int s, f, pcifunchigh; 994 uint8_t hdrtype; 995 996 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 997 ("dinfo_size too small")); 998 maxslots = PCIB_MAXSLOTS(pcib); 999 for (s = 0; s <= maxslots; s++) { 1000 pcifunchigh = 0; 1001 f = 0; 1002 hdrtype = REG(PCIR_HDRTYPE, 1); 1003 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1004 continue; 1005 if (hdrtype & PCIM_MFDEV) 1006 pcifunchigh = PCI_FUNCMAX; 1007 for (f = 0; f <= pcifunchigh; f++) { 1008 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1009 if (dinfo != NULL) { 1010 pci_add_child(dev, dinfo); 1011 } 1012 } 1013 } 1014 #undef REG 1015 } 1016 1017 void 1018 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1019 { 1020 device_t pcib; 1021 1022 pcib = device_get_parent(bus); 1023 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1024 device_set_ivars(dinfo->cfg.dev, dinfo); 1025 resource_list_init(&dinfo->resources); 1026 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1027 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1028 pci_print_verbose(dinfo); 1029 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1030 } 1031 1032 static int 1033 pci_probe(device_t dev) 1034 { 1035 1036 device_set_desc(dev, "PCI bus"); 1037 1038 /* Allow other subclasses to override this driver. */ 1039 return (-1000); 1040 } 1041 1042 static int 1043 pci_attach(device_t dev) 1044 { 1045 int busno; 1046 1047 /* 1048 * Since there can be multiple independantly numbered PCI 1049 * busses on some large alpha systems, we can't use the unit 1050 * number to decide what bus we are probing. We ask the parent 1051 * pcib what our bus number is. 1052 */ 1053 busno = pcib_get_bus(dev); 1054 if (bootverbose) 1055 device_printf(dev, "physical bus=%d\n", busno); 1056 1057 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1058 1059 return (bus_generic_attach(dev)); 1060 } 1061 1062 int 1063 pci_suspend(device_t dev) 1064 { 1065 int dstate, error, i, numdevs; 1066 device_t acpi_dev, child, *devlist; 1067 struct pci_devinfo *dinfo; 1068 1069 /* 1070 * Save the PCI configuration space for each child and set the 1071 * device in the appropriate power state for this sleep state. 1072 */ 1073 acpi_dev = NULL; 1074 if (pci_do_powerstate) 1075 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1076 device_get_children(dev, &devlist, &numdevs); 1077 for (i = 0; i < numdevs; i++) { 1078 child = devlist[i]; 1079 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1080 pci_cfg_save(child, dinfo, 0); 1081 } 1082 1083 /* Suspend devices before potentially powering them down. */ 1084 error = bus_generic_suspend(dev); 1085 if (error) { 1086 free(devlist, M_TEMP); 1087 return (error); 1088 } 1089 1090 /* 1091 * Always set the device to D3. If ACPI suggests a different 1092 * power state, use it instead. If ACPI is not present, the 1093 * firmware is responsible for managing device power. Skip 1094 * children who aren't attached since they are powered down 1095 * separately. Only manage type 0 devices for now. 1096 */ 1097 for (i = 0; acpi_dev && i < numdevs; i++) { 1098 child = devlist[i]; 1099 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1100 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1101 dstate = PCI_POWERSTATE_D3; 1102 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1103 pci_set_powerstate(child, dstate); 1104 } 1105 } 1106 free(devlist, M_TEMP); 1107 return (0); 1108 } 1109 1110 int 1111 pci_resume(device_t dev) 1112 { 1113 int i, numdevs; 1114 device_t acpi_dev, child, *devlist; 1115 struct pci_devinfo *dinfo; 1116 1117 /* 1118 * Set each child to D0 and restore its PCI configuration space. 1119 */ 1120 acpi_dev = NULL; 1121 if (pci_do_powerstate) 1122 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1123 device_get_children(dev, &devlist, &numdevs); 1124 for (i = 0; i < numdevs; i++) { 1125 /* 1126 * Notify ACPI we're going to D0 but ignore the result. If 1127 * ACPI is not present, the firmware is responsible for 1128 * managing device power. Only manage type 0 devices for now. 1129 */ 1130 child = devlist[i]; 1131 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1132 if (acpi_dev && device_is_attached(child) && 1133 dinfo->cfg.hdrtype == 0) { 1134 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1135 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1136 } 1137 1138 /* Now the device is powered up, restore its config space. */ 1139 pci_cfg_restore(child, dinfo); 1140 } 1141 free(devlist, M_TEMP); 1142 return (bus_generic_resume(dev)); 1143 } 1144 1145 static void 1146 pci_load_vendor_data(void) 1147 { 1148 caddr_t vendordata, info; 1149 1150 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1151 info = preload_search_info(vendordata, MODINFO_ADDR); 1152 pci_vendordata = *(char **)info; 1153 info = preload_search_info(vendordata, MODINFO_SIZE); 1154 pci_vendordata_size = *(size_t *)info; 1155 /* terminate the database */ 1156 pci_vendordata[pci_vendordata_size] = '\n'; 1157 } 1158 } 1159 1160 void 1161 pci_driver_added(device_t dev, driver_t *driver) 1162 { 1163 int numdevs; 1164 device_t *devlist; 1165 device_t child; 1166 struct pci_devinfo *dinfo; 1167 int i; 1168 1169 if (bootverbose) 1170 device_printf(dev, "driver added\n"); 1171 DEVICE_IDENTIFY(driver, dev); 1172 device_get_children(dev, &devlist, &numdevs); 1173 for (i = 0; i < numdevs; i++) { 1174 child = devlist[i]; 1175 if (device_get_state(child) != DS_NOTPRESENT) 1176 continue; 1177 dinfo = device_get_ivars(child); 1178 pci_print_verbose(dinfo); 1179 if (bootverbose) 1180 printf("pci%d:%d:%d: reprobing on driver added\n", 1181 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1182 pci_cfg_restore(child, dinfo); 1183 if (device_probe_and_attach(child) != 0) 1184 pci_cfg_save(child, dinfo, 1); 1185 } 1186 free(devlist, M_TEMP); 1187 } 1188 1189 int 1190 pci_print_child(device_t dev, device_t child) 1191 { 1192 struct pci_devinfo *dinfo; 1193 struct resource_list *rl; 1194 int retval = 0; 1195 1196 dinfo = device_get_ivars(child); 1197 rl = &dinfo->resources; 1198 1199 retval += bus_print_child_header(dev, child); 1200 1201 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1202 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1203 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1204 if (device_get_flags(dev)) 1205 retval += printf(" flags %#x", device_get_flags(dev)); 1206 1207 retval += printf(" at device %d.%d", pci_get_slot(child), 1208 pci_get_function(child)); 1209 1210 retval += bus_print_child_footer(dev, child); 1211 1212 return (retval); 1213 } 1214 1215 static struct 1216 { 1217 int class; 1218 int subclass; 1219 char *desc; 1220 } pci_nomatch_tab[] = { 1221 {PCIC_OLD, -1, "old"}, 1222 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1223 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1224 {PCIC_STORAGE, -1, "mass storage"}, 1225 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1226 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1227 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1228 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1229 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1230 {PCIC_NETWORK, -1, "network"}, 1231 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1232 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1233 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1234 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1235 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1236 {PCIC_DISPLAY, -1, "display"}, 1237 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1238 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1239 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1240 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1241 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1242 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1243 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1244 {PCIC_MEMORY, -1, "memory"}, 1245 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1246 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1247 {PCIC_BRIDGE, -1, "bridge"}, 1248 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1249 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1250 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1251 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1252 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1253 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1254 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1255 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1256 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1257 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1258 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1259 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1260 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1261 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1262 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1263 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1264 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1265 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1266 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1267 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1268 {PCIC_INPUTDEV, -1, "input device"}, 1269 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1270 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1271 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1272 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1273 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1274 {PCIC_DOCKING, -1, "docking station"}, 1275 {PCIC_PROCESSOR, -1, "processor"}, 1276 {PCIC_SERIALBUS, -1, "serial bus"}, 1277 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1278 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1279 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1280 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1281 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1282 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1283 {PCIC_WIRELESS, -1, "wireless controller"}, 1284 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1285 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1286 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1287 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1288 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1289 {PCIC_SATCOM, -1, "satellite communication"}, 1290 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1291 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1292 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1293 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1294 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1295 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1296 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1297 {PCIC_DASP, -1, "dasp"}, 1298 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1299 {0, 0, NULL} 1300 }; 1301 1302 void 1303 pci_probe_nomatch(device_t dev, device_t child) 1304 { 1305 int i; 1306 char *cp, *scp, *device; 1307 1308 /* 1309 * Look for a listing for this device in a loaded device database. 1310 */ 1311 if ((device = pci_describe_device(child)) != NULL) { 1312 device_printf(dev, "<%s>", device); 1313 free(device, M_DEVBUF); 1314 } else { 1315 /* 1316 * Scan the class/subclass descriptions for a general 1317 * description. 1318 */ 1319 cp = "unknown"; 1320 scp = NULL; 1321 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1322 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1323 if (pci_nomatch_tab[i].subclass == -1) { 1324 cp = pci_nomatch_tab[i].desc; 1325 } else if (pci_nomatch_tab[i].subclass == 1326 pci_get_subclass(child)) { 1327 scp = pci_nomatch_tab[i].desc; 1328 } 1329 } 1330 } 1331 device_printf(dev, "<%s%s%s>", 1332 cp ? cp : "", 1333 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1334 scp ? scp : ""); 1335 } 1336 printf(" at device %d.%d (no driver attached)\n", 1337 pci_get_slot(child), pci_get_function(child)); 1338 if (pci_do_powerstate) 1339 pci_cfg_save(child, 1340 (struct pci_devinfo *) device_get_ivars(child), 1); 1341 return; 1342 } 1343 1344 /* 1345 * Parse the PCI device database, if loaded, and return a pointer to a 1346 * description of the device. 1347 * 1348 * The database is flat text formatted as follows: 1349 * 1350 * Any line not in a valid format is ignored. 1351 * Lines are terminated with newline '\n' characters. 1352 * 1353 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1354 * the vendor name. 1355 * 1356 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1357 * - devices cannot be listed without a corresponding VENDOR line. 1358 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1359 * another TAB, then the device name. 1360 */ 1361 1362 /* 1363 * Assuming (ptr) points to the beginning of a line in the database, 1364 * return the vendor or device and description of the next entry. 1365 * The value of (vendor) or (device) inappropriate for the entry type 1366 * is set to -1. Returns nonzero at the end of the database. 1367 * 1368 * Note that this is slightly unrobust in the face of corrupt data; 1369 * we attempt to safeguard against this by spamming the end of the 1370 * database with a newline when we initialise. 1371 */ 1372 static int 1373 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1374 { 1375 char *cp = *ptr; 1376 int left; 1377 1378 *device = -1; 1379 *vendor = -1; 1380 **desc = '\0'; 1381 for (;;) { 1382 left = pci_vendordata_size - (cp - pci_vendordata); 1383 if (left <= 0) { 1384 *ptr = cp; 1385 return(1); 1386 } 1387 1388 /* vendor entry? */ 1389 if (*cp != '\t' && 1390 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1391 break; 1392 /* device entry? */ 1393 if (*cp == '\t' && 1394 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1395 break; 1396 1397 /* skip to next line */ 1398 while (*cp != '\n' && left > 0) { 1399 cp++; 1400 left--; 1401 } 1402 if (*cp == '\n') { 1403 cp++; 1404 left--; 1405 } 1406 } 1407 /* skip to next line */ 1408 while (*cp != '\n' && left > 0) { 1409 cp++; 1410 left--; 1411 } 1412 if (*cp == '\n' && left > 0) 1413 cp++; 1414 *ptr = cp; 1415 return(0); 1416 } 1417 1418 static char * 1419 pci_describe_device(device_t dev) 1420 { 1421 int vendor, device; 1422 char *desc, *vp, *dp, *line; 1423 1424 desc = vp = dp = NULL; 1425 1426 /* 1427 * If we have no vendor data, we can't do anything. 1428 */ 1429 if (pci_vendordata == NULL) 1430 goto out; 1431 1432 /* 1433 * Scan the vendor data looking for this device 1434 */ 1435 line = pci_vendordata; 1436 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1437 goto out; 1438 for (;;) { 1439 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1440 goto out; 1441 if (vendor == pci_get_vendor(dev)) 1442 break; 1443 } 1444 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1445 goto out; 1446 for (;;) { 1447 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1448 *dp = 0; 1449 break; 1450 } 1451 if (vendor != -1) { 1452 *dp = 0; 1453 break; 1454 } 1455 if (device == pci_get_device(dev)) 1456 break; 1457 } 1458 if (dp[0] == '\0') 1459 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1460 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1461 NULL) 1462 sprintf(desc, "%s, %s", vp, dp); 1463 out: 1464 if (vp != NULL) 1465 free(vp, M_DEVBUF); 1466 if (dp != NULL) 1467 free(dp, M_DEVBUF); 1468 return(desc); 1469 } 1470 1471 int 1472 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1473 { 1474 struct pci_devinfo *dinfo; 1475 pcicfgregs *cfg; 1476 1477 dinfo = device_get_ivars(child); 1478 cfg = &dinfo->cfg; 1479 1480 switch (which) { 1481 case PCI_IVAR_ETHADDR: 1482 /* 1483 * The generic accessor doesn't deal with failure, so 1484 * we set the return value, then return an error. 1485 */ 1486 *((uint8_t **) result) = NULL; 1487 return (EINVAL); 1488 case PCI_IVAR_SUBVENDOR: 1489 *result = cfg->subvendor; 1490 break; 1491 case PCI_IVAR_SUBDEVICE: 1492 *result = cfg->subdevice; 1493 break; 1494 case PCI_IVAR_VENDOR: 1495 *result = cfg->vendor; 1496 break; 1497 case PCI_IVAR_DEVICE: 1498 *result = cfg->device; 1499 break; 1500 case PCI_IVAR_DEVID: 1501 *result = (cfg->device << 16) | cfg->vendor; 1502 break; 1503 case PCI_IVAR_CLASS: 1504 *result = cfg->baseclass; 1505 break; 1506 case PCI_IVAR_SUBCLASS: 1507 *result = cfg->subclass; 1508 break; 1509 case PCI_IVAR_PROGIF: 1510 *result = cfg->progif; 1511 break; 1512 case PCI_IVAR_REVID: 1513 *result = cfg->revid; 1514 break; 1515 case PCI_IVAR_INTPIN: 1516 *result = cfg->intpin; 1517 break; 1518 case PCI_IVAR_IRQ: 1519 *result = cfg->intline; 1520 break; 1521 case PCI_IVAR_BUS: 1522 *result = cfg->bus; 1523 break; 1524 case PCI_IVAR_SLOT: 1525 *result = cfg->slot; 1526 break; 1527 case PCI_IVAR_FUNCTION: 1528 *result = cfg->func; 1529 break; 1530 case PCI_IVAR_CMDREG: 1531 *result = cfg->cmdreg; 1532 break; 1533 case PCI_IVAR_CACHELNSZ: 1534 *result = cfg->cachelnsz; 1535 break; 1536 case PCI_IVAR_MINGNT: 1537 *result = cfg->mingnt; 1538 break; 1539 case PCI_IVAR_MAXLAT: 1540 *result = cfg->maxlat; 1541 break; 1542 case PCI_IVAR_LATTIMER: 1543 *result = cfg->lattimer; 1544 break; 1545 default: 1546 return (ENOENT); 1547 } 1548 return (0); 1549 } 1550 1551 int 1552 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1553 { 1554 struct pci_devinfo *dinfo; 1555 1556 dinfo = device_get_ivars(child); 1557 1558 switch (which) { 1559 case PCI_IVAR_INTPIN: 1560 dinfo->cfg.intpin = value; 1561 return (0); 1562 case PCI_IVAR_ETHADDR: 1563 case PCI_IVAR_SUBVENDOR: 1564 case PCI_IVAR_SUBDEVICE: 1565 case PCI_IVAR_VENDOR: 1566 case PCI_IVAR_DEVICE: 1567 case PCI_IVAR_DEVID: 1568 case PCI_IVAR_CLASS: 1569 case PCI_IVAR_SUBCLASS: 1570 case PCI_IVAR_PROGIF: 1571 case PCI_IVAR_REVID: 1572 case PCI_IVAR_IRQ: 1573 case PCI_IVAR_BUS: 1574 case PCI_IVAR_SLOT: 1575 case PCI_IVAR_FUNCTION: 1576 return (EINVAL); /* disallow for now */ 1577 1578 default: 1579 return (ENOENT); 1580 } 1581 } 1582 1583 1584 #include "opt_ddb.h" 1585 #ifdef DDB 1586 #include <ddb/ddb.h> 1587 #include <sys/cons.h> 1588 1589 /* 1590 * List resources based on pci map registers, used for within ddb 1591 */ 1592 1593 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1594 { 1595 struct pci_devinfo *dinfo; 1596 struct devlist *devlist_head; 1597 struct pci_conf *p; 1598 const char *name; 1599 int i, error, none_count, quit; 1600 1601 none_count = 0; 1602 /* get the head of the device queue */ 1603 devlist_head = &pci_devq; 1604 1605 /* 1606 * Go through the list of devices and print out devices 1607 */ 1608 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1609 for (error = 0, i = 0, quit = 0, 1610 dinfo = STAILQ_FIRST(devlist_head); 1611 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1612 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1613 1614 /* Populate pd_name and pd_unit */ 1615 name = NULL; 1616 if (dinfo->cfg.dev) 1617 name = device_get_name(dinfo->cfg.dev); 1618 1619 p = &dinfo->conf; 1620 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1621 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1622 (name && *name) ? name : "none", 1623 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1624 none_count++, 1625 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1626 p->pc_sel.pc_func, (p->pc_class << 16) | 1627 (p->pc_subclass << 8) | p->pc_progif, 1628 (p->pc_subdevice << 16) | p->pc_subvendor, 1629 (p->pc_device << 16) | p->pc_vendor, 1630 p->pc_revid, p->pc_hdr); 1631 } 1632 } 1633 #endif /* DDB */ 1634 1635 static struct resource * 1636 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1637 u_long start, u_long end, u_long count, u_int flags) 1638 { 1639 struct pci_devinfo *dinfo = device_get_ivars(child); 1640 struct resource_list *rl = &dinfo->resources; 1641 struct resource_list_entry *rle; 1642 struct resource *res; 1643 uint32_t map, testval; 1644 int mapsize; 1645 1646 /* 1647 * Weed out the bogons, and figure out how large the BAR/map 1648 * is. Bars that read back 0 here are bogus and unimplemented. 1649 * Note: atapci in legacy mode are special and handled elsewhere 1650 * in the code. If you have a atapci device in legacy mode and 1651 * it fails here, that other code is broken. 1652 */ 1653 res = NULL; 1654 map = pci_read_config(child, *rid, 4); 1655 pci_write_config(child, *rid, 0xffffffff, 4); 1656 testval = pci_read_config(child, *rid, 4); 1657 if (pci_mapbase(testval) == 0) 1658 goto out; 1659 if (pci_maptype(testval) & PCI_MAPMEM) { 1660 if (type != SYS_RES_MEMORY) { 1661 if (bootverbose) 1662 device_printf(dev, 1663 "child %s requested type %d for rid %#x," 1664 " but the BAR says it is an memio\n", 1665 device_get_nameunit(child), type, *rid); 1666 goto out; 1667 } 1668 } else { 1669 if (type != SYS_RES_IOPORT) { 1670 if (bootverbose) 1671 device_printf(dev, 1672 "child %s requested type %d for rid %#x," 1673 " but the BAR says it is an ioport\n", 1674 device_get_nameunit(child), type, *rid); 1675 goto out; 1676 } 1677 } 1678 /* 1679 * For real BARs, we need to override the size that 1680 * the driver requests, because that's what the BAR 1681 * actually uses and we would otherwise have a 1682 * situation where we might allocate the excess to 1683 * another driver, which won't work. 1684 */ 1685 mapsize = pci_mapsize(testval); 1686 count = 1 << mapsize; 1687 if (RF_ALIGNMENT(flags) < mapsize) 1688 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1689 1690 /* 1691 * Allocate enough resource, and then write back the 1692 * appropriate bar for that resource. 1693 */ 1694 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1695 start, end, count, flags); 1696 if (res == NULL) { 1697 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1698 count, *rid, type); 1699 goto out; 1700 } 1701 resource_list_add(rl, type, *rid, start, end, count); 1702 rle = resource_list_find(rl, type, *rid); 1703 if (rle == NULL) 1704 panic("pci_alloc_map: unexpectedly can't find resource."); 1705 rle->res = res; 1706 if (bootverbose) 1707 device_printf(child, 1708 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1709 count, *rid, type, rman_get_start(res)); 1710 map = rman_get_start(res); 1711 out:; 1712 pci_write_config(child, *rid, map, 4); 1713 return (res); 1714 } 1715 1716 1717 struct resource * 1718 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1719 u_long start, u_long end, u_long count, u_int flags) 1720 { 1721 struct pci_devinfo *dinfo = device_get_ivars(child); 1722 struct resource_list *rl = &dinfo->resources; 1723 struct resource_list_entry *rle; 1724 pcicfgregs *cfg = &dinfo->cfg; 1725 1726 /* 1727 * Perform lazy resource allocation 1728 */ 1729 if (device_get_parent(child) == dev) { 1730 switch (type) { 1731 case SYS_RES_IRQ: 1732 /* 1733 * If the child device doesn't have an 1734 * interrupt routed and is deserving of an 1735 * interrupt, try to assign it one. 1736 */ 1737 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1738 (cfg->intpin != 0)) { 1739 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1740 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1741 pci_write_config(child, PCIR_INTLINE, 1742 cfg->intline, 1); 1743 resource_list_add(rl, SYS_RES_IRQ, 0, 1744 cfg->intline, cfg->intline, 1); 1745 } 1746 } 1747 break; 1748 case SYS_RES_IOPORT: 1749 case SYS_RES_MEMORY: 1750 if (*rid < PCIR_BAR(cfg->nummaps)) { 1751 /* 1752 * Enable the I/O mode. We should 1753 * also be assigning resources too 1754 * when none are present. The 1755 * resource_list_alloc kind of sorta does 1756 * this... 1757 */ 1758 if (PCI_ENABLE_IO(dev, child, type)) 1759 return (NULL); 1760 } 1761 rle = resource_list_find(rl, type, *rid); 1762 if (rle == NULL) 1763 return (pci_alloc_map(dev, child, type, rid, 1764 start, end, count, flags)); 1765 break; 1766 } 1767 /* 1768 * If we've already allocated the resource, then 1769 * return it now. But first we may need to activate 1770 * it, since we don't allocate the resource as active 1771 * above. Normally this would be done down in the 1772 * nexus, but since we short-circuit that path we have 1773 * to do its job here. Not sure if we should free the 1774 * resource if it fails to activate. 1775 */ 1776 rle = resource_list_find(rl, type, *rid); 1777 if (rle != NULL && rle->res != NULL) { 1778 if (bootverbose) 1779 device_printf(child, 1780 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1781 rman_get_size(rle->res), *rid, type, 1782 rman_get_start(rle->res)); 1783 if ((flags & RF_ACTIVE) && 1784 bus_generic_activate_resource(dev, child, type, 1785 *rid, rle->res) != 0) 1786 return NULL; 1787 return (rle->res); 1788 } 1789 } 1790 return (resource_list_alloc(rl, dev, child, type, rid, 1791 start, end, count, flags)); 1792 } 1793 1794 void 1795 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1796 { 1797 struct pci_devinfo *dinfo; 1798 struct resource_list *rl; 1799 struct resource_list_entry *rle; 1800 1801 if (device_get_parent(child) != dev) 1802 return; 1803 1804 dinfo = device_get_ivars(child); 1805 rl = &dinfo->resources; 1806 rle = resource_list_find(rl, type, rid); 1807 if (rle) { 1808 if (rle->res) { 1809 if (rman_get_device(rle->res) != dev || 1810 rman_get_flags(rle->res) & RF_ACTIVE) { 1811 device_printf(dev, "delete_resource: " 1812 "Resource still owned by child, oops. " 1813 "(type=%d, rid=%d, addr=%lx)\n", 1814 rle->type, rle->rid, 1815 rman_get_start(rle->res)); 1816 return; 1817 } 1818 bus_release_resource(dev, type, rid, rle->res); 1819 } 1820 resource_list_delete(rl, type, rid); 1821 } 1822 /* 1823 * Why do we turn off the PCI configuration BAR when we delete a 1824 * resource? -- imp 1825 */ 1826 pci_write_config(child, rid, 0, 4); 1827 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1828 } 1829 1830 struct resource_list * 1831 pci_get_resource_list (device_t dev, device_t child) 1832 { 1833 struct pci_devinfo *dinfo = device_get_ivars(child); 1834 1835 return (&dinfo->resources); 1836 } 1837 1838 uint32_t 1839 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1840 { 1841 struct pci_devinfo *dinfo = device_get_ivars(child); 1842 pcicfgregs *cfg = &dinfo->cfg; 1843 1844 return (PCIB_READ_CONFIG(device_get_parent(dev), 1845 cfg->bus, cfg->slot, cfg->func, reg, width)); 1846 } 1847 1848 void 1849 pci_write_config_method(device_t dev, device_t child, int reg, 1850 uint32_t val, int width) 1851 { 1852 struct pci_devinfo *dinfo = device_get_ivars(child); 1853 pcicfgregs *cfg = &dinfo->cfg; 1854 1855 PCIB_WRITE_CONFIG(device_get_parent(dev), 1856 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1857 } 1858 1859 int 1860 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1861 size_t buflen) 1862 { 1863 1864 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1865 pci_get_function(child)); 1866 return (0); 1867 } 1868 1869 int 1870 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1871 size_t buflen) 1872 { 1873 struct pci_devinfo *dinfo; 1874 pcicfgregs *cfg; 1875 1876 dinfo = device_get_ivars(child); 1877 cfg = &dinfo->cfg; 1878 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1879 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1880 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1881 cfg->progif); 1882 return (0); 1883 } 1884 1885 int 1886 pci_assign_interrupt_method(device_t dev, device_t child) 1887 { 1888 struct pci_devinfo *dinfo = device_get_ivars(child); 1889 pcicfgregs *cfg = &dinfo->cfg; 1890 1891 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1892 cfg->intpin)); 1893 } 1894 1895 static int 1896 pci_modevent(module_t mod, int what, void *arg) 1897 { 1898 static struct cdev *pci_cdev; 1899 1900 switch (what) { 1901 case MOD_LOAD: 1902 STAILQ_INIT(&pci_devq); 1903 pci_generation = 0; 1904 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1905 "pci"); 1906 pci_load_vendor_data(); 1907 break; 1908 1909 case MOD_UNLOAD: 1910 destroy_dev(pci_cdev); 1911 break; 1912 } 1913 1914 return (0); 1915 } 1916 1917 void 1918 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1919 { 1920 int i; 1921 1922 /* 1923 * Only do header type 0 devices. Type 1 devices are bridges, 1924 * which we know need special treatment. Type 2 devices are 1925 * cardbus bridges which also require special treatment. 1926 * Other types are unknown, and we err on the side of safety 1927 * by ignoring them. 1928 */ 1929 if (dinfo->cfg.hdrtype != 0) 1930 return; 1931 1932 /* 1933 * Restore the device to full power mode. We must do this 1934 * before we restore the registers because moving from D3 to 1935 * D0 will cause the chip's BARs and some other registers to 1936 * be reset to some unknown power on reset values. Cut down 1937 * the noise on boot by doing nothing if we are already in 1938 * state D0. 1939 */ 1940 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1941 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1942 } 1943 for (i = 0; i < dinfo->cfg.nummaps; i++) 1944 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1945 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1946 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1947 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1948 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1949 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1950 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1951 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1952 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1953 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1954 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1955 } 1956 1957 void 1958 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1959 { 1960 int i; 1961 uint32_t cls; 1962 int ps; 1963 1964 /* 1965 * Only do header type 0 devices. Type 1 devices are bridges, which 1966 * we know need special treatment. Type 2 devices are cardbus bridges 1967 * which also require special treatment. Other types are unknown, and 1968 * we err on the side of safety by ignoring them. Powering down 1969 * bridges should not be undertaken lightly. 1970 */ 1971 if (dinfo->cfg.hdrtype != 0) 1972 return; 1973 for (i = 0; i < dinfo->cfg.nummaps; i++) 1974 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1975 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1976 1977 /* 1978 * Some drivers apparently write to these registers w/o updating our 1979 * cached copy. No harm happens if we update the copy, so do so here 1980 * so we can restore them. The COMMAND register is modified by the 1981 * bus w/o updating the cache. This should represent the normally 1982 * writable portion of the 'defined' part of type 0 headers. In 1983 * theory we also need to save/restore the PCI capability structures 1984 * we know about, but apart from power we don't know any that are 1985 * writable. 1986 */ 1987 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1988 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1989 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1990 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1991 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1992 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1993 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1994 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1995 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1996 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1997 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1998 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1999 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2000 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2001 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2002 2003 /* 2004 * don't set the state for display devices, base peripherals and 2005 * memory devices since bad things happen when they are powered down. 2006 * We should (a) have drivers that can easily detach and (b) use 2007 * generic drivers for these devices so that some device actually 2008 * attaches. We need to make sure that when we implement (a) we don't 2009 * power the device down on a reattach. 2010 */ 2011 cls = pci_get_class(dev); 2012 if (!setstate) 2013 return; 2014 switch (pci_do_powerstate) 2015 { 2016 case 0: /* NO powerdown at all */ 2017 return; 2018 case 1: /* Conservative about what to power down */ 2019 if (cls == PCIC_STORAGE) 2020 return; 2021 /*FALLTHROUGH*/ 2022 case 2: /* Agressive about what to power down */ 2023 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2024 cls == PCIC_BASEPERIPH) 2025 return; 2026 /*FALLTHROUGH*/ 2027 case 3: /* Power down everything */ 2028 break; 2029 } 2030 /* 2031 * PCI spec says we can only go into D3 state from D0 state. 2032 * Transition from D[12] into D0 before going to D3 state. 2033 */ 2034 ps = pci_get_powerstate(dev); 2035 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2036 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2037 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2038 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2039 } 2040