1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #if defined(__i386__) || defined(__amd64__) 56 #include <machine/intr_machdep.h> 57 #endif 58 59 #include <sys/pciio.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pci_private.h> 63 64 #include "pcib_if.h" 65 #include "pci_if.h" 66 67 #ifdef __HAVE_ACPI 68 #include <contrib/dev/acpica/acpi.h> 69 #include "acpi_if.h" 70 #else 71 #define ACPI_PWR_FOR_SLEEP(x, y, z) 72 #endif 73 74 static uint32_t pci_mapbase(unsigned mapreg); 75 static int pci_maptype(unsigned mapreg); 76 static int pci_mapsize(unsigned testval); 77 static int pci_maprange(unsigned mapreg); 78 static void pci_fixancient(pcicfgregs *cfg); 79 80 static int pci_porten(device_t pcib, int b, int s, int f); 81 static int pci_memen(device_t pcib, int b, int s, int f); 82 static void pci_assign_interrupt(device_t bus, device_t dev, 83 int force_route); 84 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 85 int b, int s, int f, int reg, 86 struct resource_list *rl, int force, int prefetch); 87 static int pci_probe(device_t dev); 88 static int pci_attach(device_t dev); 89 static void pci_load_vendor_data(void); 90 static int pci_describe_parse_line(char **ptr, int *vendor, 91 int *device, char **desc); 92 static char *pci_describe_device(device_t dev); 93 static int pci_modevent(module_t mod, int what, void *arg); 94 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 95 pcicfgregs *cfg); 96 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 97 static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 98 int reg); 99 #if 0 100 static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 101 int reg, uint32_t data); 102 #endif 103 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 104 105 static device_method_t pci_methods[] = { 106 /* Device interface */ 107 DEVMETHOD(device_probe, pci_probe), 108 DEVMETHOD(device_attach, pci_attach), 109 DEVMETHOD(device_detach, bus_generic_detach), 110 DEVMETHOD(device_shutdown, bus_generic_shutdown), 111 DEVMETHOD(device_suspend, pci_suspend), 112 DEVMETHOD(device_resume, pci_resume), 113 114 /* Bus interface */ 115 DEVMETHOD(bus_print_child, pci_print_child), 116 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 117 DEVMETHOD(bus_read_ivar, pci_read_ivar), 118 DEVMETHOD(bus_write_ivar, pci_write_ivar), 119 DEVMETHOD(bus_driver_added, pci_driver_added), 120 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 121 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 122 123 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 124 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 125 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 126 DEVMETHOD(bus_delete_resource, pci_delete_resource), 127 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 128 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 129 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 130 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 131 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 132 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 133 134 /* PCI interface */ 135 DEVMETHOD(pci_read_config, pci_read_config_method), 136 DEVMETHOD(pci_write_config, pci_write_config_method), 137 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 138 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 139 DEVMETHOD(pci_enable_io, pci_enable_io_method), 140 DEVMETHOD(pci_disable_io, pci_disable_io_method), 141 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 142 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 143 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 144 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 145 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 146 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 147 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 148 DEVMETHOD(pci_release_msi, pci_release_msi_method), 149 DEVMETHOD(pci_msi_count, pci_msi_count_method), 150 151 { 0, 0 } 152 }; 153 154 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 155 156 static devclass_t pci_devclass; 157 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 158 MODULE_VERSION(pci, 1); 159 160 static char *pci_vendordata; 161 static size_t pci_vendordata_size; 162 163 164 struct pci_quirk { 165 uint32_t devid; /* Vendor/device of the card */ 166 int type; 167 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 168 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */ 169 int arg1; 170 int arg2; 171 }; 172 173 struct pci_quirk pci_quirks[] = { 174 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 175 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 176 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 177 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 178 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 179 180 /* 181 * MSI doesn't work with the Intel E7501 chipset, at least on 182 * the Tyan 2721 motherboard. 183 */ 184 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 185 186 { 0 } 187 }; 188 189 /* map register information */ 190 #define PCI_MAPMEM 0x01 /* memory map */ 191 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 192 #define PCI_MAPPORT 0x04 /* port map */ 193 194 struct devlist pci_devq; 195 uint32_t pci_generation; 196 uint32_t pci_numdevs = 0; 197 198 /* sysctl vars */ 199 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 200 201 static int pci_enable_io_modes = 1; 202 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 203 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 204 &pci_enable_io_modes, 1, 205 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 206 enable these bits correctly. We'd like to do this all the time, but there\n\ 207 are some peripherals that this causes problems with."); 208 209 static int pci_do_power_nodriver = 0; 210 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 211 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 212 &pci_do_power_nodriver, 0, 213 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 214 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 215 agressively place devices into D3 state. 3 means put absolutely everything\n\ 216 in D3 state."); 217 218 static int pci_do_power_resume = 1; 219 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 220 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 221 &pci_do_power_resume, 1, 222 "Transition from D3 -> D0 on resume."); 223 224 static int pci_do_msi = 1; 225 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 226 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 227 "Enable support for MSI interrupts"); 228 229 static int pci_do_msix = 1; 230 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 231 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 232 "Enable support for MSI-X interrupts"); 233 234 static int pci_honor_msi_blacklist = 1; 235 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); 236 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, 237 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI"); 238 239 /* Find a device_t by bus/slot/function */ 240 241 device_t 242 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 243 { 244 struct pci_devinfo *dinfo; 245 246 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 247 if ((dinfo->cfg.bus == bus) && 248 (dinfo->cfg.slot == slot) && 249 (dinfo->cfg.func == func)) { 250 return (dinfo->cfg.dev); 251 } 252 } 253 254 return (NULL); 255 } 256 257 /* Find a device_t by vendor/device ID */ 258 259 device_t 260 pci_find_device(uint16_t vendor, uint16_t device) 261 { 262 struct pci_devinfo *dinfo; 263 264 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 265 if ((dinfo->cfg.vendor == vendor) && 266 (dinfo->cfg.device == device)) { 267 return (dinfo->cfg.dev); 268 } 269 } 270 271 return (NULL); 272 } 273 274 /* return base address of memory or port map */ 275 276 static uint32_t 277 pci_mapbase(uint32_t mapreg) 278 { 279 int mask = 0x03; 280 if ((mapreg & 0x01) == 0) 281 mask = 0x0f; 282 return (mapreg & ~mask); 283 } 284 285 /* return map type of memory or port map */ 286 287 static int 288 pci_maptype(unsigned mapreg) 289 { 290 static uint8_t maptype[0x10] = { 291 PCI_MAPMEM, PCI_MAPPORT, 292 PCI_MAPMEM, 0, 293 PCI_MAPMEM, PCI_MAPPORT, 294 0, 0, 295 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 296 PCI_MAPMEM|PCI_MAPMEMP, 0, 297 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 298 0, 0, 299 }; 300 301 return maptype[mapreg & 0x0f]; 302 } 303 304 /* return log2 of map size decoded for memory or port map */ 305 306 static int 307 pci_mapsize(uint32_t testval) 308 { 309 int ln2size; 310 311 testval = pci_mapbase(testval); 312 ln2size = 0; 313 if (testval != 0) { 314 while ((testval & 1) == 0) 315 { 316 ln2size++; 317 testval >>= 1; 318 } 319 } 320 return (ln2size); 321 } 322 323 /* return log2 of address range supported by map register */ 324 325 static int 326 pci_maprange(unsigned mapreg) 327 { 328 int ln2range = 0; 329 switch (mapreg & 0x07) { 330 case 0x00: 331 case 0x01: 332 case 0x05: 333 ln2range = 32; 334 break; 335 case 0x02: 336 ln2range = 20; 337 break; 338 case 0x04: 339 ln2range = 64; 340 break; 341 } 342 return (ln2range); 343 } 344 345 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 346 347 static void 348 pci_fixancient(pcicfgregs *cfg) 349 { 350 if (cfg->hdrtype != 0) 351 return; 352 353 /* PCI to PCI bridges use header type 1 */ 354 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 355 cfg->hdrtype = 1; 356 } 357 358 /* extract header type specific config data */ 359 360 static void 361 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 362 { 363 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 364 switch (cfg->hdrtype) { 365 case 0: 366 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 367 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 368 cfg->nummaps = PCI_MAXMAPS_0; 369 break; 370 case 1: 371 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 372 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 373 cfg->nummaps = PCI_MAXMAPS_1; 374 break; 375 case 2: 376 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 377 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 378 cfg->nummaps = PCI_MAXMAPS_2; 379 break; 380 } 381 #undef REG 382 } 383 384 /* read configuration header into pcicfgregs structure */ 385 struct pci_devinfo * 386 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 387 { 388 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 389 pcicfgregs *cfg = NULL; 390 struct pci_devinfo *devlist_entry; 391 struct devlist *devlist_head; 392 393 devlist_head = &pci_devq; 394 395 devlist_entry = NULL; 396 397 if (REG(PCIR_DEVVENDOR, 4) != -1) { 398 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 399 if (devlist_entry == NULL) 400 return (NULL); 401 402 cfg = &devlist_entry->cfg; 403 404 cfg->bus = b; 405 cfg->slot = s; 406 cfg->func = f; 407 cfg->vendor = REG(PCIR_VENDOR, 2); 408 cfg->device = REG(PCIR_DEVICE, 2); 409 cfg->cmdreg = REG(PCIR_COMMAND, 2); 410 cfg->statreg = REG(PCIR_STATUS, 2); 411 cfg->baseclass = REG(PCIR_CLASS, 1); 412 cfg->subclass = REG(PCIR_SUBCLASS, 1); 413 cfg->progif = REG(PCIR_PROGIF, 1); 414 cfg->revid = REG(PCIR_REVID, 1); 415 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 416 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 417 cfg->lattimer = REG(PCIR_LATTIMER, 1); 418 cfg->intpin = REG(PCIR_INTPIN, 1); 419 cfg->intline = REG(PCIR_INTLINE, 1); 420 421 cfg->mingnt = REG(PCIR_MINGNT, 1); 422 cfg->maxlat = REG(PCIR_MAXLAT, 1); 423 424 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 425 cfg->hdrtype &= ~PCIM_MFDEV; 426 427 pci_fixancient(cfg); 428 pci_hdrtypedata(pcib, b, s, f, cfg); 429 430 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 431 pci_read_extcap(pcib, cfg); 432 433 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 434 435 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 436 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 437 devlist_entry->conf.pc_sel.pc_func = cfg->func; 438 devlist_entry->conf.pc_hdr = cfg->hdrtype; 439 440 devlist_entry->conf.pc_subvendor = cfg->subvendor; 441 devlist_entry->conf.pc_subdevice = cfg->subdevice; 442 devlist_entry->conf.pc_vendor = cfg->vendor; 443 devlist_entry->conf.pc_device = cfg->device; 444 445 devlist_entry->conf.pc_class = cfg->baseclass; 446 devlist_entry->conf.pc_subclass = cfg->subclass; 447 devlist_entry->conf.pc_progif = cfg->progif; 448 devlist_entry->conf.pc_revid = cfg->revid; 449 450 pci_numdevs++; 451 pci_generation++; 452 } 453 return (devlist_entry); 454 #undef REG 455 } 456 457 static void 458 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 459 { 460 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 461 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 462 #if defined(__i386__) || defined(__amd64__) 463 uint64_t addr; 464 #endif 465 uint32_t val; 466 int ptr, nextptr, ptrptr; 467 468 switch (cfg->hdrtype & PCIM_HDRTYPE) { 469 case 0: 470 case 1: 471 ptrptr = PCIR_CAP_PTR; 472 break; 473 case 2: 474 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 475 break; 476 default: 477 return; /* no extended capabilities support */ 478 } 479 nextptr = REG(ptrptr, 1); /* sanity check? */ 480 481 /* 482 * Read capability entries. 483 */ 484 while (nextptr != 0) { 485 /* Sanity check */ 486 if (nextptr > 255) { 487 printf("illegal PCI extended capability offset %d\n", 488 nextptr); 489 return; 490 } 491 /* Find the next entry */ 492 ptr = nextptr; 493 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 494 495 /* Process this entry */ 496 switch (REG(ptr + PCICAP_ID, 1)) { 497 case PCIY_PMG: /* PCI power management */ 498 if (cfg->pp.pp_cap == 0) { 499 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 500 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 501 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 502 if ((nextptr - ptr) > PCIR_POWER_DATA) 503 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 504 } 505 break; 506 #if defined(__i386__) || defined(__amd64__) 507 case PCIY_HT: /* HyperTransport */ 508 /* Determine HT-specific capability type. */ 509 val = REG(ptr + PCIR_HT_COMMAND, 2); 510 switch (val & PCIM_HTCMD_CAP_MASK) { 511 case PCIM_HTCAP_MSI_MAPPING: 512 /* Sanity check the mapping window. */ 513 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4); 514 addr <<= 32; 515 addr = REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4); 516 if (addr != MSI_INTEL_ADDR_BASE) 517 device_printf(pcib, 518 "HT Bridge at %d:%d:%d has non-default MSI window 0x%llx\n", 519 cfg->bus, cfg->slot, cfg->func, 520 (long long)addr); 521 522 /* Enable MSI -> HT mapping. */ 523 val |= PCIM_HTCMD_MSI_ENABLE; 524 WREG(ptr + PCIR_HT_COMMAND, val, 2); 525 break; 526 } 527 break; 528 #endif 529 case PCIY_MSI: /* PCI MSI */ 530 cfg->msi.msi_location = ptr; 531 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 532 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 533 PCIM_MSICTRL_MMC_MASK)>>1); 534 break; 535 case PCIY_MSIX: /* PCI MSI-X */ 536 cfg->msix.msix_location = ptr; 537 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 538 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 539 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 540 val = REG(ptr + PCIR_MSIX_TABLE, 4); 541 cfg->msix.msix_table_bar = PCIR_BAR(val & 542 PCIM_MSIX_BIR_MASK); 543 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 544 val = REG(ptr + PCIR_MSIX_PBA, 4); 545 cfg->msix.msix_pba_bar = PCIR_BAR(val & 546 PCIM_MSIX_BIR_MASK); 547 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 548 break; 549 case PCIY_VPD: /* PCI Vital Product Data */ 550 cfg->vpd.vpd_reg = ptr; 551 pci_read_vpd(pcib, cfg); 552 break; 553 default: 554 break; 555 } 556 } 557 /* REG and WREG use carry through to next functions */ 558 } 559 560 /* 561 * PCI Vital Product Data 562 */ 563 static uint32_t 564 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 565 { 566 567 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 568 569 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 570 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 571 DELAY(1); /* limit looping */ 572 573 return REG(cfg->vpd.vpd_reg + 4, 4); 574 } 575 576 #if 0 577 static void 578 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 579 { 580 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 581 582 WREG(cfg->vpd.vpd_reg + 4, data, 4); 583 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 584 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 585 DELAY(1); /* limit looping */ 586 587 return; 588 } 589 #endif 590 591 struct vpd_readstate { 592 device_t pcib; 593 pcicfgregs *cfg; 594 uint32_t val; 595 int bytesinval; 596 int off; 597 uint8_t cksum; 598 }; 599 600 static uint8_t 601 vpd_nextbyte(struct vpd_readstate *vrs) 602 { 603 uint8_t byte; 604 605 if (vrs->bytesinval == 0) { 606 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 607 vrs->off)); 608 vrs->off += 4; 609 byte = vrs->val & 0xff; 610 vrs->bytesinval = 3; 611 } else { 612 vrs->val = vrs->val >> 8; 613 byte = vrs->val & 0xff; 614 vrs->bytesinval--; 615 } 616 617 vrs->cksum += byte; 618 return byte; 619 } 620 621 static void 622 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 623 { 624 struct vpd_readstate vrs; 625 int state; 626 int name; 627 int remain; 628 int end; 629 int i; 630 uint8_t byte; 631 int alloc, off; /* alloc/off for RO/W arrays */ 632 int cksumvalid; 633 int dflen; 634 635 /* init vpd reader */ 636 vrs.bytesinval = 0; 637 vrs.off = 0; 638 vrs.pcib = pcib; 639 vrs.cfg = cfg; 640 vrs.cksum = 0; 641 642 state = 0; 643 name = remain = i = 0; /* shut up stupid gcc */ 644 alloc = off = 0; /* shut up stupid gcc */ 645 dflen = 0; /* shut up stupid gcc */ 646 end = 0; 647 cksumvalid = -1; 648 for (; !end;) { 649 byte = vpd_nextbyte(&vrs); 650 #if 0 651 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 652 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 653 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 654 #endif 655 switch (state) { 656 case 0: /* item name */ 657 if (byte & 0x80) { 658 remain = vpd_nextbyte(&vrs); 659 remain |= vpd_nextbyte(&vrs) << 8; 660 if (remain > (0x7f*4 - vrs.off)) { 661 end = 1; 662 printf( 663 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 664 cfg->bus, cfg->slot, cfg->func, 665 remain); 666 } 667 name = byte & 0x7f; 668 } else { 669 remain = byte & 0x7; 670 name = (byte >> 3) & 0xf; 671 } 672 switch (name) { 673 case 0x2: /* String */ 674 cfg->vpd.vpd_ident = malloc(remain + 1, 675 M_DEVBUF, M_WAITOK); 676 i = 0; 677 state = 1; 678 break; 679 case 0xf: /* End */ 680 end = 1; 681 state = -1; 682 break; 683 case 0x10: /* VPD-R */ 684 alloc = 8; 685 off = 0; 686 cfg->vpd.vpd_ros = malloc(alloc * 687 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 688 M_WAITOK); 689 state = 2; 690 break; 691 case 0x11: /* VPD-W */ 692 alloc = 8; 693 off = 0; 694 cfg->vpd.vpd_w = malloc(alloc * 695 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 696 M_WAITOK); 697 state = 5; 698 break; 699 default: /* Invalid data, abort */ 700 end = 1; 701 continue; 702 } 703 break; 704 705 case 1: /* Identifier String */ 706 cfg->vpd.vpd_ident[i++] = byte; 707 remain--; 708 if (remain == 0) { 709 cfg->vpd.vpd_ident[i] = '\0'; 710 state = 0; 711 } 712 break; 713 714 case 2: /* VPD-R Keyword Header */ 715 if (off == alloc) { 716 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 717 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 718 M_DEVBUF, M_WAITOK); 719 } 720 cfg->vpd.vpd_ros[off].keyword[0] = byte; 721 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 722 dflen = vpd_nextbyte(&vrs); 723 if (dflen == 0 && 724 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 725 2) == 0) { 726 /* 727 * if this happens, we can't trust the rest 728 * of the VPD. 729 */ 730 printf("pci%d:%d:%d: bad keyword length: %d\n", 731 cfg->bus, cfg->slot, cfg->func, dflen); 732 cksumvalid = 0; 733 end = 1; 734 break; 735 } else if (dflen == 0) { 736 cfg->vpd.vpd_ros[off].value = malloc(1 * 737 sizeof *cfg->vpd.vpd_ros[off].value, 738 M_DEVBUF, M_WAITOK); 739 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 740 } else 741 cfg->vpd.vpd_ros[off].value = malloc( 742 (dflen + 1) * 743 sizeof *cfg->vpd.vpd_ros[off].value, 744 M_DEVBUF, M_WAITOK); 745 remain -= 3; 746 i = 0; 747 /* keep in sync w/ state 3's transistions */ 748 if (dflen == 0 && remain == 0) 749 state = 0; 750 else if (dflen == 0) 751 state = 2; 752 else 753 state = 3; 754 break; 755 756 case 3: /* VPD-R Keyword Value */ 757 cfg->vpd.vpd_ros[off].value[i++] = byte; 758 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 759 "RV", 2) == 0 && cksumvalid == -1) { 760 if (vrs.cksum == 0) 761 cksumvalid = 1; 762 else { 763 printf( 764 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 765 cfg->bus, cfg->slot, cfg->func, 766 vrs.cksum); 767 cksumvalid = 0; 768 end = 1; 769 break; 770 } 771 } 772 dflen--; 773 remain--; 774 /* keep in sync w/ state 2's transistions */ 775 if (dflen == 0) 776 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 777 if (dflen == 0 && remain == 0) { 778 cfg->vpd.vpd_rocnt = off; 779 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 780 off * sizeof *cfg->vpd.vpd_ros, 781 M_DEVBUF, M_WAITOK); 782 state = 0; 783 } else if (dflen == 0) 784 state = 2; 785 break; 786 787 case 4: 788 remain--; 789 if (remain == 0) 790 state = 0; 791 break; 792 793 case 5: /* VPD-W Keyword Header */ 794 if (off == alloc) { 795 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 796 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 797 M_DEVBUF, M_WAITOK); 798 } 799 cfg->vpd.vpd_w[off].keyword[0] = byte; 800 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 801 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 802 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 803 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 804 sizeof *cfg->vpd.vpd_w[off].value, 805 M_DEVBUF, M_WAITOK); 806 remain -= 3; 807 i = 0; 808 /* keep in sync w/ state 6's transistions */ 809 if (dflen == 0 && remain == 0) 810 state = 0; 811 else if (dflen == 0) 812 state = 5; 813 else 814 state = 6; 815 break; 816 817 case 6: /* VPD-W Keyword Value */ 818 cfg->vpd.vpd_w[off].value[i++] = byte; 819 dflen--; 820 remain--; 821 /* keep in sync w/ state 5's transistions */ 822 if (dflen == 0) 823 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 824 if (dflen == 0 && remain == 0) { 825 cfg->vpd.vpd_wcnt = off; 826 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 827 off * sizeof *cfg->vpd.vpd_w, 828 M_DEVBUF, M_WAITOK); 829 state = 0; 830 } else if (dflen == 0) 831 state = 5; 832 break; 833 834 default: 835 printf("pci%d:%d:%d: invalid state: %d\n", 836 cfg->bus, cfg->slot, cfg->func, state); 837 end = 1; 838 break; 839 } 840 } 841 842 if (cksumvalid == 0) { 843 /* read-only data bad, clean up */ 844 for (; off; off--) 845 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 846 847 free(cfg->vpd.vpd_ros, M_DEVBUF); 848 cfg->vpd.vpd_ros = NULL; 849 } 850 #undef REG 851 #undef WREG 852 } 853 854 int 855 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 856 { 857 struct pci_devinfo *dinfo = device_get_ivars(child); 858 pcicfgregs *cfg = &dinfo->cfg; 859 860 *identptr = cfg->vpd.vpd_ident; 861 862 if (*identptr == NULL) 863 return ENXIO; 864 865 return 0; 866 } 867 868 int 869 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 870 const char **vptr) 871 { 872 struct pci_devinfo *dinfo = device_get_ivars(child); 873 pcicfgregs *cfg = &dinfo->cfg; 874 int i; 875 876 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 877 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 878 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 879 *vptr = cfg->vpd.vpd_ros[i].value; 880 } 881 882 if (i != cfg->vpd.vpd_rocnt) 883 return 0; 884 885 *vptr = NULL; 886 return ENXIO; 887 } 888 889 /* 890 * Return the offset in configuration space of the requested extended 891 * capability entry or 0 if the specified capability was not found. 892 */ 893 int 894 pci_find_extcap_method(device_t dev, device_t child, int capability, 895 int *capreg) 896 { 897 struct pci_devinfo *dinfo = device_get_ivars(child); 898 pcicfgregs *cfg = &dinfo->cfg; 899 u_int32_t status; 900 u_int8_t ptr; 901 902 /* 903 * Check the CAP_LIST bit of the PCI status register first. 904 */ 905 status = pci_read_config(child, PCIR_STATUS, 2); 906 if (!(status & PCIM_STATUS_CAPPRESENT)) 907 return (ENXIO); 908 909 /* 910 * Determine the start pointer of the capabilities list. 911 */ 912 switch (cfg->hdrtype & PCIM_HDRTYPE) { 913 case 0: 914 case 1: 915 ptr = PCIR_CAP_PTR; 916 break; 917 case 2: 918 ptr = PCIR_CAP_PTR_2; 919 break; 920 default: 921 /* XXX: panic? */ 922 return (ENXIO); /* no extended capabilities support */ 923 } 924 ptr = pci_read_config(child, ptr, 1); 925 926 /* 927 * Traverse the capabilities list. 928 */ 929 while (ptr != 0) { 930 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 931 if (capreg != NULL) 932 *capreg = ptr; 933 return (0); 934 } 935 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 936 } 937 938 return (ENOENT); 939 } 940 941 /* 942 * Support for MSI-X message interrupts. 943 */ 944 void 945 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 946 { 947 struct pci_devinfo *dinfo = device_get_ivars(dev); 948 pcicfgregs *cfg = &dinfo->cfg; 949 uint32_t offset; 950 951 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 952 offset = cfg->msix.msix_table_offset + index * 16; 953 bus_write_4(cfg->msix.msix_table_res, offset, address & 0xffffffff); 954 bus_write_4(cfg->msix.msix_table_res, offset + 4, address >> 32); 955 bus_write_4(cfg->msix.msix_table_res, offset + 8, data); 956 } 957 958 void 959 pci_mask_msix(device_t dev, u_int index) 960 { 961 struct pci_devinfo *dinfo = device_get_ivars(dev); 962 pcicfgregs *cfg = &dinfo->cfg; 963 uint32_t offset, val; 964 965 KASSERT(cfg->msix.msix_msgnum > index, ("bogus index")); 966 offset = cfg->msix.msix_table_offset + index * 16 + 12; 967 val = bus_read_4(cfg->msix.msix_table_res, offset); 968 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 969 val |= PCIM_MSIX_VCTRL_MASK; 970 bus_write_4(cfg->msix.msix_table_res, offset, val); 971 } 972 } 973 974 void 975 pci_unmask_msix(device_t dev, u_int index) 976 { 977 struct pci_devinfo *dinfo = device_get_ivars(dev); 978 pcicfgregs *cfg = &dinfo->cfg; 979 uint32_t offset, val; 980 981 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 982 offset = cfg->msix.msix_table_offset + index * 16 + 12; 983 val = bus_read_4(cfg->msix.msix_table_res, offset); 984 if (val & PCIM_MSIX_VCTRL_MASK) { 985 val &= ~PCIM_MSIX_VCTRL_MASK; 986 bus_write_4(cfg->msix.msix_table_res, offset, val); 987 } 988 } 989 990 int 991 pci_pending_msix(device_t dev, u_int index) 992 { 993 struct pci_devinfo *dinfo = device_get_ivars(dev); 994 pcicfgregs *cfg = &dinfo->cfg; 995 uint32_t offset, bit; 996 997 KASSERT(cfg->msix.msix_alloc > index, ("bogus index")); 998 offset = cfg->msix.msix_pba_offset + (index / 4) * 4; 999 bit = 1 << index % 32; 1000 return (bus_read_4(cfg->msix.msix_pba_res, offset) & bit); 1001 } 1002 1003 static int 1004 pci_alloc_msix(device_t dev, device_t child, int *count) 1005 { 1006 struct pci_devinfo *dinfo = device_get_ivars(child); 1007 pcicfgregs *cfg = &dinfo->cfg; 1008 struct resource_list_entry *rle; 1009 int actual, error, i, irq, max; 1010 1011 /* MSI-X capability present? */ 1012 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1013 return (ENODEV); 1014 1015 /* Make sure the appropriate BARs are mapped. */ 1016 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1017 cfg->msix.msix_table_bar); 1018 if (rle == NULL || rle->res == NULL || 1019 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1020 return (ENXIO); 1021 cfg->msix.msix_table_res = rle->res; 1022 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1023 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1024 cfg->msix.msix_pba_bar); 1025 if (rle == NULL || rle->res == NULL || 1026 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1027 return (ENXIO); 1028 } 1029 cfg->msix.msix_pba_res = rle->res; 1030 1031 /* Already have allocated messages? */ 1032 if (cfg->msix.msix_alloc != 0) 1033 return (ENXIO); 1034 1035 if (bootverbose) 1036 device_printf(child, 1037 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1038 *count, cfg->msix.msix_msgnum); 1039 max = min(*count, cfg->msix.msix_msgnum); 1040 for (i = 0; i < max; i++) { 1041 /* Allocate a message. */ 1042 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, i, 1043 &irq); 1044 if (error) 1045 break; 1046 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1047 irq, 1); 1048 } 1049 actual = i; 1050 1051 if (bootverbose) { 1052 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1053 if (actual == 1) 1054 device_printf(child, "using IRQ %lu for MSI-X\n", 1055 rle->start); 1056 else { 1057 int run; 1058 1059 /* 1060 * Be fancy and try to print contiguous runs of 1061 * IRQ values as ranges. 'irq' is the previous IRQ. 1062 * 'run' is true if we are in a range. 1063 */ 1064 device_printf(child, "using IRQs %lu", rle->start); 1065 irq = rle->start; 1066 run = 0; 1067 for (i = 1; i < actual; i++) { 1068 rle = resource_list_find(&dinfo->resources, 1069 SYS_RES_IRQ, i + 1); 1070 1071 /* Still in a run? */ 1072 if (rle->start == irq + 1) { 1073 run = 1; 1074 irq++; 1075 continue; 1076 } 1077 1078 /* Finish previous range. */ 1079 if (run) { 1080 printf("-%d", irq); 1081 run = 0; 1082 } 1083 1084 /* Start new range. */ 1085 printf(",%lu", rle->start); 1086 irq = rle->start; 1087 } 1088 1089 /* Unfinished range? */ 1090 if (run) 1091 printf("%d", irq); 1092 printf(" for MSI-X\n"); 1093 } 1094 } 1095 1096 /* Mask all vectors. */ 1097 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1098 pci_mask_msix(child, i); 1099 1100 /* Update control register to enable MSI-X. */ 1101 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1102 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1103 cfg->msix.msix_ctrl, 2); 1104 1105 /* Update counts of alloc'd messages. */ 1106 cfg->msix.msix_alloc = actual; 1107 *count = actual; 1108 return (0); 1109 } 1110 1111 static int 1112 pci_release_msix(device_t dev, device_t child) 1113 { 1114 struct pci_devinfo *dinfo = device_get_ivars(child); 1115 pcicfgregs *cfg = &dinfo->cfg; 1116 struct resource_list_entry *rle; 1117 int i; 1118 1119 /* Do we have any messages to release? */ 1120 if (cfg->msix.msix_alloc == 0) 1121 return (ENODEV); 1122 1123 /* Make sure none of the resources are allocated. */ 1124 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1125 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1126 KASSERT(rle != NULL, ("missing MSI resource")); 1127 if (rle->res != NULL) 1128 return (EBUSY); 1129 } 1130 1131 /* Update control register with to disable MSI-X. */ 1132 cfg->msix.msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1133 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1134 cfg->msix.msix_ctrl, 2); 1135 1136 /* Release the messages. */ 1137 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1138 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1139 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1140 rle->start); 1141 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1142 } 1143 1144 /* Update alloc count. */ 1145 cfg->msix.msix_alloc = 0; 1146 return (0); 1147 } 1148 1149 /* 1150 * Support for MSI message signalled interrupts. 1151 */ 1152 void 1153 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1154 { 1155 struct pci_devinfo *dinfo = device_get_ivars(dev); 1156 pcicfgregs *cfg = &dinfo->cfg; 1157 1158 /* Write data and address values. */ 1159 cfg->msi.msi_addr = address; 1160 cfg->msi.msi_data = data; 1161 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1162 address & 0xffffffff, 4); 1163 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1164 pci_write_config(dev, cfg->msi.msi_location + 1165 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1166 pci_write_config(dev, cfg->msi.msi_location + 1167 PCIR_MSI_DATA_64BIT, data, 2); 1168 } else 1169 pci_write_config(dev, cfg->msi.msi_location + 1170 PCIR_MSI_DATA, data, 2); 1171 1172 /* Enable MSI in the control register. */ 1173 cfg->msi.msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1174 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1175 cfg->msi.msi_ctrl, 2); 1176 } 1177 1178 /* 1179 * Restore MSI registers during resume. If MSI is enabled then 1180 * restore the data and address registers in addition to the control 1181 * register. 1182 */ 1183 static void 1184 pci_resume_msi(device_t dev) 1185 { 1186 struct pci_devinfo *dinfo = device_get_ivars(dev); 1187 pcicfgregs *cfg = &dinfo->cfg; 1188 uint64_t address; 1189 uint16_t data; 1190 1191 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1192 address = cfg->msi.msi_addr; 1193 data = cfg->msi.msi_data; 1194 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR, 1195 address & 0xffffffff, 4); 1196 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) { 1197 pci_write_config(dev, cfg->msi.msi_location + 1198 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1199 pci_write_config(dev, cfg->msi.msi_location + 1200 PCIR_MSI_DATA_64BIT, data, 2); 1201 } else 1202 pci_write_config(dev, cfg->msi.msi_location + 1203 PCIR_MSI_DATA, data, 2); 1204 } 1205 pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL, 1206 cfg->msi.msi_ctrl, 2); 1207 } 1208 1209 /* 1210 * Returns true if the specified device is blacklisted because MSI 1211 * doesn't work. 1212 */ 1213 int 1214 pci_msi_device_blacklisted(device_t dev) 1215 { 1216 struct pci_quirk *q; 1217 1218 if (!pci_honor_msi_blacklist) 1219 return (0); 1220 1221 for (q = &pci_quirks[0]; q->devid; q++) { 1222 if (q->devid == pci_get_devid(dev) && 1223 q->type == PCI_QUIRK_DISABLE_MSI) 1224 return (1); 1225 } 1226 return (0); 1227 } 1228 1229 /* 1230 * Determine if MSI is blacklisted globally on this sytem. Currently, 1231 * we just check for blacklisted chipsets as represented by the 1232 * host-PCI bridge at device 0:0:0. In the future, it may become 1233 * necessary to check other system attributes, such as the kenv values 1234 * that give the motherboard manufacturer and model number. 1235 */ 1236 static int 1237 pci_msi_blacklisted(void) 1238 { 1239 device_t dev; 1240 1241 if (!pci_honor_msi_blacklist) 1242 return (0); 1243 1244 dev = pci_find_bsf(0, 0, 0); 1245 if (dev != NULL) 1246 return (pci_msi_device_blacklisted(dev)); 1247 return (0); 1248 } 1249 1250 /* 1251 * Attempt to allocate *count MSI messages. The actual number allocated is 1252 * returned in *count. After this function returns, each message will be 1253 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1254 */ 1255 int 1256 pci_alloc_msi_method(device_t dev, device_t child, int *count) 1257 { 1258 struct pci_devinfo *dinfo = device_get_ivars(child); 1259 pcicfgregs *cfg = &dinfo->cfg; 1260 struct resource_list_entry *rle; 1261 int actual, error, i, irqs[32]; 1262 uint16_t ctrl; 1263 1264 /* Don't let count == 0 get us into trouble. */ 1265 if (*count == 0) 1266 return (EINVAL); 1267 1268 /* If rid 0 is allocated, then fail. */ 1269 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1270 if (rle != NULL && rle->res != NULL) 1271 return (ENXIO); 1272 1273 /* If MSI is blacklisted for this system, fail. */ 1274 if (pci_msi_blacklisted()) 1275 return (ENXIO); 1276 1277 /* Try MSI-X first. */ 1278 error = pci_alloc_msix(dev, child, count); 1279 if (error != ENODEV) 1280 return (error); 1281 1282 /* MSI capability present? */ 1283 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1284 return (ENODEV); 1285 1286 /* Already have allocated messages? */ 1287 if (cfg->msi.msi_alloc != 0) 1288 return (ENXIO); 1289 1290 if (bootverbose) 1291 device_printf(child, 1292 "attempting to allocate %d MSI vectors (%d supported)\n", 1293 *count, cfg->msi.msi_msgnum); 1294 1295 /* Don't ask for more than the device supports. */ 1296 actual = min(*count, cfg->msi.msi_msgnum); 1297 1298 /* Don't ask for more than 32 messages. */ 1299 actual = min(actual, 32); 1300 1301 /* MSI requires power of 2 number of messages. */ 1302 if (!powerof2(actual)) 1303 return (EINVAL); 1304 1305 for (;;) { 1306 /* Try to allocate N messages. */ 1307 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1308 cfg->msi.msi_msgnum, irqs); 1309 if (error == 0) 1310 break; 1311 if (actual == 1) 1312 return (error); 1313 1314 /* Try N / 2. */ 1315 actual >>= 1; 1316 } 1317 1318 /* 1319 * We now have N actual messages mapped onto SYS_RES_IRQ 1320 * resources in the irqs[] array, so add new resources 1321 * starting at rid 1. 1322 */ 1323 for (i = 0; i < actual; i++) 1324 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1325 irqs[i], irqs[i], 1); 1326 1327 if (bootverbose) { 1328 if (actual == 1) 1329 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 1330 else { 1331 int run; 1332 1333 /* 1334 * Be fancy and try to print contiguous runs 1335 * of IRQ values as ranges. 'run' is true if 1336 * we are in a range. 1337 */ 1338 device_printf(child, "using IRQs %d", irqs[0]); 1339 run = 0; 1340 for (i = 1; i < actual; i++) { 1341 1342 /* Still in a run? */ 1343 if (irqs[i] == irqs[i - 1] + 1) { 1344 run = 1; 1345 continue; 1346 } 1347 1348 /* Finish previous range. */ 1349 if (run) { 1350 printf("-%d", irqs[i - 1]); 1351 run = 0; 1352 } 1353 1354 /* Start new range. */ 1355 printf(",%d", irqs[i]); 1356 } 1357 1358 /* Unfinished range? */ 1359 if (run) 1360 printf("%d", irqs[actual - 1]); 1361 printf(" for MSI\n"); 1362 } 1363 } 1364 1365 /* Update control register with actual count and enable MSI. */ 1366 ctrl = cfg->msi.msi_ctrl; 1367 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1368 ctrl |= (ffs(actual) - 1) << 4; 1369 cfg->msi.msi_ctrl = ctrl; 1370 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1371 1372 /* Update counts of alloc'd messages. */ 1373 cfg->msi.msi_alloc = actual; 1374 *count = actual; 1375 return (0); 1376 } 1377 1378 /* Release the MSI messages associated with this device. */ 1379 int 1380 pci_release_msi_method(device_t dev, device_t child) 1381 { 1382 struct pci_devinfo *dinfo = device_get_ivars(child); 1383 pcicfgregs *cfg = &dinfo->cfg; 1384 struct resource_list_entry *rle; 1385 int error, i, irqs[32]; 1386 1387 /* Try MSI-X first. */ 1388 error = pci_release_msix(dev, child); 1389 if (error != ENODEV) 1390 return (error); 1391 1392 /* Do we have any messages to release? */ 1393 if (cfg->msi.msi_alloc == 0) 1394 return (ENODEV); 1395 KASSERT(cfg->msi.msi_alloc <= 32, ("more than 32 alloc'd messages")); 1396 1397 /* Make sure none of the resources are allocated. */ 1398 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1399 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1400 KASSERT(rle != NULL, ("missing MSI resource")); 1401 if (rle->res != NULL) 1402 return (EBUSY); 1403 irqs[i] = rle->start; 1404 } 1405 1406 /* Update control register with 0 count and disable MSI. */ 1407 cfg->msi.msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE); 1408 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 1409 cfg->msi.msi_ctrl, 2); 1410 1411 /* Release the messages. */ 1412 PCIB_RELEASE_MSI(device_get_parent(dev), child, cfg->msi.msi_alloc, 1413 irqs); 1414 for (i = 0; i < cfg->msi.msi_alloc; i++) 1415 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1416 1417 /* Update alloc count. */ 1418 cfg->msi.msi_alloc = 0; 1419 return (0); 1420 } 1421 1422 /* 1423 * Return the max supported MSI or MSI-X messages this device supports. 1424 * Basically, assuming the MD code can alloc messages, this function 1425 * should return the maximum value that pci_alloc_msi() can return. Thus, 1426 * it is subject to the tunables, etc. 1427 */ 1428 int 1429 pci_msi_count_method(device_t dev, device_t child) 1430 { 1431 struct pci_devinfo *dinfo = device_get_ivars(child); 1432 pcicfgregs *cfg = &dinfo->cfg; 1433 1434 if (pci_do_msix && cfg->msix.msix_location != 0) 1435 return (cfg->msix.msix_msgnum); 1436 if (pci_do_msi && cfg->msi.msi_location != 0) 1437 return (cfg->msi.msi_msgnum); 1438 return (0); 1439 } 1440 1441 /* free pcicfgregs structure and all depending data structures */ 1442 1443 int 1444 pci_freecfg(struct pci_devinfo *dinfo) 1445 { 1446 struct devlist *devlist_head; 1447 int i; 1448 1449 devlist_head = &pci_devq; 1450 1451 if (dinfo->cfg.vpd.vpd_reg) { 1452 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 1453 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 1454 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 1455 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 1456 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 1457 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 1458 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 1459 } 1460 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 1461 free(dinfo, M_DEVBUF); 1462 1463 /* increment the generation count */ 1464 pci_generation++; 1465 1466 /* we're losing one device */ 1467 pci_numdevs--; 1468 return (0); 1469 } 1470 1471 /* 1472 * PCI power manangement 1473 */ 1474 int 1475 pci_set_powerstate_method(device_t dev, device_t child, int state) 1476 { 1477 struct pci_devinfo *dinfo = device_get_ivars(child); 1478 pcicfgregs *cfg = &dinfo->cfg; 1479 uint16_t status; 1480 int result, oldstate, highest, delay; 1481 1482 if (cfg->pp.pp_cap == 0) 1483 return (EOPNOTSUPP); 1484 1485 /* 1486 * Optimize a no state change request away. While it would be OK to 1487 * write to the hardware in theory, some devices have shown odd 1488 * behavior when going from D3 -> D3. 1489 */ 1490 oldstate = pci_get_powerstate(child); 1491 if (oldstate == state) 1492 return (0); 1493 1494 /* 1495 * The PCI power management specification states that after a state 1496 * transition between PCI power states, system software must 1497 * guarantee a minimal delay before the function accesses the device. 1498 * Compute the worst case delay that we need to guarantee before we 1499 * access the device. Many devices will be responsive much more 1500 * quickly than this delay, but there are some that don't respond 1501 * instantly to state changes. Transitions to/from D3 state require 1502 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 1503 * is done below with DELAY rather than a sleeper function because 1504 * this function can be called from contexts where we cannot sleep. 1505 */ 1506 highest = (oldstate > state) ? oldstate : state; 1507 if (highest == PCI_POWERSTATE_D3) 1508 delay = 10000; 1509 else if (highest == PCI_POWERSTATE_D2) 1510 delay = 200; 1511 else 1512 delay = 0; 1513 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 1514 & ~PCIM_PSTAT_DMASK; 1515 result = 0; 1516 switch (state) { 1517 case PCI_POWERSTATE_D0: 1518 status |= PCIM_PSTAT_D0; 1519 break; 1520 case PCI_POWERSTATE_D1: 1521 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 1522 return (EOPNOTSUPP); 1523 status |= PCIM_PSTAT_D1; 1524 break; 1525 case PCI_POWERSTATE_D2: 1526 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 1527 return (EOPNOTSUPP); 1528 status |= PCIM_PSTAT_D2; 1529 break; 1530 case PCI_POWERSTATE_D3: 1531 status |= PCIM_PSTAT_D3; 1532 break; 1533 default: 1534 return (EINVAL); 1535 } 1536 1537 if (bootverbose) 1538 printf( 1539 "pci%d:%d:%d: Transition from D%d to D%d\n", 1540 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1541 oldstate, state); 1542 1543 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 1544 if (delay) 1545 DELAY(delay); 1546 return (0); 1547 } 1548 1549 int 1550 pci_get_powerstate_method(device_t dev, device_t child) 1551 { 1552 struct pci_devinfo *dinfo = device_get_ivars(child); 1553 pcicfgregs *cfg = &dinfo->cfg; 1554 uint16_t status; 1555 int result; 1556 1557 if (cfg->pp.pp_cap != 0) { 1558 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 1559 switch (status & PCIM_PSTAT_DMASK) { 1560 case PCIM_PSTAT_D0: 1561 result = PCI_POWERSTATE_D0; 1562 break; 1563 case PCIM_PSTAT_D1: 1564 result = PCI_POWERSTATE_D1; 1565 break; 1566 case PCIM_PSTAT_D2: 1567 result = PCI_POWERSTATE_D2; 1568 break; 1569 case PCIM_PSTAT_D3: 1570 result = PCI_POWERSTATE_D3; 1571 break; 1572 default: 1573 result = PCI_POWERSTATE_UNKNOWN; 1574 break; 1575 } 1576 } else { 1577 /* No support, device is always at D0 */ 1578 result = PCI_POWERSTATE_D0; 1579 } 1580 return (result); 1581 } 1582 1583 /* 1584 * Some convenience functions for PCI device drivers. 1585 */ 1586 1587 static __inline void 1588 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1589 { 1590 uint16_t command; 1591 1592 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1593 command |= bit; 1594 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1595 } 1596 1597 static __inline void 1598 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1599 { 1600 uint16_t command; 1601 1602 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1603 command &= ~bit; 1604 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1605 } 1606 1607 int 1608 pci_enable_busmaster_method(device_t dev, device_t child) 1609 { 1610 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1611 return (0); 1612 } 1613 1614 int 1615 pci_disable_busmaster_method(device_t dev, device_t child) 1616 { 1617 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1618 return (0); 1619 } 1620 1621 int 1622 pci_enable_io_method(device_t dev, device_t child, int space) 1623 { 1624 uint16_t command; 1625 uint16_t bit; 1626 char *error; 1627 1628 bit = 0; 1629 error = NULL; 1630 1631 switch(space) { 1632 case SYS_RES_IOPORT: 1633 bit = PCIM_CMD_PORTEN; 1634 error = "port"; 1635 break; 1636 case SYS_RES_MEMORY: 1637 bit = PCIM_CMD_MEMEN; 1638 error = "memory"; 1639 break; 1640 default: 1641 return (EINVAL); 1642 } 1643 pci_set_command_bit(dev, child, bit); 1644 /* Some devices seem to need a brief stall here, what do to? */ 1645 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1646 if (command & bit) 1647 return (0); 1648 device_printf(child, "failed to enable %s mapping!\n", error); 1649 return (ENXIO); 1650 } 1651 1652 int 1653 pci_disable_io_method(device_t dev, device_t child, int space) 1654 { 1655 uint16_t command; 1656 uint16_t bit; 1657 char *error; 1658 1659 bit = 0; 1660 error = NULL; 1661 1662 switch(space) { 1663 case SYS_RES_IOPORT: 1664 bit = PCIM_CMD_PORTEN; 1665 error = "port"; 1666 break; 1667 case SYS_RES_MEMORY: 1668 bit = PCIM_CMD_MEMEN; 1669 error = "memory"; 1670 break; 1671 default: 1672 return (EINVAL); 1673 } 1674 pci_clear_command_bit(dev, child, bit); 1675 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1676 if (command & bit) { 1677 device_printf(child, "failed to disable %s mapping!\n", error); 1678 return (ENXIO); 1679 } 1680 return (0); 1681 } 1682 1683 /* 1684 * New style pci driver. Parent device is either a pci-host-bridge or a 1685 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1686 */ 1687 1688 void 1689 pci_print_verbose(struct pci_devinfo *dinfo) 1690 { 1691 int i; 1692 1693 if (bootverbose) { 1694 pcicfgregs *cfg = &dinfo->cfg; 1695 1696 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1697 cfg->vendor, cfg->device, cfg->revid); 1698 printf("\tbus=%d, slot=%d, func=%d\n", 1699 cfg->bus, cfg->slot, cfg->func); 1700 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1701 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1702 cfg->mfdev); 1703 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1704 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1705 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1706 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1707 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1708 if (cfg->intpin > 0) 1709 printf("\tintpin=%c, irq=%d\n", 1710 cfg->intpin +'a' -1, cfg->intline); 1711 if (cfg->pp.pp_cap) { 1712 uint16_t status; 1713 1714 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1715 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1716 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1717 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1718 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1719 status & PCIM_PSTAT_DMASK); 1720 } 1721 if (cfg->vpd.vpd_reg) { 1722 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1723 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1724 struct vpd_readonly *vrop; 1725 vrop = &cfg->vpd.vpd_ros[i]; 1726 if (strncmp("CP", vrop->keyword, 2) == 0) 1727 printf("\tCP: id %d, BAR%d, off %#x\n", 1728 vrop->value[0], vrop->value[1], 1729 le16toh( 1730 *(uint16_t *)&vrop->value[2])); 1731 else if (strncmp("RV", vrop->keyword, 2) == 0) 1732 printf("\tRV: %#hhx\n", vrop->value[0]); 1733 else 1734 printf("\t%.2s: %s\n", vrop->keyword, 1735 vrop->value); 1736 } 1737 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1738 struct vpd_write *vwp; 1739 vwp = &cfg->vpd.vpd_w[i]; 1740 if (strncmp("RW", vwp->keyword, 2) != 0) 1741 printf("\t%.2s(%#x-%#x): %s\n", 1742 vwp->keyword, vwp->start, 1743 vwp->start + vwp->len, vwp->value); 1744 } 1745 } 1746 if (cfg->msi.msi_location) { 1747 int ctrl; 1748 1749 ctrl = cfg->msi.msi_ctrl; 1750 printf("\tMSI supports %d message%s%s%s\n", 1751 cfg->msi.msi_msgnum, 1752 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1753 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1754 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1755 } 1756 if (cfg->msix.msix_location) { 1757 printf("\tMSI-X supports %d message%s ", 1758 cfg->msix.msix_msgnum, 1759 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 1760 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 1761 printf("in map 0x%x\n", 1762 cfg->msix.msix_table_bar); 1763 else 1764 printf("in maps 0x%x and 0x%x\n", 1765 cfg->msix.msix_table_bar, 1766 cfg->msix.msix_pba_bar); 1767 } 1768 } 1769 } 1770 1771 static int 1772 pci_porten(device_t pcib, int b, int s, int f) 1773 { 1774 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1775 & PCIM_CMD_PORTEN) != 0; 1776 } 1777 1778 static int 1779 pci_memen(device_t pcib, int b, int s, int f) 1780 { 1781 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1782 & PCIM_CMD_MEMEN) != 0; 1783 } 1784 1785 /* 1786 * Add a resource based on a pci map register. Return 1 if the map 1787 * register is a 32bit map register or 2 if it is a 64bit register. 1788 */ 1789 static int 1790 pci_add_map(device_t pcib, device_t bus, device_t dev, 1791 int b, int s, int f, int reg, struct resource_list *rl, int force, 1792 int prefetch) 1793 { 1794 uint32_t map; 1795 pci_addr_t base; 1796 pci_addr_t start, end, count; 1797 uint8_t ln2size; 1798 uint8_t ln2range; 1799 uint32_t testval; 1800 uint16_t cmd; 1801 int type; 1802 int barlen; 1803 struct resource *res; 1804 1805 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1806 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1807 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1808 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1809 1810 if (pci_maptype(map) & PCI_MAPMEM) 1811 type = SYS_RES_MEMORY; 1812 else 1813 type = SYS_RES_IOPORT; 1814 ln2size = pci_mapsize(testval); 1815 ln2range = pci_maprange(testval); 1816 base = pci_mapbase(map); 1817 barlen = ln2range == 64 ? 2 : 1; 1818 1819 /* 1820 * For I/O registers, if bottom bit is set, and the next bit up 1821 * isn't clear, we know we have a BAR that doesn't conform to the 1822 * spec, so ignore it. Also, sanity check the size of the data 1823 * areas to the type of memory involved. Memory must be at least 1824 * 16 bytes in size, while I/O ranges must be at least 4. 1825 */ 1826 if ((testval & 0x1) == 0x1 && 1827 (testval & 0x2) != 0) 1828 return (barlen); 1829 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1830 (type == SYS_RES_IOPORT && ln2size < 2)) 1831 return (barlen); 1832 1833 if (ln2range == 64) 1834 /* Read the other half of a 64bit map register */ 1835 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1836 if (bootverbose) { 1837 printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d", 1838 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size); 1839 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1840 printf(", port disabled\n"); 1841 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1842 printf(", memory disabled\n"); 1843 else 1844 printf(", enabled\n"); 1845 } 1846 1847 /* 1848 * If base is 0, then we have problems. It is best to ignore 1849 * such entries for the moment. These will be allocated later if 1850 * the driver specifically requests them. However, some 1851 * removable busses look better when all resources are allocated, 1852 * so allow '0' to be overriden. 1853 * 1854 * Similarly treat maps whose values is the same as the test value 1855 * read back. These maps have had all f's written to them by the 1856 * BIOS in an attempt to disable the resources. 1857 */ 1858 if (!force && (base == 0 || map == testval)) 1859 return (barlen); 1860 if ((u_long)base != base) { 1861 device_printf(bus, 1862 "pci%d:%d:%d bar %#x too many address bits", b, s, f, reg); 1863 return (barlen); 1864 } 1865 1866 /* 1867 * This code theoretically does the right thing, but has 1868 * undesirable side effects in some cases where peripherals 1869 * respond oddly to having these bits enabled. Let the user 1870 * be able to turn them off (since pci_enable_io_modes is 1 by 1871 * default). 1872 */ 1873 if (pci_enable_io_modes) { 1874 /* Turn on resources that have been left off by a lazy BIOS */ 1875 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1876 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1877 cmd |= PCIM_CMD_PORTEN; 1878 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1879 } 1880 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1881 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1882 cmd |= PCIM_CMD_MEMEN; 1883 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1884 } 1885 } else { 1886 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1887 return (barlen); 1888 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1889 return (barlen); 1890 } 1891 1892 count = 1 << ln2size; 1893 if (base == 0 || base == pci_mapbase(testval)) { 1894 start = 0; /* Let the parent deside */ 1895 end = ~0ULL; 1896 } else { 1897 start = base; 1898 end = base + (1 << ln2size) - 1; 1899 } 1900 resource_list_add(rl, type, reg, start, end, count); 1901 1902 /* 1903 * Not quite sure what to do on failure of allocating the resource 1904 * since I can postulate several right answers. 1905 */ 1906 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1907 prefetch ? RF_PREFETCHABLE : 0); 1908 if (res == NULL) 1909 return (barlen); 1910 start = rman_get_start(res); 1911 if ((u_long)start != start) { 1912 /* Wait a minute! this platform can't do this address. */ 1913 device_printf(bus, 1914 "pci%d.%d.%x bar %#x start %#jx, too many bits.", 1915 b, s, f, reg, (uintmax_t)start); 1916 resource_list_release(rl, bus, dev, type, reg, res); 1917 return (barlen); 1918 } 1919 pci_write_config(dev, reg, start, 4); 1920 if (ln2range == 64) 1921 pci_write_config(dev, reg + 4, start >> 32, 4); 1922 return (barlen); 1923 } 1924 1925 /* 1926 * For ATA devices we need to decide early what addressing mode to use. 1927 * Legacy demands that the primary and secondary ATA ports sits on the 1928 * same addresses that old ISA hardware did. This dictates that we use 1929 * those addresses and ignore the BAR's if we cannot set PCI native 1930 * addressing mode. 1931 */ 1932 static void 1933 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1934 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1935 { 1936 int rid, type, progif; 1937 #if 0 1938 /* if this device supports PCI native addressing use it */ 1939 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1940 if ((progif & 0x8a) == 0x8a) { 1941 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1942 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1943 printf("Trying ATA native PCI addressing mode\n"); 1944 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1945 } 1946 } 1947 #endif 1948 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1949 type = SYS_RES_IOPORT; 1950 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1951 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1952 prefetchmask & (1 << 0)); 1953 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1954 prefetchmask & (1 << 1)); 1955 } else { 1956 rid = PCIR_BAR(0); 1957 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1958 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1959 0); 1960 rid = PCIR_BAR(1); 1961 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1962 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1963 0); 1964 } 1965 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1966 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1967 prefetchmask & (1 << 2)); 1968 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1969 prefetchmask & (1 << 3)); 1970 } else { 1971 rid = PCIR_BAR(2); 1972 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1973 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1974 0); 1975 rid = PCIR_BAR(3); 1976 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1977 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1978 0); 1979 } 1980 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1981 prefetchmask & (1 << 4)); 1982 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1983 prefetchmask & (1 << 5)); 1984 } 1985 1986 static void 1987 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1988 { 1989 struct pci_devinfo *dinfo = device_get_ivars(dev); 1990 pcicfgregs *cfg = &dinfo->cfg; 1991 char tunable_name[64]; 1992 int irq; 1993 1994 /* Has to have an intpin to have an interrupt. */ 1995 if (cfg->intpin == 0) 1996 return; 1997 1998 /* Let the user override the IRQ with a tunable. */ 1999 irq = PCI_INVALID_IRQ; 2000 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 2001 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 2002 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 2003 irq = PCI_INVALID_IRQ; 2004 2005 /* 2006 * If we didn't get an IRQ via the tunable, then we either use the 2007 * IRQ value in the intline register or we ask the bus to route an 2008 * interrupt for us. If force_route is true, then we only use the 2009 * value in the intline register if the bus was unable to assign an 2010 * IRQ. 2011 */ 2012 if (!PCI_INTERRUPT_VALID(irq)) { 2013 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 2014 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 2015 if (!PCI_INTERRUPT_VALID(irq)) 2016 irq = cfg->intline; 2017 } 2018 2019 /* If after all that we don't have an IRQ, just bail. */ 2020 if (!PCI_INTERRUPT_VALID(irq)) 2021 return; 2022 2023 /* Update the config register if it changed. */ 2024 if (irq != cfg->intline) { 2025 cfg->intline = irq; 2026 pci_write_config(dev, PCIR_INTLINE, irq, 1); 2027 } 2028 2029 /* Add this IRQ as rid 0 interrupt resource. */ 2030 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 2031 } 2032 2033 void 2034 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 2035 { 2036 device_t pcib; 2037 struct pci_devinfo *dinfo = device_get_ivars(dev); 2038 pcicfgregs *cfg = &dinfo->cfg; 2039 struct resource_list *rl = &dinfo->resources; 2040 struct pci_quirk *q; 2041 int b, i, f, s; 2042 2043 pcib = device_get_parent(bus); 2044 2045 b = cfg->bus; 2046 s = cfg->slot; 2047 f = cfg->func; 2048 2049 /* ATA devices needs special map treatment */ 2050 if ((pci_get_class(dev) == PCIC_STORAGE) && 2051 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 2052 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 2053 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 2054 else 2055 for (i = 0; i < cfg->nummaps;) 2056 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 2057 rl, force, prefetchmask & (1 << i)); 2058 2059 /* 2060 * Add additional, quirked resources. 2061 */ 2062 for (q = &pci_quirks[0]; q->devid; q++) { 2063 if (q->devid == ((cfg->device << 16) | cfg->vendor) 2064 && q->type == PCI_QUIRK_MAP_REG) 2065 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 2066 force, 0); 2067 } 2068 2069 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2070 #ifdef __PCI_REROUTE_INTERRUPT 2071 /* 2072 * Try to re-route interrupts. Sometimes the BIOS or 2073 * firmware may leave bogus values in these registers. 2074 * If the re-route fails, then just stick with what we 2075 * have. 2076 */ 2077 pci_assign_interrupt(bus, dev, 1); 2078 #else 2079 pci_assign_interrupt(bus, dev, 0); 2080 #endif 2081 } 2082 } 2083 2084 void 2085 pci_add_children(device_t dev, int busno, size_t dinfo_size) 2086 { 2087 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 2088 device_t pcib = device_get_parent(dev); 2089 struct pci_devinfo *dinfo; 2090 int maxslots; 2091 int s, f, pcifunchigh; 2092 uint8_t hdrtype; 2093 2094 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 2095 ("dinfo_size too small")); 2096 maxslots = PCIB_MAXSLOTS(pcib); 2097 for (s = 0; s <= maxslots; s++) { 2098 pcifunchigh = 0; 2099 f = 0; 2100 DELAY(1); 2101 hdrtype = REG(PCIR_HDRTYPE, 1); 2102 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 2103 continue; 2104 if (hdrtype & PCIM_MFDEV) 2105 pcifunchigh = PCI_FUNCMAX; 2106 for (f = 0; f <= pcifunchigh; f++) { 2107 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 2108 if (dinfo != NULL) { 2109 pci_add_child(dev, dinfo); 2110 } 2111 } 2112 } 2113 #undef REG 2114 } 2115 2116 void 2117 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 2118 { 2119 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 2120 device_set_ivars(dinfo->cfg.dev, dinfo); 2121 resource_list_init(&dinfo->resources); 2122 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 2123 pci_cfg_restore(dinfo->cfg.dev, dinfo); 2124 pci_print_verbose(dinfo); 2125 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 2126 } 2127 2128 static int 2129 pci_probe(device_t dev) 2130 { 2131 2132 device_set_desc(dev, "PCI bus"); 2133 2134 /* Allow other subclasses to override this driver. */ 2135 return (-1000); 2136 } 2137 2138 static int 2139 pci_attach(device_t dev) 2140 { 2141 int busno; 2142 2143 /* 2144 * Since there can be multiple independantly numbered PCI 2145 * busses on systems with multiple PCI domains, we can't use 2146 * the unit number to decide which bus we are probing. We ask 2147 * the parent pcib what our bus number is. 2148 */ 2149 busno = pcib_get_bus(dev); 2150 if (bootverbose) 2151 device_printf(dev, "physical bus=%d\n", busno); 2152 2153 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 2154 2155 return (bus_generic_attach(dev)); 2156 } 2157 2158 int 2159 pci_suspend(device_t dev) 2160 { 2161 int dstate, error, i, numdevs; 2162 device_t acpi_dev, child, *devlist; 2163 struct pci_devinfo *dinfo; 2164 2165 /* 2166 * Save the PCI configuration space for each child and set the 2167 * device in the appropriate power state for this sleep state. 2168 */ 2169 acpi_dev = NULL; 2170 if (pci_do_power_resume) 2171 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2172 device_get_children(dev, &devlist, &numdevs); 2173 for (i = 0; i < numdevs; i++) { 2174 child = devlist[i]; 2175 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2176 pci_cfg_save(child, dinfo, 0); 2177 } 2178 2179 /* Suspend devices before potentially powering them down. */ 2180 error = bus_generic_suspend(dev); 2181 if (error) { 2182 free(devlist, M_TEMP); 2183 return (error); 2184 } 2185 2186 /* 2187 * Always set the device to D3. If ACPI suggests a different 2188 * power state, use it instead. If ACPI is not present, the 2189 * firmware is responsible for managing device power. Skip 2190 * children who aren't attached since they are powered down 2191 * separately. Only manage type 0 devices for now. 2192 */ 2193 for (i = 0; acpi_dev && i < numdevs; i++) { 2194 child = devlist[i]; 2195 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2196 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2197 dstate = PCI_POWERSTATE_D3; 2198 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2199 pci_set_powerstate(child, dstate); 2200 } 2201 } 2202 free(devlist, M_TEMP); 2203 return (0); 2204 } 2205 2206 int 2207 pci_resume(device_t dev) 2208 { 2209 int i, numdevs; 2210 device_t acpi_dev, child, *devlist; 2211 struct pci_devinfo *dinfo; 2212 2213 /* 2214 * Set each child to D0 and restore its PCI configuration space. 2215 */ 2216 acpi_dev = NULL; 2217 if (pci_do_power_resume) 2218 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2219 device_get_children(dev, &devlist, &numdevs); 2220 for (i = 0; i < numdevs; i++) { 2221 /* 2222 * Notify ACPI we're going to D0 but ignore the result. If 2223 * ACPI is not present, the firmware is responsible for 2224 * managing device power. Only manage type 0 devices for now. 2225 */ 2226 child = devlist[i]; 2227 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2228 if (acpi_dev && device_is_attached(child) && 2229 dinfo->cfg.hdrtype == 0) { 2230 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2231 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2232 } 2233 2234 /* Now the device is powered up, restore its config space. */ 2235 pci_cfg_restore(child, dinfo); 2236 } 2237 free(devlist, M_TEMP); 2238 return (bus_generic_resume(dev)); 2239 } 2240 2241 static void 2242 pci_load_vendor_data(void) 2243 { 2244 caddr_t vendordata, info; 2245 2246 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 2247 info = preload_search_info(vendordata, MODINFO_ADDR); 2248 pci_vendordata = *(char **)info; 2249 info = preload_search_info(vendordata, MODINFO_SIZE); 2250 pci_vendordata_size = *(size_t *)info; 2251 /* terminate the database */ 2252 pci_vendordata[pci_vendordata_size] = '\n'; 2253 } 2254 } 2255 2256 void 2257 pci_driver_added(device_t dev, driver_t *driver) 2258 { 2259 int numdevs; 2260 device_t *devlist; 2261 device_t child; 2262 struct pci_devinfo *dinfo; 2263 int i; 2264 2265 if (bootverbose) 2266 device_printf(dev, "driver added\n"); 2267 DEVICE_IDENTIFY(driver, dev); 2268 device_get_children(dev, &devlist, &numdevs); 2269 for (i = 0; i < numdevs; i++) { 2270 child = devlist[i]; 2271 if (device_get_state(child) != DS_NOTPRESENT) 2272 continue; 2273 dinfo = device_get_ivars(child); 2274 pci_print_verbose(dinfo); 2275 if (bootverbose) 2276 printf("pci%d:%d:%d: reprobing on driver added\n", 2277 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 2278 pci_cfg_restore(child, dinfo); 2279 if (device_probe_and_attach(child) != 0) 2280 pci_cfg_save(child, dinfo, 1); 2281 } 2282 free(devlist, M_TEMP); 2283 } 2284 2285 int 2286 pci_print_child(device_t dev, device_t child) 2287 { 2288 struct pci_devinfo *dinfo; 2289 struct resource_list *rl; 2290 int retval = 0; 2291 2292 dinfo = device_get_ivars(child); 2293 rl = &dinfo->resources; 2294 2295 retval += bus_print_child_header(dev, child); 2296 2297 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 2298 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 2299 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 2300 if (device_get_flags(dev)) 2301 retval += printf(" flags %#x", device_get_flags(dev)); 2302 2303 retval += printf(" at device %d.%d", pci_get_slot(child), 2304 pci_get_function(child)); 2305 2306 retval += bus_print_child_footer(dev, child); 2307 2308 return (retval); 2309 } 2310 2311 static struct 2312 { 2313 int class; 2314 int subclass; 2315 char *desc; 2316 } pci_nomatch_tab[] = { 2317 {PCIC_OLD, -1, "old"}, 2318 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 2319 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 2320 {PCIC_STORAGE, -1, "mass storage"}, 2321 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 2322 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 2323 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 2324 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 2325 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 2326 {PCIC_NETWORK, -1, "network"}, 2327 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 2328 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 2329 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 2330 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 2331 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 2332 {PCIC_DISPLAY, -1, "display"}, 2333 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 2334 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 2335 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 2336 {PCIC_MULTIMEDIA, -1, "multimedia"}, 2337 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 2338 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 2339 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 2340 {PCIC_MEMORY, -1, "memory"}, 2341 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 2342 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 2343 {PCIC_BRIDGE, -1, "bridge"}, 2344 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 2345 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 2346 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 2347 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 2348 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 2349 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 2350 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 2351 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 2352 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 2353 {PCIC_SIMPLECOMM, -1, "simple comms"}, 2354 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 2355 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 2356 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 2357 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 2358 {PCIC_BASEPERIPH, -1, "base peripheral"}, 2359 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 2360 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 2361 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 2362 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 2363 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 2364 {PCIC_INPUTDEV, -1, "input device"}, 2365 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 2366 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 2367 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 2368 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 2369 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 2370 {PCIC_DOCKING, -1, "docking station"}, 2371 {PCIC_PROCESSOR, -1, "processor"}, 2372 {PCIC_SERIALBUS, -1, "serial bus"}, 2373 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 2374 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 2375 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 2376 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 2377 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 2378 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 2379 {PCIC_WIRELESS, -1, "wireless controller"}, 2380 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 2381 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 2382 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 2383 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 2384 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 2385 {PCIC_SATCOM, -1, "satellite communication"}, 2386 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 2387 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 2388 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 2389 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 2390 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 2391 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 2392 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 2393 {PCIC_DASP, -1, "dasp"}, 2394 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 2395 {0, 0, NULL} 2396 }; 2397 2398 void 2399 pci_probe_nomatch(device_t dev, device_t child) 2400 { 2401 int i; 2402 char *cp, *scp, *device; 2403 2404 /* 2405 * Look for a listing for this device in a loaded device database. 2406 */ 2407 if ((device = pci_describe_device(child)) != NULL) { 2408 device_printf(dev, "<%s>", device); 2409 free(device, M_DEVBUF); 2410 } else { 2411 /* 2412 * Scan the class/subclass descriptions for a general 2413 * description. 2414 */ 2415 cp = "unknown"; 2416 scp = NULL; 2417 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 2418 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 2419 if (pci_nomatch_tab[i].subclass == -1) { 2420 cp = pci_nomatch_tab[i].desc; 2421 } else if (pci_nomatch_tab[i].subclass == 2422 pci_get_subclass(child)) { 2423 scp = pci_nomatch_tab[i].desc; 2424 } 2425 } 2426 } 2427 device_printf(dev, "<%s%s%s>", 2428 cp ? cp : "", 2429 ((cp != NULL) && (scp != NULL)) ? ", " : "", 2430 scp ? scp : ""); 2431 } 2432 printf(" at device %d.%d (no driver attached)\n", 2433 pci_get_slot(child), pci_get_function(child)); 2434 if (pci_do_power_nodriver) 2435 pci_cfg_save(child, 2436 (struct pci_devinfo *) device_get_ivars(child), 1); 2437 return; 2438 } 2439 2440 /* 2441 * Parse the PCI device database, if loaded, and return a pointer to a 2442 * description of the device. 2443 * 2444 * The database is flat text formatted as follows: 2445 * 2446 * Any line not in a valid format is ignored. 2447 * Lines are terminated with newline '\n' characters. 2448 * 2449 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 2450 * the vendor name. 2451 * 2452 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 2453 * - devices cannot be listed without a corresponding VENDOR line. 2454 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 2455 * another TAB, then the device name. 2456 */ 2457 2458 /* 2459 * Assuming (ptr) points to the beginning of a line in the database, 2460 * return the vendor or device and description of the next entry. 2461 * The value of (vendor) or (device) inappropriate for the entry type 2462 * is set to -1. Returns nonzero at the end of the database. 2463 * 2464 * Note that this is slightly unrobust in the face of corrupt data; 2465 * we attempt to safeguard against this by spamming the end of the 2466 * database with a newline when we initialise. 2467 */ 2468 static int 2469 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 2470 { 2471 char *cp = *ptr; 2472 int left; 2473 2474 *device = -1; 2475 *vendor = -1; 2476 **desc = '\0'; 2477 for (;;) { 2478 left = pci_vendordata_size - (cp - pci_vendordata); 2479 if (left <= 0) { 2480 *ptr = cp; 2481 return(1); 2482 } 2483 2484 /* vendor entry? */ 2485 if (*cp != '\t' && 2486 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 2487 break; 2488 /* device entry? */ 2489 if (*cp == '\t' && 2490 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 2491 break; 2492 2493 /* skip to next line */ 2494 while (*cp != '\n' && left > 0) { 2495 cp++; 2496 left--; 2497 } 2498 if (*cp == '\n') { 2499 cp++; 2500 left--; 2501 } 2502 } 2503 /* skip to next line */ 2504 while (*cp != '\n' && left > 0) { 2505 cp++; 2506 left--; 2507 } 2508 if (*cp == '\n' && left > 0) 2509 cp++; 2510 *ptr = cp; 2511 return(0); 2512 } 2513 2514 static char * 2515 pci_describe_device(device_t dev) 2516 { 2517 int vendor, device; 2518 char *desc, *vp, *dp, *line; 2519 2520 desc = vp = dp = NULL; 2521 2522 /* 2523 * If we have no vendor data, we can't do anything. 2524 */ 2525 if (pci_vendordata == NULL) 2526 goto out; 2527 2528 /* 2529 * Scan the vendor data looking for this device 2530 */ 2531 line = pci_vendordata; 2532 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2533 goto out; 2534 for (;;) { 2535 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 2536 goto out; 2537 if (vendor == pci_get_vendor(dev)) 2538 break; 2539 } 2540 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 2541 goto out; 2542 for (;;) { 2543 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 2544 *dp = 0; 2545 break; 2546 } 2547 if (vendor != -1) { 2548 *dp = 0; 2549 break; 2550 } 2551 if (device == pci_get_device(dev)) 2552 break; 2553 } 2554 if (dp[0] == '\0') 2555 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 2556 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 2557 NULL) 2558 sprintf(desc, "%s, %s", vp, dp); 2559 out: 2560 if (vp != NULL) 2561 free(vp, M_DEVBUF); 2562 if (dp != NULL) 2563 free(dp, M_DEVBUF); 2564 return(desc); 2565 } 2566 2567 int 2568 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 2569 { 2570 struct pci_devinfo *dinfo; 2571 pcicfgregs *cfg; 2572 2573 dinfo = device_get_ivars(child); 2574 cfg = &dinfo->cfg; 2575 2576 switch (which) { 2577 case PCI_IVAR_ETHADDR: 2578 /* 2579 * The generic accessor doesn't deal with failure, so 2580 * we set the return value, then return an error. 2581 */ 2582 *((uint8_t **) result) = NULL; 2583 return (EINVAL); 2584 case PCI_IVAR_SUBVENDOR: 2585 *result = cfg->subvendor; 2586 break; 2587 case PCI_IVAR_SUBDEVICE: 2588 *result = cfg->subdevice; 2589 break; 2590 case PCI_IVAR_VENDOR: 2591 *result = cfg->vendor; 2592 break; 2593 case PCI_IVAR_DEVICE: 2594 *result = cfg->device; 2595 break; 2596 case PCI_IVAR_DEVID: 2597 *result = (cfg->device << 16) | cfg->vendor; 2598 break; 2599 case PCI_IVAR_CLASS: 2600 *result = cfg->baseclass; 2601 break; 2602 case PCI_IVAR_SUBCLASS: 2603 *result = cfg->subclass; 2604 break; 2605 case PCI_IVAR_PROGIF: 2606 *result = cfg->progif; 2607 break; 2608 case PCI_IVAR_REVID: 2609 *result = cfg->revid; 2610 break; 2611 case PCI_IVAR_INTPIN: 2612 *result = cfg->intpin; 2613 break; 2614 case PCI_IVAR_IRQ: 2615 *result = cfg->intline; 2616 break; 2617 case PCI_IVAR_BUS: 2618 *result = cfg->bus; 2619 break; 2620 case PCI_IVAR_SLOT: 2621 *result = cfg->slot; 2622 break; 2623 case PCI_IVAR_FUNCTION: 2624 *result = cfg->func; 2625 break; 2626 case PCI_IVAR_CMDREG: 2627 *result = cfg->cmdreg; 2628 break; 2629 case PCI_IVAR_CACHELNSZ: 2630 *result = cfg->cachelnsz; 2631 break; 2632 case PCI_IVAR_MINGNT: 2633 *result = cfg->mingnt; 2634 break; 2635 case PCI_IVAR_MAXLAT: 2636 *result = cfg->maxlat; 2637 break; 2638 case PCI_IVAR_LATTIMER: 2639 *result = cfg->lattimer; 2640 break; 2641 default: 2642 return (ENOENT); 2643 } 2644 return (0); 2645 } 2646 2647 int 2648 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2649 { 2650 struct pci_devinfo *dinfo; 2651 2652 dinfo = device_get_ivars(child); 2653 2654 switch (which) { 2655 case PCI_IVAR_INTPIN: 2656 dinfo->cfg.intpin = value; 2657 return (0); 2658 case PCI_IVAR_ETHADDR: 2659 case PCI_IVAR_SUBVENDOR: 2660 case PCI_IVAR_SUBDEVICE: 2661 case PCI_IVAR_VENDOR: 2662 case PCI_IVAR_DEVICE: 2663 case PCI_IVAR_DEVID: 2664 case PCI_IVAR_CLASS: 2665 case PCI_IVAR_SUBCLASS: 2666 case PCI_IVAR_PROGIF: 2667 case PCI_IVAR_REVID: 2668 case PCI_IVAR_IRQ: 2669 case PCI_IVAR_BUS: 2670 case PCI_IVAR_SLOT: 2671 case PCI_IVAR_FUNCTION: 2672 return (EINVAL); /* disallow for now */ 2673 2674 default: 2675 return (ENOENT); 2676 } 2677 } 2678 2679 2680 #include "opt_ddb.h" 2681 #ifdef DDB 2682 #include <ddb/ddb.h> 2683 #include <sys/cons.h> 2684 2685 /* 2686 * List resources based on pci map registers, used for within ddb 2687 */ 2688 2689 DB_SHOW_COMMAND(pciregs, db_pci_dump) 2690 { 2691 struct pci_devinfo *dinfo; 2692 struct devlist *devlist_head; 2693 struct pci_conf *p; 2694 const char *name; 2695 int i, error, none_count; 2696 2697 none_count = 0; 2698 /* get the head of the device queue */ 2699 devlist_head = &pci_devq; 2700 2701 /* 2702 * Go through the list of devices and print out devices 2703 */ 2704 for (error = 0, i = 0, 2705 dinfo = STAILQ_FIRST(devlist_head); 2706 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2707 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2708 2709 /* Populate pd_name and pd_unit */ 2710 name = NULL; 2711 if (dinfo->cfg.dev) 2712 name = device_get_name(dinfo->cfg.dev); 2713 2714 p = &dinfo->conf; 2715 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2716 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2717 (name && *name) ? name : "none", 2718 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2719 none_count++, 2720 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2721 p->pc_sel.pc_func, (p->pc_class << 16) | 2722 (p->pc_subclass << 8) | p->pc_progif, 2723 (p->pc_subdevice << 16) | p->pc_subvendor, 2724 (p->pc_device << 16) | p->pc_vendor, 2725 p->pc_revid, p->pc_hdr); 2726 } 2727 } 2728 #endif /* DDB */ 2729 2730 static struct resource * 2731 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2732 u_long start, u_long end, u_long count, u_int flags) 2733 { 2734 struct pci_devinfo *dinfo = device_get_ivars(child); 2735 struct resource_list *rl = &dinfo->resources; 2736 struct resource_list_entry *rle; 2737 struct resource *res; 2738 pci_addr_t map, testval; 2739 int mapsize; 2740 2741 /* 2742 * Weed out the bogons, and figure out how large the BAR/map 2743 * is. Bars that read back 0 here are bogus and unimplemented. 2744 * Note: atapci in legacy mode are special and handled elsewhere 2745 * in the code. If you have a atapci device in legacy mode and 2746 * it fails here, that other code is broken. 2747 */ 2748 res = NULL; 2749 map = pci_read_config(child, *rid, 4); 2750 pci_write_config(child, *rid, 0xffffffff, 4); 2751 testval = pci_read_config(child, *rid, 4); 2752 if (pci_maprange(testval) == 64) 2753 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32; 2754 if (pci_mapbase(testval) == 0) 2755 goto out; 2756 if (pci_maptype(testval) & PCI_MAPMEM) { 2757 if (type != SYS_RES_MEMORY) { 2758 if (bootverbose) 2759 device_printf(dev, 2760 "child %s requested type %d for rid %#x," 2761 " but the BAR says it is an memio\n", 2762 device_get_nameunit(child), type, *rid); 2763 goto out; 2764 } 2765 } else { 2766 if (type != SYS_RES_IOPORT) { 2767 if (bootverbose) 2768 device_printf(dev, 2769 "child %s requested type %d for rid %#x," 2770 " but the BAR says it is an ioport\n", 2771 device_get_nameunit(child), type, *rid); 2772 goto out; 2773 } 2774 } 2775 /* 2776 * For real BARs, we need to override the size that 2777 * the driver requests, because that's what the BAR 2778 * actually uses and we would otherwise have a 2779 * situation where we might allocate the excess to 2780 * another driver, which won't work. 2781 */ 2782 mapsize = pci_mapsize(testval); 2783 count = 1UL << mapsize; 2784 if (RF_ALIGNMENT(flags) < mapsize) 2785 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2786 2787 /* 2788 * Allocate enough resource, and then write back the 2789 * appropriate bar for that resource. 2790 */ 2791 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2792 start, end, count, flags); 2793 if (res == NULL) { 2794 device_printf(child, 2795 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2796 count, *rid, type, start, end); 2797 goto out; 2798 } 2799 resource_list_add(rl, type, *rid, start, end, count); 2800 rle = resource_list_find(rl, type, *rid); 2801 if (rle == NULL) 2802 panic("pci_alloc_map: unexpectedly can't find resource."); 2803 rle->res = res; 2804 rle->start = rman_get_start(res); 2805 rle->end = rman_get_end(res); 2806 rle->count = count; 2807 if (bootverbose) 2808 device_printf(child, 2809 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2810 count, *rid, type, rman_get_start(res)); 2811 map = rman_get_start(res); 2812 out:; 2813 pci_write_config(child, *rid, map, 4); 2814 if (pci_maprange(testval) == 64) 2815 pci_write_config(child, *rid + 4, map >> 32, 4); 2816 return (res); 2817 } 2818 2819 2820 struct resource * 2821 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2822 u_long start, u_long end, u_long count, u_int flags) 2823 { 2824 struct pci_devinfo *dinfo = device_get_ivars(child); 2825 struct resource_list *rl = &dinfo->resources; 2826 struct resource_list_entry *rle; 2827 pcicfgregs *cfg = &dinfo->cfg; 2828 2829 /* 2830 * Perform lazy resource allocation 2831 */ 2832 if (device_get_parent(child) == dev) { 2833 switch (type) { 2834 case SYS_RES_IRQ: 2835 /* 2836 * Can't alloc legacy interrupt once MSI messages 2837 * have been allocated. 2838 */ 2839 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 2840 cfg->msix.msix_alloc > 0)) 2841 return (NULL); 2842 /* 2843 * If the child device doesn't have an 2844 * interrupt routed and is deserving of an 2845 * interrupt, try to assign it one. 2846 */ 2847 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 2848 (cfg->intpin != 0)) 2849 pci_assign_interrupt(dev, child, 0); 2850 break; 2851 case SYS_RES_IOPORT: 2852 case SYS_RES_MEMORY: 2853 if (*rid < PCIR_BAR(cfg->nummaps)) { 2854 /* 2855 * Enable the I/O mode. We should 2856 * also be assigning resources too 2857 * when none are present. The 2858 * resource_list_alloc kind of sorta does 2859 * this... 2860 */ 2861 if (PCI_ENABLE_IO(dev, child, type)) 2862 return (NULL); 2863 } 2864 rle = resource_list_find(rl, type, *rid); 2865 if (rle == NULL) 2866 return (pci_alloc_map(dev, child, type, rid, 2867 start, end, count, flags)); 2868 break; 2869 } 2870 /* 2871 * If we've already allocated the resource, then 2872 * return it now. But first we may need to activate 2873 * it, since we don't allocate the resource as active 2874 * above. Normally this would be done down in the 2875 * nexus, but since we short-circuit that path we have 2876 * to do its job here. Not sure if we should free the 2877 * resource if it fails to activate. 2878 */ 2879 rle = resource_list_find(rl, type, *rid); 2880 if (rle != NULL && rle->res != NULL) { 2881 if (bootverbose) 2882 device_printf(child, 2883 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2884 rman_get_size(rle->res), *rid, type, 2885 rman_get_start(rle->res)); 2886 if ((flags & RF_ACTIVE) && 2887 bus_generic_activate_resource(dev, child, type, 2888 *rid, rle->res) != 0) 2889 return NULL; 2890 return (rle->res); 2891 } 2892 } 2893 return (resource_list_alloc(rl, dev, child, type, rid, 2894 start, end, count, flags)); 2895 } 2896 2897 void 2898 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2899 { 2900 struct pci_devinfo *dinfo; 2901 struct resource_list *rl; 2902 struct resource_list_entry *rle; 2903 2904 if (device_get_parent(child) != dev) 2905 return; 2906 2907 dinfo = device_get_ivars(child); 2908 rl = &dinfo->resources; 2909 rle = resource_list_find(rl, type, rid); 2910 if (rle) { 2911 if (rle->res) { 2912 if (rman_get_device(rle->res) != dev || 2913 rman_get_flags(rle->res) & RF_ACTIVE) { 2914 device_printf(dev, "delete_resource: " 2915 "Resource still owned by child, oops. " 2916 "(type=%d, rid=%d, addr=%lx)\n", 2917 rle->type, rle->rid, 2918 rman_get_start(rle->res)); 2919 return; 2920 } 2921 bus_release_resource(dev, type, rid, rle->res); 2922 } 2923 resource_list_delete(rl, type, rid); 2924 } 2925 /* 2926 * Why do we turn off the PCI configuration BAR when we delete a 2927 * resource? -- imp 2928 */ 2929 pci_write_config(child, rid, 0, 4); 2930 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2931 } 2932 2933 struct resource_list * 2934 pci_get_resource_list (device_t dev, device_t child) 2935 { 2936 struct pci_devinfo *dinfo = device_get_ivars(child); 2937 2938 return (&dinfo->resources); 2939 } 2940 2941 uint32_t 2942 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2943 { 2944 struct pci_devinfo *dinfo = device_get_ivars(child); 2945 pcicfgregs *cfg = &dinfo->cfg; 2946 2947 return (PCIB_READ_CONFIG(device_get_parent(dev), 2948 cfg->bus, cfg->slot, cfg->func, reg, width)); 2949 } 2950 2951 void 2952 pci_write_config_method(device_t dev, device_t child, int reg, 2953 uint32_t val, int width) 2954 { 2955 struct pci_devinfo *dinfo = device_get_ivars(child); 2956 pcicfgregs *cfg = &dinfo->cfg; 2957 2958 PCIB_WRITE_CONFIG(device_get_parent(dev), 2959 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2960 } 2961 2962 int 2963 pci_child_location_str_method(device_t dev, device_t child, char *buf, 2964 size_t buflen) 2965 { 2966 2967 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2968 pci_get_function(child)); 2969 return (0); 2970 } 2971 2972 int 2973 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2974 size_t buflen) 2975 { 2976 struct pci_devinfo *dinfo; 2977 pcicfgregs *cfg; 2978 2979 dinfo = device_get_ivars(child); 2980 cfg = &dinfo->cfg; 2981 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2982 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2983 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2984 cfg->progif); 2985 return (0); 2986 } 2987 2988 int 2989 pci_assign_interrupt_method(device_t dev, device_t child) 2990 { 2991 struct pci_devinfo *dinfo = device_get_ivars(child); 2992 pcicfgregs *cfg = &dinfo->cfg; 2993 2994 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2995 cfg->intpin)); 2996 } 2997 2998 static int 2999 pci_modevent(module_t mod, int what, void *arg) 3000 { 3001 static struct cdev *pci_cdev; 3002 3003 switch (what) { 3004 case MOD_LOAD: 3005 STAILQ_INIT(&pci_devq); 3006 pci_generation = 0; 3007 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 3008 "pci"); 3009 pci_load_vendor_data(); 3010 break; 3011 3012 case MOD_UNLOAD: 3013 destroy_dev(pci_cdev); 3014 break; 3015 } 3016 3017 return (0); 3018 } 3019 3020 void 3021 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 3022 { 3023 int i; 3024 3025 /* 3026 * Only do header type 0 devices. Type 1 devices are bridges, 3027 * which we know need special treatment. Type 2 devices are 3028 * cardbus bridges which also require special treatment. 3029 * Other types are unknown, and we err on the side of safety 3030 * by ignoring them. 3031 */ 3032 if (dinfo->cfg.hdrtype != 0) 3033 return; 3034 3035 /* 3036 * Restore the device to full power mode. We must do this 3037 * before we restore the registers because moving from D3 to 3038 * D0 will cause the chip's BARs and some other registers to 3039 * be reset to some unknown power on reset values. Cut down 3040 * the noise on boot by doing nothing if we are already in 3041 * state D0. 3042 */ 3043 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 3044 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 3045 } 3046 for (i = 0; i < dinfo->cfg.nummaps; i++) 3047 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 3048 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 3049 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 3050 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 3051 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 3052 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 3053 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 3054 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 3055 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 3056 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 3057 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 3058 3059 /* 3060 * Restore MSI configuration if it is present. If MSI is enabled, 3061 * then restore the data and addr registers. 3062 */ 3063 if (dinfo->cfg.msi.msi_location != 0) 3064 pci_resume_msi(dev); 3065 } 3066 3067 void 3068 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 3069 { 3070 int i; 3071 uint32_t cls; 3072 int ps; 3073 3074 /* 3075 * Only do header type 0 devices. Type 1 devices are bridges, which 3076 * we know need special treatment. Type 2 devices are cardbus bridges 3077 * which also require special treatment. Other types are unknown, and 3078 * we err on the side of safety by ignoring them. Powering down 3079 * bridges should not be undertaken lightly. 3080 */ 3081 if (dinfo->cfg.hdrtype != 0) 3082 return; 3083 for (i = 0; i < dinfo->cfg.nummaps; i++) 3084 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3085 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 3086 3087 /* 3088 * Some drivers apparently write to these registers w/o updating our 3089 * cached copy. No harm happens if we update the copy, so do so here 3090 * so we can restore them. The COMMAND register is modified by the 3091 * bus w/o updating the cache. This should represent the normally 3092 * writable portion of the 'defined' part of type 0 headers. In 3093 * theory we also need to save/restore the PCI capability structures 3094 * we know about, but apart from power we don't know any that are 3095 * writable. 3096 */ 3097 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 3098 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 3099 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 3100 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 3101 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 3102 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 3103 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 3104 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 3105 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 3106 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3107 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3108 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 3109 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 3110 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 3111 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 3112 3113 /* 3114 * don't set the state for display devices, base peripherals and 3115 * memory devices since bad things happen when they are powered down. 3116 * We should (a) have drivers that can easily detach and (b) use 3117 * generic drivers for these devices so that some device actually 3118 * attaches. We need to make sure that when we implement (a) we don't 3119 * power the device down on a reattach. 3120 */ 3121 cls = pci_get_class(dev); 3122 if (!setstate) 3123 return; 3124 switch (pci_do_power_nodriver) 3125 { 3126 case 0: /* NO powerdown at all */ 3127 return; 3128 case 1: /* Conservative about what to power down */ 3129 if (cls == PCIC_STORAGE) 3130 return; 3131 /*FALLTHROUGH*/ 3132 case 2: /* Agressive about what to power down */ 3133 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 3134 cls == PCIC_BASEPERIPH) 3135 return; 3136 /*FALLTHROUGH*/ 3137 case 3: /* Power down everything */ 3138 break; 3139 } 3140 /* 3141 * PCI spec says we can only go into D3 state from D0 state. 3142 * Transition from D[12] into D0 before going to D3 state. 3143 */ 3144 ps = pci_get_powerstate(dev); 3145 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 3146 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 3147 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 3148 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 3149 } 3150