1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pci.c,v 1.78 1997/08/02 14:33:12 bde Exp $ 27 * 28 */ 29 30 #include "pci.h" 31 #if NPCI > 0 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/fcntl.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #ifdef DEVFS 40 #include <sys/devfsext.h> 41 #endif /* DEVFS */ 42 43 #include <vm/vm.h> 44 #include <vm/pmap.h> 45 46 #include <pci/pcireg.h> 47 #include <pci/pcivar.h> 48 #include <pci/pci_ioctl.h> 49 50 #ifdef APIC_IO 51 #include <machine/smp.h> 52 #endif /* APIC_IO */ 53 54 /* return highest PCI bus number known to be used, or -1 if none */ 55 56 static int 57 pci_bushigh(void) 58 { 59 if (pci_cfgopen() == 0) 60 return (-1); 61 return (0); 62 } 63 64 /* return base address of memory or port map */ 65 66 static int 67 pci_mapbase(unsigned mapreg) 68 { 69 int mask = 0x03; 70 if ((mapreg & 0x01) == 0) 71 mask = 0x0f; 72 return (mapreg & ~mask); 73 } 74 75 /* return map type of memory or port map */ 76 77 static int 78 pci_maptype(unsigned mapreg) 79 { 80 static u_int8_t maptype[0x10] = { 81 PCI_MAPMEM, PCI_MAPPORT, 82 PCI_MAPMEM, 0, 83 PCI_MAPMEM, PCI_MAPPORT, 84 0, 0, 85 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 86 PCI_MAPMEM|PCI_MAPMEMP, 0, 87 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 88 0, 0, 89 }; 90 91 return maptype[mapreg & 0x0f]; 92 } 93 94 /* return log2 of map size decoded for memory or port map */ 95 96 static int 97 pci_mapsize(unsigned testval) 98 { 99 int ln2size; 100 101 testval = pci_mapbase(testval); 102 ln2size = 0; 103 if (testval != 0) { 104 while ((testval & 1) == 0) 105 { 106 ln2size++; 107 testval >>= 1; 108 } 109 } 110 return (ln2size); 111 } 112 113 /* return log2 of address range supported by map register */ 114 115 static int 116 pci_maprange(unsigned mapreg) 117 { 118 int ln2range = 0; 119 switch (mapreg & 0x07) { 120 case 0x00: 121 case 0x01: 122 case 0x05: 123 ln2range = 32; 124 break; 125 case 0x02: 126 ln2range = 20; 127 break; 128 case 0x04: 129 ln2range = 64; 130 break; 131 } 132 return (ln2range); 133 } 134 135 /* extract map parameters into newly allocated array of pcimap structures */ 136 137 static pcimap * 138 pci_readmaps(pcicfgregs *cfg, int maxmaps) 139 { 140 int i; 141 pcimap *map; 142 int map64 = 0; 143 144 for (i = 0; i < maxmaps; i++) { 145 int reg = PCIR_MAPS + i*4; 146 u_int32_t base; 147 u_int32_t ln2range; 148 149 base = pci_cfgread(cfg, reg, 4); 150 ln2range = pci_maprange(base); 151 152 if (base == 0 || ln2range == 0) 153 maxmaps = i; 154 else if (ln2range > 32) 155 i++; 156 } 157 158 map = malloc(maxmaps * sizeof (pcimap), M_DEVBUF, M_WAITOK); 159 if (map != NULL) { 160 bzero(map, sizeof(pcimap) * maxmaps); 161 162 for (i = 0; i < maxmaps; i++) { 163 int reg = PCIR_MAPS + i*4; 164 u_int32_t base; 165 u_int32_t testval; 166 167 base = pci_cfgread(cfg, reg, 4); 168 169 if (map64 == 0) { 170 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 171 testval = pci_cfgread(cfg, reg, 4); 172 pci_cfgwrite(cfg, reg, base, 4); 173 174 map[i].base = pci_mapbase(base); 175 map[i].type = pci_maptype(base); 176 map[i].ln2size = pci_mapsize(testval); 177 map[i].ln2range = pci_maprange(testval); 178 map64 = map[i].ln2range == 64; 179 } else { 180 /* only fill in base, other fields are 0 */ 181 map[i].base = base; 182 map64 = 0; 183 } 184 } 185 cfg->nummaps = maxmaps; 186 } 187 return (map); 188 } 189 190 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 191 192 static void 193 pci_fixancient(pcicfgregs *cfg) 194 { 195 if (cfg->hdrtype != 0) 196 return; 197 198 /* PCI to PCI bridges use header type 1 */ 199 if (cfg->class == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 200 cfg->hdrtype = 1; 201 } 202 203 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 204 205 static void * 206 pci_readppb(pcicfgregs *cfg) 207 { 208 pcih1cfgregs *p; 209 210 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 211 if (p == NULL) 212 return (NULL); 213 214 bzero(p, sizeof *p); 215 216 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 217 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 218 219 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 220 221 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 222 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 223 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 224 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 225 226 p->membase = PCI_PPBMEMBASE (0, 227 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 228 p->memlimit = PCI_PPBMEMLIMIT (0, 229 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 230 231 p->pmembase = PCI_PPBMEMBASE ( 232 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 233 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 234 235 p->pmemlimit = PCI_PPBMEMLIMIT ( 236 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 237 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 238 return (p); 239 } 240 241 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 242 243 static void * 244 pci_readpcb(pcicfgregs *cfg) 245 { 246 pcih2cfgregs *p; 247 248 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 249 if (p == NULL) 250 return (NULL); 251 252 bzero(p, sizeof *p); 253 254 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 255 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 256 257 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 258 259 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 260 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 261 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 262 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 263 264 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 265 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 266 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 267 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 268 269 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 270 return p; 271 } 272 273 /* extract header type specific config data */ 274 275 static void 276 pci_hdrtypedata(pcicfgregs *cfg) 277 { 278 switch (cfg->hdrtype) { 279 case 0: 280 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 281 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 282 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 283 break; 284 case 1: 285 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 286 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 287 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 288 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 289 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 290 cfg->hdrspec = pci_readppb(cfg); 291 break; 292 case 2: 293 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 294 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 295 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 296 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 297 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 298 cfg->hdrspec = pci_readpcb(cfg); 299 break; 300 } 301 } 302 303 /* read configuration header into pcicfgrect structure */ 304 305 static pcicfgregs * 306 pci_readcfg(pcicfgregs *probe) 307 { 308 pcicfgregs *cfg = NULL; 309 310 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 311 cfg = malloc(sizeof (pcicfgregs), M_DEVBUF, M_WAITOK); 312 if (cfg == NULL) 313 return (cfg); 314 315 bzero(cfg, sizeof *cfg); 316 317 cfg->bus = probe->bus; 318 cfg->slot = probe->slot; 319 cfg->func = probe->func; 320 cfg->parent = probe->parent; 321 322 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 323 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 324 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 325 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 326 cfg->class = pci_cfgread(cfg, PCIR_CLASS, 1); 327 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 328 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 329 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 330 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 331 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 332 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 333 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 334 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 335 336 #ifdef APIC_IO 337 if (cfg->intpin != 0) { 338 int airq; 339 340 airq = pci_apic_pin(cfg->bus, cfg->slot, cfg->intpin); 341 if ((airq >= 0) && (airq != cfg->intline)) { 342 undirect_pci_irq(cfg->intline); 343 cfg->intline = airq; 344 } 345 } 346 #endif /* APIC_IO */ 347 348 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 349 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 350 351 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 352 cfg->hdrtype &= ~PCIM_MFDEV; 353 354 pci_fixancient(cfg); 355 pci_hdrtypedata(cfg); 356 } 357 return (cfg); 358 } 359 360 /* free pcicfgregs structure and all depending data structures */ 361 362 static int 363 pci_freecfg(pcicfgregs *cfg) 364 { 365 if (cfg->hdrspec != NULL) 366 free(cfg->hdrspec, M_DEVBUF); 367 if (cfg->map != NULL) 368 free(cfg->map, M_DEVBUF); 369 free(cfg, M_DEVBUF); 370 return (0); 371 } 372 373 static void 374 pci_addcfg(pcicfgregs *cfg) 375 { 376 if (bootverbose) { 377 int i; 378 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 379 cfg->vendor, cfg->device, cfg->revid); 380 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 381 cfg->class, cfg->subclass, cfg->progif, cfg->hdrtype, cfg->mfdev); 382 #ifdef PCI_DEBUG 383 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 384 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 385 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 386 cfg->lattimer, cfg->lattimer * 30, 387 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 388 #endif /* PCI_DEBUG */ 389 if (cfg->intpin > 0) 390 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 391 392 for (i = 0; i < cfg->nummaps; i++) { 393 pcimap *m = &cfg->map[i]; 394 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 395 i, m->type, m->ln2range, m->base, m->ln2size); 396 } 397 } 398 pci_drvattach(cfg); /* XXX currently defined in pci_compat.c */ 399 } 400 401 /* return pointer to device that is a bridge to this bus */ 402 403 static pcicfgregs * 404 pci_bridgeto(int bus) 405 { 406 return (NULL); /* XXX not yet implemented */ 407 } 408 409 /* scan one PCI bus for devices */ 410 411 static int 412 pci_probebus(int bus) 413 { 414 pcicfgregs probe; 415 int bushigh = bus; 416 417 bzero(&probe, sizeof probe); 418 probe.parent = pci_bridgeto(bus); 419 probe.bus = bus; 420 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 421 int pcifunchigh = 0; 422 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 423 pcicfgregs *cfg = pci_readcfg(&probe); 424 if (cfg != NULL) { 425 if (cfg->mfdev) 426 pcifunchigh = 7; 427 /* 428 * XXX: Temporarily move pci_addcfg() up before 429 * the use of cfg->subordinatebus. This is 430 * necessary, since pci_addcfg() calls the 431 * device's probe(), which may read the bus# 432 * from some device dependent register of 433 * some host to PCI bridges. The probe will 434 * eventually be moved to pci_readcfg(), and 435 * pci_addcfg() will then be moved back down 436 * below the conditional statement ... 437 */ 438 pci_addcfg(cfg); 439 440 if (bushigh < cfg->subordinatebus) 441 bushigh = cfg->subordinatebus; 442 443 cfg = NULL; /* we don't own this anymore ... */ 444 } 445 } 446 } 447 return (bushigh); 448 } 449 450 /* scan a PCI bus tree reached through one PCI attachment point */ 451 452 int 453 pci_probe(pciattach *parent) 454 { 455 int bushigh; 456 int bus = 0; 457 458 bushigh = pci_bushigh(); 459 while (bus <= bushigh) { 460 int newbushigh; 461 462 printf("Probing for devices on PCI bus %d:\n", bus); 463 newbushigh = pci_probebus(bus); 464 465 if (bushigh < newbushigh) 466 bushigh = newbushigh; 467 bus++; 468 } 469 return (bushigh); 470 } 471 472 /* 473 * This is the user interface to PCI configuration space. 474 */ 475 476 static int 477 pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 478 { 479 if ((oflags & FWRITE) && securelevel > 0) { 480 return EPERM; 481 } 482 return 0; 483 } 484 485 static int 486 pci_close(dev_t dev, int flag, int devtype, struct proc *p) 487 { 488 return 0; 489 } 490 491 static int 492 pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p) 493 { 494 struct pci_conf_io *cio; 495 struct pci_io *io; 496 size_t iolen; 497 int error; 498 499 if (cmd != PCIOCGETCONF && !(flag & FWRITE)) 500 return EPERM; 501 502 switch(cmd) { 503 case PCIOCGETCONF: 504 #ifdef NOTYET 505 static struct pci_conf *pci_dev_list; 506 static unsigned pci_dev_list_count; 507 static unsigned pci_dev_list_size; 508 509 cio = (struct pci_conf_io *)data; 510 iolen = min(cio->pci_len, 511 pci_dev_list_count * sizeof(struct pci_conf)); 512 cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf); 513 514 error = copyout(pci_dev_list, cio->pci_buf, iolen); 515 #else 516 error = ENODEV; 517 #endif 518 break; 519 520 case PCIOCREAD: 521 io = (struct pci_io *)data; 522 switch(io->pi_width) { 523 pcicfgregs probe; 524 case 4: 525 case 2: 526 case 1: 527 probe.bus = io->pi_sel.pc_bus; 528 probe.slot = io->pi_sel.pc_dev; 529 probe.func = io->pi_sel.pc_func; 530 io->pi_data = pci_cfgread(&probe, 531 io->pi_reg, io->pi_width); 532 error = 0; 533 break; 534 default: 535 error = ENODEV; 536 break; 537 } 538 break; 539 540 case PCIOCWRITE: 541 io = (struct pci_io *)data; 542 switch(io->pi_width) { 543 pcicfgregs probe; 544 case 4: 545 case 2: 546 case 1: 547 probe.bus = io->pi_sel.pc_bus; 548 probe.slot = io->pi_sel.pc_dev; 549 probe.func = io->pi_sel.pc_func; 550 pci_cfgwrite(&probe, 551 io->pi_reg, io->pi_data, io->pi_width); 552 error = 0; 553 break; 554 default: 555 error = ENODEV; 556 break; 557 } 558 break; 559 560 default: 561 error = ENOTTY; 562 break; 563 } 564 565 return (error); 566 } 567 568 #define PCI_CDEV 78 569 570 static struct cdevsw pcicdev = { 571 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 572 nodevtotty, seltrue, nommap, nostrategy, "pci", 0, PCI_CDEV 573 }; 574 575 #ifdef DEVFS 576 static void *pci_devfs_token; 577 #endif 578 579 static void 580 pci_cdevinit(void *dummy) 581 { 582 dev_t dev; 583 584 dev = makedev(PCI_CDEV, 0); 585 cdevsw_add(&dev, &pcicdev, NULL); 586 #ifdef DEVFS 587 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 588 UID_ROOT, GID_WHEEL, 0644, "pci"); 589 #endif 590 } 591 592 SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 593 594 #endif /* NPCI > 0 */ 595