1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 #include <vm/vm_extern.h> 56 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 #include <machine/stdarg.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include "pcib_if.h" 85 #include "pci_if.h" 86 87 #define PCIR_IS_BIOS(cfg, reg) \ 88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 90 91 static device_probe_t pci_probe; 92 93 static bus_reset_post_t pci_reset_post; 94 static bus_reset_prepare_t pci_reset_prepare; 95 static bus_reset_child_t pci_reset_child; 96 static bus_hint_device_unit_t pci_hint_device_unit; 97 static bus_remap_intr_t pci_remap_intr_method; 98 99 static pci_get_id_t pci_get_id_method; 100 101 static int pci_has_quirk(uint32_t devid, int quirk); 102 static pci_addr_t pci_mapbase(uint64_t mapreg); 103 static const char *pci_maptype(uint64_t mapreg); 104 static int pci_maprange(uint64_t mapreg); 105 static pci_addr_t pci_rombase(uint64_t mapreg); 106 static int pci_romsize(uint64_t testval); 107 static void pci_fixancient(pcicfgregs *cfg); 108 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 109 110 static int pci_porten(device_t dev); 111 static int pci_memen(device_t dev); 112 static void pci_assign_interrupt(device_t bus, device_t dev, 113 int force_route); 114 static int pci_add_map(device_t bus, device_t dev, int reg, 115 struct resource_list *rl, int force, int prefetch); 116 static void pci_load_vendor_data(void); 117 static int pci_describe_parse_line(char **ptr, int *vendor, 118 int *device, char **desc); 119 static char *pci_describe_device(device_t dev); 120 static int pci_modevent(module_t mod, int what, void *arg); 121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 122 pcicfgregs *cfg); 123 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 124 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 125 int reg, uint32_t *data); 126 #if 0 127 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t data); 129 #endif 130 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 131 static void pci_mask_msix(device_t dev, u_int index); 132 static void pci_unmask_msix(device_t dev, u_int index); 133 static int pci_msi_blacklisted(void); 134 static int pci_msix_blacklisted(void); 135 static void pci_resume_msi(device_t dev); 136 static void pci_resume_msix(device_t dev); 137 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 138 int b, int s, int f, uint16_t vid, uint16_t did); 139 140 static device_method_t pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, pci_probe), 143 DEVMETHOD(device_attach, pci_attach), 144 DEVMETHOD(device_detach, pci_detach), 145 DEVMETHOD(device_shutdown, bus_generic_shutdown), 146 DEVMETHOD(device_suspend, bus_generic_suspend), 147 DEVMETHOD(device_resume, pci_resume), 148 149 /* Bus interface */ 150 DEVMETHOD(bus_print_child, pci_print_child), 151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 152 DEVMETHOD(bus_read_ivar, pci_read_ivar), 153 DEVMETHOD(bus_write_ivar, pci_write_ivar), 154 DEVMETHOD(bus_driver_added, pci_driver_added), 155 DEVMETHOD(bus_setup_intr, pci_setup_intr), 156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 157 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 158 DEVMETHOD(bus_reset_post, pci_reset_post), 159 DEVMETHOD(bus_reset_child, pci_reset_child), 160 161 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 162 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 163 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 164 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 165 DEVMETHOD(bus_delete_resource, pci_delete_resource), 166 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 167 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 168 DEVMETHOD(bus_release_resource, pci_release_resource), 169 DEVMETHOD(bus_activate_resource, pci_activate_resource), 170 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 171 DEVMETHOD(bus_map_resource, pci_map_resource), 172 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 173 DEVMETHOD(bus_child_deleted, pci_child_deleted), 174 DEVMETHOD(bus_child_detached, pci_child_detached), 175 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 176 DEVMETHOD(bus_child_location, pci_child_location_method), 177 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 178 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 179 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 180 DEVMETHOD(bus_suspend_child, pci_suspend_child), 181 DEVMETHOD(bus_resume_child, pci_resume_child), 182 DEVMETHOD(bus_rescan, pci_rescan_method), 183 184 /* PCI interface */ 185 DEVMETHOD(pci_read_config, pci_read_config_method), 186 DEVMETHOD(pci_write_config, pci_write_config_method), 187 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 188 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 189 DEVMETHOD(pci_enable_io, pci_enable_io_method), 190 DEVMETHOD(pci_disable_io, pci_disable_io_method), 191 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 192 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 193 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 194 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 195 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 196 DEVMETHOD(pci_find_cap, pci_find_cap_method), 197 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 198 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 199 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 200 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 201 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 202 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 203 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 204 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 205 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 206 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 207 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 208 DEVMETHOD(pci_release_msi, pci_release_msi_method), 209 DEVMETHOD(pci_msi_count, pci_msi_count_method), 210 DEVMETHOD(pci_msix_count, pci_msix_count_method), 211 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 212 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 213 DEVMETHOD(pci_get_id, pci_get_id_method), 214 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 215 DEVMETHOD(pci_child_added, pci_child_added_method), 216 #ifdef PCI_IOV 217 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 218 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 219 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 220 #endif 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 226 227 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 int arg1; 244 int arg2; 245 }; 246 247 static const struct pci_quirk pci_quirks[] = { 248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 249 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 250 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 252 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 254 /* 255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 256 * or the CMIC-SL (AKA ServerWorks GC_LE). 257 */ 258 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 259 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 261 /* 262 * MSI doesn't work on earlier Intel chipsets including 263 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 264 */ 265 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 273 /* 274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 275 * bridge. 276 */ 277 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 278 279 /* 280 * Some virtualization environments emulate an older chipset 281 * but support MSI just fine. QEMU uses the Intel 82440. 282 */ 283 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 284 285 /* 286 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 287 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 288 * It prevents us from attaching hpet(4) when the bit is unset. 289 * Note this quirk only affects SB600 revision A13 and earlier. 290 * For SB600 A21 and later, firmware must set the bit to hide it. 291 * For SB700 and later, it is unused and hardcoded to zero. 292 */ 293 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 294 295 /* 296 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 297 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 298 * of the command register is set. 299 */ 300 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 306 /* 307 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 308 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 309 */ 310 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 311 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 312 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 313 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 314 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 315 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 316 317 /* 318 * HPE Gen 10 VGA has a memory range that can't be allocated in the 319 * expected place. 320 */ 321 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 322 { 0 } 323 }; 324 325 /* map register information */ 326 #define PCI_MAPMEM 0x01 /* memory map */ 327 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 328 #define PCI_MAPPORT 0x04 /* port map */ 329 330 struct devlist pci_devq; 331 uint32_t pci_generation; 332 uint32_t pci_numdevs = 0; 333 static int pcie_chipset, pcix_chipset; 334 335 /* sysctl vars */ 336 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 337 "PCI bus tuning parameters"); 338 339 static int pci_enable_io_modes = 1; 340 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 341 &pci_enable_io_modes, 1, 342 "Enable I/O and memory bits in the config register. Some BIOSes do not" 343 " enable these bits correctly. We'd like to do this all the time, but" 344 " there are some peripherals that this causes problems with."); 345 346 static int pci_do_realloc_bars = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 348 &pci_do_realloc_bars, 0, 349 "Attempt to allocate a new range for any BARs whose original " 350 "firmware-assigned ranges fail to allocate during the initial device scan."); 351 352 static int pci_do_power_nodriver = 0; 353 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 354 &pci_do_power_nodriver, 0, 355 "Place a function into D3 state when no driver attaches to it. 0 means" 356 " disable. 1 means conservatively place function into D3 state. 2 means" 357 " aggressively place function into D3 state. 3 means put absolutely" 358 " everything in D3 state."); 359 360 int pci_do_power_resume = 1; 361 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 362 &pci_do_power_resume, 1, 363 "Transition from D3 -> D0 on resume."); 364 365 int pci_do_power_suspend = 1; 366 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 367 &pci_do_power_suspend, 1, 368 "Transition from D0 -> D3 on suspend."); 369 370 static int pci_do_msi = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 372 "Enable support for MSI interrupts"); 373 374 static int pci_do_msix = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 376 "Enable support for MSI-X interrupts"); 377 378 static int pci_msix_rewrite_table = 0; 379 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 380 &pci_msix_rewrite_table, 0, 381 "Rewrite entire MSI-X table when updating MSI-X entries"); 382 383 static int pci_honor_msi_blacklist = 1; 384 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 386 387 #if defined(__i386__) || defined(__amd64__) 388 static int pci_usb_takeover = 1; 389 #else 390 static int pci_usb_takeover = 0; 391 #endif 392 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 393 &pci_usb_takeover, 1, 394 "Enable early takeover of USB controllers. Disable this if you depend on" 395 " BIOS emulation of USB devices, that is you use USB devices (like" 396 " keyboard or mouse) but do not load USB drivers"); 397 398 static int pci_clear_bars; 399 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 400 "Ignore firmware-assigned resources for BARs."); 401 402 static int pci_clear_buses; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 404 "Ignore firmware-assigned bus numbers."); 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 /* 411 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 412 * however enabling it breaks some arm64 firmware as it powers off devices. 413 */ 414 #if defined(__i386__) || defined(__amd64__) 415 int pci_enable_aspm = 1; 416 #else 417 int pci_enable_aspm = 0; 418 #endif 419 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 420 0, "Enable support for PCIe Active State Power Management"); 421 422 static int pci_clear_aer_on_attach = 0; 423 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 424 &pci_clear_aer_on_attach, 0, 425 "Clear port and device AER state on driver attach"); 426 427 static bool pci_enable_mps_tune = true; 428 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 429 &pci_enable_mps_tune, 1, 430 "Enable tuning of MPS(maximum payload size)." ); 431 432 static int 433 pci_has_quirk(uint32_t devid, int quirk) 434 { 435 const struct pci_quirk *q; 436 437 for (q = &pci_quirks[0]; q->devid; q++) { 438 if (q->devid == devid && q->type == quirk) 439 return (1); 440 } 441 return (0); 442 } 443 444 /* Find a device_t by bus/slot/function in domain 0 */ 445 446 device_t 447 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 448 { 449 450 return (pci_find_dbsf(0, bus, slot, func)); 451 } 452 453 /* Find a device_t by domain/bus/slot/function */ 454 455 device_t 456 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 457 { 458 struct pci_devinfo *dinfo = NULL; 459 460 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 461 if ((dinfo->cfg.domain == domain) && 462 (dinfo->cfg.bus == bus) && 463 (dinfo->cfg.slot == slot) && 464 (dinfo->cfg.func == func)) { 465 break; 466 } 467 } 468 469 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 470 } 471 472 /* Find a device_t by vendor/device ID */ 473 474 device_t 475 pci_find_device(uint16_t vendor, uint16_t device) 476 { 477 struct pci_devinfo *dinfo; 478 479 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 480 if ((dinfo->cfg.vendor == vendor) && 481 (dinfo->cfg.device == device)) { 482 return (dinfo->cfg.dev); 483 } 484 } 485 486 return (NULL); 487 } 488 489 device_t 490 pci_find_class(uint8_t class, uint8_t subclass) 491 { 492 struct pci_devinfo *dinfo; 493 494 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 495 if (dinfo->cfg.baseclass == class && 496 dinfo->cfg.subclass == subclass) { 497 return (dinfo->cfg.dev); 498 } 499 } 500 501 return (NULL); 502 } 503 504 device_t 505 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 506 { 507 struct pci_devinfo *dinfo; 508 bool found = false; 509 510 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 511 if (from != NULL && found == false) { 512 if (from != dinfo->cfg.dev) 513 continue; 514 found = true; 515 continue; 516 } 517 if (dinfo->cfg.baseclass == class && 518 dinfo->cfg.subclass == subclass) { 519 return (dinfo->cfg.dev); 520 } 521 } 522 523 return (NULL); 524 } 525 526 device_t 527 pci_find_base_class_from(uint8_t class, device_t from) 528 { 529 struct pci_devinfo *dinfo; 530 bool found = false; 531 532 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 533 if (from != NULL && found == false) { 534 if (from != dinfo->cfg.dev) 535 continue; 536 found = true; 537 continue; 538 } 539 if (dinfo->cfg.baseclass == class) { 540 return (dinfo->cfg.dev); 541 } 542 } 543 544 return (NULL); 545 } 546 547 static int 548 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 549 { 550 va_list ap; 551 int retval; 552 553 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 554 cfg->func); 555 va_start(ap, fmt); 556 retval += vprintf(fmt, ap); 557 va_end(ap); 558 return (retval); 559 } 560 561 /* return base address of memory or port map */ 562 563 static pci_addr_t 564 pci_mapbase(uint64_t mapreg) 565 { 566 567 if (PCI_BAR_MEM(mapreg)) 568 return (mapreg & PCIM_BAR_MEM_BASE); 569 else 570 return (mapreg & PCIM_BAR_IO_BASE); 571 } 572 573 /* return map type of memory or port map */ 574 575 static const char * 576 pci_maptype(uint64_t mapreg) 577 { 578 579 if (PCI_BAR_IO(mapreg)) 580 return ("I/O Port"); 581 if (mapreg & PCIM_BAR_MEM_PREFETCH) 582 return ("Prefetchable Memory"); 583 return ("Memory"); 584 } 585 586 /* return log2 of map size decoded for memory or port map */ 587 588 int 589 pci_mapsize(uint64_t testval) 590 { 591 int ln2size; 592 593 testval = pci_mapbase(testval); 594 ln2size = 0; 595 if (testval != 0) { 596 while ((testval & 1) == 0) 597 { 598 ln2size++; 599 testval >>= 1; 600 } 601 } 602 return (ln2size); 603 } 604 605 /* return base address of device ROM */ 606 607 static pci_addr_t 608 pci_rombase(uint64_t mapreg) 609 { 610 611 return (mapreg & PCIM_BIOS_ADDR_MASK); 612 } 613 614 /* return log2 of map size decided for device ROM */ 615 616 static int 617 pci_romsize(uint64_t testval) 618 { 619 int ln2size; 620 621 testval = pci_rombase(testval); 622 ln2size = 0; 623 if (testval != 0) { 624 while ((testval & 1) == 0) 625 { 626 ln2size++; 627 testval >>= 1; 628 } 629 } 630 return (ln2size); 631 } 632 633 /* return log2 of address range supported by map register */ 634 635 static int 636 pci_maprange(uint64_t mapreg) 637 { 638 int ln2range = 0; 639 640 if (PCI_BAR_IO(mapreg)) 641 ln2range = 32; 642 else 643 switch (mapreg & PCIM_BAR_MEM_TYPE) { 644 case PCIM_BAR_MEM_32: 645 ln2range = 32; 646 break; 647 case PCIM_BAR_MEM_1MB: 648 ln2range = 20; 649 break; 650 case PCIM_BAR_MEM_64: 651 ln2range = 64; 652 break; 653 } 654 return (ln2range); 655 } 656 657 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 658 659 static void 660 pci_fixancient(pcicfgregs *cfg) 661 { 662 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 663 return; 664 665 /* PCI to PCI bridges use header type 1 */ 666 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 667 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 668 } 669 670 /* extract header type specific config data */ 671 672 static void 673 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 674 { 675 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 676 switch (cfg->hdrtype & PCIM_HDRTYPE) { 677 case PCIM_HDRTYPE_NORMAL: 678 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 679 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 680 cfg->mingnt = REG(PCIR_MINGNT, 1); 681 cfg->maxlat = REG(PCIR_MAXLAT, 1); 682 cfg->nummaps = PCI_MAXMAPS_0; 683 break; 684 case PCIM_HDRTYPE_BRIDGE: 685 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 686 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 687 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 688 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 689 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 690 cfg->nummaps = PCI_MAXMAPS_1; 691 break; 692 case PCIM_HDRTYPE_CARDBUS: 693 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 694 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 695 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 696 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 697 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 698 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 699 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 700 cfg->nummaps = PCI_MAXMAPS_2; 701 break; 702 } 703 #undef REG 704 } 705 706 /* read configuration header into pcicfgregs structure */ 707 struct pci_devinfo * 708 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 709 { 710 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 711 uint16_t vid, did; 712 713 vid = REG(PCIR_VENDOR, 2); 714 if (vid == PCIV_INVALID) 715 return (NULL); 716 717 did = REG(PCIR_DEVICE, 2); 718 719 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 720 } 721 722 struct pci_devinfo * 723 pci_alloc_devinfo_method(device_t dev) 724 { 725 726 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 727 M_WAITOK | M_ZERO)); 728 } 729 730 static struct pci_devinfo * 731 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 732 uint16_t vid, uint16_t did) 733 { 734 struct pci_devinfo *devlist_entry; 735 pcicfgregs *cfg; 736 737 devlist_entry = PCI_ALLOC_DEVINFO(bus); 738 739 cfg = &devlist_entry->cfg; 740 741 cfg->domain = d; 742 cfg->bus = b; 743 cfg->slot = s; 744 cfg->func = f; 745 cfg->vendor = vid; 746 cfg->device = did; 747 cfg->cmdreg = REG(PCIR_COMMAND, 2); 748 cfg->statreg = REG(PCIR_STATUS, 2); 749 cfg->baseclass = REG(PCIR_CLASS, 1); 750 cfg->subclass = REG(PCIR_SUBCLASS, 1); 751 cfg->progif = REG(PCIR_PROGIF, 1); 752 cfg->revid = REG(PCIR_REVID, 1); 753 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 754 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 755 cfg->lattimer = REG(PCIR_LATTIMER, 1); 756 cfg->intpin = REG(PCIR_INTPIN, 1); 757 cfg->intline = REG(PCIR_INTLINE, 1); 758 759 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 760 cfg->hdrtype &= ~PCIM_MFDEV; 761 STAILQ_INIT(&cfg->maps); 762 763 cfg->iov = NULL; 764 765 pci_fixancient(cfg); 766 pci_hdrtypedata(pcib, b, s, f, cfg); 767 768 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 769 pci_read_cap(pcib, cfg); 770 771 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 772 773 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 774 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 775 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 776 devlist_entry->conf.pc_sel.pc_func = cfg->func; 777 devlist_entry->conf.pc_hdr = cfg->hdrtype; 778 779 devlist_entry->conf.pc_subvendor = cfg->subvendor; 780 devlist_entry->conf.pc_subdevice = cfg->subdevice; 781 devlist_entry->conf.pc_vendor = cfg->vendor; 782 devlist_entry->conf.pc_device = cfg->device; 783 784 devlist_entry->conf.pc_class = cfg->baseclass; 785 devlist_entry->conf.pc_subclass = cfg->subclass; 786 devlist_entry->conf.pc_progif = cfg->progif; 787 devlist_entry->conf.pc_revid = cfg->revid; 788 789 pci_numdevs++; 790 pci_generation++; 791 792 return (devlist_entry); 793 } 794 #undef REG 795 796 static void 797 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 798 { 799 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 800 cfg->ea.ea_location + (n), w) 801 int num_ent; 802 int ptr; 803 int a, b; 804 uint32_t val; 805 int ent_size; 806 uint32_t dw[4]; 807 uint64_t base, max_offset; 808 struct pci_ea_entry *eae; 809 810 if (cfg->ea.ea_location == 0) 811 return; 812 813 STAILQ_INIT(&cfg->ea.ea_entries); 814 815 /* Determine the number of entries */ 816 num_ent = REG(PCIR_EA_NUM_ENT, 2); 817 num_ent &= PCIM_EA_NUM_ENT_MASK; 818 819 /* Find the first entry to care of */ 820 ptr = PCIR_EA_FIRST_ENT; 821 822 /* Skip DWORD 2 for type 1 functions */ 823 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 824 ptr += 4; 825 826 for (a = 0; a < num_ent; a++) { 827 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 828 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 829 830 /* Read a number of dwords in the entry */ 831 val = REG(ptr, 4); 832 ptr += 4; 833 ent_size = (val & PCIM_EA_ES); 834 835 for (b = 0; b < ent_size; b++) { 836 dw[b] = REG(ptr, 4); 837 ptr += 4; 838 } 839 840 eae->eae_flags = val; 841 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 842 843 base = dw[0] & PCIM_EA_FIELD_MASK; 844 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 845 b = 2; 846 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 847 base |= (uint64_t)dw[b] << 32UL; 848 b++; 849 } 850 if (((dw[1] & PCIM_EA_IS_64) != 0) 851 && (b < ent_size)) { 852 max_offset |= (uint64_t)dw[b] << 32UL; 853 b++; 854 } 855 856 eae->eae_base = base; 857 eae->eae_max_offset = max_offset; 858 859 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 860 861 if (bootverbose) { 862 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 863 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 864 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 865 } 866 } 867 } 868 #undef REG 869 870 static void 871 pci_read_cap(device_t pcib, pcicfgregs *cfg) 872 { 873 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 874 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 875 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 876 uint64_t addr; 877 #endif 878 uint32_t val; 879 int ptr, nextptr, ptrptr; 880 881 switch (cfg->hdrtype & PCIM_HDRTYPE) { 882 case PCIM_HDRTYPE_NORMAL: 883 case PCIM_HDRTYPE_BRIDGE: 884 ptrptr = PCIR_CAP_PTR; 885 break; 886 case PCIM_HDRTYPE_CARDBUS: 887 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 888 break; 889 default: 890 return; /* no extended capabilities support */ 891 } 892 nextptr = REG(ptrptr, 1); /* sanity check? */ 893 894 /* 895 * Read capability entries. 896 */ 897 while (nextptr != 0) { 898 /* Sanity check */ 899 if (nextptr > 255) { 900 printf("illegal PCI extended capability offset %d\n", 901 nextptr); 902 return; 903 } 904 /* Find the next entry */ 905 ptr = nextptr; 906 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 907 908 /* Process this entry */ 909 switch (REG(ptr + PCICAP_ID, 1)) { 910 case PCIY_PMG: /* PCI power management */ 911 cfg->pp.pp_location = ptr; 912 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 913 break; 914 case PCIY_HT: /* HyperTransport */ 915 /* Determine HT-specific capability type. */ 916 val = REG(ptr + PCIR_HT_COMMAND, 2); 917 918 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 919 cfg->ht.ht_slave = ptr; 920 921 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 922 switch (val & PCIM_HTCMD_CAP_MASK) { 923 case PCIM_HTCAP_MSI_MAPPING: 924 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 925 /* Sanity check the mapping window. */ 926 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 927 4); 928 addr <<= 32; 929 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 930 4); 931 if (addr != MSI_INTEL_ADDR_BASE) 932 device_printf(pcib, 933 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 934 cfg->domain, cfg->bus, 935 cfg->slot, cfg->func, 936 (long long)addr); 937 } else 938 addr = MSI_INTEL_ADDR_BASE; 939 940 cfg->ht.ht_msimap = ptr; 941 cfg->ht.ht_msictrl = val; 942 cfg->ht.ht_msiaddr = addr; 943 break; 944 } 945 #endif 946 break; 947 case PCIY_MSI: /* PCI MSI */ 948 cfg->msi.msi_location = ptr; 949 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 950 break; 951 case PCIY_MSIX: /* PCI MSI-X */ 952 cfg->msix.msix_location = ptr; 953 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 954 val = REG(ptr + PCIR_MSIX_TABLE, 4); 955 cfg->msix.msix_table_bar = PCIR_BAR(val & 956 PCIM_MSIX_BIR_MASK); 957 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 958 val = REG(ptr + PCIR_MSIX_PBA, 4); 959 cfg->msix.msix_pba_bar = PCIR_BAR(val & 960 PCIM_MSIX_BIR_MASK); 961 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 962 break; 963 case PCIY_VPD: /* PCI Vital Product Data */ 964 cfg->vpd.vpd_reg = ptr; 965 break; 966 case PCIY_SUBVENDOR: 967 /* Should always be true. */ 968 if ((cfg->hdrtype & PCIM_HDRTYPE) == 969 PCIM_HDRTYPE_BRIDGE) { 970 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 971 cfg->subvendor = val & 0xffff; 972 cfg->subdevice = val >> 16; 973 } 974 break; 975 case PCIY_PCIX: /* PCI-X */ 976 /* 977 * Assume we have a PCI-X chipset if we have 978 * at least one PCI-PCI bridge with a PCI-X 979 * capability. Note that some systems with 980 * PCI-express or HT chipsets might match on 981 * this check as well. 982 */ 983 if ((cfg->hdrtype & PCIM_HDRTYPE) == 984 PCIM_HDRTYPE_BRIDGE) 985 pcix_chipset = 1; 986 cfg->pcix.pcix_location = ptr; 987 break; 988 case PCIY_EXPRESS: /* PCI-express */ 989 /* 990 * Assume we have a PCI-express chipset if we have 991 * at least one PCI-express device. 992 */ 993 pcie_chipset = 1; 994 cfg->pcie.pcie_location = ptr; 995 val = REG(ptr + PCIER_FLAGS, 2); 996 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 997 break; 998 case PCIY_EA: /* Enhanced Allocation */ 999 cfg->ea.ea_location = ptr; 1000 pci_ea_fill_info(pcib, cfg); 1001 break; 1002 default: 1003 break; 1004 } 1005 } 1006 1007 #if defined(__powerpc__) 1008 /* 1009 * Enable the MSI mapping window for all HyperTransport 1010 * slaves. PCI-PCI bridges have their windows enabled via 1011 * PCIB_MAP_MSI(). 1012 */ 1013 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1014 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1015 device_printf(pcib, 1016 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1017 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1018 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1019 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1020 2); 1021 } 1022 #endif 1023 /* REG and WREG use carry through to next functions */ 1024 } 1025 1026 /* 1027 * PCI Vital Product Data 1028 */ 1029 1030 #define PCI_VPD_TIMEOUT 1000000 1031 1032 static int 1033 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1034 { 1035 int count = PCI_VPD_TIMEOUT; 1036 1037 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1038 1039 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1040 1041 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1042 if (--count < 0) 1043 return (ENXIO); 1044 DELAY(1); /* limit looping */ 1045 } 1046 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1047 1048 return (0); 1049 } 1050 1051 #if 0 1052 static int 1053 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1054 { 1055 int count = PCI_VPD_TIMEOUT; 1056 1057 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1058 1059 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1060 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1061 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1062 if (--count < 0) 1063 return (ENXIO); 1064 DELAY(1); /* limit looping */ 1065 } 1066 1067 return (0); 1068 } 1069 #endif 1070 1071 #undef PCI_VPD_TIMEOUT 1072 1073 struct vpd_readstate { 1074 device_t pcib; 1075 pcicfgregs *cfg; 1076 uint32_t val; 1077 int bytesinval; 1078 int off; 1079 uint8_t cksum; 1080 }; 1081 1082 /* return 0 and one byte in *data if no read error, -1 else */ 1083 static int 1084 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1085 { 1086 uint32_t reg; 1087 uint8_t byte; 1088 1089 if (vrs->bytesinval == 0) { 1090 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1091 return (-1); 1092 vrs->val = le32toh(reg); 1093 vrs->off += 4; 1094 byte = vrs->val & 0xff; 1095 vrs->bytesinval = 3; 1096 } else { 1097 vrs->val = vrs->val >> 8; 1098 byte = vrs->val & 0xff; 1099 vrs->bytesinval--; 1100 } 1101 1102 vrs->cksum += byte; 1103 *data = byte; 1104 return (0); 1105 } 1106 1107 /* return 0 on match, -1 and "unget" byte on no match */ 1108 static int 1109 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1110 { 1111 uint8_t data; 1112 1113 if (vpd_nextbyte(vrs, &data) != 0) 1114 return (-1); 1115 1116 if (data == expected) 1117 return (0); 1118 1119 vrs->cksum -= data; 1120 vrs->val = (vrs->val << 8) + data; 1121 vrs->bytesinval++; 1122 return (-1); 1123 } 1124 1125 /* return size if tag matches, -1 on no match, -2 on read error */ 1126 static int 1127 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1128 { 1129 uint8_t byte1, byte2; 1130 1131 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1132 return (-1); 1133 1134 if ((vpd_tag & 0x80) == 0) 1135 return (vpd_tag & 0x07); 1136 1137 if (vpd_nextbyte(vrs, &byte1) != 0) 1138 return (-2); 1139 if (vpd_nextbyte(vrs, &byte2) != 0) 1140 return (-2); 1141 1142 return ((byte2 << 8) + byte1); 1143 } 1144 1145 /* (re)allocate buffer in multiples of 8 elements */ 1146 static void* 1147 alloc_buffer(void* buffer, size_t element_size, int needed) 1148 { 1149 int alloc, new_alloc; 1150 1151 alloc = roundup2(needed, 8); 1152 new_alloc = roundup2(needed + 1, 8); 1153 if (alloc != new_alloc) { 1154 buffer = reallocf(buffer, 1155 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1156 } 1157 1158 return (buffer); 1159 } 1160 1161 /* read VPD keyword and return element size, return -1 on read error */ 1162 static int 1163 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1164 { 1165 uint8_t data; 1166 1167 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1168 return (-1); 1169 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1170 return (-1); 1171 if (vpd_nextbyte(vrs, &data) != 0) 1172 return (-1); 1173 1174 return (data); 1175 } 1176 1177 /* read VPD data element of given size into allocated buffer */ 1178 static char * 1179 vpd_read_value(struct vpd_readstate *vrs, int size) 1180 { 1181 int i; 1182 char char1; 1183 char *value; 1184 1185 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1186 for (i = 0; i < size; i++) { 1187 if (vpd_nextbyte(vrs, &char1) != 0) { 1188 free(value, M_DEVBUF); 1189 return (NULL); 1190 } 1191 value[i] = char1; 1192 } 1193 value[size] = '\0'; 1194 1195 return (value); 1196 } 1197 1198 /* read VPD into *keyword and *value, return length of data element */ 1199 static int 1200 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1201 { 1202 int len; 1203 1204 len = vpd_read_elem_head(vrs, keyword); 1205 if (len < 0 || len > maxlen) 1206 return (-1); 1207 *value = vpd_read_value(vrs, len); 1208 1209 return (len); 1210 } 1211 1212 /* subtract all data following first byte from checksum of RV element */ 1213 static void 1214 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1215 { 1216 int i; 1217 uint8_t fixup; 1218 1219 fixup = 0; 1220 for (i = 1; i < len; i++) 1221 fixup += rvstring[i]; 1222 vrs->cksum -= fixup; 1223 } 1224 1225 /* fetch one read-only element and return size of heading + data */ 1226 static int 1227 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1228 { 1229 struct pcicfg_vpd *vpd; 1230 pcicfgregs *cfg; 1231 struct vpd_readonly *vpd_ros; 1232 int len; 1233 1234 cfg = vrs->cfg; 1235 vpd = &cfg->vpd; 1236 1237 if (maxsize < 3) 1238 return (-1); 1239 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1240 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1241 maxsize -= 3; 1242 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1243 if (vpd_ros->value == NULL) 1244 return (-1); 1245 vpd_ros->len = len; 1246 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1247 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1248 if (vrs->cksum != 0) { 1249 pci_printf(cfg, 1250 "invalid VPD checksum %#hhx\n", vrs->cksum); 1251 return (-1); 1252 } 1253 } 1254 vpd->vpd_rocnt++; 1255 1256 return (len + 3); 1257 } 1258 1259 /* fetch one writable element and return size of heading + data */ 1260 static int 1261 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1262 { 1263 struct pcicfg_vpd *vpd; 1264 pcicfgregs *cfg; 1265 struct vpd_write *vpd_w; 1266 int len; 1267 1268 cfg = vrs->cfg; 1269 vpd = &cfg->vpd; 1270 1271 if (maxsize < 3) 1272 return (-1); 1273 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1274 if (vpd->vpd_w == NULL) { 1275 pci_printf(cfg, "out of memory"); 1276 return (-1); 1277 } 1278 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1279 maxsize -= 3; 1280 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1281 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1282 if (vpd_w->value == NULL) 1283 return (-1); 1284 vpd_w->len = len; 1285 vpd->vpd_wcnt++; 1286 1287 return (len + 3); 1288 } 1289 1290 /* free all memory allocated for VPD data */ 1291 static void 1292 vpd_free(struct pcicfg_vpd *vpd) 1293 { 1294 int i; 1295 1296 free(vpd->vpd_ident, M_DEVBUF); 1297 for (i = 0; i < vpd->vpd_rocnt; i++) 1298 free(vpd->vpd_ros[i].value, M_DEVBUF); 1299 free(vpd->vpd_ros, M_DEVBUF); 1300 vpd->vpd_rocnt = 0; 1301 for (i = 0; i < vpd->vpd_wcnt; i++) 1302 free(vpd->vpd_w[i].value, M_DEVBUF); 1303 free(vpd->vpd_w, M_DEVBUF); 1304 vpd->vpd_wcnt = 0; 1305 } 1306 1307 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1308 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1309 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1310 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1311 1312 static int 1313 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1314 { 1315 struct vpd_readstate vrs; 1316 int cksumvalid; 1317 int size, elem_size; 1318 1319 /* init vpd reader */ 1320 vrs.bytesinval = 0; 1321 vrs.off = 0; 1322 vrs.pcib = pcib; 1323 vrs.cfg = cfg; 1324 vrs.cksum = 0; 1325 1326 /* read VPD ident element - mandatory */ 1327 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1328 if (size <= 0) { 1329 pci_printf(cfg, "no VPD ident found\n"); 1330 return (0); 1331 } 1332 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1333 if (cfg->vpd.vpd_ident == NULL) { 1334 pci_printf(cfg, "error accessing VPD ident data\n"); 1335 return (0); 1336 } 1337 1338 /* read VPD RO elements - mandatory */ 1339 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1340 if (size <= 0) { 1341 pci_printf(cfg, "no read-only VPD data found\n"); 1342 return (0); 1343 } 1344 while (size > 0) { 1345 elem_size = next_vpd_ro_elem(&vrs, size); 1346 if (elem_size < 0) { 1347 pci_printf(cfg, "error accessing read-only VPD data\n"); 1348 return (-1); 1349 } 1350 size -= elem_size; 1351 } 1352 cksumvalid = (vrs.cksum == 0); 1353 if (!cksumvalid) 1354 return (-1); 1355 1356 /* read VPD RW elements - optional */ 1357 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1358 if (size == -2) 1359 return (-1); 1360 while (size > 0) { 1361 elem_size = next_vpd_rw_elem(&vrs, size); 1362 if (elem_size < 0) { 1363 pci_printf(cfg, "error accessing writeable VPD data\n"); 1364 return (-1); 1365 } 1366 size -= elem_size; 1367 } 1368 1369 /* read empty END tag - mandatory */ 1370 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1371 if (size != 0) { 1372 pci_printf(cfg, "No valid VPD end tag found\n"); 1373 } 1374 return (0); 1375 } 1376 1377 static void 1378 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1379 { 1380 int status; 1381 1382 status = pci_parse_vpd(pcib, cfg); 1383 if (status < 0) 1384 vpd_free(&cfg->vpd); 1385 cfg->vpd.vpd_cached = 1; 1386 #undef REG 1387 #undef WREG 1388 } 1389 1390 int 1391 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1392 { 1393 struct pci_devinfo *dinfo = device_get_ivars(child); 1394 pcicfgregs *cfg = &dinfo->cfg; 1395 1396 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1397 pci_read_vpd(device_get_parent(dev), cfg); 1398 1399 *identptr = cfg->vpd.vpd_ident; 1400 1401 if (*identptr == NULL) 1402 return (ENXIO); 1403 1404 return (0); 1405 } 1406 1407 int 1408 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1409 const char **vptr) 1410 { 1411 struct pci_devinfo *dinfo = device_get_ivars(child); 1412 pcicfgregs *cfg = &dinfo->cfg; 1413 int i; 1414 1415 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1416 pci_read_vpd(device_get_parent(dev), cfg); 1417 1418 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1419 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1420 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1421 *vptr = cfg->vpd.vpd_ros[i].value; 1422 return (0); 1423 } 1424 1425 *vptr = NULL; 1426 return (ENXIO); 1427 } 1428 1429 struct pcicfg_vpd * 1430 pci_fetch_vpd_list(device_t dev) 1431 { 1432 struct pci_devinfo *dinfo = device_get_ivars(dev); 1433 pcicfgregs *cfg = &dinfo->cfg; 1434 1435 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1436 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1437 return (&cfg->vpd); 1438 } 1439 1440 /* 1441 * Find the requested HyperTransport capability and return the offset 1442 * in configuration space via the pointer provided. The function 1443 * returns 0 on success and an error code otherwise. 1444 */ 1445 int 1446 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1447 { 1448 int ptr, error; 1449 uint16_t val; 1450 1451 error = pci_find_cap(child, PCIY_HT, &ptr); 1452 if (error) 1453 return (error); 1454 1455 /* 1456 * Traverse the capabilities list checking each HT capability 1457 * to see if it matches the requested HT capability. 1458 */ 1459 for (;;) { 1460 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1461 if (capability == PCIM_HTCAP_SLAVE || 1462 capability == PCIM_HTCAP_HOST) 1463 val &= 0xe000; 1464 else 1465 val &= PCIM_HTCMD_CAP_MASK; 1466 if (val == capability) { 1467 if (capreg != NULL) 1468 *capreg = ptr; 1469 return (0); 1470 } 1471 1472 /* Skip to the next HT capability. */ 1473 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1474 break; 1475 } 1476 1477 return (ENOENT); 1478 } 1479 1480 /* 1481 * Find the next requested HyperTransport capability after start and return 1482 * the offset in configuration space via the pointer provided. The function 1483 * returns 0 on success and an error code otherwise. 1484 */ 1485 int 1486 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1487 int start, int *capreg) 1488 { 1489 int ptr; 1490 uint16_t val; 1491 1492 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1493 ("start capability is not HyperTransport capability")); 1494 ptr = start; 1495 1496 /* 1497 * Traverse the capabilities list checking each HT capability 1498 * to see if it matches the requested HT capability. 1499 */ 1500 for (;;) { 1501 /* Skip to the next HT capability. */ 1502 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1503 break; 1504 1505 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1506 if (capability == PCIM_HTCAP_SLAVE || 1507 capability == PCIM_HTCAP_HOST) 1508 val &= 0xe000; 1509 else 1510 val &= PCIM_HTCMD_CAP_MASK; 1511 if (val == capability) { 1512 if (capreg != NULL) 1513 *capreg = ptr; 1514 return (0); 1515 } 1516 } 1517 1518 return (ENOENT); 1519 } 1520 1521 /* 1522 * Find the requested capability and return the offset in 1523 * configuration space via the pointer provided. The function returns 1524 * 0 on success and an error code otherwise. 1525 */ 1526 int 1527 pci_find_cap_method(device_t dev, device_t child, int capability, 1528 int *capreg) 1529 { 1530 struct pci_devinfo *dinfo = device_get_ivars(child); 1531 pcicfgregs *cfg = &dinfo->cfg; 1532 uint32_t status; 1533 uint8_t ptr; 1534 int cnt; 1535 1536 /* 1537 * Check the CAP_LIST bit of the PCI status register first. 1538 */ 1539 status = pci_read_config(child, PCIR_STATUS, 2); 1540 if (!(status & PCIM_STATUS_CAPPRESENT)) 1541 return (ENXIO); 1542 1543 /* 1544 * Determine the start pointer of the capabilities list. 1545 */ 1546 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1547 case PCIM_HDRTYPE_NORMAL: 1548 case PCIM_HDRTYPE_BRIDGE: 1549 ptr = PCIR_CAP_PTR; 1550 break; 1551 case PCIM_HDRTYPE_CARDBUS: 1552 ptr = PCIR_CAP_PTR_2; 1553 break; 1554 default: 1555 /* XXX: panic? */ 1556 return (ENXIO); /* no extended capabilities support */ 1557 } 1558 ptr = pci_read_config(child, ptr, 1); 1559 1560 /* 1561 * Traverse the capabilities list. Limit by total theoretical 1562 * maximum number of caps: capability needs at least id and 1563 * next registers, and any type X header cannot contain caps. 1564 */ 1565 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1566 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1567 if (capreg != NULL) 1568 *capreg = ptr; 1569 return (0); 1570 } 1571 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1572 } 1573 1574 return (ENOENT); 1575 } 1576 1577 /* 1578 * Find the next requested capability after start and return the offset in 1579 * configuration space via the pointer provided. The function returns 1580 * 0 on success and an error code otherwise. 1581 */ 1582 int 1583 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1584 int start, int *capreg) 1585 { 1586 uint8_t ptr; 1587 1588 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1589 ("start capability is not expected capability")); 1590 1591 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1592 while (ptr != 0) { 1593 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1594 if (capreg != NULL) 1595 *capreg = ptr; 1596 return (0); 1597 } 1598 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1599 } 1600 1601 return (ENOENT); 1602 } 1603 1604 /* 1605 * Find the requested extended capability and return the offset in 1606 * configuration space via the pointer provided. The function returns 1607 * 0 on success and an error code otherwise. 1608 */ 1609 int 1610 pci_find_extcap_method(device_t dev, device_t child, int capability, 1611 int *capreg) 1612 { 1613 struct pci_devinfo *dinfo = device_get_ivars(child); 1614 pcicfgregs *cfg = &dinfo->cfg; 1615 uint32_t ecap; 1616 uint16_t ptr; 1617 1618 /* Only supported for PCI-express devices. */ 1619 if (cfg->pcie.pcie_location == 0) 1620 return (ENXIO); 1621 1622 ptr = PCIR_EXTCAP; 1623 ecap = pci_read_config(child, ptr, 4); 1624 if (ecap == 0xffffffff || ecap == 0) 1625 return (ENOENT); 1626 for (;;) { 1627 if (PCI_EXTCAP_ID(ecap) == capability) { 1628 if (capreg != NULL) 1629 *capreg = ptr; 1630 return (0); 1631 } 1632 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1633 if (ptr == 0) 1634 break; 1635 ecap = pci_read_config(child, ptr, 4); 1636 } 1637 1638 return (ENOENT); 1639 } 1640 1641 /* 1642 * Find the next requested extended capability after start and return the 1643 * offset in configuration space via the pointer provided. The function 1644 * returns 0 on success and an error code otherwise. 1645 */ 1646 int 1647 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1648 int start, int *capreg) 1649 { 1650 struct pci_devinfo *dinfo = device_get_ivars(child); 1651 pcicfgregs *cfg = &dinfo->cfg; 1652 uint32_t ecap; 1653 uint16_t ptr; 1654 1655 /* Only supported for PCI-express devices. */ 1656 if (cfg->pcie.pcie_location == 0) 1657 return (ENXIO); 1658 1659 ecap = pci_read_config(child, start, 4); 1660 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1661 ("start extended capability is not expected capability")); 1662 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1663 while (ptr != 0) { 1664 ecap = pci_read_config(child, ptr, 4); 1665 if (PCI_EXTCAP_ID(ecap) == capability) { 1666 if (capreg != NULL) 1667 *capreg = ptr; 1668 return (0); 1669 } 1670 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1671 } 1672 1673 return (ENOENT); 1674 } 1675 1676 /* 1677 * Support for MSI-X message interrupts. 1678 */ 1679 static void 1680 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1681 { 1682 struct pci_devinfo *dinfo = device_get_ivars(dev); 1683 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1684 uint32_t offset; 1685 1686 KASSERT(msix->msix_table_len > index, ("bogus index")); 1687 offset = msix->msix_table_offset + index * 16; 1688 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1689 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1690 bus_write_4(msix->msix_table_res, offset + 8, data); 1691 } 1692 1693 void 1694 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1695 uint64_t address, uint32_t data) 1696 { 1697 1698 if (pci_msix_rewrite_table) { 1699 struct pci_devinfo *dinfo = device_get_ivars(child); 1700 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1701 1702 /* 1703 * Some VM hosts require MSIX to be disabled in the 1704 * control register before updating the MSIX table 1705 * entries are allowed. It is not enough to only 1706 * disable MSIX while updating a single entry. MSIX 1707 * must be disabled while updating all entries in the 1708 * table. 1709 */ 1710 pci_write_config(child, 1711 msix->msix_location + PCIR_MSIX_CTRL, 1712 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1713 pci_resume_msix(child); 1714 } else 1715 pci_write_msix_entry(child, index, address, data); 1716 1717 /* Enable MSI -> HT mapping. */ 1718 pci_ht_map_msi(child, address); 1719 } 1720 1721 void 1722 pci_mask_msix(device_t dev, u_int index) 1723 { 1724 struct pci_devinfo *dinfo = device_get_ivars(dev); 1725 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1726 uint32_t offset, val; 1727 1728 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1729 offset = msix->msix_table_offset + index * 16 + 12; 1730 val = bus_read_4(msix->msix_table_res, offset); 1731 val |= PCIM_MSIX_VCTRL_MASK; 1732 1733 /* 1734 * Some devices (e.g. Samsung PM961) do not support reads of this 1735 * register, so always write the new value. 1736 */ 1737 bus_write_4(msix->msix_table_res, offset, val); 1738 } 1739 1740 void 1741 pci_unmask_msix(device_t dev, u_int index) 1742 { 1743 struct pci_devinfo *dinfo = device_get_ivars(dev); 1744 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1745 uint32_t offset, val; 1746 1747 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1748 offset = msix->msix_table_offset + index * 16 + 12; 1749 val = bus_read_4(msix->msix_table_res, offset); 1750 val &= ~PCIM_MSIX_VCTRL_MASK; 1751 1752 /* 1753 * Some devices (e.g. Samsung PM961) do not support reads of this 1754 * register, so always write the new value. 1755 */ 1756 bus_write_4(msix->msix_table_res, offset, val); 1757 } 1758 1759 int 1760 pci_pending_msix(device_t dev, u_int index) 1761 { 1762 struct pci_devinfo *dinfo = device_get_ivars(dev); 1763 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1764 uint32_t offset, bit; 1765 1766 KASSERT(msix->msix_table_len > index, ("bogus index")); 1767 offset = msix->msix_pba_offset + (index / 32) * 4; 1768 bit = 1 << index % 32; 1769 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1770 } 1771 1772 /* 1773 * Restore MSI-X registers and table during resume. If MSI-X is 1774 * enabled then walk the virtual table to restore the actual MSI-X 1775 * table. 1776 */ 1777 static void 1778 pci_resume_msix(device_t dev) 1779 { 1780 struct pci_devinfo *dinfo = device_get_ivars(dev); 1781 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1782 struct msix_table_entry *mte; 1783 struct msix_vector *mv; 1784 u_int i, msgnum; 1785 1786 if (msix->msix_alloc > 0) { 1787 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); 1788 1789 /* First, mask all vectors. */ 1790 for (i = 0; i < msgnum; i++) 1791 pci_mask_msix(dev, i); 1792 1793 /* Second, program any messages with at least one handler. */ 1794 for (i = 0; i < msix->msix_table_len; i++) { 1795 mte = &msix->msix_table[i]; 1796 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1797 continue; 1798 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1799 pci_write_msix_entry(dev, i, mv->mv_address, 1800 mv->mv_data); 1801 pci_unmask_msix(dev, i); 1802 } 1803 } 1804 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1805 msix->msix_ctrl, 2); 1806 } 1807 1808 /* 1809 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1810 * returned in *count. After this function returns, each message will be 1811 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1812 */ 1813 int 1814 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1815 { 1816 struct pci_devinfo *dinfo = device_get_ivars(child); 1817 pcicfgregs *cfg = &dinfo->cfg; 1818 struct resource_list_entry *rle; 1819 u_int actual, i, max; 1820 int error, irq; 1821 uint16_t ctrl, msgnum; 1822 1823 /* Don't let count == 0 get us into trouble. */ 1824 if (*count < 1) 1825 return (EINVAL); 1826 1827 /* If rid 0 is allocated, then fail. */ 1828 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1829 if (rle != NULL && rle->res != NULL) 1830 return (ENXIO); 1831 1832 /* Already have allocated messages? */ 1833 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1834 return (ENXIO); 1835 1836 /* If MSI-X is blacklisted for this system, fail. */ 1837 if (pci_msix_blacklisted()) 1838 return (ENXIO); 1839 1840 /* MSI-X capability present? */ 1841 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1842 return (ENODEV); 1843 1844 /* Make sure the appropriate BARs are mapped. */ 1845 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1846 cfg->msix.msix_table_bar); 1847 if (rle == NULL || rle->res == NULL || 1848 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1849 return (ENXIO); 1850 cfg->msix.msix_table_res = rle->res; 1851 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1852 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1853 cfg->msix.msix_pba_bar); 1854 if (rle == NULL || rle->res == NULL || 1855 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1856 return (ENXIO); 1857 } 1858 cfg->msix.msix_pba_res = rle->res; 1859 1860 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1861 2); 1862 msgnum = PCI_MSIX_MSGNUM(ctrl); 1863 if (bootverbose) 1864 device_printf(child, 1865 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1866 *count, msgnum); 1867 max = min(*count, msgnum); 1868 for (i = 0; i < max; i++) { 1869 /* Allocate a message. */ 1870 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1871 if (error) { 1872 if (i == 0) 1873 return (error); 1874 break; 1875 } 1876 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1877 irq, 1); 1878 } 1879 actual = i; 1880 1881 if (bootverbose) { 1882 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1883 if (actual == 1) 1884 device_printf(child, "using IRQ %ju for MSI-X\n", 1885 rle->start); 1886 else { 1887 bool run; 1888 1889 /* 1890 * Be fancy and try to print contiguous runs of 1891 * IRQ values as ranges. 'irq' is the previous IRQ. 1892 * 'run' is true if we are in a range. 1893 */ 1894 device_printf(child, "using IRQs %ju", rle->start); 1895 irq = rle->start; 1896 run = false; 1897 for (i = 1; i < actual; i++) { 1898 rle = resource_list_find(&dinfo->resources, 1899 SYS_RES_IRQ, i + 1); 1900 1901 /* Still in a run? */ 1902 if (rle->start == irq + 1) { 1903 run = true; 1904 irq++; 1905 continue; 1906 } 1907 1908 /* Finish previous range. */ 1909 if (run) { 1910 printf("-%d", irq); 1911 run = false; 1912 } 1913 1914 /* Start new range. */ 1915 printf(",%ju", rle->start); 1916 irq = rle->start; 1917 } 1918 1919 /* Unfinished range? */ 1920 if (run) 1921 printf("-%d", irq); 1922 printf(" for MSI-X\n"); 1923 } 1924 } 1925 1926 /* Mask all vectors. */ 1927 for (i = 0; i < msgnum; i++) 1928 pci_mask_msix(child, i); 1929 1930 /* Allocate and initialize vector data and virtual table. */ 1931 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), 1932 M_DEVBUF, M_WAITOK | M_ZERO); 1933 cfg->msix.msix_table = mallocarray(actual, 1934 sizeof(struct msix_table_entry), M_DEVBUF, M_WAITOK | M_ZERO); 1935 for (i = 0; i < actual; i++) { 1936 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1937 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1938 cfg->msix.msix_table[i].mte_vector = i + 1; 1939 } 1940 1941 /* Update control register to enable MSI-X. */ 1942 ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1943 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1944 ctrl, 2); 1945 cfg->msix.msix_ctrl = ctrl; 1946 1947 /* Update counts of alloc'd messages. */ 1948 cfg->msix.msix_alloc = actual; 1949 cfg->msix.msix_table_len = actual; 1950 *count = actual; 1951 return (0); 1952 } 1953 1954 /* 1955 * By default, pci_alloc_msix() will assign the allocated IRQ 1956 * resources consecutively to the first N messages in the MSI-X table. 1957 * However, device drivers may want to use different layouts if they 1958 * either receive fewer messages than they asked for, or they wish to 1959 * populate the MSI-X table sparsely. This method allows the driver 1960 * to specify what layout it wants. It must be called after a 1961 * successful pci_alloc_msix() but before any of the associated 1962 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1963 * 1964 * The 'vectors' array contains 'count' message vectors. The array 1965 * maps directly to the MSI-X table in that index 0 in the array 1966 * specifies the vector for the first message in the MSI-X table, etc. 1967 * The vector value in each array index can either be 0 to indicate 1968 * that no vector should be assigned to a message slot, or it can be a 1969 * number from 1 to N (where N is the count returned from a 1970 * succcessful call to pci_alloc_msix()) to indicate which message 1971 * vector (IRQ) to be used for the corresponding message. 1972 * 1973 * On successful return, each message with a non-zero vector will have 1974 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1975 * 1. Additionally, if any of the IRQs allocated via the previous 1976 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1977 * will be freed back to the system automatically. 1978 * 1979 * For example, suppose a driver has a MSI-X table with 6 messages and 1980 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1981 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1982 * C. After the call to pci_alloc_msix(), the device will be setup to 1983 * have an MSI-X table of ABC--- (where - means no vector assigned). 1984 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1985 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1986 * be freed back to the system. This device will also have valid 1987 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1988 * 1989 * In any case, the SYS_RES_IRQ rid X will always map to the message 1990 * at MSI-X table index X - 1 and will only be valid if a vector is 1991 * assigned to that table entry. 1992 */ 1993 int 1994 pci_remap_msix_method(device_t dev, device_t child, int count, 1995 const u_int *vectors) 1996 { 1997 struct pci_devinfo *dinfo = device_get_ivars(child); 1998 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1999 struct resource_list_entry *rle; 2000 u_int i, irq, j; 2001 bool *used; 2002 2003 /* 2004 * Have to have at least one message in the table but the 2005 * table can't be bigger than the actual MSI-X table in the 2006 * device. 2007 */ 2008 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) 2009 return (EINVAL); 2010 2011 /* Sanity check the vectors. */ 2012 for (i = 0; i < count; i++) 2013 if (vectors[i] > msix->msix_alloc) 2014 return (EINVAL); 2015 2016 /* 2017 * Make sure there aren't any holes in the vectors to be used. 2018 * It's a big pain to support it, and it doesn't really make 2019 * sense anyway. Also, at least one vector must be used. 2020 */ 2021 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | 2022 M_ZERO); 2023 for (i = 0; i < count; i++) 2024 if (vectors[i] != 0) 2025 used[vectors[i] - 1] = true; 2026 for (i = 0; i < msix->msix_alloc - 1; i++) 2027 if (!used[i] && used[i + 1]) { 2028 free(used, M_DEVBUF); 2029 return (EINVAL); 2030 } 2031 if (!used[0]) { 2032 free(used, M_DEVBUF); 2033 return (EINVAL); 2034 } 2035 2036 /* Make sure none of the resources are allocated. */ 2037 for (i = 0; i < msix->msix_table_len; i++) { 2038 if (msix->msix_table[i].mte_vector == 0) 2039 continue; 2040 if (msix->msix_table[i].mte_handlers > 0) { 2041 free(used, M_DEVBUF); 2042 return (EBUSY); 2043 } 2044 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2045 KASSERT(rle != NULL, ("missing resource")); 2046 if (rle->res != NULL) { 2047 free(used, M_DEVBUF); 2048 return (EBUSY); 2049 } 2050 } 2051 2052 /* Free the existing resource list entries. */ 2053 for (i = 0; i < msix->msix_table_len; i++) { 2054 if (msix->msix_table[i].mte_vector == 0) 2055 continue; 2056 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2057 } 2058 2059 /* 2060 * Build the new virtual table keeping track of which vectors are 2061 * used. 2062 */ 2063 free(msix->msix_table, M_DEVBUF); 2064 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), 2065 M_DEVBUF, M_WAITOK | M_ZERO); 2066 for (i = 0; i < count; i++) 2067 msix->msix_table[i].mte_vector = vectors[i]; 2068 msix->msix_table_len = count; 2069 2070 /* Free any unused IRQs and resize the vectors array if necessary. */ 2071 j = msix->msix_alloc - 1; 2072 if (!used[j]) { 2073 struct msix_vector *vec; 2074 2075 while (!used[j]) { 2076 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2077 msix->msix_vectors[j].mv_irq); 2078 j--; 2079 } 2080 vec = mallocarray(j + 1, sizeof(struct msix_vector), M_DEVBUF, 2081 M_WAITOK); 2082 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2083 (j + 1)); 2084 free(msix->msix_vectors, M_DEVBUF); 2085 msix->msix_vectors = vec; 2086 msix->msix_alloc = j + 1; 2087 } 2088 free(used, M_DEVBUF); 2089 2090 /* Map the IRQs onto the rids. */ 2091 for (i = 0; i < count; i++) { 2092 if (vectors[i] == 0) 2093 continue; 2094 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2095 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2096 irq, 1); 2097 } 2098 2099 if (bootverbose) { 2100 device_printf(child, "Remapped MSI-X IRQs as: "); 2101 for (i = 0; i < count; i++) { 2102 if (i != 0) 2103 printf(", "); 2104 if (vectors[i] == 0) 2105 printf("---"); 2106 else 2107 printf("%d", 2108 msix->msix_vectors[vectors[i] - 1].mv_irq); 2109 } 2110 printf("\n"); 2111 } 2112 2113 return (0); 2114 } 2115 2116 static int 2117 pci_release_msix(device_t dev, device_t child) 2118 { 2119 struct pci_devinfo *dinfo = device_get_ivars(child); 2120 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2121 struct resource_list_entry *rle; 2122 u_int i; 2123 2124 /* Do we have any messages to release? */ 2125 if (msix->msix_alloc == 0) 2126 return (ENODEV); 2127 2128 /* Make sure none of the resources are allocated. */ 2129 for (i = 0; i < msix->msix_table_len; i++) { 2130 if (msix->msix_table[i].mte_vector == 0) 2131 continue; 2132 if (msix->msix_table[i].mte_handlers > 0) 2133 return (EBUSY); 2134 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2135 KASSERT(rle != NULL, ("missing resource")); 2136 if (rle->res != NULL) 2137 return (EBUSY); 2138 } 2139 2140 /* Update control register to disable MSI-X. */ 2141 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2142 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2143 msix->msix_ctrl, 2); 2144 2145 /* Free the resource list entries. */ 2146 for (i = 0; i < msix->msix_table_len; i++) { 2147 if (msix->msix_table[i].mte_vector == 0) 2148 continue; 2149 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2150 } 2151 free(msix->msix_table, M_DEVBUF); 2152 msix->msix_table_len = 0; 2153 2154 /* Release the IRQs. */ 2155 for (i = 0; i < msix->msix_alloc; i++) 2156 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2157 msix->msix_vectors[i].mv_irq); 2158 free(msix->msix_vectors, M_DEVBUF); 2159 msix->msix_alloc = 0; 2160 return (0); 2161 } 2162 2163 /* 2164 * Return the max supported MSI-X messages this device supports. 2165 * Basically, assuming the MD code can alloc messages, this function 2166 * should return the maximum value that pci_alloc_msix() can return. 2167 * Thus, it is subject to the tunables, etc. 2168 */ 2169 int 2170 pci_msix_count_method(device_t dev, device_t child) 2171 { 2172 struct pci_devinfo *dinfo = device_get_ivars(child); 2173 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2174 uint16_t ctrl; 2175 2176 if (pci_do_msix && msix->msix_location != 0) { 2177 ctrl = pci_read_config(child, msix->msix_location + 2178 PCIR_MSI_CTRL, 2); 2179 return (PCI_MSIX_MSGNUM(ctrl)); 2180 } 2181 return (0); 2182 } 2183 2184 int 2185 pci_msix_pba_bar_method(device_t dev, device_t child) 2186 { 2187 struct pci_devinfo *dinfo = device_get_ivars(child); 2188 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2189 2190 if (pci_do_msix && msix->msix_location != 0) 2191 return (msix->msix_pba_bar); 2192 return (-1); 2193 } 2194 2195 int 2196 pci_msix_table_bar_method(device_t dev, device_t child) 2197 { 2198 struct pci_devinfo *dinfo = device_get_ivars(child); 2199 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2200 2201 if (pci_do_msix && msix->msix_location != 0) 2202 return (msix->msix_table_bar); 2203 return (-1); 2204 } 2205 2206 /* 2207 * HyperTransport MSI mapping control 2208 */ 2209 void 2210 pci_ht_map_msi(device_t dev, uint64_t addr) 2211 { 2212 struct pci_devinfo *dinfo = device_get_ivars(dev); 2213 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2214 2215 if (!ht->ht_msimap) 2216 return; 2217 2218 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2219 ht->ht_msiaddr >> 20 == addr >> 20) { 2220 /* Enable MSI -> HT mapping. */ 2221 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2222 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2223 ht->ht_msictrl, 2); 2224 } 2225 2226 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2227 /* Disable MSI -> HT mapping. */ 2228 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2229 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2230 ht->ht_msictrl, 2); 2231 } 2232 } 2233 2234 int 2235 pci_get_relaxed_ordering_enabled(device_t dev) 2236 { 2237 struct pci_devinfo *dinfo = device_get_ivars(dev); 2238 int cap; 2239 uint16_t val; 2240 2241 cap = dinfo->cfg.pcie.pcie_location; 2242 if (cap == 0) 2243 return (0); 2244 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2245 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2246 return (val != 0); 2247 } 2248 2249 int 2250 pci_get_max_payload(device_t dev) 2251 { 2252 struct pci_devinfo *dinfo = device_get_ivars(dev); 2253 int cap; 2254 uint16_t val; 2255 2256 cap = dinfo->cfg.pcie.pcie_location; 2257 if (cap == 0) 2258 return (0); 2259 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2260 val &= PCIEM_CTL_MAX_PAYLOAD; 2261 val >>= 5; 2262 return (1 << (val + 7)); 2263 } 2264 2265 int 2266 pci_get_max_read_req(device_t dev) 2267 { 2268 struct pci_devinfo *dinfo = device_get_ivars(dev); 2269 int cap; 2270 uint16_t val; 2271 2272 cap = dinfo->cfg.pcie.pcie_location; 2273 if (cap == 0) 2274 return (0); 2275 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2276 val &= PCIEM_CTL_MAX_READ_REQUEST; 2277 val >>= 12; 2278 return (1 << (val + 7)); 2279 } 2280 2281 int 2282 pci_set_max_read_req(device_t dev, int size) 2283 { 2284 struct pci_devinfo *dinfo = device_get_ivars(dev); 2285 int cap; 2286 uint16_t val; 2287 2288 cap = dinfo->cfg.pcie.pcie_location; 2289 if (cap == 0) 2290 return (0); 2291 if (size < 128) 2292 size = 128; 2293 if (size > 4096) 2294 size = 4096; 2295 size = (1 << (fls(size) - 1)); 2296 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2297 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2298 val |= (fls(size) - 8) << 12; 2299 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2300 return (size); 2301 } 2302 2303 uint32_t 2304 pcie_read_config(device_t dev, int reg, int width) 2305 { 2306 struct pci_devinfo *dinfo = device_get_ivars(dev); 2307 int cap; 2308 2309 cap = dinfo->cfg.pcie.pcie_location; 2310 if (cap == 0) { 2311 if (width == 2) 2312 return (0xffff); 2313 return (0xffffffff); 2314 } 2315 2316 return (pci_read_config(dev, cap + reg, width)); 2317 } 2318 2319 void 2320 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2321 { 2322 struct pci_devinfo *dinfo = device_get_ivars(dev); 2323 int cap; 2324 2325 cap = dinfo->cfg.pcie.pcie_location; 2326 if (cap == 0) 2327 return; 2328 pci_write_config(dev, cap + reg, value, width); 2329 } 2330 2331 /* 2332 * Adjusts a PCI-e capability register by clearing the bits in mask 2333 * and setting the bits in (value & mask). Bits not set in mask are 2334 * not adjusted. 2335 * 2336 * Returns the old value on success or all ones on failure. 2337 */ 2338 uint32_t 2339 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2340 int width) 2341 { 2342 struct pci_devinfo *dinfo = device_get_ivars(dev); 2343 uint32_t old, new; 2344 int cap; 2345 2346 cap = dinfo->cfg.pcie.pcie_location; 2347 if (cap == 0) { 2348 if (width == 2) 2349 return (0xffff); 2350 return (0xffffffff); 2351 } 2352 2353 old = pci_read_config(dev, cap + reg, width); 2354 new = old & ~mask; 2355 new |= (value & mask); 2356 pci_write_config(dev, cap + reg, new, width); 2357 return (old); 2358 } 2359 2360 /* 2361 * Support for MSI message signalled interrupts. 2362 */ 2363 void 2364 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2365 uint16_t data) 2366 { 2367 struct pci_devinfo *dinfo = device_get_ivars(child); 2368 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2369 2370 /* Write data and address values. */ 2371 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2372 address & 0xffffffff, 4); 2373 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2374 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2375 address >> 32, 4); 2376 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2377 data, 2); 2378 } else 2379 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2380 2); 2381 2382 /* Enable MSI in the control register. */ 2383 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2384 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2385 msi->msi_ctrl, 2); 2386 2387 /* Enable MSI -> HT mapping. */ 2388 pci_ht_map_msi(child, address); 2389 } 2390 2391 void 2392 pci_disable_msi_method(device_t dev, device_t child) 2393 { 2394 struct pci_devinfo *dinfo = device_get_ivars(child); 2395 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2396 2397 /* Disable MSI -> HT mapping. */ 2398 pci_ht_map_msi(child, 0); 2399 2400 /* Disable MSI in the control register. */ 2401 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2402 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2403 msi->msi_ctrl, 2); 2404 } 2405 2406 /* 2407 * Restore MSI registers during resume. If MSI is enabled then 2408 * restore the data and address registers in addition to the control 2409 * register. 2410 */ 2411 static void 2412 pci_resume_msi(device_t dev) 2413 { 2414 struct pci_devinfo *dinfo = device_get_ivars(dev); 2415 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2416 uint64_t address; 2417 uint16_t data; 2418 2419 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2420 address = msi->msi_addr; 2421 data = msi->msi_data; 2422 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2423 address & 0xffffffff, 4); 2424 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2425 pci_write_config(dev, msi->msi_location + 2426 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2427 pci_write_config(dev, msi->msi_location + 2428 PCIR_MSI_DATA_64BIT, data, 2); 2429 } else 2430 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2431 data, 2); 2432 } 2433 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2434 2); 2435 } 2436 2437 static int 2438 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2439 { 2440 struct pci_devinfo *dinfo = device_get_ivars(dev); 2441 pcicfgregs *cfg = &dinfo->cfg; 2442 struct resource_list_entry *rle; 2443 struct msix_table_entry *mte; 2444 struct msix_vector *mv; 2445 uint64_t addr; 2446 uint32_t data; 2447 u_int i, j; 2448 int error; 2449 2450 /* 2451 * Handle MSI first. We try to find this IRQ among our list 2452 * of MSI IRQs. If we find it, we request updated address and 2453 * data registers and apply the results. 2454 */ 2455 if (cfg->msi.msi_alloc > 0) { 2456 /* If we don't have any active handlers, nothing to do. */ 2457 if (cfg->msi.msi_handlers == 0) 2458 return (0); 2459 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2460 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2461 i + 1); 2462 if (rle->start == irq) { 2463 error = PCIB_MAP_MSI(device_get_parent(bus), 2464 dev, irq, &addr, &data); 2465 if (error) 2466 return (error); 2467 pci_disable_msi(dev); 2468 dinfo->cfg.msi.msi_addr = addr; 2469 dinfo->cfg.msi.msi_data = data; 2470 pci_enable_msi(dev, addr, data); 2471 return (0); 2472 } 2473 } 2474 return (ENOENT); 2475 } 2476 2477 /* 2478 * For MSI-X, we check to see if we have this IRQ. If we do, 2479 * we request the updated mapping info. If that works, we go 2480 * through all the slots that use this IRQ and update them. 2481 */ 2482 if (cfg->msix.msix_alloc > 0) { 2483 bool found = false; 2484 2485 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2486 mv = &cfg->msix.msix_vectors[i]; 2487 if (mv->mv_irq == irq) { 2488 error = PCIB_MAP_MSI(device_get_parent(bus), 2489 dev, irq, &addr, &data); 2490 if (error) 2491 return (error); 2492 mv->mv_address = addr; 2493 mv->mv_data = data; 2494 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2495 mte = &cfg->msix.msix_table[j]; 2496 if (mte->mte_vector != i + 1) 2497 continue; 2498 if (mte->mte_handlers == 0) 2499 continue; 2500 pci_mask_msix(dev, j); 2501 pci_enable_msix(dev, j, addr, data); 2502 pci_unmask_msix(dev, j); 2503 } 2504 found = true; 2505 } 2506 } 2507 return (found ? 0 : ENOENT); 2508 } 2509 2510 return (ENOENT); 2511 } 2512 2513 /* 2514 * Returns true if the specified device is blacklisted because MSI 2515 * doesn't work. 2516 */ 2517 int 2518 pci_msi_device_blacklisted(device_t dev) 2519 { 2520 2521 if (!pci_honor_msi_blacklist) 2522 return (0); 2523 2524 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2525 } 2526 2527 /* 2528 * Determine if MSI is blacklisted globally on this system. Currently, 2529 * we just check for blacklisted chipsets as represented by the 2530 * host-PCI bridge at device 0:0:0. In the future, it may become 2531 * necessary to check other system attributes, such as the kenv values 2532 * that give the motherboard manufacturer and model number. 2533 */ 2534 static int 2535 pci_msi_blacklisted(void) 2536 { 2537 device_t dev; 2538 2539 if (!pci_honor_msi_blacklist) 2540 return (0); 2541 2542 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2543 if (!(pcie_chipset || pcix_chipset)) { 2544 if (vm_guest != VM_GUEST_NO) { 2545 /* 2546 * Whitelist older chipsets in virtual 2547 * machines known to support MSI. 2548 */ 2549 dev = pci_find_bsf(0, 0, 0); 2550 if (dev != NULL) 2551 return (!pci_has_quirk(pci_get_devid(dev), 2552 PCI_QUIRK_ENABLE_MSI_VM)); 2553 } 2554 return (1); 2555 } 2556 2557 dev = pci_find_bsf(0, 0, 0); 2558 if (dev != NULL) 2559 return (pci_msi_device_blacklisted(dev)); 2560 return (0); 2561 } 2562 2563 /* 2564 * Returns true if the specified device is blacklisted because MSI-X 2565 * doesn't work. Note that this assumes that if MSI doesn't work, 2566 * MSI-X doesn't either. 2567 */ 2568 int 2569 pci_msix_device_blacklisted(device_t dev) 2570 { 2571 2572 if (!pci_honor_msi_blacklist) 2573 return (0); 2574 2575 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2576 return (1); 2577 2578 return (pci_msi_device_blacklisted(dev)); 2579 } 2580 2581 /* 2582 * Determine if MSI-X is blacklisted globally on this system. If MSI 2583 * is blacklisted, assume that MSI-X is as well. Check for additional 2584 * chipsets where MSI works but MSI-X does not. 2585 */ 2586 static int 2587 pci_msix_blacklisted(void) 2588 { 2589 device_t dev; 2590 2591 if (!pci_honor_msi_blacklist) 2592 return (0); 2593 2594 dev = pci_find_bsf(0, 0, 0); 2595 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2596 PCI_QUIRK_DISABLE_MSIX)) 2597 return (1); 2598 2599 return (pci_msi_blacklisted()); 2600 } 2601 2602 /* 2603 * Attempt to allocate *count MSI messages. The actual number allocated is 2604 * returned in *count. After this function returns, each message will be 2605 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2606 */ 2607 int 2608 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2609 { 2610 struct pci_devinfo *dinfo = device_get_ivars(child); 2611 pcicfgregs *cfg = &dinfo->cfg; 2612 struct resource_list_entry *rle; 2613 u_int actual, i; 2614 int error, irqs[32]; 2615 uint16_t ctrl, msgnum; 2616 2617 /* Don't let count == 0 get us into trouble. */ 2618 if (*count < 1) 2619 return (EINVAL); 2620 2621 /* If rid 0 is allocated, then fail. */ 2622 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2623 if (rle != NULL && rle->res != NULL) 2624 return (ENXIO); 2625 2626 /* Already have allocated messages? */ 2627 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2628 return (ENXIO); 2629 2630 /* If MSI is blacklisted for this system, fail. */ 2631 if (pci_msi_blacklisted()) 2632 return (ENXIO); 2633 2634 /* MSI capability present? */ 2635 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2636 return (ENODEV); 2637 2638 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); 2639 msgnum = PCI_MSI_MSGNUM(ctrl); 2640 if (bootverbose) 2641 device_printf(child, 2642 "attempting to allocate %d MSI vectors (%u supported)\n", 2643 *count, msgnum); 2644 2645 /* Don't ask for more than the device supports. */ 2646 actual = min(*count, msgnum); 2647 2648 /* Don't ask for more than 32 messages. */ 2649 actual = min(actual, 32); 2650 2651 /* MSI requires power of 2 number of messages. */ 2652 if (!powerof2(actual)) 2653 return (EINVAL); 2654 2655 for (;;) { 2656 /* Try to allocate N messages. */ 2657 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2658 actual, irqs); 2659 if (error == 0) 2660 break; 2661 if (actual == 1) 2662 return (error); 2663 2664 /* Try N / 2. */ 2665 actual >>= 1; 2666 } 2667 2668 /* 2669 * We now have N actual messages mapped onto SYS_RES_IRQ 2670 * resources in the irqs[] array, so add new resources 2671 * starting at rid 1. 2672 */ 2673 for (i = 0; i < actual; i++) 2674 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2675 irqs[i], irqs[i], 1); 2676 2677 if (bootverbose) { 2678 if (actual == 1) 2679 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2680 else { 2681 bool run; 2682 2683 /* 2684 * Be fancy and try to print contiguous runs 2685 * of IRQ values as ranges. 'run' is true if 2686 * we are in a range. 2687 */ 2688 device_printf(child, "using IRQs %d", irqs[0]); 2689 run = false; 2690 for (i = 1; i < actual; i++) { 2691 /* Still in a run? */ 2692 if (irqs[i] == irqs[i - 1] + 1) { 2693 run = true; 2694 continue; 2695 } 2696 2697 /* Finish previous range. */ 2698 if (run) { 2699 printf("-%d", irqs[i - 1]); 2700 run = false; 2701 } 2702 2703 /* Start new range. */ 2704 printf(",%d", irqs[i]); 2705 } 2706 2707 /* Unfinished range? */ 2708 if (run) 2709 printf("-%d", irqs[actual - 1]); 2710 printf(" for MSI\n"); 2711 } 2712 } 2713 2714 /* Update control register with actual count. */ 2715 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2716 ctrl |= (ffs(actual) - 1) << 4; 2717 cfg->msi.msi_ctrl = ctrl; 2718 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2719 2720 /* Update counts of alloc'd messages. */ 2721 cfg->msi.msi_alloc = actual; 2722 cfg->msi.msi_handlers = 0; 2723 *count = actual; 2724 return (0); 2725 } 2726 2727 /* Release the MSI messages associated with this device. */ 2728 int 2729 pci_release_msi_method(device_t dev, device_t child) 2730 { 2731 struct pci_devinfo *dinfo = device_get_ivars(child); 2732 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2733 struct resource_list_entry *rle; 2734 u_int i, irqs[32]; 2735 int error; 2736 2737 /* Try MSI-X first. */ 2738 error = pci_release_msix(dev, child); 2739 if (error != ENODEV) 2740 return (error); 2741 2742 /* Do we have any messages to release? */ 2743 if (msi->msi_alloc == 0) 2744 return (ENODEV); 2745 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2746 2747 /* Make sure none of the resources are allocated. */ 2748 if (msi->msi_handlers > 0) 2749 return (EBUSY); 2750 for (i = 0; i < msi->msi_alloc; i++) { 2751 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2752 KASSERT(rle != NULL, ("missing MSI resource")); 2753 if (rle->res != NULL) 2754 return (EBUSY); 2755 irqs[i] = rle->start; 2756 } 2757 2758 /* Update control register with 0 count. */ 2759 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2760 ("%s: MSI still enabled", __func__)); 2761 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2762 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2763 msi->msi_ctrl, 2); 2764 2765 /* Release the messages. */ 2766 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2767 for (i = 0; i < msi->msi_alloc; i++) 2768 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2769 2770 /* Update alloc count. */ 2771 msi->msi_alloc = 0; 2772 msi->msi_addr = 0; 2773 msi->msi_data = 0; 2774 return (0); 2775 } 2776 2777 /* 2778 * Return the max supported MSI messages this device supports. 2779 * Basically, assuming the MD code can alloc messages, this function 2780 * should return the maximum value that pci_alloc_msi() can return. 2781 * Thus, it is subject to the tunables, etc. 2782 */ 2783 int 2784 pci_msi_count_method(device_t dev, device_t child) 2785 { 2786 struct pci_devinfo *dinfo = device_get_ivars(child); 2787 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2788 uint16_t ctrl; 2789 2790 if (pci_do_msi && msi->msi_location != 0) { 2791 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, 2792 2); 2793 return (PCI_MSI_MSGNUM(ctrl)); 2794 } 2795 return (0); 2796 } 2797 2798 /* free pcicfgregs structure and all depending data structures */ 2799 2800 int 2801 pci_freecfg(struct pci_devinfo *dinfo) 2802 { 2803 struct devlist *devlist_head; 2804 struct pci_map *pm, *next; 2805 2806 devlist_head = &pci_devq; 2807 2808 if (dinfo->cfg.vpd.vpd_reg) 2809 vpd_free(&dinfo->cfg.vpd); 2810 2811 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2812 free(pm, M_DEVBUF); 2813 } 2814 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2815 free(dinfo, M_DEVBUF); 2816 2817 /* increment the generation count */ 2818 pci_generation++; 2819 2820 /* we're losing one device */ 2821 pci_numdevs--; 2822 return (0); 2823 } 2824 2825 /* 2826 * PCI power manangement 2827 */ 2828 int 2829 pci_set_powerstate_method(device_t dev, device_t child, int state) 2830 { 2831 struct pci_devinfo *dinfo = device_get_ivars(child); 2832 pcicfgregs *cfg = &dinfo->cfg; 2833 uint16_t status; 2834 int oldstate, highest, delay; 2835 2836 if (cfg->pp.pp_location == 0) 2837 return (EOPNOTSUPP); 2838 2839 /* 2840 * Optimize a no state change request away. While it would be OK to 2841 * write to the hardware in theory, some devices have shown odd 2842 * behavior when going from D3 -> D3. 2843 */ 2844 oldstate = pci_get_powerstate(child); 2845 if (oldstate == state) 2846 return (0); 2847 2848 /* 2849 * The PCI power management specification states that after a state 2850 * transition between PCI power states, system software must 2851 * guarantee a minimal delay before the function accesses the device. 2852 * Compute the worst case delay that we need to guarantee before we 2853 * access the device. Many devices will be responsive much more 2854 * quickly than this delay, but there are some that don't respond 2855 * instantly to state changes. Transitions to/from D3 state require 2856 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2857 * is done below with DELAY rather than a sleeper function because 2858 * this function can be called from contexts where we cannot sleep. 2859 */ 2860 highest = (oldstate > state) ? oldstate : state; 2861 if (highest == PCI_POWERSTATE_D3) 2862 delay = 10000; 2863 else if (highest == PCI_POWERSTATE_D2) 2864 delay = 200; 2865 else 2866 delay = 0; 2867 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2868 PCIR_POWER_STATUS, 2) & ~PCIM_PSTAT_DMASK; 2869 switch (state) { 2870 case PCI_POWERSTATE_D0: 2871 status |= PCIM_PSTAT_D0; 2872 break; 2873 case PCI_POWERSTATE_D1: 2874 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2875 return (EOPNOTSUPP); 2876 status |= PCIM_PSTAT_D1; 2877 break; 2878 case PCI_POWERSTATE_D2: 2879 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2880 return (EOPNOTSUPP); 2881 status |= PCIM_PSTAT_D2; 2882 break; 2883 case PCI_POWERSTATE_D3: 2884 status |= PCIM_PSTAT_D3; 2885 break; 2886 default: 2887 return (EINVAL); 2888 } 2889 2890 if (bootverbose) 2891 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2892 state); 2893 2894 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, 2895 status, 2); 2896 if (delay) 2897 DELAY(delay); 2898 return (0); 2899 } 2900 2901 int 2902 pci_get_powerstate_method(device_t dev, device_t child) 2903 { 2904 struct pci_devinfo *dinfo = device_get_ivars(child); 2905 pcicfgregs *cfg = &dinfo->cfg; 2906 uint16_t status; 2907 int result; 2908 2909 if (cfg->pp.pp_location != 0) { 2910 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2911 PCIR_POWER_STATUS, 2); 2912 switch (status & PCIM_PSTAT_DMASK) { 2913 case PCIM_PSTAT_D0: 2914 result = PCI_POWERSTATE_D0; 2915 break; 2916 case PCIM_PSTAT_D1: 2917 result = PCI_POWERSTATE_D1; 2918 break; 2919 case PCIM_PSTAT_D2: 2920 result = PCI_POWERSTATE_D2; 2921 break; 2922 case PCIM_PSTAT_D3: 2923 result = PCI_POWERSTATE_D3; 2924 break; 2925 default: 2926 result = PCI_POWERSTATE_UNKNOWN; 2927 break; 2928 } 2929 } else { 2930 /* No support, device is always at D0 */ 2931 result = PCI_POWERSTATE_D0; 2932 } 2933 return (result); 2934 } 2935 2936 /* Clear any active PME# and disable PME# generation. */ 2937 void 2938 pci_clear_pme(device_t dev) 2939 { 2940 struct pci_devinfo *dinfo = device_get_ivars(dev); 2941 pcicfgregs *cfg = &dinfo->cfg; 2942 uint16_t status; 2943 2944 if (cfg->pp.pp_location != 0) { 2945 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2946 PCIR_POWER_STATUS, 2); 2947 status &= ~PCIM_PSTAT_PMEENABLE; 2948 status |= PCIM_PSTAT_PME; 2949 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2950 PCIR_POWER_STATUS, status, 2); 2951 } 2952 } 2953 2954 /* Clear any active PME# and enable PME# generation. */ 2955 void 2956 pci_enable_pme(device_t dev) 2957 { 2958 struct pci_devinfo *dinfo = device_get_ivars(dev); 2959 pcicfgregs *cfg = &dinfo->cfg; 2960 uint16_t status; 2961 2962 if (cfg->pp.pp_location != 0) { 2963 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2964 PCIR_POWER_STATUS, 2); 2965 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2966 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2967 PCIR_POWER_STATUS, status, 2); 2968 } 2969 } 2970 2971 bool 2972 pci_has_pm(device_t dev) 2973 { 2974 struct pci_devinfo *dinfo = device_get_ivars(dev); 2975 pcicfgregs *cfg = &dinfo->cfg; 2976 2977 return (cfg->pp.pp_location != 0); 2978 } 2979 2980 /* 2981 * Some convenience functions for PCI device drivers. 2982 */ 2983 2984 static __inline void 2985 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2986 { 2987 uint16_t command; 2988 2989 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2990 command |= bit; 2991 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2992 } 2993 2994 static __inline void 2995 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2996 { 2997 uint16_t command; 2998 2999 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3000 command &= ~bit; 3001 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3002 } 3003 3004 int 3005 pci_enable_busmaster_method(device_t dev, device_t child) 3006 { 3007 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3008 return (0); 3009 } 3010 3011 int 3012 pci_disable_busmaster_method(device_t dev, device_t child) 3013 { 3014 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3015 return (0); 3016 } 3017 3018 int 3019 pci_enable_io_method(device_t dev, device_t child, int space) 3020 { 3021 uint16_t bit; 3022 3023 switch(space) { 3024 case SYS_RES_IOPORT: 3025 bit = PCIM_CMD_PORTEN; 3026 break; 3027 case SYS_RES_MEMORY: 3028 bit = PCIM_CMD_MEMEN; 3029 break; 3030 default: 3031 return (EINVAL); 3032 } 3033 pci_set_command_bit(dev, child, bit); 3034 return (0); 3035 } 3036 3037 int 3038 pci_disable_io_method(device_t dev, device_t child, int space) 3039 { 3040 uint16_t bit; 3041 3042 switch(space) { 3043 case SYS_RES_IOPORT: 3044 bit = PCIM_CMD_PORTEN; 3045 break; 3046 case SYS_RES_MEMORY: 3047 bit = PCIM_CMD_MEMEN; 3048 break; 3049 default: 3050 return (EINVAL); 3051 } 3052 pci_clear_command_bit(dev, child, bit); 3053 return (0); 3054 } 3055 3056 /* 3057 * New style pci driver. Parent device is either a pci-host-bridge or a 3058 * pci-pci-bridge. Both kinds are represented by instances of pcib. 3059 */ 3060 3061 void 3062 pci_print_verbose(struct pci_devinfo *dinfo) 3063 { 3064 3065 if (bootverbose) { 3066 pcicfgregs *cfg = &dinfo->cfg; 3067 3068 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 3069 cfg->vendor, cfg->device, cfg->revid); 3070 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 3071 cfg->domain, cfg->bus, cfg->slot, cfg->func); 3072 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 3073 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 3074 cfg->mfdev); 3075 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 3076 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 3077 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 3078 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3079 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3080 if (cfg->intpin > 0) 3081 printf("\tintpin=%c, irq=%d\n", 3082 cfg->intpin +'a' -1, cfg->intline); 3083 if (cfg->pp.pp_location) { 3084 uint16_t status; 3085 3086 status = pci_read_config(cfg->dev, cfg->pp.pp_location + 3087 PCIR_POWER_STATUS, 2); 3088 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3089 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3090 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3091 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3092 status & PCIM_PSTAT_DMASK); 3093 } 3094 if (cfg->msi.msi_location) { 3095 uint16_t ctrl, msgnum; 3096 3097 ctrl = cfg->msi.msi_ctrl; 3098 msgnum = PCI_MSI_MSGNUM(ctrl); 3099 printf("\tMSI supports %d message%s%s%s\n", 3100 msgnum, (msgnum == 1) ? "" : "s", 3101 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3102 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3103 } 3104 if (cfg->msix.msix_location) { 3105 uint16_t msgnum; 3106 3107 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); 3108 printf("\tMSI-X supports %d message%s ", 3109 msgnum, (msgnum == 1) ? "" : "s"); 3110 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3111 printf("in map 0x%x\n", 3112 cfg->msix.msix_table_bar); 3113 else 3114 printf("in maps 0x%x and 0x%x\n", 3115 cfg->msix.msix_table_bar, 3116 cfg->msix.msix_pba_bar); 3117 } 3118 } 3119 } 3120 3121 static int 3122 pci_porten(device_t dev) 3123 { 3124 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3125 } 3126 3127 static int 3128 pci_memen(device_t dev) 3129 { 3130 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3131 } 3132 3133 void 3134 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3135 int *bar64) 3136 { 3137 struct pci_devinfo *dinfo; 3138 pci_addr_t map, testval; 3139 int ln2range; 3140 uint16_t cmd; 3141 3142 /* 3143 * The device ROM BAR is special. It is always a 32-bit 3144 * memory BAR. Bit 0 is special and should not be set when 3145 * sizing the BAR. 3146 */ 3147 dinfo = device_get_ivars(dev); 3148 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3149 map = pci_read_config(dev, reg, 4); 3150 pci_write_config(dev, reg, 0xfffffffe, 4); 3151 testval = pci_read_config(dev, reg, 4); 3152 pci_write_config(dev, reg, map, 4); 3153 *mapp = map; 3154 *testvalp = testval; 3155 if (bar64 != NULL) 3156 *bar64 = 0; 3157 return; 3158 } 3159 3160 map = pci_read_config(dev, reg, 4); 3161 ln2range = pci_maprange(map); 3162 if (ln2range == 64) 3163 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3164 3165 /* 3166 * Disable decoding via the command register before 3167 * determining the BAR's length since we will be placing it in 3168 * a weird state. 3169 */ 3170 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3171 pci_write_config(dev, PCIR_COMMAND, 3172 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3173 3174 /* 3175 * Determine the BAR's length by writing all 1's. The bottom 3176 * log_2(size) bits of the BAR will stick as 0 when we read 3177 * the value back. 3178 * 3179 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3180 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3181 * and combines the result into a 64-bit value." (section 6.2.5.1) 3182 * 3183 * Writes to both registers must be performed before attempting to 3184 * read back the size value. 3185 */ 3186 testval = 0; 3187 pci_write_config(dev, reg, 0xffffffff, 4); 3188 if (ln2range == 64) { 3189 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3190 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3191 } 3192 testval |= pci_read_config(dev, reg, 4); 3193 3194 /* 3195 * Restore the original value of the BAR. We may have reprogrammed 3196 * the BAR of the low-level console device and when booting verbose, 3197 * we need the console device addressable. 3198 */ 3199 pci_write_config(dev, reg, map, 4); 3200 if (ln2range == 64) 3201 pci_write_config(dev, reg + 4, map >> 32, 4); 3202 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3203 3204 *mapp = map; 3205 *testvalp = testval; 3206 if (bar64 != NULL) 3207 *bar64 = (ln2range == 64); 3208 } 3209 3210 static void 3211 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3212 { 3213 struct pci_devinfo *dinfo; 3214 int ln2range; 3215 3216 /* The device ROM BAR is always a 32-bit memory BAR. */ 3217 dinfo = device_get_ivars(dev); 3218 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3219 ln2range = 32; 3220 else 3221 ln2range = pci_maprange(pm->pm_value); 3222 pci_write_config(dev, pm->pm_reg, base, 4); 3223 if (ln2range == 64) 3224 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3225 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3226 if (ln2range == 64) 3227 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3228 pm->pm_reg + 4, 4) << 32; 3229 } 3230 3231 struct pci_map * 3232 pci_find_bar(device_t dev, int reg) 3233 { 3234 struct pci_devinfo *dinfo; 3235 struct pci_map *pm; 3236 3237 dinfo = device_get_ivars(dev); 3238 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3239 if (pm->pm_reg == reg) 3240 return (pm); 3241 } 3242 return (NULL); 3243 } 3244 3245 struct pci_map * 3246 pci_first_bar(device_t dev) 3247 { 3248 struct pci_devinfo *dinfo; 3249 3250 dinfo = device_get_ivars(dev); 3251 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3252 } 3253 3254 struct pci_map * 3255 pci_next_bar(struct pci_map *pm) 3256 { 3257 return (STAILQ_NEXT(pm, pm_link)); 3258 } 3259 3260 int 3261 pci_bar_enabled(device_t dev, struct pci_map *pm) 3262 { 3263 struct pci_devinfo *dinfo; 3264 uint16_t cmd; 3265 3266 dinfo = device_get_ivars(dev); 3267 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3268 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3269 return (0); 3270 #ifdef PCI_IOV 3271 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3272 struct pcicfg_iov *iov; 3273 3274 iov = dinfo->cfg.iov; 3275 cmd = pci_read_config(iov->iov_pf, 3276 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3277 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3278 } 3279 #endif 3280 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3281 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3282 return ((cmd & PCIM_CMD_MEMEN) != 0); 3283 else 3284 return ((cmd & PCIM_CMD_PORTEN) != 0); 3285 } 3286 3287 struct pci_map * 3288 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3289 { 3290 struct pci_devinfo *dinfo; 3291 struct pci_map *pm, *prev; 3292 3293 dinfo = device_get_ivars(dev); 3294 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3295 pm->pm_reg = reg; 3296 pm->pm_value = value; 3297 pm->pm_size = size; 3298 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3299 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3300 reg)); 3301 if (STAILQ_NEXT(prev, pm_link) == NULL || 3302 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3303 break; 3304 } 3305 if (prev != NULL) 3306 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3307 else 3308 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3309 return (pm); 3310 } 3311 3312 static void 3313 pci_restore_bars(device_t dev) 3314 { 3315 struct pci_devinfo *dinfo; 3316 struct pci_map *pm; 3317 int ln2range; 3318 3319 dinfo = device_get_ivars(dev); 3320 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3321 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3322 ln2range = 32; 3323 else 3324 ln2range = pci_maprange(pm->pm_value); 3325 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3326 if (ln2range == 64) 3327 pci_write_config(dev, pm->pm_reg + 4, 3328 pm->pm_value >> 32, 4); 3329 } 3330 } 3331 3332 /* 3333 * Add a resource based on a pci map register. Return 1 if the map 3334 * register is a 32bit map register or 2 if it is a 64bit register. 3335 */ 3336 static int 3337 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3338 int force, int prefetch) 3339 { 3340 struct pci_map *pm; 3341 pci_addr_t base, map, testval; 3342 pci_addr_t start, end, count; 3343 int barlen, basezero, flags, maprange, mapsize, type; 3344 uint16_t cmd; 3345 struct resource *res; 3346 3347 /* 3348 * The BAR may already exist if the device is a CardBus card 3349 * whose CIS is stored in this BAR. 3350 */ 3351 pm = pci_find_bar(dev, reg); 3352 if (pm != NULL) { 3353 maprange = pci_maprange(pm->pm_value); 3354 barlen = maprange == 64 ? 2 : 1; 3355 return (barlen); 3356 } 3357 3358 pci_read_bar(dev, reg, &map, &testval, NULL); 3359 if (PCI_BAR_MEM(map)) { 3360 type = SYS_RES_MEMORY; 3361 if (map & PCIM_BAR_MEM_PREFETCH) 3362 prefetch = 1; 3363 } else 3364 type = SYS_RES_IOPORT; 3365 mapsize = pci_mapsize(testval); 3366 base = pci_mapbase(map); 3367 #ifdef __PCI_BAR_ZERO_VALID 3368 basezero = 0; 3369 #else 3370 basezero = base == 0; 3371 #endif 3372 maprange = pci_maprange(map); 3373 barlen = maprange == 64 ? 2 : 1; 3374 3375 /* 3376 * For I/O registers, if bottom bit is set, and the next bit up 3377 * isn't clear, we know we have a BAR that doesn't conform to the 3378 * spec, so ignore it. Also, sanity check the size of the data 3379 * areas to the type of memory involved. Memory must be at least 3380 * 16 bytes in size, while I/O ranges must be at least 4. 3381 */ 3382 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3383 return (barlen); 3384 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3385 (type == SYS_RES_IOPORT && mapsize < 2)) 3386 return (barlen); 3387 3388 /* Save a record of this BAR. */ 3389 pm = pci_add_bar(dev, reg, map, mapsize); 3390 if (bootverbose) { 3391 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3392 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3393 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3394 printf(", port disabled\n"); 3395 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3396 printf(", memory disabled\n"); 3397 else 3398 printf(", enabled\n"); 3399 } 3400 3401 /* 3402 * If base is 0, then we have problems if this architecture does 3403 * not allow that. It is best to ignore such entries for the 3404 * moment. These will be allocated later if the driver specifically 3405 * requests them. However, some removable buses look better when 3406 * all resources are allocated, so allow '0' to be overridden. 3407 * 3408 * Similarly treat maps whose values is the same as the test value 3409 * read back. These maps have had all f's written to them by the 3410 * BIOS in an attempt to disable the resources. 3411 */ 3412 if (!force && (basezero || map == testval)) 3413 return (barlen); 3414 if ((u_long)base != base) { 3415 device_printf(bus, 3416 "pci%d:%d:%d:%d bar %#x too many address bits", 3417 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3418 pci_get_function(dev), reg); 3419 return (barlen); 3420 } 3421 3422 /* 3423 * This code theoretically does the right thing, but has 3424 * undesirable side effects in some cases where peripherals 3425 * respond oddly to having these bits enabled. Let the user 3426 * be able to turn them off (since pci_enable_io_modes is 1 by 3427 * default). 3428 */ 3429 if (pci_enable_io_modes) { 3430 /* Turn on resources that have been left off by a lazy BIOS */ 3431 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3432 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3433 cmd |= PCIM_CMD_PORTEN; 3434 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3435 } 3436 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3437 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3438 cmd |= PCIM_CMD_MEMEN; 3439 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3440 } 3441 } else { 3442 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3443 return (barlen); 3444 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3445 return (barlen); 3446 } 3447 3448 count = (pci_addr_t)1 << mapsize; 3449 flags = RF_ALIGNMENT_LOG2(mapsize); 3450 if (prefetch) 3451 flags |= RF_PREFETCHABLE; 3452 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3453 start = 0; /* Let the parent decide. */ 3454 end = ~0; 3455 } else { 3456 start = base; 3457 end = base + count - 1; 3458 } 3459 resource_list_add(rl, type, reg, start, end, count); 3460 3461 /* 3462 * Try to allocate the resource for this BAR from our parent 3463 * so that this resource range is already reserved. The 3464 * driver for this device will later inherit this resource in 3465 * pci_alloc_resource(). 3466 */ 3467 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3468 flags); 3469 if ((pci_do_realloc_bars 3470 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3471 && res == NULL && (start != 0 || end != ~0)) { 3472 /* 3473 * If the allocation fails, try to allocate a resource for 3474 * this BAR using any available range. The firmware felt 3475 * it was important enough to assign a resource, so don't 3476 * disable decoding if we can help it. 3477 */ 3478 resource_list_delete(rl, type, reg); 3479 resource_list_add(rl, type, reg, 0, ~0, count); 3480 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3481 count, flags); 3482 } 3483 if (res == NULL) { 3484 /* 3485 * If the allocation fails, delete the resource list entry 3486 * and disable decoding for this device. 3487 * 3488 * If the driver requests this resource in the future, 3489 * pci_reserve_map() will try to allocate a fresh 3490 * resource range. 3491 */ 3492 resource_list_delete(rl, type, reg); 3493 pci_disable_io(dev, type); 3494 if (bootverbose) 3495 device_printf(bus, 3496 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3497 pci_get_domain(dev), pci_get_bus(dev), 3498 pci_get_slot(dev), pci_get_function(dev), reg); 3499 } else { 3500 start = rman_get_start(res); 3501 pci_write_bar(dev, pm, start); 3502 } 3503 return (barlen); 3504 } 3505 3506 /* 3507 * For ATA devices we need to decide early what addressing mode to use. 3508 * Legacy demands that the primary and secondary ATA ports sits on the 3509 * same addresses that old ISA hardware did. This dictates that we use 3510 * those addresses and ignore the BAR's if we cannot set PCI native 3511 * addressing mode. 3512 */ 3513 static void 3514 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3515 uint32_t prefetchmask) 3516 { 3517 int rid, type, progif; 3518 #if 0 3519 /* if this device supports PCI native addressing use it */ 3520 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3521 if ((progif & 0x8a) == 0x8a) { 3522 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3523 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3524 printf("Trying ATA native PCI addressing mode\n"); 3525 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3526 } 3527 } 3528 #endif 3529 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3530 type = SYS_RES_IOPORT; 3531 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3532 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3533 prefetchmask & (1 << 0)); 3534 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3535 prefetchmask & (1 << 1)); 3536 } else { 3537 rid = PCIR_BAR(0); 3538 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3539 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3540 0x1f7, 8, 0); 3541 rid = PCIR_BAR(1); 3542 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3543 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3544 0x3f6, 1, 0); 3545 } 3546 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3547 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3548 prefetchmask & (1 << 2)); 3549 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3550 prefetchmask & (1 << 3)); 3551 } else { 3552 rid = PCIR_BAR(2); 3553 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3554 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3555 0x177, 8, 0); 3556 rid = PCIR_BAR(3); 3557 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3558 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3559 0x376, 1, 0); 3560 } 3561 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3562 prefetchmask & (1 << 4)); 3563 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3564 prefetchmask & (1 << 5)); 3565 } 3566 3567 static void 3568 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3569 { 3570 struct pci_devinfo *dinfo = device_get_ivars(dev); 3571 pcicfgregs *cfg = &dinfo->cfg; 3572 char tunable_name[64]; 3573 int irq; 3574 3575 /* Has to have an intpin to have an interrupt. */ 3576 if (cfg->intpin == 0) 3577 return; 3578 3579 /* Let the user override the IRQ with a tunable. */ 3580 irq = PCI_INVALID_IRQ; 3581 snprintf(tunable_name, sizeof(tunable_name), 3582 "hw.pci%d.%d.%d.INT%c.irq", 3583 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3584 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3585 irq = PCI_INVALID_IRQ; 3586 3587 /* 3588 * If we didn't get an IRQ via the tunable, then we either use the 3589 * IRQ value in the intline register or we ask the bus to route an 3590 * interrupt for us. If force_route is true, then we only use the 3591 * value in the intline register if the bus was unable to assign an 3592 * IRQ. 3593 */ 3594 if (!PCI_INTERRUPT_VALID(irq)) { 3595 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3596 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3597 if (!PCI_INTERRUPT_VALID(irq)) 3598 irq = cfg->intline; 3599 } 3600 3601 /* If after all that we don't have an IRQ, just bail. */ 3602 if (!PCI_INTERRUPT_VALID(irq)) 3603 return; 3604 3605 /* Update the config register if it changed. */ 3606 if (irq != cfg->intline) { 3607 cfg->intline = irq; 3608 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3609 } 3610 3611 /* Add this IRQ as rid 0 interrupt resource. */ 3612 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3613 } 3614 3615 /* Perform early OHCI takeover from SMM. */ 3616 static void 3617 ohci_early_takeover(device_t self) 3618 { 3619 struct resource *res; 3620 uint32_t ctl; 3621 int rid; 3622 int i; 3623 3624 rid = PCIR_BAR(0); 3625 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3626 if (res == NULL) 3627 return; 3628 3629 ctl = bus_read_4(res, OHCI_CONTROL); 3630 if (ctl & OHCI_IR) { 3631 if (bootverbose) 3632 printf("ohci early: " 3633 "SMM active, request owner change\n"); 3634 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3635 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3636 DELAY(1000); 3637 ctl = bus_read_4(res, OHCI_CONTROL); 3638 } 3639 if (ctl & OHCI_IR) { 3640 if (bootverbose) 3641 printf("ohci early: " 3642 "SMM does not respond, resetting\n"); 3643 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3644 } 3645 /* Disable interrupts */ 3646 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3647 } 3648 3649 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3650 } 3651 3652 /* Perform early UHCI takeover from SMM. */ 3653 static void 3654 uhci_early_takeover(device_t self) 3655 { 3656 struct resource *res; 3657 int rid; 3658 3659 /* 3660 * Set the PIRQD enable bit and switch off all the others. We don't 3661 * want legacy support to interfere with us XXX Does this also mean 3662 * that the BIOS won't touch the keyboard anymore if it is connected 3663 * to the ports of the root hub? 3664 */ 3665 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3666 3667 /* Disable interrupts */ 3668 rid = PCI_UHCI_BASE_REG; 3669 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3670 if (res != NULL) { 3671 bus_write_2(res, UHCI_INTR, 0); 3672 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3673 } 3674 } 3675 3676 /* Perform early EHCI takeover from SMM. */ 3677 static void 3678 ehci_early_takeover(device_t self) 3679 { 3680 struct resource *res; 3681 uint32_t cparams; 3682 uint32_t eec; 3683 uint8_t eecp; 3684 uint8_t bios_sem; 3685 uint8_t offs; 3686 int rid; 3687 int i; 3688 3689 rid = PCIR_BAR(0); 3690 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3691 if (res == NULL) 3692 return; 3693 3694 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3695 3696 /* Synchronise with the BIOS if it owns the controller. */ 3697 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3698 eecp = EHCI_EECP_NEXT(eec)) { 3699 eec = pci_read_config(self, eecp, 4); 3700 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3701 continue; 3702 } 3703 bios_sem = pci_read_config(self, eecp + 3704 EHCI_LEGSUP_BIOS_SEM, 1); 3705 if (bios_sem == 0) { 3706 continue; 3707 } 3708 if (bootverbose) 3709 printf("ehci early: " 3710 "SMM active, request owner change\n"); 3711 3712 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3713 3714 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3715 DELAY(1000); 3716 bios_sem = pci_read_config(self, eecp + 3717 EHCI_LEGSUP_BIOS_SEM, 1); 3718 } 3719 3720 if (bios_sem != 0) { 3721 if (bootverbose) 3722 printf("ehci early: " 3723 "SMM does not respond\n"); 3724 } 3725 /* Disable interrupts */ 3726 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3727 bus_write_4(res, offs + EHCI_USBINTR, 0); 3728 } 3729 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3730 } 3731 3732 /* Perform early XHCI takeover from SMM. */ 3733 static void 3734 xhci_early_takeover(device_t self) 3735 { 3736 struct resource *res; 3737 uint32_t cparams; 3738 uint32_t eec; 3739 uint8_t eecp; 3740 uint8_t bios_sem; 3741 uint8_t offs; 3742 int rid; 3743 int i; 3744 3745 rid = PCIR_BAR(0); 3746 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3747 if (res == NULL) 3748 return; 3749 3750 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3751 3752 eec = -1; 3753 3754 /* Synchronise with the BIOS if it owns the controller. */ 3755 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3756 eecp += XHCI_XECP_NEXT(eec) << 2) { 3757 eec = bus_read_4(res, eecp); 3758 3759 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3760 continue; 3761 3762 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3763 if (bios_sem == 0) 3764 continue; 3765 3766 if (bootverbose) 3767 printf("xhci early: " 3768 "SMM active, request owner change\n"); 3769 3770 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3771 3772 /* wait a maximum of 5 second */ 3773 3774 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3775 DELAY(1000); 3776 bios_sem = bus_read_1(res, eecp + 3777 XHCI_XECP_BIOS_SEM); 3778 } 3779 3780 if (bios_sem != 0) { 3781 if (bootverbose) 3782 printf("xhci early: " 3783 "SMM does not respond\n"); 3784 } 3785 3786 /* Disable interrupts */ 3787 offs = bus_read_1(res, XHCI_CAPLENGTH); 3788 bus_write_4(res, offs + XHCI_USBCMD, 0); 3789 bus_read_4(res, offs + XHCI_USBSTS); 3790 } 3791 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3792 } 3793 3794 static void 3795 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3796 struct resource_list *rl) 3797 { 3798 struct resource *res; 3799 char *cp; 3800 rman_res_t start, end, count; 3801 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3802 3803 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3804 case PCIM_HDRTYPE_BRIDGE: 3805 sec_reg = PCIR_SECBUS_1; 3806 sub_reg = PCIR_SUBBUS_1; 3807 break; 3808 case PCIM_HDRTYPE_CARDBUS: 3809 sec_reg = PCIR_SECBUS_2; 3810 sub_reg = PCIR_SUBBUS_2; 3811 break; 3812 default: 3813 return; 3814 } 3815 3816 /* 3817 * If the existing bus range is valid, attempt to reserve it 3818 * from our parent. If this fails for any reason, clear the 3819 * secbus and subbus registers. 3820 * 3821 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3822 * This would at least preserve the existing sec_bus if it is 3823 * valid. 3824 */ 3825 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3826 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3827 3828 /* Quirk handling. */ 3829 switch (pci_get_devid(dev)) { 3830 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3831 sup_bus = pci_read_config(dev, 0x41, 1); 3832 if (sup_bus != 0xff) { 3833 sec_bus = sup_bus + 1; 3834 sub_bus = sup_bus + 1; 3835 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3836 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3837 } 3838 break; 3839 3840 case 0x00dd10de: 3841 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3842 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3843 break; 3844 if (strncmp(cp, "Compal", 6) != 0) { 3845 freeenv(cp); 3846 break; 3847 } 3848 freeenv(cp); 3849 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3850 break; 3851 if (strncmp(cp, "08A0", 4) != 0) { 3852 freeenv(cp); 3853 break; 3854 } 3855 freeenv(cp); 3856 if (sub_bus < 0xa) { 3857 sub_bus = 0xa; 3858 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3859 } 3860 break; 3861 } 3862 3863 if (bootverbose) 3864 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3865 if (sec_bus > 0 && sub_bus >= sec_bus) { 3866 start = sec_bus; 3867 end = sub_bus; 3868 count = end - start + 1; 3869 3870 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3871 3872 /* 3873 * If requested, clear secondary bus registers in 3874 * bridge devices to force a complete renumbering 3875 * rather than reserving the existing range. However, 3876 * preserve the existing size. 3877 */ 3878 if (pci_clear_buses) 3879 goto clear; 3880 3881 rid = 0; 3882 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3883 start, end, count, 0); 3884 if (res != NULL) 3885 return; 3886 3887 if (bootverbose) 3888 device_printf(bus, 3889 "pci%d:%d:%d:%d secbus failed to allocate\n", 3890 pci_get_domain(dev), pci_get_bus(dev), 3891 pci_get_slot(dev), pci_get_function(dev)); 3892 } 3893 3894 clear: 3895 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3896 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3897 } 3898 3899 static struct resource * 3900 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3901 rman_res_t end, rman_res_t count, u_int flags) 3902 { 3903 struct pci_devinfo *dinfo; 3904 pcicfgregs *cfg; 3905 struct resource_list *rl; 3906 struct resource *res; 3907 int sec_reg, sub_reg; 3908 3909 dinfo = device_get_ivars(child); 3910 cfg = &dinfo->cfg; 3911 rl = &dinfo->resources; 3912 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3913 case PCIM_HDRTYPE_BRIDGE: 3914 sec_reg = PCIR_SECBUS_1; 3915 sub_reg = PCIR_SUBBUS_1; 3916 break; 3917 case PCIM_HDRTYPE_CARDBUS: 3918 sec_reg = PCIR_SECBUS_2; 3919 sub_reg = PCIR_SUBBUS_2; 3920 break; 3921 default: 3922 return (NULL); 3923 } 3924 3925 if (*rid != 0) 3926 return (NULL); 3927 3928 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3929 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3930 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3931 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3932 start, end, count, flags & ~RF_ACTIVE); 3933 if (res == NULL) { 3934 resource_list_delete(rl, PCI_RES_BUS, *rid); 3935 device_printf(child, "allocating %ju bus%s failed\n", 3936 count, count == 1 ? "" : "es"); 3937 return (NULL); 3938 } 3939 if (bootverbose) 3940 device_printf(child, 3941 "Lazy allocation of %ju bus%s at %ju\n", count, 3942 count == 1 ? "" : "es", rman_get_start(res)); 3943 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3944 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3945 } 3946 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3947 end, count, flags)); 3948 } 3949 3950 static int 3951 pci_ea_bei_to_rid(device_t dev, int bei) 3952 { 3953 #ifdef PCI_IOV 3954 struct pci_devinfo *dinfo; 3955 int iov_pos; 3956 struct pcicfg_iov *iov; 3957 3958 dinfo = device_get_ivars(dev); 3959 iov = dinfo->cfg.iov; 3960 if (iov != NULL) 3961 iov_pos = iov->iov_pos; 3962 else 3963 iov_pos = 0; 3964 #endif 3965 3966 /* Check if matches BAR */ 3967 if ((bei >= PCIM_EA_BEI_BAR_0) && 3968 (bei <= PCIM_EA_BEI_BAR_5)) 3969 return (PCIR_BAR(bei)); 3970 3971 /* Check ROM */ 3972 if (bei == PCIM_EA_BEI_ROM) 3973 return (PCIR_BIOS); 3974 3975 #ifdef PCI_IOV 3976 /* Check if matches VF_BAR */ 3977 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3978 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3979 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3980 iov_pos); 3981 #endif 3982 3983 return (-1); 3984 } 3985 3986 int 3987 pci_ea_is_enabled(device_t dev, int rid) 3988 { 3989 struct pci_ea_entry *ea; 3990 struct pci_devinfo *dinfo; 3991 3992 dinfo = device_get_ivars(dev); 3993 3994 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3995 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3996 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3997 } 3998 3999 return (0); 4000 } 4001 4002 void 4003 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 4004 { 4005 struct pci_ea_entry *ea; 4006 struct pci_devinfo *dinfo; 4007 pci_addr_t start, end, count; 4008 struct resource_list *rl; 4009 int type, flags, rid; 4010 struct resource *res; 4011 uint32_t tmp; 4012 #ifdef PCI_IOV 4013 struct pcicfg_iov *iov; 4014 #endif 4015 4016 dinfo = device_get_ivars(dev); 4017 rl = &dinfo->resources; 4018 flags = 0; 4019 4020 #ifdef PCI_IOV 4021 iov = dinfo->cfg.iov; 4022 #endif 4023 4024 if (dinfo->cfg.ea.ea_location == 0) 4025 return; 4026 4027 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4028 /* 4029 * TODO: Ignore EA-BAR if is not enabled. 4030 * Currently the EA implementation supports 4031 * only situation, where EA structure contains 4032 * predefined entries. In case they are not enabled 4033 * leave them unallocated and proceed with 4034 * a legacy-BAR mechanism. 4035 */ 4036 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 4037 continue; 4038 4039 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 4040 case PCIM_EA_P_MEM_PREFETCH: 4041 case PCIM_EA_P_VF_MEM_PREFETCH: 4042 flags = RF_PREFETCHABLE; 4043 /* FALLTHROUGH */ 4044 case PCIM_EA_P_VF_MEM: 4045 case PCIM_EA_P_MEM: 4046 type = SYS_RES_MEMORY; 4047 break; 4048 case PCIM_EA_P_IO: 4049 type = SYS_RES_IOPORT; 4050 break; 4051 default: 4052 continue; 4053 } 4054 4055 if (alloc_iov != 0) { 4056 #ifdef PCI_IOV 4057 /* Allocating IOV, confirm BEI matches */ 4058 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 4059 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 4060 continue; 4061 #else 4062 continue; 4063 #endif 4064 } else { 4065 /* Allocating BAR, confirm BEI matches */ 4066 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 4067 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 4068 (ea->eae_bei != PCIM_EA_BEI_ROM)) 4069 continue; 4070 } 4071 4072 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 4073 if (rid < 0) 4074 continue; 4075 4076 /* Skip resources already allocated by EA */ 4077 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 4078 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 4079 continue; 4080 4081 start = ea->eae_base; 4082 count = ea->eae_max_offset + 1; 4083 #ifdef PCI_IOV 4084 if (iov != NULL) 4085 count = count * iov->iov_num_vfs; 4086 #endif 4087 end = start + count - 1; 4088 if (count == 0) 4089 continue; 4090 4091 resource_list_add(rl, type, rid, start, end, count); 4092 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4093 flags); 4094 if (res == NULL) { 4095 resource_list_delete(rl, type, rid); 4096 4097 /* 4098 * Failed to allocate using EA, disable entry. 4099 * Another attempt to allocation will be performed 4100 * further, but this time using legacy BAR registers 4101 */ 4102 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4103 tmp &= ~PCIM_EA_ENABLE; 4104 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4105 4106 /* 4107 * Disabling entry might fail in case it is hardwired. 4108 * Read flags again to match current status. 4109 */ 4110 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4111 4112 continue; 4113 } 4114 4115 /* As per specification, fill BAR with zeros */ 4116 pci_write_config(dev, rid, 0, 4); 4117 } 4118 } 4119 4120 void 4121 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4122 { 4123 struct pci_devinfo *dinfo; 4124 pcicfgregs *cfg; 4125 struct resource_list *rl; 4126 const struct pci_quirk *q; 4127 uint32_t devid; 4128 int i; 4129 4130 dinfo = device_get_ivars(dev); 4131 cfg = &dinfo->cfg; 4132 rl = &dinfo->resources; 4133 devid = (cfg->device << 16) | cfg->vendor; 4134 4135 /* Allocate resources using Enhanced Allocation */ 4136 pci_add_resources_ea(bus, dev, 0); 4137 4138 /* ATA devices needs special map treatment */ 4139 if ((pci_get_class(dev) == PCIC_STORAGE) && 4140 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4141 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4142 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4143 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4144 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4145 else 4146 for (i = 0; i < cfg->nummaps;) { 4147 /* Skip resources already managed by EA */ 4148 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4149 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4150 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4151 i++; 4152 continue; 4153 } 4154 4155 /* 4156 * Skip quirked resources. 4157 */ 4158 for (q = &pci_quirks[0]; q->devid != 0; q++) 4159 if (q->devid == devid && 4160 q->type == PCI_QUIRK_UNMAP_REG && 4161 q->arg1 == PCIR_BAR(i)) 4162 break; 4163 if (q->devid != 0) { 4164 i++; 4165 continue; 4166 } 4167 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4168 prefetchmask & (1 << i)); 4169 } 4170 4171 /* 4172 * Add additional, quirked resources. 4173 */ 4174 for (q = &pci_quirks[0]; q->devid != 0; q++) 4175 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4176 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4177 4178 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4179 /* 4180 * Try to re-route interrupts. Sometimes the BIOS or 4181 * firmware may leave bogus values in these registers. 4182 * If the re-route fails, then just stick with what we 4183 * have. 4184 */ 4185 pci_assign_interrupt(bus, dev, 1); 4186 } 4187 4188 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4189 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4190 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4191 xhci_early_takeover(dev); 4192 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4193 ehci_early_takeover(dev); 4194 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4195 ohci_early_takeover(dev); 4196 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4197 uhci_early_takeover(dev); 4198 } 4199 4200 /* 4201 * Reserve resources for secondary bus ranges behind bridge 4202 * devices. 4203 */ 4204 pci_reserve_secbus(bus, dev, cfg, rl); 4205 } 4206 4207 static struct pci_devinfo * 4208 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4209 int slot, int func) 4210 { 4211 struct pci_devinfo *dinfo; 4212 4213 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4214 if (dinfo != NULL) 4215 pci_add_child(dev, dinfo); 4216 4217 return (dinfo); 4218 } 4219 4220 void 4221 pci_add_children(device_t dev, int domain, int busno) 4222 { 4223 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4224 device_t pcib = device_get_parent(dev); 4225 struct pci_devinfo *dinfo; 4226 int maxslots; 4227 int s, f, pcifunchigh; 4228 uint8_t hdrtype; 4229 int first_func; 4230 4231 /* 4232 * Try to detect a device at slot 0, function 0. If it exists, try to 4233 * enable ARI. We must enable ARI before detecting the rest of the 4234 * functions on this bus as ARI changes the set of slots and functions 4235 * that are legal on this bus. 4236 */ 4237 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4238 if (dinfo != NULL && pci_enable_ari) 4239 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4240 4241 /* 4242 * Start looking for new devices on slot 0 at function 1 because we 4243 * just identified the device at slot 0, function 0. 4244 */ 4245 first_func = 1; 4246 4247 maxslots = PCIB_MAXSLOTS(pcib); 4248 for (s = 0; s <= maxslots; s++, first_func = 0) { 4249 pcifunchigh = 0; 4250 f = 0; 4251 DELAY(1); 4252 4253 /* If function 0 is not present, skip to the next slot. */ 4254 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4255 continue; 4256 hdrtype = REG(PCIR_HDRTYPE, 1); 4257 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4258 continue; 4259 if (hdrtype & PCIM_MFDEV) 4260 pcifunchigh = PCIB_MAXFUNCS(pcib); 4261 for (f = first_func; f <= pcifunchigh; f++) 4262 pci_identify_function(pcib, dev, domain, busno, s, f); 4263 } 4264 #undef REG 4265 } 4266 4267 int 4268 pci_rescan_method(device_t dev) 4269 { 4270 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4271 device_t pcib = device_get_parent(dev); 4272 device_t child, *devlist, *unchanged; 4273 int devcount, error, i, j, maxslots, oldcount; 4274 int busno, domain, s, f, pcifunchigh; 4275 uint8_t hdrtype; 4276 4277 /* No need to check for ARI on a rescan. */ 4278 error = device_get_children(dev, &devlist, &devcount); 4279 if (error) 4280 return (error); 4281 if (devcount != 0) { 4282 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4283 M_NOWAIT | M_ZERO); 4284 if (unchanged == NULL) { 4285 free(devlist, M_TEMP); 4286 return (ENOMEM); 4287 } 4288 } else 4289 unchanged = NULL; 4290 4291 domain = pcib_get_domain(dev); 4292 busno = pcib_get_bus(dev); 4293 maxslots = PCIB_MAXSLOTS(pcib); 4294 for (s = 0; s <= maxslots; s++) { 4295 /* If function 0 is not present, skip to the next slot. */ 4296 f = 0; 4297 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4298 continue; 4299 pcifunchigh = 0; 4300 hdrtype = REG(PCIR_HDRTYPE, 1); 4301 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4302 continue; 4303 if (hdrtype & PCIM_MFDEV) 4304 pcifunchigh = PCIB_MAXFUNCS(pcib); 4305 for (f = 0; f <= pcifunchigh; f++) { 4306 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4307 continue; 4308 4309 /* 4310 * Found a valid function. Check if a 4311 * device_t for this device already exists. 4312 */ 4313 for (i = 0; i < devcount; i++) { 4314 child = devlist[i]; 4315 if (child == NULL) 4316 continue; 4317 if (pci_get_slot(child) == s && 4318 pci_get_function(child) == f) { 4319 unchanged[i] = child; 4320 goto next_func; 4321 } 4322 } 4323 4324 pci_identify_function(pcib, dev, domain, busno, s, f); 4325 next_func:; 4326 } 4327 } 4328 4329 /* Remove devices that are no longer present. */ 4330 for (i = 0; i < devcount; i++) { 4331 if (unchanged[i] != NULL) 4332 continue; 4333 device_delete_child(dev, devlist[i]); 4334 } 4335 4336 free(devlist, M_TEMP); 4337 oldcount = devcount; 4338 4339 /* Try to attach the devices just added. */ 4340 error = device_get_children(dev, &devlist, &devcount); 4341 if (error) { 4342 free(unchanged, M_TEMP); 4343 return (error); 4344 } 4345 4346 for (i = 0; i < devcount; i++) { 4347 for (j = 0; j < oldcount; j++) { 4348 if (devlist[i] == unchanged[j]) 4349 goto next_device; 4350 } 4351 4352 device_probe_and_attach(devlist[i]); 4353 next_device:; 4354 } 4355 4356 free(unchanged, M_TEMP); 4357 free(devlist, M_TEMP); 4358 return (0); 4359 #undef REG 4360 } 4361 4362 #ifdef PCI_IOV 4363 device_t 4364 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4365 uint16_t did) 4366 { 4367 struct pci_devinfo *vf_dinfo; 4368 device_t pcib; 4369 int busno, slot, func; 4370 4371 pcib = device_get_parent(bus); 4372 4373 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4374 4375 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4376 slot, func, vid, did); 4377 4378 vf_dinfo->cfg.flags |= PCICFG_VF; 4379 pci_add_child(bus, vf_dinfo); 4380 4381 return (vf_dinfo->cfg.dev); 4382 } 4383 4384 device_t 4385 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4386 uint16_t vid, uint16_t did) 4387 { 4388 4389 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4390 } 4391 #endif 4392 4393 /* 4394 * For PCIe device set Max_Payload_Size to match PCIe root's. 4395 */ 4396 static void 4397 pcie_setup_mps(device_t dev) 4398 { 4399 struct pci_devinfo *dinfo = device_get_ivars(dev); 4400 device_t root; 4401 uint16_t rmps, mmps, mps; 4402 4403 if (dinfo->cfg.pcie.pcie_location == 0) 4404 return; 4405 root = pci_find_pcie_root_port(dev); 4406 if (root == NULL) 4407 return; 4408 /* Check whether the MPS is already configured. */ 4409 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4410 PCIEM_CTL_MAX_PAYLOAD; 4411 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4412 PCIEM_CTL_MAX_PAYLOAD; 4413 if (mps == rmps) 4414 return; 4415 /* Check whether the device is capable of the root's MPS. */ 4416 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4417 PCIEM_CAP_MAX_PAYLOAD) << 5; 4418 if (rmps > mmps) { 4419 /* 4420 * The device is unable to handle root's MPS. Limit root. 4421 * XXX: We should traverse through all the tree, applying 4422 * it to all the devices. 4423 */ 4424 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4425 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4426 } else { 4427 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4428 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4429 } 4430 } 4431 4432 static void 4433 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4434 { 4435 int aer; 4436 uint32_t r; 4437 uint16_t r2; 4438 4439 if (dinfo->cfg.pcie.pcie_location != 0 && 4440 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4441 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4442 PCIER_ROOT_CTL, 2); 4443 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4444 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4445 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4446 PCIER_ROOT_CTL, r2, 2); 4447 } 4448 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4449 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4450 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4451 if (r != 0 && bootverbose) { 4452 pci_printf(&dinfo->cfg, 4453 "clearing AER UC 0x%08x -> 0x%08x\n", 4454 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4455 4)); 4456 } 4457 4458 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4459 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4460 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4461 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4462 PCIM_AER_UC_POISONED_TLP | 4463 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4464 PCIM_AER_UC_COMPLETION_TIMEOUT | 4465 PCIM_AER_UC_COMPLETER_ABORT | 4466 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4467 PCIM_AER_UC_RECEIVER_OVERFLOW | 4468 PCIM_AER_UC_MALFORMED_TLP | 4469 PCIM_AER_UC_ECRC_ERROR | 4470 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4471 PCIM_AER_UC_ACS_VIOLATION | 4472 PCIM_AER_UC_INTERNAL_ERROR | 4473 PCIM_AER_UC_MC_BLOCKED_TLP | 4474 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4475 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4476 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4477 4478 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4479 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4480 if (r != 0 && bootverbose) { 4481 pci_printf(&dinfo->cfg, 4482 "clearing AER COR 0x%08x -> 0x%08x\n", 4483 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4484 4)); 4485 } 4486 4487 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4488 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4489 PCIM_AER_COR_BAD_TLP | 4490 PCIM_AER_COR_BAD_DLLP | 4491 PCIM_AER_COR_REPLAY_ROLLOVER | 4492 PCIM_AER_COR_REPLAY_TIMEOUT | 4493 PCIM_AER_COR_ADVISORY_NF_ERROR | 4494 PCIM_AER_COR_INTERNAL_ERROR | 4495 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4496 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4497 4498 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4499 PCIER_DEVICE_CTL, 2); 4500 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4501 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4502 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4503 PCIER_DEVICE_CTL, r, 2); 4504 } 4505 } 4506 4507 void 4508 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4509 { 4510 device_t dev; 4511 4512 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4513 device_set_ivars(dev, dinfo); 4514 resource_list_init(&dinfo->resources); 4515 pci_cfg_save(dev, dinfo, 0); 4516 pci_cfg_restore(dev, dinfo); 4517 pci_clear_pme(dev); 4518 pci_print_verbose(dinfo); 4519 pci_add_resources(bus, dev, 0, 0); 4520 if (pci_enable_mps_tune) 4521 pcie_setup_mps(dev); 4522 pci_child_added(dinfo->cfg.dev); 4523 4524 if (pci_clear_aer_on_attach) 4525 pci_add_child_clear_aer(dev, dinfo); 4526 4527 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4528 } 4529 4530 void 4531 pci_child_added_method(device_t dev, device_t child) 4532 { 4533 4534 } 4535 4536 static int 4537 pci_probe(device_t dev) 4538 { 4539 4540 device_set_desc(dev, "PCI bus"); 4541 4542 /* Allow other subclasses to override this driver. */ 4543 return (BUS_PROBE_GENERIC); 4544 } 4545 4546 int 4547 pci_attach_common(device_t dev) 4548 { 4549 struct pci_softc *sc; 4550 int busno, domain; 4551 int rid; 4552 4553 sc = device_get_softc(dev); 4554 domain = pcib_get_domain(dev); 4555 busno = pcib_get_bus(dev); 4556 rid = 0; 4557 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4558 1, 0); 4559 if (sc->sc_bus == NULL) { 4560 device_printf(dev, "failed to allocate bus number\n"); 4561 return (ENXIO); 4562 } 4563 if (bootverbose) 4564 device_printf(dev, "domain=%d, physical bus=%d\n", 4565 domain, busno); 4566 sc->sc_dma_tag = bus_get_dma_tag(dev); 4567 return (0); 4568 } 4569 4570 int 4571 pci_attach(device_t dev) 4572 { 4573 int busno, domain, error; 4574 4575 error = pci_attach_common(dev); 4576 if (error) 4577 return (error); 4578 4579 /* 4580 * Since there can be multiple independently numbered PCI 4581 * buses on systems with multiple PCI domains, we can't use 4582 * the unit number to decide which bus we are probing. We ask 4583 * the parent pcib what our domain and bus numbers are. 4584 */ 4585 domain = pcib_get_domain(dev); 4586 busno = pcib_get_bus(dev); 4587 pci_add_children(dev, domain, busno); 4588 bus_attach_children(dev); 4589 return (0); 4590 } 4591 4592 int 4593 pci_detach(device_t dev) 4594 { 4595 struct pci_softc *sc; 4596 int error; 4597 4598 error = bus_generic_detach(dev); 4599 if (error) 4600 return (error); 4601 sc = device_get_softc(dev); 4602 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4603 return (error); 4604 } 4605 4606 static void 4607 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4608 { 4609 int line, unit; 4610 const char *at; 4611 char me1[24], me2[32]; 4612 uint8_t b, s, f; 4613 uint32_t d; 4614 device_location_cache_t *cache; 4615 4616 d = pci_get_domain(child); 4617 b = pci_get_bus(child); 4618 s = pci_get_slot(child); 4619 f = pci_get_function(child); 4620 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4621 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4622 line = 0; 4623 cache = dev_wired_cache_init(); 4624 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4625 resource_string_value(name, unit, "at", &at); 4626 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4627 *unitp = unit; 4628 break; 4629 } 4630 if (dev_wired_cache_match(cache, child, at)) { 4631 *unitp = unit; 4632 break; 4633 } 4634 } 4635 dev_wired_cache_fini(cache); 4636 } 4637 4638 static void 4639 pci_set_power_child(device_t dev, device_t child, int state) 4640 { 4641 device_t pcib; 4642 int dstate; 4643 4644 /* 4645 * Set the device to the given state. If the firmware suggests 4646 * a different power state, use it instead. If power management 4647 * is not present, the firmware is responsible for managing 4648 * device power. Skip children who aren't attached since they 4649 * are handled separately. 4650 */ 4651 pcib = device_get_parent(dev); 4652 dstate = state; 4653 if (device_is_attached(child) && 4654 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4655 pci_set_powerstate(child, dstate); 4656 } 4657 4658 int 4659 pci_suspend_child(device_t dev, device_t child) 4660 { 4661 struct pci_devinfo *dinfo; 4662 struct resource_list_entry *rle; 4663 int error; 4664 4665 dinfo = device_get_ivars(child); 4666 4667 /* 4668 * Save the PCI configuration space for the child and set the 4669 * device in the appropriate power state for this sleep state. 4670 */ 4671 pci_cfg_save(child, dinfo, 0); 4672 4673 /* Suspend devices before potentially powering them down. */ 4674 error = bus_generic_suspend_child(dev, child); 4675 4676 if (error) 4677 return (error); 4678 4679 if (pci_do_power_suspend) { 4680 /* 4681 * Make sure this device's interrupt handler is not invoked 4682 * in the case the device uses a shared interrupt that can 4683 * be raised by some other device. 4684 * This is applicable only to regular (legacy) PCI interrupts 4685 * as MSI/MSI-X interrupts are never shared. 4686 */ 4687 rle = resource_list_find(&dinfo->resources, 4688 SYS_RES_IRQ, 0); 4689 if (rle != NULL && rle->res != NULL) 4690 (void)bus_suspend_intr(child, rle->res); 4691 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4692 } 4693 4694 return (0); 4695 } 4696 4697 int 4698 pci_resume_child(device_t dev, device_t child) 4699 { 4700 struct pci_devinfo *dinfo; 4701 struct resource_list_entry *rle; 4702 4703 if (pci_do_power_resume) 4704 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4705 4706 dinfo = device_get_ivars(child); 4707 pci_cfg_restore(child, dinfo); 4708 pci_clear_pme(child); 4709 if (!device_is_attached(child)) 4710 pci_cfg_save(child, dinfo, 1); 4711 4712 bus_generic_resume_child(dev, child); 4713 4714 /* 4715 * Allow interrupts only after fully resuming the driver and hardware. 4716 */ 4717 if (pci_do_power_suspend) { 4718 /* See pci_suspend_child for details. */ 4719 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4720 if (rle != NULL && rle->res != NULL) 4721 (void)bus_resume_intr(child, rle->res); 4722 } 4723 4724 return (0); 4725 } 4726 4727 int 4728 pci_resume(device_t dev) 4729 { 4730 device_t child, *devlist; 4731 int error, i, numdevs; 4732 4733 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4734 return (error); 4735 4736 /* 4737 * Resume critical devices first, then everything else later. 4738 */ 4739 for (i = 0; i < numdevs; i++) { 4740 child = devlist[i]; 4741 switch (pci_get_class(child)) { 4742 case PCIC_DISPLAY: 4743 case PCIC_MEMORY: 4744 case PCIC_BRIDGE: 4745 case PCIC_BASEPERIPH: 4746 BUS_RESUME_CHILD(dev, child); 4747 break; 4748 } 4749 } 4750 for (i = 0; i < numdevs; i++) { 4751 child = devlist[i]; 4752 switch (pci_get_class(child)) { 4753 case PCIC_DISPLAY: 4754 case PCIC_MEMORY: 4755 case PCIC_BRIDGE: 4756 case PCIC_BASEPERIPH: 4757 break; 4758 default: 4759 BUS_RESUME_CHILD(dev, child); 4760 } 4761 } 4762 free(devlist, M_TEMP); 4763 return (0); 4764 } 4765 4766 static void 4767 pci_load_vendor_data(void) 4768 { 4769 caddr_t data; 4770 void *ptr; 4771 size_t sz; 4772 4773 data = preload_search_by_type("pci_vendor_data"); 4774 if (data != NULL) { 4775 ptr = preload_fetch_addr(data); 4776 sz = preload_fetch_size(data); 4777 if (ptr != NULL && sz != 0) { 4778 pci_vendordata = ptr; 4779 pci_vendordata_size = sz; 4780 /* terminate the database */ 4781 pci_vendordata[pci_vendordata_size] = '\n'; 4782 } 4783 } 4784 } 4785 4786 void 4787 pci_driver_added(device_t dev, driver_t *driver) 4788 { 4789 int numdevs; 4790 device_t *devlist; 4791 device_t child; 4792 struct pci_devinfo *dinfo; 4793 int i; 4794 4795 if (bootverbose) 4796 device_printf(dev, "driver added\n"); 4797 DEVICE_IDENTIFY(driver, dev); 4798 if (device_get_children(dev, &devlist, &numdevs) != 0) 4799 return; 4800 for (i = 0; i < numdevs; i++) { 4801 child = devlist[i]; 4802 if (device_get_state(child) != DS_NOTPRESENT) 4803 continue; 4804 dinfo = device_get_ivars(child); 4805 pci_print_verbose(dinfo); 4806 if (bootverbose) 4807 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4808 pci_cfg_restore(child, dinfo); 4809 if (device_probe_and_attach(child) != 0) 4810 pci_child_detached(dev, child); 4811 } 4812 free(devlist, M_TEMP); 4813 } 4814 4815 int 4816 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4817 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4818 { 4819 struct pci_devinfo *dinfo; 4820 struct msix_table_entry *mte; 4821 struct msix_vector *mv; 4822 uint64_t addr; 4823 uint32_t data; 4824 void *cookie; 4825 int error, rid; 4826 4827 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4828 arg, &cookie); 4829 if (error) 4830 return (error); 4831 4832 /* If this is not a direct child, just bail out. */ 4833 if (device_get_parent(child) != dev) { 4834 *cookiep = cookie; 4835 return(0); 4836 } 4837 4838 rid = rman_get_rid(irq); 4839 if (rid == 0) { 4840 /* Make sure that INTx is enabled */ 4841 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4842 } else { 4843 /* 4844 * Check to see if the interrupt is MSI or MSI-X. 4845 * Ask our parent to map the MSI and give 4846 * us the address and data register values. 4847 * If we fail for some reason, teardown the 4848 * interrupt handler. 4849 */ 4850 dinfo = device_get_ivars(child); 4851 if (dinfo->cfg.msi.msi_alloc > 0) { 4852 if (dinfo->cfg.msi.msi_addr == 0) { 4853 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4854 ("MSI has handlers, but vectors not mapped")); 4855 error = PCIB_MAP_MSI(device_get_parent(dev), 4856 child, rman_get_start(irq), &addr, &data); 4857 if (error) 4858 goto bad; 4859 dinfo->cfg.msi.msi_addr = addr; 4860 dinfo->cfg.msi.msi_data = data; 4861 } 4862 if (dinfo->cfg.msi.msi_handlers == 0) 4863 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4864 dinfo->cfg.msi.msi_data); 4865 dinfo->cfg.msi.msi_handlers++; 4866 } else { 4867 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4868 ("No MSI or MSI-X interrupts allocated")); 4869 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4870 ("MSI-X index too high")); 4871 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4872 KASSERT(mte->mte_vector != 0, ("no message vector")); 4873 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4874 KASSERT(mv->mv_irq == rman_get_start(irq), 4875 ("IRQ mismatch")); 4876 if (mv->mv_address == 0) { 4877 KASSERT(mte->mte_handlers == 0, 4878 ("MSI-X table entry has handlers, but vector not mapped")); 4879 error = PCIB_MAP_MSI(device_get_parent(dev), 4880 child, rman_get_start(irq), &addr, &data); 4881 if (error) 4882 goto bad; 4883 mv->mv_address = addr; 4884 mv->mv_data = data; 4885 } 4886 4887 /* 4888 * The MSIX table entry must be made valid by 4889 * incrementing the mte_handlers before 4890 * calling pci_enable_msix() and 4891 * pci_resume_msix(). Else the MSIX rewrite 4892 * table quirk will not work as expected. 4893 */ 4894 mte->mte_handlers++; 4895 if (mte->mte_handlers == 1) { 4896 pci_enable_msix(child, rid - 1, mv->mv_address, 4897 mv->mv_data); 4898 pci_unmask_msix(child, rid - 1); 4899 } 4900 } 4901 4902 /* 4903 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4904 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4905 * in which case we "enable" INTx so MSI/MSI-X actually works. 4906 */ 4907 if (!pci_has_quirk(pci_get_devid(child), 4908 PCI_QUIRK_MSI_INTX_BUG)) 4909 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4910 else 4911 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4912 bad: 4913 if (error) { 4914 (void)bus_generic_teardown_intr(dev, child, irq, 4915 cookie); 4916 return (error); 4917 } 4918 } 4919 *cookiep = cookie; 4920 return (0); 4921 } 4922 4923 int 4924 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4925 void *cookie) 4926 { 4927 struct msix_table_entry *mte; 4928 struct resource_list_entry *rle; 4929 struct pci_devinfo *dinfo; 4930 int error, rid; 4931 4932 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4933 return (EINVAL); 4934 4935 /* If this isn't a direct child, just bail out */ 4936 if (device_get_parent(child) != dev) 4937 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4938 4939 rid = rman_get_rid(irq); 4940 if (rid == 0) { 4941 /* Mask INTx */ 4942 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4943 } else { 4944 /* 4945 * Check to see if the interrupt is MSI or MSI-X. If so, 4946 * decrement the appropriate handlers count and mask the 4947 * MSI-X message, or disable MSI messages if the count 4948 * drops to 0. 4949 */ 4950 dinfo = device_get_ivars(child); 4951 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4952 if (rle->res != irq) 4953 return (EINVAL); 4954 if (dinfo->cfg.msi.msi_alloc > 0) { 4955 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4956 ("MSI-X index too high")); 4957 if (dinfo->cfg.msi.msi_handlers == 0) 4958 return (EINVAL); 4959 dinfo->cfg.msi.msi_handlers--; 4960 if (dinfo->cfg.msi.msi_handlers == 0) 4961 pci_disable_msi(child); 4962 } else { 4963 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4964 ("No MSI or MSI-X interrupts allocated")); 4965 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4966 ("MSI-X index too high")); 4967 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4968 if (mte->mte_handlers == 0) 4969 return (EINVAL); 4970 mte->mte_handlers--; 4971 if (mte->mte_handlers == 0) 4972 pci_mask_msix(child, rid - 1); 4973 } 4974 } 4975 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4976 if (rid > 0) 4977 KASSERT(error == 0, 4978 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4979 return (error); 4980 } 4981 4982 int 4983 pci_print_child(device_t dev, device_t child) 4984 { 4985 struct pci_devinfo *dinfo; 4986 struct resource_list *rl; 4987 int retval = 0; 4988 4989 dinfo = device_get_ivars(child); 4990 rl = &dinfo->resources; 4991 4992 retval += bus_print_child_header(dev, child); 4993 4994 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4995 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4996 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4997 if (device_get_flags(dev)) 4998 retval += printf(" flags %#x", device_get_flags(dev)); 4999 5000 retval += printf(" at device %d.%d", pci_get_slot(child), 5001 pci_get_function(child)); 5002 5003 retval += bus_print_child_domain(dev, child); 5004 retval += bus_print_child_footer(dev, child); 5005 5006 return (retval); 5007 } 5008 5009 static const struct 5010 { 5011 int class; 5012 int subclass; 5013 int report; /* 0 = bootverbose, 1 = always */ 5014 const char *desc; 5015 } pci_nomatch_tab[] = { 5016 {PCIC_OLD, -1, 1, "old"}, 5017 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 5018 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 5019 {PCIC_STORAGE, -1, 1, "mass storage"}, 5020 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 5021 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 5022 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 5023 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 5024 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 5025 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 5026 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 5027 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 5028 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 5029 {PCIC_NETWORK, -1, 1, "network"}, 5030 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 5031 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 5032 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 5033 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 5034 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 5035 {PCIC_DISPLAY, -1, 1, "display"}, 5036 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 5037 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 5038 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 5039 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 5040 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 5041 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 5042 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 5043 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 5044 {PCIC_MEMORY, -1, 1, "memory"}, 5045 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 5046 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 5047 {PCIC_BRIDGE, -1, 1, "bridge"}, 5048 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 5049 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 5050 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 5051 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 5052 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 5053 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 5054 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 5055 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 5056 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 5057 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 5058 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 5059 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 5060 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 5061 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 5062 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 5063 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 5064 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 5065 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 5066 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 5067 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 5068 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 5069 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 5070 {PCIC_INPUTDEV, -1, 1, "input device"}, 5071 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 5072 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 5073 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 5074 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 5075 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 5076 {PCIC_DOCKING, -1, 1, "docking station"}, 5077 {PCIC_PROCESSOR, -1, 1, "processor"}, 5078 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 5079 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 5080 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 5081 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 5082 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 5083 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5084 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5085 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5086 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5087 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5088 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5089 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5090 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5091 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5092 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5093 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5094 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5095 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5096 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5097 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5098 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5099 {PCIC_DASP, -1, 0, "dasp"}, 5100 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5101 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5102 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5103 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5104 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5105 {0, 0, 0, NULL} 5106 }; 5107 5108 void 5109 pci_probe_nomatch(device_t dev, device_t child) 5110 { 5111 int i, report; 5112 const char *cp, *scp; 5113 char *device; 5114 5115 /* 5116 * Look for a listing for this device in a loaded device database. 5117 */ 5118 report = 1; 5119 if ((device = pci_describe_device(child)) != NULL) { 5120 device_printf(dev, "<%s>", device); 5121 free(device, M_DEVBUF); 5122 } else { 5123 /* 5124 * Scan the class/subclass descriptions for a general 5125 * description. 5126 */ 5127 cp = "unknown"; 5128 scp = NULL; 5129 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5130 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5131 if (pci_nomatch_tab[i].subclass == -1) { 5132 cp = pci_nomatch_tab[i].desc; 5133 report = pci_nomatch_tab[i].report; 5134 } else if (pci_nomatch_tab[i].subclass == 5135 pci_get_subclass(child)) { 5136 scp = pci_nomatch_tab[i].desc; 5137 report = pci_nomatch_tab[i].report; 5138 } 5139 } 5140 } 5141 if (report || bootverbose) { 5142 device_printf(dev, "<%s%s%s>", 5143 cp ? cp : "", 5144 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5145 scp ? scp : ""); 5146 } 5147 } 5148 if (report || bootverbose) { 5149 printf(" at device %d.%d (no driver attached)\n", 5150 pci_get_slot(child), pci_get_function(child)); 5151 } 5152 pci_cfg_save(child, device_get_ivars(child), 1); 5153 } 5154 5155 void 5156 pci_child_detached(device_t dev, device_t child) 5157 { 5158 struct pci_devinfo *dinfo; 5159 struct resource_list *rl; 5160 5161 dinfo = device_get_ivars(child); 5162 rl = &dinfo->resources; 5163 5164 /* 5165 * Have to deallocate IRQs before releasing any MSI messages and 5166 * have to release MSI messages before deallocating any memory 5167 * BARs. 5168 */ 5169 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5170 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5171 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5172 if (dinfo->cfg.msi.msi_alloc != 0) 5173 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5174 "vectors\n", dinfo->cfg.msi.msi_alloc); 5175 else 5176 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5177 "vectors\n", dinfo->cfg.msix.msix_alloc); 5178 (void)pci_release_msi(child); 5179 } 5180 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5181 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5182 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5183 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5184 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5185 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5186 5187 pci_cfg_save(child, dinfo, 1); 5188 } 5189 5190 /* 5191 * Parse the PCI device database, if loaded, and return a pointer to a 5192 * description of the device. 5193 * 5194 * The database is flat text formatted as follows: 5195 * 5196 * Any line not in a valid format is ignored. 5197 * Lines are terminated with newline '\n' characters. 5198 * 5199 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5200 * the vendor name. 5201 * 5202 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5203 * - devices cannot be listed without a corresponding VENDOR line. 5204 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5205 * another TAB, then the device name. 5206 */ 5207 5208 /* 5209 * Assuming (ptr) points to the beginning of a line in the database, 5210 * return the vendor or device and description of the next entry. 5211 * The value of (vendor) or (device) inappropriate for the entry type 5212 * is set to -1. Returns nonzero at the end of the database. 5213 * 5214 * Note that this is slightly unrobust in the face of corrupt data; 5215 * we attempt to safeguard against this by spamming the end of the 5216 * database with a newline when we initialise. 5217 */ 5218 static int 5219 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5220 { 5221 char *cp = *ptr; 5222 int left; 5223 5224 *device = -1; 5225 *vendor = -1; 5226 **desc = '\0'; 5227 for (;;) { 5228 left = pci_vendordata_size - (cp - pci_vendordata); 5229 if (left <= 0) { 5230 *ptr = cp; 5231 return(1); 5232 } 5233 5234 /* vendor entry? */ 5235 if (*cp != '\t' && 5236 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5237 break; 5238 /* device entry? */ 5239 if (*cp == '\t' && 5240 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5241 break; 5242 5243 /* skip to next line */ 5244 while (*cp != '\n' && left > 0) { 5245 cp++; 5246 left--; 5247 } 5248 if (*cp == '\n') { 5249 cp++; 5250 left--; 5251 } 5252 } 5253 /* skip to next line */ 5254 while (*cp != '\n' && left > 0) { 5255 cp++; 5256 left--; 5257 } 5258 if (*cp == '\n' && left > 0) 5259 cp++; 5260 *ptr = cp; 5261 return(0); 5262 } 5263 5264 static char * 5265 pci_describe_device(device_t dev) 5266 { 5267 int vendor, device; 5268 char *desc, *vp, *dp, *line; 5269 5270 desc = vp = dp = NULL; 5271 5272 /* 5273 * If we have no vendor data, we can't do anything. 5274 */ 5275 if (pci_vendordata == NULL) 5276 goto out; 5277 5278 /* 5279 * Scan the vendor data looking for this device 5280 */ 5281 line = pci_vendordata; 5282 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5283 goto out; 5284 for (;;) { 5285 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5286 goto out; 5287 if (vendor == pci_get_vendor(dev)) 5288 break; 5289 } 5290 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5291 goto out; 5292 for (;;) { 5293 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5294 *dp = 0; 5295 break; 5296 } 5297 if (vendor != -1) { 5298 *dp = 0; 5299 break; 5300 } 5301 if (device == pci_get_device(dev)) 5302 break; 5303 } 5304 if (dp[0] == '\0') 5305 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5306 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5307 NULL) 5308 sprintf(desc, "%s, %s", vp, dp); 5309 out: 5310 if (vp != NULL) 5311 free(vp, M_DEVBUF); 5312 if (dp != NULL) 5313 free(dp, M_DEVBUF); 5314 return(desc); 5315 } 5316 5317 int 5318 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5319 { 5320 struct pci_devinfo *dinfo; 5321 pcicfgregs *cfg; 5322 5323 dinfo = device_get_ivars(child); 5324 cfg = &dinfo->cfg; 5325 5326 switch (which) { 5327 case PCI_IVAR_ETHADDR: 5328 /* 5329 * The generic accessor doesn't deal with failure, so 5330 * we set the return value, then return an error. 5331 */ 5332 *((uint8_t **) result) = NULL; 5333 return (EINVAL); 5334 case PCI_IVAR_SUBVENDOR: 5335 *result = cfg->subvendor; 5336 break; 5337 case PCI_IVAR_SUBDEVICE: 5338 *result = cfg->subdevice; 5339 break; 5340 case PCI_IVAR_VENDOR: 5341 *result = cfg->vendor; 5342 break; 5343 case PCI_IVAR_DEVICE: 5344 *result = cfg->device; 5345 break; 5346 case PCI_IVAR_DEVID: 5347 *result = (cfg->device << 16) | cfg->vendor; 5348 break; 5349 case PCI_IVAR_CLASS: 5350 *result = cfg->baseclass; 5351 break; 5352 case PCI_IVAR_SUBCLASS: 5353 *result = cfg->subclass; 5354 break; 5355 case PCI_IVAR_PROGIF: 5356 *result = cfg->progif; 5357 break; 5358 case PCI_IVAR_REVID: 5359 *result = cfg->revid; 5360 break; 5361 case PCI_IVAR_INTPIN: 5362 *result = cfg->intpin; 5363 break; 5364 case PCI_IVAR_IRQ: 5365 *result = cfg->intline; 5366 break; 5367 case PCI_IVAR_DOMAIN: 5368 *result = cfg->domain; 5369 break; 5370 case PCI_IVAR_BUS: 5371 *result = cfg->bus; 5372 break; 5373 case PCI_IVAR_SLOT: 5374 *result = cfg->slot; 5375 break; 5376 case PCI_IVAR_FUNCTION: 5377 *result = cfg->func; 5378 break; 5379 case PCI_IVAR_CMDREG: 5380 *result = cfg->cmdreg; 5381 break; 5382 case PCI_IVAR_CACHELNSZ: 5383 *result = cfg->cachelnsz; 5384 break; 5385 case PCI_IVAR_MINGNT: 5386 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5387 *result = -1; 5388 return (EINVAL); 5389 } 5390 *result = cfg->mingnt; 5391 break; 5392 case PCI_IVAR_MAXLAT: 5393 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5394 *result = -1; 5395 return (EINVAL); 5396 } 5397 *result = cfg->maxlat; 5398 break; 5399 case PCI_IVAR_LATTIMER: 5400 *result = cfg->lattimer; 5401 break; 5402 default: 5403 return (ENOENT); 5404 } 5405 return (0); 5406 } 5407 5408 int 5409 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5410 { 5411 struct pci_devinfo *dinfo; 5412 5413 dinfo = device_get_ivars(child); 5414 5415 switch (which) { 5416 case PCI_IVAR_INTPIN: 5417 dinfo->cfg.intpin = value; 5418 return (0); 5419 case PCI_IVAR_ETHADDR: 5420 case PCI_IVAR_SUBVENDOR: 5421 case PCI_IVAR_SUBDEVICE: 5422 case PCI_IVAR_VENDOR: 5423 case PCI_IVAR_DEVICE: 5424 case PCI_IVAR_DEVID: 5425 case PCI_IVAR_CLASS: 5426 case PCI_IVAR_SUBCLASS: 5427 case PCI_IVAR_PROGIF: 5428 case PCI_IVAR_REVID: 5429 case PCI_IVAR_IRQ: 5430 case PCI_IVAR_DOMAIN: 5431 case PCI_IVAR_BUS: 5432 case PCI_IVAR_SLOT: 5433 case PCI_IVAR_FUNCTION: 5434 return (EINVAL); /* disallow for now */ 5435 5436 default: 5437 return (ENOENT); 5438 } 5439 } 5440 5441 #include "opt_ddb.h" 5442 #ifdef DDB 5443 #include <ddb/ddb.h> 5444 #include <sys/cons.h> 5445 5446 /* 5447 * List resources based on pci map registers, used for within ddb 5448 */ 5449 5450 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5451 { 5452 struct pci_devinfo *dinfo; 5453 struct devlist *devlist_head; 5454 struct pci_conf *p; 5455 const char *name; 5456 int i, error, none_count; 5457 5458 none_count = 0; 5459 /* get the head of the device queue */ 5460 devlist_head = &pci_devq; 5461 5462 /* 5463 * Go through the list of devices and print out devices 5464 */ 5465 for (error = 0, i = 0, 5466 dinfo = STAILQ_FIRST(devlist_head); 5467 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5468 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5469 /* Populate pd_name and pd_unit */ 5470 name = NULL; 5471 if (dinfo->cfg.dev) 5472 name = device_get_name(dinfo->cfg.dev); 5473 5474 p = &dinfo->conf; 5475 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5476 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5477 (name && *name) ? name : "none", 5478 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5479 none_count++, 5480 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5481 p->pc_sel.pc_func, (p->pc_class << 16) | 5482 (p->pc_subclass << 8) | p->pc_progif, 5483 (p->pc_subdevice << 16) | p->pc_subvendor, 5484 (p->pc_device << 16) | p->pc_vendor, 5485 p->pc_revid, p->pc_hdr); 5486 } 5487 } 5488 #endif /* DDB */ 5489 5490 struct resource * 5491 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5492 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5493 u_int flags) 5494 { 5495 struct pci_devinfo *dinfo = device_get_ivars(child); 5496 struct resource_list *rl = &dinfo->resources; 5497 struct resource *res; 5498 struct pci_map *pm; 5499 uint16_t cmd; 5500 pci_addr_t map, testval; 5501 int mapsize; 5502 5503 res = NULL; 5504 5505 /* If rid is managed by EA, ignore it */ 5506 if (pci_ea_is_enabled(child, *rid)) 5507 goto out; 5508 5509 pm = pci_find_bar(child, *rid); 5510 if (pm != NULL) { 5511 /* This is a BAR that we failed to allocate earlier. */ 5512 mapsize = pm->pm_size; 5513 map = pm->pm_value; 5514 } else { 5515 /* 5516 * Weed out the bogons, and figure out how large the 5517 * BAR/map is. BARs that read back 0 here are bogus 5518 * and unimplemented. Note: atapci in legacy mode are 5519 * special and handled elsewhere in the code. If you 5520 * have a atapci device in legacy mode and it fails 5521 * here, that other code is broken. 5522 */ 5523 pci_read_bar(child, *rid, &map, &testval, NULL); 5524 5525 /* 5526 * Determine the size of the BAR and ignore BARs with a size 5527 * of 0. Device ROM BARs use a different mask value. 5528 */ 5529 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5530 mapsize = pci_romsize(testval); 5531 else 5532 mapsize = pci_mapsize(testval); 5533 if (mapsize == 0) 5534 goto out; 5535 pm = pci_add_bar(child, *rid, map, mapsize); 5536 } 5537 5538 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5539 if (type != SYS_RES_MEMORY) { 5540 if (bootverbose) 5541 device_printf(dev, 5542 "child %s requested type %d for rid %#x," 5543 " but the BAR says it is an memio\n", 5544 device_get_nameunit(child), type, *rid); 5545 goto out; 5546 } 5547 } else { 5548 if (type != SYS_RES_IOPORT) { 5549 if (bootverbose) 5550 device_printf(dev, 5551 "child %s requested type %d for rid %#x," 5552 " but the BAR says it is an ioport\n", 5553 device_get_nameunit(child), type, *rid); 5554 goto out; 5555 } 5556 } 5557 5558 /* 5559 * For real BARs, we need to override the size that 5560 * the driver requests, because that's what the BAR 5561 * actually uses and we would otherwise have a 5562 * situation where we might allocate the excess to 5563 * another driver, which won't work. 5564 */ 5565 count = ((pci_addr_t)1 << mapsize) * num; 5566 if (RF_ALIGNMENT(flags) < mapsize) 5567 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5568 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5569 flags |= RF_PREFETCHABLE; 5570 5571 /* 5572 * Allocate enough resource, and then write back the 5573 * appropriate BAR for that resource. 5574 */ 5575 resource_list_add(rl, type, *rid, start, end, count); 5576 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5577 count, flags & ~RF_ACTIVE); 5578 if (res == NULL) { 5579 resource_list_delete(rl, type, *rid); 5580 device_printf(child, 5581 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5582 count, *rid, type, start, end); 5583 goto out; 5584 } 5585 if (bootverbose) 5586 device_printf(child, 5587 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5588 count, *rid, type, rman_get_start(res)); 5589 5590 /* Disable decoding via the CMD register before updating the BAR */ 5591 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5592 pci_write_config(child, PCIR_COMMAND, 5593 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5594 5595 map = rman_get_start(res); 5596 pci_write_bar(child, pm, map); 5597 5598 /* Restore the original value of the CMD register */ 5599 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5600 out: 5601 return (res); 5602 } 5603 5604 struct resource * 5605 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5606 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5607 u_int flags) 5608 { 5609 struct pci_devinfo *dinfo; 5610 struct resource_list *rl; 5611 struct resource_list_entry *rle; 5612 struct resource *res; 5613 pcicfgregs *cfg; 5614 5615 /* 5616 * Perform lazy resource allocation 5617 */ 5618 dinfo = device_get_ivars(child); 5619 rl = &dinfo->resources; 5620 cfg = &dinfo->cfg; 5621 switch (type) { 5622 case PCI_RES_BUS: 5623 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5624 flags)); 5625 case SYS_RES_IRQ: 5626 /* 5627 * Can't alloc legacy interrupt once MSI messages have 5628 * been allocated. 5629 */ 5630 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5631 cfg->msix.msix_alloc > 0)) 5632 return (NULL); 5633 5634 /* 5635 * If the child device doesn't have an interrupt 5636 * routed and is deserving of an interrupt, try to 5637 * assign it one. 5638 */ 5639 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5640 (cfg->intpin != 0)) 5641 pci_assign_interrupt(dev, child, 0); 5642 break; 5643 case SYS_RES_IOPORT: 5644 case SYS_RES_MEMORY: 5645 /* 5646 * PCI-PCI bridge I/O window resources are not BARs. 5647 * For those allocations just pass the request up the 5648 * tree. 5649 */ 5650 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5651 switch (*rid) { 5652 case PCIR_IOBASEL_1: 5653 case PCIR_MEMBASE_1: 5654 case PCIR_PMBASEL_1: 5655 /* 5656 * XXX: Should we bother creating a resource 5657 * list entry? 5658 */ 5659 return (bus_generic_alloc_resource(dev, child, 5660 type, rid, start, end, count, flags)); 5661 } 5662 } 5663 /* Reserve resources for this BAR if needed. */ 5664 rle = resource_list_find(rl, type, *rid); 5665 if (rle == NULL) { 5666 res = pci_reserve_map(dev, child, type, rid, start, end, 5667 count, num, flags); 5668 if (res == NULL) 5669 return (NULL); 5670 } 5671 } 5672 return (resource_list_alloc(rl, dev, child, type, rid, 5673 start, end, count, flags)); 5674 } 5675 5676 struct resource * 5677 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5678 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5679 { 5680 #ifdef PCI_IOV 5681 struct pci_devinfo *dinfo; 5682 #endif 5683 5684 if (device_get_parent(child) != dev) 5685 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5686 type, rid, start, end, count, flags)); 5687 5688 #ifdef PCI_IOV 5689 dinfo = device_get_ivars(child); 5690 if (dinfo->cfg.flags & PCICFG_VF) { 5691 switch (type) { 5692 /* VFs can't have I/O BARs. */ 5693 case SYS_RES_IOPORT: 5694 return (NULL); 5695 case SYS_RES_MEMORY: 5696 return (pci_vf_alloc_mem_resource(dev, child, rid, 5697 start, end, count, flags)); 5698 } 5699 5700 /* Fall through for other types of resource allocations. */ 5701 } 5702 #endif 5703 5704 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5705 count, 1, flags)); 5706 } 5707 5708 int 5709 pci_release_resource(device_t dev, device_t child, struct resource *r) 5710 { 5711 struct pci_devinfo *dinfo; 5712 struct resource_list *rl; 5713 pcicfgregs *cfg __unused; 5714 5715 if (device_get_parent(child) != dev) 5716 return (bus_generic_release_resource(dev, child, r)); 5717 5718 dinfo = device_get_ivars(child); 5719 cfg = &dinfo->cfg; 5720 5721 #ifdef PCI_IOV 5722 if (cfg->flags & PCICFG_VF) { 5723 switch (rman_get_type(r)) { 5724 /* VFs can't have I/O BARs. */ 5725 case SYS_RES_IOPORT: 5726 return (EDOOFUS); 5727 case SYS_RES_MEMORY: 5728 return (pci_vf_release_mem_resource(dev, child, r)); 5729 } 5730 5731 /* Fall through for other types of resource allocations. */ 5732 } 5733 #endif 5734 5735 /* 5736 * PCI-PCI bridge I/O window resources are not BARs. For 5737 * those allocations just pass the request up the tree. 5738 */ 5739 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5740 (rman_get_type(r) == SYS_RES_IOPORT || 5741 rman_get_type(r) == SYS_RES_MEMORY)) { 5742 switch (rman_get_rid(r)) { 5743 case PCIR_IOBASEL_1: 5744 case PCIR_MEMBASE_1: 5745 case PCIR_PMBASEL_1: 5746 return (bus_generic_release_resource(dev, child, r)); 5747 } 5748 } 5749 5750 rl = &dinfo->resources; 5751 return (resource_list_release(rl, dev, child, r)); 5752 } 5753 5754 int 5755 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5756 { 5757 struct pci_devinfo *dinfo; 5758 int error, rid, type; 5759 5760 if (device_get_parent(child) != dev) 5761 return (bus_generic_activate_resource(dev, child, r)); 5762 5763 dinfo = device_get_ivars(child); 5764 #ifdef PCI_IOV 5765 if (dinfo->cfg.flags & PCICFG_VF) { 5766 switch (rman_get_type(r)) { 5767 /* VFs can't have I/O BARs. */ 5768 case SYS_RES_IOPORT: 5769 error = EINVAL; 5770 break; 5771 case SYS_RES_MEMORY: 5772 error = pci_vf_activate_mem_resource(dev, child, r); 5773 break; 5774 default: 5775 error = bus_generic_activate_resource(dev, child, r); 5776 break; 5777 } 5778 } else 5779 #endif 5780 error = bus_generic_activate_resource(dev, child, r); 5781 if (error) 5782 return (error); 5783 5784 rid = rman_get_rid(r); 5785 type = rman_get_type(r); 5786 5787 /* Device ROMs need their decoding explicitly enabled. */ 5788 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5789 pci_write_bar(child, pci_find_bar(child, rid), 5790 rman_get_start(r) | PCIM_BIOS_ENABLE); 5791 5792 /* Enable decoding in the command register when activating BARs. */ 5793 switch (type) { 5794 case SYS_RES_IOPORT: 5795 case SYS_RES_MEMORY: 5796 error = PCI_ENABLE_IO(dev, child, type); 5797 break; 5798 } 5799 return (error); 5800 } 5801 5802 int 5803 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5804 { 5805 struct pci_devinfo *dinfo; 5806 int error, rid, type; 5807 5808 if (device_get_parent(child) != dev) 5809 return (bus_generic_deactivate_resource(dev, child, r)); 5810 5811 dinfo = device_get_ivars(child); 5812 #ifdef PCI_IOV 5813 if (dinfo->cfg.flags & PCICFG_VF) { 5814 switch (rman_get_type(r)) { 5815 /* VFs can't have I/O BARs. */ 5816 case SYS_RES_IOPORT: 5817 error = EINVAL; 5818 break; 5819 case SYS_RES_MEMORY: 5820 error = pci_vf_deactivate_mem_resource(dev, child, r); 5821 break; 5822 default: 5823 error = bus_generic_deactivate_resource(dev, child, r); 5824 break; 5825 } 5826 } else 5827 #endif 5828 error = bus_generic_deactivate_resource(dev, child, r); 5829 if (error) 5830 return (error); 5831 5832 /* Disable decoding for device ROMs. */ 5833 rid = rman_get_rid(r); 5834 type = rman_get_type(r); 5835 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5836 pci_write_bar(child, pci_find_bar(child, rid), 5837 rman_get_start(r)); 5838 return (0); 5839 } 5840 5841 int 5842 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5843 rman_res_t start, rman_res_t end) 5844 { 5845 #ifdef PCI_IOV 5846 struct pci_devinfo *dinfo; 5847 5848 if (device_get_parent(child) != dev) 5849 return (bus_generic_adjust_resource(dev, child, r, start, 5850 end)); 5851 5852 dinfo = device_get_ivars(child); 5853 if (dinfo->cfg.flags & PCICFG_VF) { 5854 switch (rman_get_type(r)) { 5855 /* VFs can't have I/O BARs. */ 5856 case SYS_RES_IOPORT: 5857 return (EINVAL); 5858 case SYS_RES_MEMORY: 5859 return (pci_vf_adjust_mem_resource(dev, child, r, 5860 start, end)); 5861 } 5862 5863 /* Fall through for other types of resource allocations. */ 5864 } 5865 #endif 5866 5867 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5868 } 5869 5870 int 5871 pci_map_resource(device_t dev, device_t child, struct resource *r, 5872 struct resource_map_request *argsp, struct resource_map *map) 5873 { 5874 #ifdef PCI_IOV 5875 struct pci_devinfo *dinfo; 5876 5877 if (device_get_parent(child) != dev) 5878 return (bus_generic_map_resource(dev, child, r, argsp, 5879 map)); 5880 5881 dinfo = device_get_ivars(child); 5882 if (dinfo->cfg.flags & PCICFG_VF) { 5883 switch (rman_get_type(r)) { 5884 /* VFs can't have I/O BARs. */ 5885 case SYS_RES_IOPORT: 5886 return (EINVAL); 5887 case SYS_RES_MEMORY: 5888 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5889 map)); 5890 } 5891 5892 /* Fall through for other types of resource allocations. */ 5893 } 5894 #endif 5895 5896 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5897 } 5898 5899 int 5900 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5901 struct resource_map *map) 5902 { 5903 #ifdef PCI_IOV 5904 struct pci_devinfo *dinfo; 5905 5906 if (device_get_parent(child) != dev) 5907 return (bus_generic_unmap_resource(dev, child, r, map)); 5908 5909 dinfo = device_get_ivars(child); 5910 if (dinfo->cfg.flags & PCICFG_VF) { 5911 switch (rman_get_type(r)) { 5912 /* VFs can't have I/O BARs. */ 5913 case SYS_RES_IOPORT: 5914 return (EINVAL); 5915 case SYS_RES_MEMORY: 5916 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5917 } 5918 5919 /* Fall through for other types of resource allocations. */ 5920 } 5921 #endif 5922 5923 return (bus_generic_unmap_resource(dev, child, r, map)); 5924 } 5925 5926 void 5927 pci_child_deleted(device_t dev, device_t child) 5928 { 5929 struct resource_list_entry *rle; 5930 struct resource_list *rl; 5931 struct pci_devinfo *dinfo; 5932 5933 dinfo = device_get_ivars(child); 5934 rl = &dinfo->resources; 5935 5936 EVENTHANDLER_INVOKE(pci_delete_device, child); 5937 5938 /* Turn off access to resources we're about to free */ 5939 if (bus_child_present(child) != 0) { 5940 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5941 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5942 5943 pci_disable_busmaster(child); 5944 } 5945 5946 /* Free all allocated resources */ 5947 STAILQ_FOREACH(rle, rl, link) { 5948 if (rle->res) { 5949 if (rman_get_flags(rle->res) & RF_ACTIVE || 5950 resource_list_busy(rl, rle->type, rle->rid)) { 5951 pci_printf(&dinfo->cfg, 5952 "Resource still owned, oops. " 5953 "(type=%d, rid=%d, addr=%lx)\n", 5954 rle->type, rle->rid, 5955 rman_get_start(rle->res)); 5956 bus_release_resource(child, rle->type, rle->rid, 5957 rle->res); 5958 } 5959 resource_list_unreserve(rl, dev, child, rle->type, 5960 rle->rid); 5961 } 5962 } 5963 resource_list_free(rl); 5964 5965 pci_freecfg(dinfo); 5966 } 5967 5968 void 5969 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5970 { 5971 struct pci_devinfo *dinfo; 5972 struct resource_list *rl; 5973 struct resource_list_entry *rle; 5974 5975 if (device_get_parent(child) != dev) 5976 return; 5977 5978 dinfo = device_get_ivars(child); 5979 rl = &dinfo->resources; 5980 rle = resource_list_find(rl, type, rid); 5981 if (rle == NULL) 5982 return; 5983 5984 if (rle->res) { 5985 if (rman_get_flags(rle->res) & RF_ACTIVE || 5986 resource_list_busy(rl, type, rid)) { 5987 device_printf(dev, "delete_resource: " 5988 "Resource still owned by child, oops. " 5989 "(type=%d, rid=%d, addr=%jx)\n", 5990 type, rid, rman_get_start(rle->res)); 5991 return; 5992 } 5993 resource_list_unreserve(rl, dev, child, type, rid); 5994 } 5995 resource_list_delete(rl, type, rid); 5996 } 5997 5998 struct resource_list * 5999 pci_get_resource_list (device_t dev, device_t child) 6000 { 6001 struct pci_devinfo *dinfo = device_get_ivars(child); 6002 6003 return (&dinfo->resources); 6004 } 6005 6006 #ifdef IOMMU 6007 bus_dma_tag_t 6008 pci_get_dma_tag(device_t bus, device_t dev) 6009 { 6010 bus_dma_tag_t tag; 6011 struct pci_softc *sc; 6012 6013 if (device_get_parent(dev) == bus) { 6014 /* try iommu and return if it works */ 6015 tag = iommu_get_dma_tag(bus, dev); 6016 } else 6017 tag = NULL; 6018 if (tag == NULL) { 6019 sc = device_get_softc(bus); 6020 tag = sc->sc_dma_tag; 6021 } 6022 return (tag); 6023 } 6024 #else 6025 bus_dma_tag_t 6026 pci_get_dma_tag(device_t bus, device_t dev) 6027 { 6028 struct pci_softc *sc = device_get_softc(bus); 6029 6030 return (sc->sc_dma_tag); 6031 } 6032 #endif 6033 6034 uint32_t 6035 pci_read_config_method(device_t dev, device_t child, int reg, int width) 6036 { 6037 struct pci_devinfo *dinfo = device_get_ivars(child); 6038 pcicfgregs *cfg = &dinfo->cfg; 6039 6040 #ifdef PCI_IOV 6041 /* 6042 * SR-IOV VFs don't implement the VID or DID registers, so we have to 6043 * emulate them here. 6044 */ 6045 if (cfg->flags & PCICFG_VF) { 6046 if (reg == PCIR_VENDOR) { 6047 switch (width) { 6048 case 4: 6049 return (cfg->device << 16 | cfg->vendor); 6050 case 2: 6051 return (cfg->vendor); 6052 case 1: 6053 return (cfg->vendor & 0xff); 6054 default: 6055 return (0xffffffff); 6056 } 6057 } else if (reg == PCIR_DEVICE) { 6058 switch (width) { 6059 /* Note that an unaligned 4-byte read is an error. */ 6060 case 2: 6061 return (cfg->device); 6062 case 1: 6063 return (cfg->device & 0xff); 6064 default: 6065 return (0xffffffff); 6066 } 6067 } 6068 } 6069 #endif 6070 6071 return (PCIB_READ_CONFIG(device_get_parent(dev), 6072 cfg->bus, cfg->slot, cfg->func, reg, width)); 6073 } 6074 6075 void 6076 pci_write_config_method(device_t dev, device_t child, int reg, 6077 uint32_t val, int width) 6078 { 6079 struct pci_devinfo *dinfo = device_get_ivars(child); 6080 pcicfgregs *cfg = &dinfo->cfg; 6081 6082 PCIB_WRITE_CONFIG(device_get_parent(dev), 6083 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6084 } 6085 6086 int 6087 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6088 { 6089 6090 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6091 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6092 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6093 return (0); 6094 } 6095 6096 int 6097 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6098 { 6099 struct pci_devinfo *dinfo; 6100 pcicfgregs *cfg; 6101 6102 dinfo = device_get_ivars(child); 6103 cfg = &dinfo->cfg; 6104 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6105 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6106 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6107 cfg->progif); 6108 return (0); 6109 } 6110 6111 int 6112 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6113 struct sbuf *sb) 6114 { 6115 device_t parent = device_get_parent(bus); 6116 int rv; 6117 6118 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6119 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6120 if (rv == 0) { 6121 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6122 pci_get_function(child)); 6123 } 6124 return (0); 6125 } 6126 return (bus_generic_get_device_path(bus, child, locator, sb)); 6127 } 6128 6129 int 6130 pci_assign_interrupt_method(device_t dev, device_t child) 6131 { 6132 struct pci_devinfo *dinfo = device_get_ivars(child); 6133 pcicfgregs *cfg = &dinfo->cfg; 6134 6135 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6136 cfg->intpin)); 6137 } 6138 6139 static void 6140 pci_lookup(void *arg, const char *name, device_t *dev) 6141 { 6142 long val; 6143 char *end; 6144 int domain, bus, slot, func; 6145 6146 if (*dev != NULL) 6147 return; 6148 6149 /* 6150 * Accept pciconf-style selectors of either pciD:B:S:F or 6151 * pciB:S:F. In the latter case, the domain is assumed to 6152 * be zero. 6153 */ 6154 if (strncmp(name, "pci", 3) != 0) 6155 return; 6156 val = strtol(name + 3, &end, 10); 6157 if (val < 0 || val > INT_MAX || *end != ':') 6158 return; 6159 domain = val; 6160 val = strtol(end + 1, &end, 10); 6161 if (val < 0 || val > INT_MAX || *end != ':') 6162 return; 6163 bus = val; 6164 val = strtol(end + 1, &end, 10); 6165 if (val < 0 || val > INT_MAX) 6166 return; 6167 slot = val; 6168 if (*end == ':') { 6169 val = strtol(end + 1, &end, 10); 6170 if (val < 0 || val > INT_MAX || *end != '\0') 6171 return; 6172 func = val; 6173 } else if (*end == '\0') { 6174 func = slot; 6175 slot = bus; 6176 bus = domain; 6177 domain = 0; 6178 } else 6179 return; 6180 6181 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6182 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6183 return; 6184 6185 *dev = pci_find_dbsf(domain, bus, slot, func); 6186 } 6187 6188 static int 6189 pci_modevent(module_t mod, int what, void *arg) 6190 { 6191 static struct cdev *pci_cdev; 6192 static eventhandler_tag tag; 6193 6194 switch (what) { 6195 case MOD_LOAD: 6196 STAILQ_INIT(&pci_devq); 6197 pci_generation = 0; 6198 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6199 "pci"); 6200 pci_load_vendor_data(); 6201 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6202 1000); 6203 break; 6204 6205 case MOD_UNLOAD: 6206 if (tag != NULL) 6207 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6208 destroy_dev(pci_cdev); 6209 break; 6210 } 6211 6212 return (0); 6213 } 6214 6215 static void 6216 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6217 { 6218 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6219 struct pcicfg_pcie *cfg; 6220 int version, pos; 6221 6222 cfg = &dinfo->cfg.pcie; 6223 pos = cfg->pcie_location; 6224 6225 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6226 6227 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6228 6229 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6230 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6231 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6232 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6233 6234 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6235 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6236 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6237 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6238 6239 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6240 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6241 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6242 6243 if (version > 1) { 6244 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6245 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6246 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6247 } 6248 #undef WREG 6249 } 6250 6251 static void 6252 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6253 { 6254 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6255 dinfo->cfg.pcix.pcix_command, 2); 6256 } 6257 6258 void 6259 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6260 { 6261 6262 /* 6263 * Restore the device to full power mode. We must do this 6264 * before we restore the registers because moving from D3 to 6265 * D0 will cause the chip's BARs and some other registers to 6266 * be reset to some unknown power on reset values. Cut down 6267 * the noise on boot by doing nothing if we are already in 6268 * state D0. 6269 */ 6270 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6271 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6272 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6273 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6274 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6275 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6276 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6277 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6278 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6279 case PCIM_HDRTYPE_NORMAL: 6280 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6281 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6282 break; 6283 case PCIM_HDRTYPE_BRIDGE: 6284 pci_write_config(dev, PCIR_SECLAT_1, 6285 dinfo->cfg.bridge.br_seclat, 1); 6286 pci_write_config(dev, PCIR_SUBBUS_1, 6287 dinfo->cfg.bridge.br_subbus, 1); 6288 pci_write_config(dev, PCIR_SECBUS_1, 6289 dinfo->cfg.bridge.br_secbus, 1); 6290 pci_write_config(dev, PCIR_PRIBUS_1, 6291 dinfo->cfg.bridge.br_pribus, 1); 6292 pci_write_config(dev, PCIR_BRIDGECTL_1, 6293 dinfo->cfg.bridge.br_control, 2); 6294 break; 6295 case PCIM_HDRTYPE_CARDBUS: 6296 pci_write_config(dev, PCIR_SECLAT_2, 6297 dinfo->cfg.bridge.br_seclat, 1); 6298 pci_write_config(dev, PCIR_SUBBUS_2, 6299 dinfo->cfg.bridge.br_subbus, 1); 6300 pci_write_config(dev, PCIR_SECBUS_2, 6301 dinfo->cfg.bridge.br_secbus, 1); 6302 pci_write_config(dev, PCIR_PRIBUS_2, 6303 dinfo->cfg.bridge.br_pribus, 1); 6304 pci_write_config(dev, PCIR_BRIDGECTL_2, 6305 dinfo->cfg.bridge.br_control, 2); 6306 break; 6307 } 6308 pci_restore_bars(dev); 6309 6310 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6311 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6312 6313 /* 6314 * Restore extended capabilities for PCI-Express and PCI-X 6315 */ 6316 if (dinfo->cfg.pcie.pcie_location != 0) 6317 pci_cfg_restore_pcie(dev, dinfo); 6318 if (dinfo->cfg.pcix.pcix_location != 0) 6319 pci_cfg_restore_pcix(dev, dinfo); 6320 6321 /* Restore MSI and MSI-X configurations if they are present. */ 6322 if (dinfo->cfg.msi.msi_location != 0) 6323 pci_resume_msi(dev); 6324 if (dinfo->cfg.msix.msix_location != 0) 6325 pci_resume_msix(dev); 6326 6327 #ifdef PCI_IOV 6328 if (dinfo->cfg.iov != NULL) 6329 pci_iov_cfg_restore(dev, dinfo); 6330 #endif 6331 } 6332 6333 static void 6334 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6335 { 6336 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6337 struct pcicfg_pcie *cfg; 6338 int version, pos; 6339 6340 cfg = &dinfo->cfg.pcie; 6341 pos = cfg->pcie_location; 6342 6343 cfg->pcie_flags = RREG(PCIER_FLAGS); 6344 6345 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6346 6347 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6348 6349 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6350 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6351 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6352 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6353 6354 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6355 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6356 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6357 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6358 6359 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6360 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6361 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6362 6363 if (version > 1) { 6364 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6365 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6366 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6367 } 6368 #undef RREG 6369 } 6370 6371 static void 6372 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6373 { 6374 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6375 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6376 } 6377 6378 void 6379 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6380 { 6381 uint32_t cls; 6382 int ps; 6383 6384 /* 6385 * Some drivers apparently write to these registers w/o updating our 6386 * cached copy. No harm happens if we update the copy, so do so here 6387 * so we can restore them. The COMMAND register is modified by the 6388 * bus w/o updating the cache. This should represent the normally 6389 * writable portion of the 'defined' part of type 0/1/2 headers. 6390 */ 6391 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6392 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6393 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6394 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6395 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6396 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6397 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6398 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6399 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6400 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6401 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6402 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6403 case PCIM_HDRTYPE_NORMAL: 6404 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6405 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6406 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6407 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6408 break; 6409 case PCIM_HDRTYPE_BRIDGE: 6410 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6411 PCIR_SECLAT_1, 1); 6412 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6413 PCIR_SUBBUS_1, 1); 6414 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6415 PCIR_SECBUS_1, 1); 6416 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6417 PCIR_PRIBUS_1, 1); 6418 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6419 PCIR_BRIDGECTL_1, 2); 6420 break; 6421 case PCIM_HDRTYPE_CARDBUS: 6422 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6423 PCIR_SECLAT_2, 1); 6424 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6425 PCIR_SUBBUS_2, 1); 6426 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6427 PCIR_SECBUS_2, 1); 6428 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6429 PCIR_PRIBUS_2, 1); 6430 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6431 PCIR_BRIDGECTL_2, 2); 6432 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6433 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6434 break; 6435 } 6436 6437 if (dinfo->cfg.pcie.pcie_location != 0) 6438 pci_cfg_save_pcie(dev, dinfo); 6439 6440 if (dinfo->cfg.pcix.pcix_location != 0) 6441 pci_cfg_save_pcix(dev, dinfo); 6442 6443 #ifdef PCI_IOV 6444 if (dinfo->cfg.iov != NULL) 6445 pci_iov_cfg_save(dev, dinfo); 6446 #endif 6447 6448 /* 6449 * don't set the state for display devices, base peripherals and 6450 * memory devices since bad things happen when they are powered down. 6451 * We should (a) have drivers that can easily detach and (b) use 6452 * generic drivers for these devices so that some device actually 6453 * attaches. We need to make sure that when we implement (a) we don't 6454 * power the device down on a reattach. 6455 */ 6456 cls = pci_get_class(dev); 6457 if (!setstate) 6458 return; 6459 switch (pci_do_power_nodriver) 6460 { 6461 case 0: /* NO powerdown at all */ 6462 return; 6463 case 1: /* Conservative about what to power down */ 6464 if (cls == PCIC_STORAGE) 6465 return; 6466 /*FALLTHROUGH*/ 6467 case 2: /* Aggressive about what to power down */ 6468 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6469 cls == PCIC_BASEPERIPH) 6470 return; 6471 /*FALLTHROUGH*/ 6472 case 3: /* Power down everything */ 6473 break; 6474 } 6475 /* 6476 * PCI spec says we can only go into D3 state from D0 state. 6477 * Transition from D[12] into D0 before going to D3 state. 6478 */ 6479 ps = pci_get_powerstate(dev); 6480 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6481 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6482 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6483 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6484 } 6485 6486 /* Wrapper APIs suitable for device driver use. */ 6487 void 6488 pci_save_state(device_t dev) 6489 { 6490 struct pci_devinfo *dinfo; 6491 6492 dinfo = device_get_ivars(dev); 6493 pci_cfg_save(dev, dinfo, 0); 6494 } 6495 6496 void 6497 pci_restore_state(device_t dev) 6498 { 6499 struct pci_devinfo *dinfo; 6500 6501 dinfo = device_get_ivars(dev); 6502 pci_cfg_restore(dev, dinfo); 6503 } 6504 6505 static int 6506 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6507 uintptr_t *id) 6508 { 6509 6510 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6511 } 6512 6513 /* Find the upstream port of a given PCI device in a root complex. */ 6514 device_t 6515 pci_find_pcie_root_port(device_t dev) 6516 { 6517 struct pci_devinfo *dinfo; 6518 devclass_t pci_class; 6519 device_t pcib, bus; 6520 6521 pci_class = devclass_find("pci"); 6522 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6523 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6524 6525 /* 6526 * Walk the bridge hierarchy until we find a PCI-e root 6527 * port or a non-PCI device. 6528 */ 6529 for (;;) { 6530 bus = device_get_parent(dev); 6531 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6532 device_get_nameunit(dev))); 6533 6534 pcib = device_get_parent(bus); 6535 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6536 device_get_nameunit(bus))); 6537 6538 /* 6539 * pcib's parent must be a PCI bus for this to be a 6540 * PCI-PCI bridge. 6541 */ 6542 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6543 return (NULL); 6544 6545 dinfo = device_get_ivars(pcib); 6546 if (dinfo->cfg.pcie.pcie_location != 0 && 6547 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6548 return (pcib); 6549 6550 dev = pcib; 6551 } 6552 } 6553 6554 /* 6555 * Wait for pending transactions to complete on a PCI-express function. 6556 * 6557 * The maximum delay is specified in milliseconds in max_delay. Note 6558 * that this function may sleep. 6559 * 6560 * Returns true if the function is idle and false if the timeout is 6561 * exceeded. If dev is not a PCI-express function, this returns true. 6562 */ 6563 bool 6564 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6565 { 6566 struct pci_devinfo *dinfo = device_get_ivars(dev); 6567 uint16_t sta; 6568 int cap; 6569 6570 cap = dinfo->cfg.pcie.pcie_location; 6571 if (cap == 0) 6572 return (true); 6573 6574 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6575 while (sta & PCIEM_STA_TRANSACTION_PND) { 6576 if (max_delay == 0) 6577 return (false); 6578 6579 /* Poll once every 100 milliseconds up to the timeout. */ 6580 if (max_delay > 100) { 6581 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6582 max_delay -= 100; 6583 } else { 6584 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6585 C_HARDCLOCK); 6586 max_delay = 0; 6587 } 6588 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6589 } 6590 6591 return (true); 6592 } 6593 6594 /* 6595 * Determine the maximum Completion Timeout in microseconds. 6596 * 6597 * For non-PCI-express functions this returns 0. 6598 */ 6599 int 6600 pcie_get_max_completion_timeout(device_t dev) 6601 { 6602 struct pci_devinfo *dinfo = device_get_ivars(dev); 6603 int cap; 6604 6605 cap = dinfo->cfg.pcie.pcie_location; 6606 if (cap == 0) 6607 return (0); 6608 6609 /* 6610 * Functions using the 1.x spec use the default timeout range of 6611 * 50 microseconds to 50 milliseconds. Functions that do not 6612 * support programmable timeouts also use this range. 6613 */ 6614 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6615 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6616 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6617 return (50 * 1000); 6618 6619 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6620 PCIEM_CTL2_COMP_TIMO_VAL) { 6621 case PCIEM_CTL2_COMP_TIMO_100US: 6622 return (100); 6623 case PCIEM_CTL2_COMP_TIMO_10MS: 6624 return (10 * 1000); 6625 case PCIEM_CTL2_COMP_TIMO_55MS: 6626 return (55 * 1000); 6627 case PCIEM_CTL2_COMP_TIMO_210MS: 6628 return (210 * 1000); 6629 case PCIEM_CTL2_COMP_TIMO_900MS: 6630 return (900 * 1000); 6631 case PCIEM_CTL2_COMP_TIMO_3500MS: 6632 return (3500 * 1000); 6633 case PCIEM_CTL2_COMP_TIMO_13S: 6634 return (13 * 1000 * 1000); 6635 case PCIEM_CTL2_COMP_TIMO_64S: 6636 return (64 * 1000 * 1000); 6637 default: 6638 return (50 * 1000); 6639 } 6640 } 6641 6642 void 6643 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6644 { 6645 struct pci_devinfo *dinfo = device_get_ivars(dev); 6646 const char *s; 6647 int aer; 6648 uint32_t r, r1; 6649 uint16_t rs; 6650 6651 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6652 s = "Correctable"; 6653 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6654 s = "Uncorrectable (Non-Fatal)"; 6655 else 6656 s = "Uncorrectable (Fatal)"; 6657 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6658 if (aerp) { 6659 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6660 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6661 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6662 } else { 6663 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6664 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6665 } 6666 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6667 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6668 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6669 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6670 printf(" severity 0x%08x first %d\n", 6671 r, rs & 0x1f); 6672 } else 6673 printf("\n"); 6674 } 6675 6676 /* As kind of recovery just report and clear the error statuses. */ 6677 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6678 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6679 if (r != 0) { 6680 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6681 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6682 } 6683 6684 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6685 if (r != 0) { 6686 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6687 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6688 } 6689 } 6690 if (dinfo->cfg.pcie.pcie_location != 0) { 6691 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6692 PCIER_DEVICE_STA, 2); 6693 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6694 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6695 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6696 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6697 PCIER_DEVICE_STA, rs, 2); 6698 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6699 } 6700 } 6701 } 6702 6703 /* 6704 * Perform a Function Level Reset (FLR) on a device. 6705 * 6706 * This function first waits for any pending transactions to complete 6707 * within the timeout specified by max_delay. If transactions are 6708 * still pending, the function will return false without attempting a 6709 * reset. 6710 * 6711 * If dev is not a PCI-express function or does not support FLR, this 6712 * function returns false. 6713 * 6714 * Note that no registers are saved or restored. The caller is 6715 * responsible for saving and restoring any registers including 6716 * PCI-standard registers via pci_save_state() and 6717 * pci_restore_state(). 6718 */ 6719 bool 6720 pcie_flr(device_t dev, u_int max_delay, bool force) 6721 { 6722 struct pci_devinfo *dinfo = device_get_ivars(dev); 6723 uint16_t cmd, ctl; 6724 int compl_delay; 6725 int cap; 6726 6727 cap = dinfo->cfg.pcie.pcie_location; 6728 if (cap == 0) 6729 return (false); 6730 6731 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6732 return (false); 6733 6734 /* 6735 * Disable busmastering to prevent generation of new 6736 * transactions while waiting for the device to go idle. If 6737 * the idle timeout fails, the command register is restored 6738 * which will re-enable busmastering. 6739 */ 6740 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6741 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6742 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6743 if (!force) { 6744 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6745 return (false); 6746 } 6747 pci_printf(&dinfo->cfg, 6748 "Resetting with transactions pending after %d ms\n", 6749 max_delay); 6750 6751 /* 6752 * Extend the post-FLR delay to cover the maximum 6753 * Completion Timeout delay of anything in flight 6754 * during the FLR delay. Enforce a minimum delay of 6755 * at least 10ms. 6756 */ 6757 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6758 if (compl_delay < 10) 6759 compl_delay = 10; 6760 } else 6761 compl_delay = 0; 6762 6763 /* Initiate the reset. */ 6764 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6765 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6766 PCIEM_CTL_INITIATE_FLR, 2); 6767 6768 /* Wait for 100ms. */ 6769 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6770 6771 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6772 PCIEM_STA_TRANSACTION_PND) 6773 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6774 return (true); 6775 } 6776 6777 /* 6778 * Attempt a power-management reset by cycling the device in/out of D3 6779 * state. PCI spec says we can only go into D3 state from D0 state. 6780 * Transition from D[12] into D0 before going to D3 state. 6781 */ 6782 int 6783 pci_power_reset(device_t dev) 6784 { 6785 int ps; 6786 6787 ps = pci_get_powerstate(dev); 6788 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6789 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6790 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6791 pci_set_powerstate(dev, ps); 6792 return (0); 6793 } 6794 6795 /* 6796 * Try link drop and retrain of the downstream port of upstream 6797 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6798 * cause Conventional Hot reset of the device in the slot. 6799 * Alternative, for PCIe, could be the secondary bus reset initiatied 6800 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6801 */ 6802 int 6803 pcie_link_reset(device_t port, int pcie_location) 6804 { 6805 uint16_t v; 6806 6807 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6808 v |= PCIEM_LINK_CTL_LINK_DIS; 6809 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6810 pause_sbt("pcier1", mstosbt(20), 0, 0); 6811 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6812 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6813 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6814 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6815 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6816 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6817 } 6818 6819 static int 6820 pci_reset_post(device_t dev, device_t child) 6821 { 6822 6823 if (dev == device_get_parent(child)) 6824 pci_restore_state(child); 6825 return (0); 6826 } 6827 6828 static int 6829 pci_reset_prepare(device_t dev, device_t child) 6830 { 6831 6832 if (dev == device_get_parent(child)) 6833 pci_save_state(child); 6834 return (0); 6835 } 6836 6837 static int 6838 pci_reset_child(device_t dev, device_t child, int flags) 6839 { 6840 int error; 6841 6842 if (dev == NULL || device_get_parent(child) != dev) 6843 return (0); 6844 if ((flags & DEVF_RESET_DETACH) != 0) { 6845 error = device_get_state(child) == DS_ATTACHED ? 6846 device_detach(child) : 0; 6847 } else { 6848 error = BUS_SUSPEND_CHILD(dev, child); 6849 } 6850 if (error == 0) { 6851 if (!pcie_flr(child, 1000, false)) { 6852 error = BUS_RESET_PREPARE(dev, child); 6853 if (error == 0) 6854 pci_power_reset(child); 6855 BUS_RESET_POST(dev, child); 6856 } 6857 if ((flags & DEVF_RESET_DETACH) != 0) 6858 device_probe_and_attach(child); 6859 else 6860 BUS_RESUME_CHILD(dev, child); 6861 } 6862 return (error); 6863 } 6864 6865 const struct pci_device_table * 6866 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6867 { 6868 bool match; 6869 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6870 6871 vendor = pci_get_vendor(child); 6872 device = pci_get_device(child); 6873 subvendor = pci_get_subvendor(child); 6874 subdevice = pci_get_subdevice(child); 6875 class = pci_get_class(child); 6876 subclass = pci_get_subclass(child); 6877 revid = pci_get_revid(child); 6878 while (nelt-- > 0) { 6879 match = true; 6880 if (id->match_flag_vendor) 6881 match &= vendor == id->vendor; 6882 if (id->match_flag_device) 6883 match &= device == id->device; 6884 if (id->match_flag_subvendor) 6885 match &= subvendor == id->subvendor; 6886 if (id->match_flag_subdevice) 6887 match &= subdevice == id->subdevice; 6888 if (id->match_flag_class) 6889 match &= class == id->class_id; 6890 if (id->match_flag_subclass) 6891 match &= subclass == id->subclass; 6892 if (id->match_flag_revid) 6893 match &= revid == id->revid; 6894 if (match) 6895 return (id); 6896 id++; 6897 } 6898 return (NULL); 6899 } 6900 6901 static void 6902 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6903 { 6904 const char *dev_name; 6905 device_t dev; 6906 6907 dev = dinfo->cfg.dev; 6908 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6909 dinfo->cfg.slot, dinfo->cfg.func); 6910 dev_name = device_get_name(dev); 6911 if (dev_name != NULL) 6912 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6913 } 6914 6915 void 6916 pci_print_faulted_dev(void) 6917 { 6918 struct pci_devinfo *dinfo; 6919 device_t dev; 6920 int aer, i; 6921 uint32_t r1, r2; 6922 uint16_t status; 6923 6924 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6925 dev = dinfo->cfg.dev; 6926 status = pci_read_config(dev, PCIR_STATUS, 2); 6927 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6928 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6929 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6930 if (status != 0) { 6931 pci_print_faulted_dev_name(dinfo); 6932 printf(" error 0x%04x\n", status); 6933 } 6934 if (dinfo->cfg.pcie.pcie_location != 0) { 6935 status = pci_read_config(dev, 6936 dinfo->cfg.pcie.pcie_location + 6937 PCIER_DEVICE_STA, 2); 6938 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6939 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6940 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6941 pci_print_faulted_dev_name(dinfo); 6942 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6943 pci_read_config(dev, 6944 dinfo->cfg.pcie.pcie_location + 6945 PCIER_DEVICE_CTL, 2), 6946 status); 6947 } 6948 } 6949 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6950 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6951 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6952 if (r1 != 0 || r2 != 0) { 6953 pci_print_faulted_dev_name(dinfo); 6954 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6955 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6956 r1, pci_read_config(dev, aer + 6957 PCIR_AER_UC_MASK, 4), 6958 pci_read_config(dev, aer + 6959 PCIR_AER_UC_SEVERITY, 4), 6960 r2, pci_read_config(dev, aer + 6961 PCIR_AER_COR_MASK, 4), 6962 pci_read_config(dev, aer + 6963 PCIR_AER_CAP_CONTROL, 4)); 6964 for (i = 0; i < 4; i++) { 6965 r1 = pci_read_config(dev, aer + 6966 PCIR_AER_HEADER_LOG + i * 4, 4); 6967 printf(" HL%d: 0x%08x\n", i, r1); 6968 } 6969 } 6970 } 6971 } 6972 } 6973 6974 #ifdef DDB 6975 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6976 { 6977 6978 pci_print_faulted_dev(); 6979 } 6980 6981 static void 6982 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6983 { 6984 device_t dev; 6985 int aer; 6986 uint32_t r; 6987 6988 dev = dinfo->cfg.dev; 6989 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6990 PCIER_DEVICE_STA, 2); 6991 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6992 PCIER_DEVICE_STA, r, 2); 6993 6994 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6995 return; 6996 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6997 if (r != 0) 6998 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6999 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 7000 if (r != 0) 7001 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 7002 } 7003 7004 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 7005 { 7006 struct pci_devinfo *dinfo; 7007 device_t dev; 7008 uint16_t status, status1; 7009 7010 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 7011 dev = dinfo->cfg.dev; 7012 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 7013 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 7014 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 7015 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 7016 if (status1 != 0) { 7017 status &= ~status1; 7018 pci_write_config(dev, PCIR_STATUS, status, 2); 7019 } 7020 if (dinfo->cfg.pcie.pcie_location != 0) 7021 db_clear_pcie_errors(dinfo); 7022 } 7023 } 7024 #endif 7025