1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcireg.h> 42 43 /* 44 * Chipset fixups. 45 * 46 * These routines are invoked during the probe phase for devices which 47 * typically don't have specific device drivers, but which require 48 * some cleaning up. 49 */ 50 51 static int fixup_pci_probe(device_t dev); 52 static void fixwsc_natoma(device_t dev); 53 static void fixc1_nforce2(device_t dev); 54 55 static device_method_t fixup_pci_methods[] = { 56 /* Device interface */ 57 DEVMETHOD(device_probe, fixup_pci_probe), 58 DEVMETHOD(device_attach, bus_generic_attach), 59 { 0, 0 } 60 }; 61 62 static driver_t fixup_pci_driver = { 63 "fixup_pci", 64 fixup_pci_methods, 65 0, 66 }; 67 68 DRIVER_MODULE(fixup_pci, pci, fixup_pci_driver, 0, 0); 69 70 static int 71 fixup_pci_probe(device_t dev) 72 { 73 switch (pci_get_devid(dev)) { 74 case 0x12378086: /* Intel 82440FX (Natoma) */ 75 fixwsc_natoma(dev); 76 break; 77 case 0x01e010de: /* nVidia nForce2 */ 78 fixc1_nforce2(dev); 79 break; 80 } 81 return(ENXIO); 82 } 83 84 static void 85 fixwsc_natoma(device_t dev) 86 { 87 int pmccfg; 88 89 pmccfg = pci_read_config(dev, 0x50, 2); 90 #if defined(SMP) 91 if (pmccfg & 0x8000) { 92 device_printf(dev, "correcting Natoma config for SMP\n"); 93 pmccfg &= ~0x8000; 94 pci_write_config(dev, 0x50, pmccfg, 2); 95 } 96 #else 97 if ((pmccfg & 0x8000) == 0) { 98 device_printf(dev, "correcting Natoma config for non-SMP\n"); 99 pmccfg |= 0x8000; 100 pci_write_config(dev, 0x50, pmccfg, 2); 101 } 102 #endif 103 } 104 105 /* 106 * Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work 107 * around a hang that is triggered when the CPU generates a very fast 108 * CONNECT/HALT cycle sequence. Specifically, the hang can result in 109 * the lapic timer being stopped. 110 * 111 * This requires changing the value for config register at offset 0x6c 112 * for the Host-PCI bridge at bus/dev/function 0/0/0: 113 * 114 * Chip Current Value New Value 115 * ---- ---------- ---------- 116 * C17 0x1F0FFF01 0x1F01FF01 117 * C18D 0x9F0FFF01 0x9F01FF01 118 * 119 * We do this by always clearing the bits in 0x000e0000. 120 * 121 * See also: http://lkml.org/lkml/2004/5/3/157 122 */ 123 static void 124 fixc1_nforce2(device_t dev) 125 { 126 uint32_t val; 127 128 if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 && 129 pci_get_function(dev) == 0) { 130 val = pci_read_config(dev, 0x6c, 4); 131 if (val & 0x000e0000) { 132 device_printf(dev, 133 "correcting nForce2 C1 CPU disconnect hangs\n"); 134 val &= ~0x000e0000; 135 pci_write_config(dev, 0x6c, val, 4); 136 } 137 } 138 } 139