xref: /freebsd/sys/dev/pci/controller/pci_n1sdp.c (revision 22cf89c938886d14f5796fc49f9f020c23ea8eaf)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2019 Andrew Turner
5  * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
6  *
7  * This software was developed by SRI International and the University of
8  * Cambridge Computer Laboratory (Department of Computer Science and
9  * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
10  * DARPA SSITH research programme.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  */
33 
34 #include <sys/cdefs.h>
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/bus.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/rman.h>
43 
44 #include <vm/vm.h>
45 #include <vm/vm_extern.h>
46 #include <vm/vm_page.h>
47 #include <vm/vm_phys.h>
48 
49 #include <contrib/dev/acpica/include/acpi.h>
50 #include <contrib/dev/acpica/include/accommon.h>
51 
52 #include <dev/acpica/acpivar.h>
53 #include <dev/acpica/acpi_pcibvar.h>
54 
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcib_private.h>
58 #include <dev/pci/pci_host_generic.h>
59 #include <dev/pci/pci_host_generic_acpi.h>
60 
61 #include "pcib_if.h"
62 
63 #define	AP_NS_SHARED_MEM_BASE	0x06000000
64 #define	N1SDP_MAX_SEGMENTS	2 /* Two PCIe root complex devices. */
65 #define	BDF_TABLE_SIZE		(16 * 1024)
66 #define	PCI_CFG_SPACE_SIZE	0x1000
67 
68 _Static_assert(BDF_TABLE_SIZE >= PAGE_SIZE,
69     "pci_n1sdp.c assumes a 4k or 16k page size when mapping the shared data");
70 
71 struct pcie_discovery_data {
72 	uint32_t rc_base_addr;
73 	uint32_t nr_bdfs;
74 	uint32_t valid_bdfs[0];
75 };
76 
77 struct generic_pcie_n1sdp_softc {
78 	struct generic_pcie_acpi_softc acpi;
79 	struct pcie_discovery_data *n1_discovery_data;
80 	bus_space_handle_t n1_bsh;
81 };
82 
83 static int
84 n1sdp_init(struct generic_pcie_n1sdp_softc *sc)
85 {
86 	struct pcie_discovery_data *shared_data;
87 	vm_offset_t vaddr;
88 	vm_paddr_t paddr_rc;
89 	vm_paddr_t paddr;
90 	vm_page_t m[BDF_TABLE_SIZE / PAGE_SIZE];
91 	int table_count;
92 	int bdfs_size;
93 	int error, i;
94 
95 	paddr = AP_NS_SHARED_MEM_BASE + sc->acpi.segment * BDF_TABLE_SIZE;
96 	vm_phys_fictitious_reg_range(paddr, paddr + BDF_TABLE_SIZE,
97 	    VM_MEMATTR_UNCACHEABLE);
98 
99 	for (i = 0; i < nitems(m); i++) {
100 		m[i] = PHYS_TO_VM_PAGE(paddr + i * PAGE_SIZE);
101 		MPASS(m[i] != NULL);
102 	}
103 
104 	vaddr = kva_alloc((vm_size_t)BDF_TABLE_SIZE);
105 	if (vaddr == 0) {
106 		printf("%s: Can't allocate KVA memory.", __func__);
107 		error = ENXIO;
108 		goto out;
109 	}
110 	pmap_qenter(vaddr, m, nitems(m));
111 
112 	shared_data = (struct pcie_discovery_data *)vaddr;
113 	paddr_rc = (vm_offset_t)shared_data->rc_base_addr;
114 	error = bus_space_map(sc->acpi.base.res->r_bustag, paddr_rc,
115 	    PCI_CFG_SPACE_SIZE, 0, &sc->n1_bsh);
116 	if (error != 0)
117 		goto out_pmap;
118 
119 	bdfs_size = sizeof(struct pcie_discovery_data) +
120 	    sizeof(uint32_t) * shared_data->nr_bdfs;
121 	sc->n1_discovery_data = malloc(bdfs_size, M_DEVBUF,
122 	    M_WAITOK | M_ZERO);
123 	memcpy(sc->n1_discovery_data, shared_data, bdfs_size);
124 
125 	if (bootverbose) {
126 		table_count = sc->n1_discovery_data->nr_bdfs;
127 		for (i = 0; i < table_count; i++)
128 			printf("valid bdf %x\n",
129 			    sc->n1_discovery_data->valid_bdfs[i]);
130 	}
131 
132 out_pmap:
133 	pmap_qremove(vaddr, nitems(m));
134 	kva_free(vaddr, (vm_size_t)BDF_TABLE_SIZE);
135 
136 out:
137 	vm_phys_fictitious_unreg_range(paddr, paddr + BDF_TABLE_SIZE);
138 	return (error);
139 }
140 
141 static int
142 n1sdp_check_bdf(struct generic_pcie_n1sdp_softc *sc,
143     u_int bus, u_int slot, u_int func)
144 {
145 	int table_count;
146 	int bdf;
147 	int i;
148 
149 	bdf = PCIE_ADDR_OFFSET(bus, slot, func, 0);
150 	if (bdf == 0)
151 		return (1);
152 
153 	table_count = sc->n1_discovery_data->nr_bdfs;
154 
155 	for (i = 0; i < table_count; i++)
156 		if (bdf == sc->n1_discovery_data->valid_bdfs[i])
157 			return (1);
158 
159 	return (0);
160 }
161 
162 static int
163 n1sdp_pcie_acpi_probe(device_t dev)
164 {
165 	ACPI_DEVICE_INFO *devinfo;
166 	ACPI_TABLE_HEADER *hdr;
167 	ACPI_STATUS status;
168 	ACPI_HANDLE h;
169 	int root;
170 
171 	if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
172 	    ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
173 		return (ENXIO);
174 
175 	root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
176 	AcpiOsFree(devinfo);
177 	if (!root)
178 		return (ENXIO);
179 
180 	/* TODO: Move this to an ACPI quirk? */
181 	status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
182 	if (ACPI_FAILURE(status))
183 		return (ENXIO);
184 
185 	if (memcmp(hdr->OemId, "ARMLTD", ACPI_OEM_ID_SIZE) != 0 ||
186 	    memcmp(hdr->OemTableId, "ARMN1SDP", ACPI_OEM_TABLE_ID_SIZE) != 0 ||
187 	    hdr->OemRevision != 0x20181101)
188 		return (ENXIO);
189 
190 	device_set_desc(dev, "ARM N1SDP PCI host controller");
191 	return (BUS_PROBE_DEFAULT);
192 }
193 
194 static int
195 n1sdp_pcie_acpi_attach(device_t dev)
196 {
197 	struct generic_pcie_n1sdp_softc *sc;
198 	ACPI_HANDLE handle;
199 	ACPI_STATUS status;
200 	int err;
201 
202 	err = pci_host_generic_acpi_init(dev);
203 	if (err != 0)
204 		return (err);
205 
206 	sc = device_get_softc(dev);
207 	handle = acpi_get_handle(dev);
208 
209 	/* Get PCI Segment (domain) needed for IOMMU space remap. */
210 	status = acpi_GetInteger(handle, "_SEG", &sc->acpi.segment);
211 	if (ACPI_FAILURE(status)) {
212 		device_printf(dev, "No _SEG for PCI Bus\n");
213 		return (ENXIO);
214 	}
215 
216 	if (sc->acpi.segment >= N1SDP_MAX_SEGMENTS) {
217 		device_printf(dev, "Unknown PCI Bus segment (domain) %d\n",
218 		    sc->acpi.segment);
219 		return (ENXIO);
220 	}
221 
222 	err = n1sdp_init(sc);
223 	if (err)
224 		return (err);
225 
226 	device_add_child(dev, "pci", -1);
227 	return (bus_generic_attach(dev));
228 }
229 
230 static int
231 n1sdp_get_bus_space(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
232     bus_space_tag_t *bst, bus_space_handle_t *bsh, bus_size_t *offset)
233 {
234 	struct generic_pcie_n1sdp_softc *sc;
235 
236 	sc = device_get_softc(dev);
237 
238 	if (n1sdp_check_bdf(sc, bus, slot, func) == 0)
239 		return (EINVAL);
240 
241 	if (bus == sc->acpi.base.bus_start) {
242 		if (slot != 0 || func != 0)
243 			return (EINVAL);
244 		*bsh = sc->n1_bsh;
245 	} else {
246 		*bsh = rman_get_bushandle(sc->acpi.base.res);
247 	}
248 
249 	*bst = rman_get_bustag(sc->acpi.base.res);
250 	*offset = PCIE_ADDR_OFFSET(bus - sc->acpi.base.bus_start, slot, func,
251 	    reg);
252 
253 	return (0);
254 }
255 
256 static uint32_t
257 n1sdp_pcie_read_config(device_t dev, u_int bus, u_int slot,
258     u_int func, u_int reg, int bytes)
259 {
260 	struct generic_pcie_n1sdp_softc *sc_n1sdp;
261 	struct generic_pcie_acpi_softc *sc_acpi;
262 	struct generic_pcie_core_softc *sc;
263 	bus_space_handle_t h;
264 	bus_space_tag_t t;
265 	bus_size_t offset;
266 	uint32_t data;
267 
268 	sc_n1sdp = device_get_softc(dev);
269 	sc_acpi = &sc_n1sdp->acpi;
270 	sc = &sc_acpi->base;
271 
272 	if ((bus < sc->bus_start) || (bus > sc->bus_end))
273 		return (~0U);
274 	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
275 	    (reg > PCIE_REGMAX))
276 		return (~0U);
277 
278 	if (n1sdp_get_bus_space(dev, bus, slot, func, reg, &t, &h, &offset) !=0)
279 		return (~0U);
280 
281 	data = bus_space_read_4(t, h, offset & ~3);
282 
283 	switch (bytes) {
284 	case 1:
285 		data >>= (offset & 3) * 8;
286 		data &= 0xff;
287 		break;
288 	case 2:
289 		data >>= (offset & 3) * 8;
290 		data = le16toh(data);
291 		break;
292 	case 4:
293 		data = le32toh(data);
294 		break;
295 	default:
296 		return (~0U);
297 	}
298 
299 	return (data);
300 }
301 
302 static void
303 n1sdp_pcie_write_config(device_t dev, u_int bus, u_int slot,
304     u_int func, u_int reg, uint32_t val, int bytes)
305 {
306 	struct generic_pcie_n1sdp_softc *sc_n1sdp;
307 	struct generic_pcie_acpi_softc *sc_acpi;
308 	struct generic_pcie_core_softc *sc;
309 	bus_space_handle_t h;
310 	bus_space_tag_t t;
311 	bus_size_t offset;
312 	uint32_t data;
313 
314 	sc_n1sdp = device_get_softc(dev);
315 	sc_acpi = &sc_n1sdp->acpi;
316 	sc = &sc_acpi->base;
317 
318 	if ((bus < sc->bus_start) || (bus > sc->bus_end))
319 		return;
320 	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
321 	    (reg > PCIE_REGMAX))
322 		return;
323 
324 	if (n1sdp_get_bus_space(dev, bus, slot, func, reg, &t, &h, &offset) !=0)
325 		return;
326 
327 	data = bus_space_read_4(t, h, offset & ~3);
328 
329 	switch (bytes) {
330 	case 1:
331 		data &= ~(0xff << ((offset & 3) * 8));
332 		data |= (val & 0xff) << ((offset & 3) * 8);
333 		break;
334 	case 2:
335 		data &= ~(0xffff << ((offset & 3) * 8));
336 		data |= (val & 0xffff) << ((offset & 3) * 8);
337 		break;
338 	case 4:
339 		data = val;
340 		break;
341 	default:
342 		return;
343 	}
344 
345 	bus_space_write_4(t, h, offset & ~3, data);
346 }
347 
348 static device_method_t n1sdp_pcie_acpi_methods[] = {
349 	DEVMETHOD(device_probe,		n1sdp_pcie_acpi_probe),
350 	DEVMETHOD(device_attach,	n1sdp_pcie_acpi_attach),
351 
352 	/* pcib interface */
353 	DEVMETHOD(pcib_read_config,	n1sdp_pcie_read_config),
354 	DEVMETHOD(pcib_write_config,	n1sdp_pcie_write_config),
355 
356 	DEVMETHOD_END
357 };
358 
359 DEFINE_CLASS_1(pcib, n1sdp_pcie_acpi_driver, n1sdp_pcie_acpi_methods,
360     sizeof(struct generic_pcie_n1sdp_softc), generic_pcie_acpi_driver);
361 
362 DRIVER_MODULE(n1sdp_pcib, acpi, n1sdp_pcie_acpi_driver, 0, 0);
363