1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 Nicolas Souchu, Marc Bouget 5 * Copyright (c) 2004 Joerg Wunsch 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef __PCFVAR_H__ 31 #define __PCFVAR_H__ 32 33 #define IO_PCFSIZE 2 34 35 #define TIMEOUT 9999 /* XXX */ 36 37 /* Status bits of S1 register (read only) */ 38 #define nBB 0x01 /* busy when low set/reset by STOP/START*/ 39 #define LAB 0x02 /* lost arbitration bit in multi-master mode */ 40 #define AAS 0x04 /* addressed as slave */ 41 #define LRB 0x08 /* last received byte when not AAS */ 42 #define AD0 0x08 /* general call received when AAS */ 43 #define BER 0x10 /* bus error, misplaced START or STOP */ 44 #define STS 0x20 /* STOP detected in slave receiver mode */ 45 #define PIN 0x80 /* pending interrupt not (r/w) */ 46 47 /* Control bits of S1 register (write only) */ 48 #define ACK 0x01 49 #define STO 0x02 50 #define STA 0x04 51 #define ENI 0x08 52 #define ES2 0x10 53 #define ES1 0x20 54 #define ESO 0x40 55 56 #define BUFSIZE 2048 57 58 #define SLAVE_TRANSMITTER 0x1 59 #define SLAVE_RECEIVER 0x2 60 61 #define PCF_DEFAULT_ADDR 0xaa 62 63 struct pcf_softc { 64 u_char pcf_addr; /* interface I2C address */ 65 int pcf_flags; /* IIC_POLLED? */ 66 int pcf_slave_mode; /* receiver or transmitter */ 67 int pcf_started; /* 1 if start condition sent */ 68 69 struct mtx pcf_lock; 70 device_t iicbus; /* the corresponding iicbus */ 71 72 /* Resource handling stuff. */ 73 struct resource *res_ioport; 74 int rid_ioport; 75 struct resource *res_irq; 76 int rid_irq; 77 void *intr_cookie; 78 }; 79 #define DEVTOSOFTC(dev) ((struct pcf_softc *)device_get_softc(dev)) 80 81 #define PCF_LOCK(sc) mtx_lock(&(sc)->pcf_lock) 82 #define PCF_UNLOCK(sc) mtx_unlock(&(sc)->pcf_lock) 83 #define PCF_ASSERT_LOCKED(sc) mtx_assert(&(sc)->pcf_lock, MA_OWNED) 84 85 /* 86 * PCF8584 datasheet : when operate at 8 MHz or more, a minimun time of 87 * 6 clocks cycles must be left between two consecutives access 88 */ 89 #define pcf_nops() DELAY(10) 90 91 #define dummy_read(sc) pcf_get_S0(sc) 92 #define dummy_write(sc) pcf_set_S0(sc, 0) 93 94 /* 95 * Specific register access to PCF8584 96 */ 97 static __inline void 98 pcf_set_S0(struct pcf_softc *sc, int data) 99 { 100 101 bus_write_1(sc->res_ioport, 0, data); 102 pcf_nops(); 103 } 104 105 static __inline void 106 pcf_set_S1(struct pcf_softc *sc, int data) 107 { 108 109 bus_write_1(sc->res_ioport, 1, data); 110 pcf_nops(); 111 } 112 113 static __inline char 114 pcf_get_S0(struct pcf_softc *sc) 115 { 116 char data; 117 118 data = bus_read_1(sc->res_ioport, 0); 119 pcf_nops(); 120 121 return (data); 122 } 123 124 static __inline char 125 pcf_get_S1(struct pcf_softc *sc) 126 { 127 char data; 128 129 data = bus_read_1(sc->res_ioport, 1); 130 pcf_nops(); 131 132 return (data); 133 } 134 135 extern int pcf_repeated_start(device_t, u_char, int); 136 extern int pcf_start(device_t, u_char, int); 137 extern int pcf_stop(device_t); 138 extern int pcf_write(device_t, const char *, int, int *, int); 139 extern int pcf_read(device_t, char *, int, int *, int, int); 140 extern int pcf_rst_card(device_t, u_char, u_char, u_char *); 141 extern driver_intr_t pcf_intr; 142 143 #define PCF_MODVER 1 144 #define PCF_MINVER 1 145 #define PCF_MAXVER 1 146 #define PCF_PREFVER PCF_MODVER 147 148 #endif /* !__PCFVAR_H__ */ 149