1 /* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Copyright (c) 1998, 1999 and 2000 33 * HAYAKAWA Koichi. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by HAYAKAWA Koichi. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Register definitions for PCI to Cardbus Bridge chips 63 */ 64 65 66 /* PCI header registers */ 67 #define CBBR_SOCKBASE 0x10 /* len=4 */ 68 69 #define CBBR_MEMBASE0 0x1c /* len=4 */ 70 #define CBBR_MEMLIMIT0 0x20 /* len=4 */ 71 #define CBBR_MEMBASE1 0x24 /* len=4 */ 72 #define CBBR_MEMLIMIT1 0x28 /* len=4 */ 73 #define CBBR_IOBASE0 0x2c /* len=4 */ 74 #define CBBR_IOLIMIT0 0x30 /* len=4 */ 75 #define CBBR_IOBASE1 0x34 /* len=4 */ 76 #define CBBR_IOLIMIT1 0x38 /* len=4 */ 77 #define CBB_MEMALIGN 4096 78 #define CBB_IOALIGN 4 79 80 #define CBBR_INTRLINE 0x3c /* len=1 */ 81 #define CBBR_INTRPIN 0x3d /* len=1 */ 82 #define CBBR_BRIDGECTRL 0x3e /* len=2 */ 83 # define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 84 # define CBBM_BRIDGECTRL_RESET 0x0040 85 # define CBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080 86 # define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 87 # define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 88 # define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 89 /* additional bit for RF5C46[567] */ 90 # define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 91 # define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 92 93 #define CBBR_LEGACY 0x44 /* len=4 */ 94 95 #define CBBR_CBCTRL 0x91 /* len=1 */ 96 /* bits for TI 113X */ 97 # define CBBM_CBCTRL_113X_RI_EN 0x80 98 # define CBBM_CBCTRL_113X_ZV_EN 0x40 99 # define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 100 # define CBBM_CBCTRL_113X_PCI_INTR 0x10 101 # define CBBM_CBCTRL_113X_PCI_CSC 0x08 102 # define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 103 # define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 104 # define CBBM_CBCTRL_113X_INTR_DET 0x01 105 /* bits for TI 12XX */ 106 # define CBBM_CBCTRL_12XX_RI_EN 0x80 107 # define CBBM_CBCTRL_12XX_ZV_EN 0x40 108 # define CBBM_CBCTRL_12XX_AUD2MUX 0x04 109 # define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 110 # define CBBM_CBCTRL_12XX_INTR_DET 0x01 111 #define CBBR_DEVCTRL 0x92 /* len=1 */ 112 # define CBBM_DEVCTRL_INT_SERIAL 0x04 113 # define CBBM_DEVCTRL_INT_PCI 0x02 114 115 /* ToPIC 95 ONLY */ 116 #define CBBR_TOPIC_SOCKETCTRL 0x90 117 # define CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 118 /* ToPIC 97, 100 */ 119 #define CBBR_TOPIC_ZV_CONTROL 0x9c /* 1 byte */ 120 # define CBBM_TOPIC_ZVC_ENABLE 0x1 121 122 /* TOPIC 95+ */ 123 #define CBBR_TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 124 # define CBBM_TOPIC_SLOTCTRL_SLOTON 0x80 125 # define CBBM_TOPIC_SLOTCTRL_SLOTEN 0x40 126 # define CBBM_TOPIC_SLOTCTRL_ID_LOCK 0x20 127 # define CBBM_TOPIC_SLOTCTRL_ID_WP 0x10 128 # define CBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0c 129 # define CBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2 130 # define CBBM_TOPIC_SLOTCTRL_OSF_MASK 0x03 131 # define CBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0 132 133 /* TOPIC 95+ */ 134 #define CBBR_TOPIC_INTCTRL 0xa1 /* 1 byte */ 135 # define CBBM_TOPIC_INTCTRL_INTB 0x20 136 # define CBBM_TOPIC_INTCTRL_INTA 0x10 137 # define CBBM_TOPIC_INTCTRL_INT_MASK 0x30 138 /* The following bits may be for ToPIC 95 only */ 139 # define CBBM_TOPIC_INTCTRL_CLOCK_MASK 0x0c 140 # define CBBM_TOPIC_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 141 # define CBBM_TOPIC_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 142 # define CBBM_TOPIC_INTCTRL_CLOCK_0 0x00 /* no clock */ 143 /* ToPIC97, 100 defines the following bits */ 144 # define CBBM_TOPIC_INTCTRL_STSIRQNP 0x04 145 # define CBBM_TOPIC_INTCTRL_IRQNP 0x02 146 # define CBBM_TOPIC_INTCTRL_INTIRQSEL 0x01 147 148 /* TOPIC 95+ */ 149 #define CBBR_TOPIC_CDC 0xa3 /* 1 byte */ 150 # define CBBM_TOPIC_CDC_CARDBUS 0x80 151 # define CBBM_TOPIC_CDC_VS1 0x04 152 # define CBBM_TOPIC_CDC_VS2 0x02 153 # define CBBM_TOPIC_CDC_SWDETECT 0x01 154 155 /* Socket definitions */ 156 #define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 157 #define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 158 #define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 159 #define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 160 #define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 161 162 #define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 163 #define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 164 #define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 165 166 #define CBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */ 167 #define CBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */ 168 #define CBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */ 169 #define CBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */ 170 #define CBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */ 171 #define CBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */ 172 #define CBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */ 173 #define CBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */ 174 #define CBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */ 175 #define CBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */ 176 #define CBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */ 177 #define CBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */ 178 #define CBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */ 179 #define CBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */ 180 #define CBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */ 181 #define CBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 182 #define CBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 183 #define CBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 184 #define CBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 185 186 #define CBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */ 187 188 #define CBB_SOCKET_CTRL_VPPMASK 0x07 189 #define CBB_SOCKET_CTRL_VPP_OFF 0x00 190 #define CBB_SOCKET_CTRL_VPP_12V 0x01 191 #define CBB_SOCKET_CTRL_VPP_5V 0x02 192 #define CBB_SOCKET_CTRL_VPP_3V 0x03 193 #define CBB_SOCKET_CTRL_VPP_XV 0x04 194 #define CBB_SOCKET_CTRL_VPP_YV 0x05 195 196 #define CBB_SOCKET_CTRL_VCCMASK 0x70 197 #define CBB_SOCKET_CTRL_VCC_OFF 0x00 198 #define CBB_SOCKET_CTRL_VCC_5V 0x20 199 #define CBB_SOCKET_CTRL_VCC_3V 0x30 200 #define CBB_SOCKET_CTRL_VCC_XV 0x40 201 #define CBB_SOCKET_CTRL_VCC_YV 0x50 202 203 #define CBB_SOCKET_CTRL_STOPCLK 0x80 204 205 #include <dev/pccbb/pccbbdevid.h> 206 207 #define CBB_SOCKET_EVENT 0x00 208 #define CBB_SOCKET_MASK 0x04 209 #define CBB_SOCKET_STATE 0x08 210 #define CBB_SOCKET_FORCE 0x0c 211 #define CBB_SOCKET_CONTROL 0x10 212 #define CBB_SOCKET_POWER 0x14 213