1 /* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Register definitions for PCI to Cardbus Bridge chips 33 */ 34 35 36 /* PCI header registers */ 37 #define PCCBBR_SOCKBASE 0x10 /* len=4 */ 38 39 #define PCCBBR_MEMBASE0 0x1c /* len=4 */ 40 #define PCCBBR_MEMLIMIT0 0x20 /* len=4 */ 41 #define PCCBBR_MEMBASE1 0x24 /* len=4 */ 42 #define PCCBBR_MEMLIMIT1 0x28 /* len=4 */ 43 #define PCCBBR_IOBASE0 0x2c /* len=4 */ 44 #define PCCBBR_IOLIMIT0 0x30 /* len=4 */ 45 #define PCCBBR_IOBASE1 0x34 /* len=4 */ 46 #define PCCBBR_IOLIMIT1 0x38 /* len=4 */ 47 #define PCCBB_MEMALIGN 4096 48 #define PCCBB_IOALIGN 4 49 50 #define PCCBBR_INTRLINE 0x3c /* len=1 */ 51 #define PCCBBR_INTRPIN 0x3d /* len=1 */ 52 #define PCCBBR_BRIDGECTRL 0x3e /* len=2 */ 53 # define PCCBBM_BRIDGECTRL_MASTER_ABORT 0x0020 54 # define PCCBBM_BRIDGECTRL_RESET 0x0040 55 # define PCCBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080 56 # define PCCBBM_BRIDGECTRL_PREFETCH_0 0x0100 57 # define PCCBBM_BRIDGECTRL_PREFETCH_1 0x0200 58 # define PCCBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 59 /* additional bit for RF5C46[567] */ 60 # define PCCBBM_BRIDGECTRL_RL_3E0_EN 0x0800 61 # define PCCBBM_BRIDGECTRL_RL_3E2_EN 0x1000 62 63 #define PCCBBR_LEGACY 0x44 /* len=4 */ 64 65 #define PCCBBR_CBCTRL 0x91 /* len=1 */ 66 /* bits for TI 113X */ 67 # define PCCBBM_CBCTRL_113X_RI_EN 0x80 68 # define PCCBBM_CBCTRL_113X_ZV_EN 0x40 69 # define PCCBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 70 # define PCCBBM_CBCTRL_113X_PCI_INTR 0x10 71 # define PCCBBM_CBCTRL_113X_PCI_CSC 0x08 72 # define PCCBBM_CBCTRL_113X_PCI_CSC_D 0x04 73 # define PCCBBM_CBCTRL_113X_SPEAKER_EN 0x02 74 # define PCCBBM_CBCTRL_113X_INTR_DET 0x01 75 /* bits for TI 12XX */ 76 # define PCCBBM_CBCTRL_12XX_RI_EN 0x80 77 # define PCCBBM_CBCTRL_12XX_ZV_EN 0x40 78 # define PCCBBM_CBCTRL_12XX_AUD2MUX 0x04 79 # define PCCBBM_CBCTRL_12XX_SPEAKER_EN 0x02 80 # define PCCBBM_CBCTRL_12XX_INTR_DET 0x01 81 #define PCCBBR_DEVCTRL 0x92 /* len=1 */ 82 # define PCCBBM_DEVCTRL_INT_SERIAL 0x04 83 # define PCCBBM_DEVCTRL_INT_PCI 0x02 84 85 #define PCCBBR_TOPIC_SOCKETCTRL 0x90 86 # define PCCBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 87 88 #define PCCBBR_TOPIC_SLOTCTRL 0xa0 89 # define PCCBBM_TOPIC_SLOTCTRL_SLOTON 0x00000080 90 # define PCCBBM_TOPIC_SLOTCTRL_SLOTEN 0x00000040 91 # define PCCBBM_TOPIC_SLOTCTRL_ID_LOCK 0x00000020 92 # define PCCBBM_TOPIC_SLOTCTRL_ID_WP 0x00000010 93 # define PCCBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0000000c 94 # define PCCBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2 95 # define PCCBBM_TOPIC_SLOTCTRL_OSF_MASK 0x00000003 96 # define PCCBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0 97 # define PCCBBM_TOPIC_SLOTCTRL_INTB 0x00002000 98 # define PCCBBM_TOPIC_SLOTCTRL_INTA 0x00001000 99 # define PCCBBM_TOPIC_SLOTCTRL_INT_MASK 0x00003000 100 # define PCCBBM_TOPIC_SLOTCTRL_CLOCK_MASK 0x00000c00 101 # define PCCBBM_TOPIC_SLOTCTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */ 102 # define PCCBBM_TOPIC_SLOTCTRL_CLOCK_1 0x00000400 /* PCI Clock */ 103 # define PCCBBM_TOPIC_SLOTCTRL_CLOCK_0 0x00000000 /* no clock */ 104 # define PCCBBM_TOPIC_SLOTCTRL_CARDBUS 0x80000000 105 # define PCCBBM_TOPIC_SLOTCTRL_VS1 0x04000000 106 # define PCCBBM_TOPIC_SLOTCTRL_VS2 0x02000000 107 # define PCCBBM_TOPIC_SLOTCTRL_SWDETECT 0x01000000 108 109 /* Socket definitions */ 110 #define PCCBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 111 #define PCCBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 112 #define PCCBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 113 #define PCCBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 114 #define PCCBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 115 116 #define PCCBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 117 #define PCCBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 118 #define PCCBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 119 120 #define PCCBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */ 121 #define PCCBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */ 122 #define PCCBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */ 123 #define PCCBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */ 124 #define PCCBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */ 125 #define PCCBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */ 126 #define PCCBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */ 127 #define PCCBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */ 128 #define PCCBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */ 129 #define PCCBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */ 130 #define PCCBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */ 131 #define PCCBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */ 132 #define PCCBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */ 133 #define PCCBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */ 134 #define PCCBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */ 135 #define PCCBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 136 #define PCCBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 137 #define PCCBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 138 #define PCCBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 139 140 #define PCCBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */ 141 142 #define PCCBB_SOCKET_CTRL_VPPMASK 0x07 143 #define PCCBB_SOCKET_CTRL_VPP_OFF 0x00 144 #define PCCBB_SOCKET_CTRL_VPP_12V 0x01 145 #define PCCBB_SOCKET_CTRL_VPP_5V 0x02 146 #define PCCBB_SOCKET_CTRL_VPP_3V 0x03 147 #define PCCBB_SOCKET_CTRL_VPP_XV 0x04 148 #define PCCBB_SOCKET_CTRL_VPP_YV 0x05 149 150 #define PCCBB_SOCKET_CTRL_VCCMASK 0x70 151 #define PCCBB_SOCKET_CTRL_VCC_OFF 0x00 152 #define PCCBB_SOCKET_CTRL_VCC_5V 0x20 153 #define PCCBB_SOCKET_CTRL_VCC_3V 0x30 154 #define PCCBB_SOCKET_CTRL_VCC_XV 0x40 155 #define PCCBB_SOCKET_CTRL_VCC_YV 0x50 156 157 #define PCCBB_SOCKET_CTRL_STOPCLK 0x80 158 159 #include <dev/pccbb/pccbbdevid.h> 160