1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * 62 * References: 63 * TI Datasheets: 64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 65 * 66 * Written by Jonathan Chen <jon@freebsd.org> 67 * The author would like to acknowledge: 68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 71 * * David Cross: Author of the initial ugly hack for a specific cardbus card 72 */ 73 74 #include <sys/cdefs.h> 75 __FBSDID("$FreeBSD$"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 #include <sys/module.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcib_private.h> 97 98 #include <dev/pccard/pccardreg.h> 99 #include <dev/pccard/pccardvar.h> 100 101 #include <dev/exca/excareg.h> 102 #include <dev/exca/excavar.h> 103 104 #include <dev/pccbb/pccbbreg.h> 105 #include <dev/pccbb/pccbbvar.h> 106 107 #include "power_if.h" 108 #include "card_if.h" 109 #include "pcib_if.h" 110 111 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 112 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 113 114 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 116 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 117 pci_write_config(DEV, REG, ( \ 118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 119 120 static void cbb_chipinit(struct cbb_softc *sc); 121 static int cbb_pci_filt(void *arg); 122 123 static struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 163 164 /* ENE */ 165 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 170 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 171 172 /* Ricoh chips */ 173 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 174 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 175 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 177 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 178 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 179 180 /* Toshiba products */ 181 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 182 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 183 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 184 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 185 186 /* Cirrus Logic */ 187 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 188 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 189 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 190 191 /* 02Micro */ 192 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 203 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 204 205 /* SMC */ 206 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 207 208 /* sentinel */ 209 {0 /* null id */, "unknown", CB_UNKNOWN}, 210 }; 211 212 /************************************************************************/ 213 /* Probe/Attach */ 214 /************************************************************************/ 215 216 static int 217 cbb_chipset(uint32_t pci_id, const char **namep) 218 { 219 struct yenta_chipinfo *ycp; 220 221 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 222 continue; 223 if (namep != NULL) 224 *namep = ycp->yc_name; 225 return (ycp->yc_chiptype); 226 } 227 228 static int 229 cbb_pci_probe(device_t brdev) 230 { 231 const char *name; 232 uint32_t progif; 233 uint32_t baseclass; 234 uint32_t subclass; 235 236 /* 237 * Do we know that we support the chipset? If so, then we 238 * accept the device. 239 */ 240 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 241 device_set_desc(brdev, name); 242 return (BUS_PROBE_DEFAULT); 243 } 244 245 /* 246 * We do support generic CardBus bridges. All that we've seen 247 * to date have progif 0 (the Yenta spec, and successors mandate 248 * this). 249 */ 250 baseclass = pci_get_class(brdev); 251 subclass = pci_get_subclass(brdev); 252 progif = pci_get_progif(brdev); 253 if (baseclass == PCIC_BRIDGE && 254 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 255 device_set_desc(brdev, "PCI-CardBus Bridge"); 256 return (BUS_PROBE_GENERIC); 257 } 258 return (ENXIO); 259 } 260 261 /* 262 * Print out the config space 263 */ 264 static void 265 cbb_print_config(device_t dev) 266 { 267 int i; 268 269 device_printf(dev, "PCI Configuration space:"); 270 for (i = 0; i < 256; i += 4) { 271 if (i % 16 == 0) 272 printf("\n 0x%02x: ", i); 273 printf("0x%08x ", pci_read_config(dev, i, 4)); 274 } 275 printf("\n"); 276 } 277 278 static int 279 cbb_pci_attach(device_t brdev) 280 { 281 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 282 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 283 uint32_t pribus; 284 #endif 285 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 286 struct sysctl_ctx_list *sctx; 287 struct sysctl_oid *soid; 288 int rid; 289 device_t parent; 290 291 parent = device_get_parent(brdev); 292 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 293 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 294 sc->dev = brdev; 295 sc->cbdev = NULL; 296 sc->exca[0].pccarddev = NULL; 297 sc->domain = pci_get_domain(brdev); 298 sc->pribus = pcib_get_bus(parent); 299 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 300 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 301 pcib_setup_secbus(brdev, &sc->bus, 1); 302 #else 303 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); 304 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 305 #endif 306 SLIST_INIT(&sc->rl); 307 308 rid = CBBR_SOCKBASE; 309 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 310 RF_ACTIVE); 311 if (!sc->base_res) { 312 device_printf(brdev, "Could not map register memory\n"); 313 mtx_destroy(&sc->mtx); 314 return (ENOMEM); 315 } else { 316 DEVPRINTF((brdev, "Found memory at %08lx\n", 317 rman_get_start(sc->base_res))); 318 } 319 320 sc->bst = rman_get_bustag(sc->base_res); 321 sc->bsh = rman_get_bushandle(sc->base_res); 322 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 323 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 324 sc->exca[0].chipset = EXCA_CARDBUS; 325 sc->chipinit = cbb_chipinit; 326 sc->chipinit(sc); 327 328 /*Sysctls*/ 329 sctx = device_get_sysctl_ctx(brdev); 330 soid = device_get_sysctl_tree(brdev); 331 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 332 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 333 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 334 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 335 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 336 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 337 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 338 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 339 #if 0 340 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 341 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 342 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 343 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memroy window open"); 344 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 345 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 346 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 347 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 348 #endif 349 350 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 351 /* 352 * This is a gross hack. We should be scanning the entire pci 353 * tree, assigning bus numbers in a way such that we (1) can 354 * reserve 1 extra bus just in case and (2) all sub busses 355 * are in an appropriate range. 356 */ 357 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); 358 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 359 if (sc->bus.sec == 0 || sc->pribus != pribus) { 360 if (curr_bus_number <= sc->pribus) 361 curr_bus_number = sc->pribus + 1; 362 if (pribus != sc->pribus) { 363 DEVPRINTF((brdev, "Setting primary bus to %d\n", 364 sc->pribus)); 365 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 366 } 367 sc->bus.sec = curr_bus_number++; 368 sc->bus.sub = curr_bus_number++; 369 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 370 sc->bus.sec, sc->bus.sub)); 371 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); 372 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); 373 } 374 #endif 375 376 /* attach children */ 377 sc->cbdev = device_add_child(brdev, "cardbus", -1); 378 if (sc->cbdev == NULL) 379 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 380 else if (device_probe_and_attach(sc->cbdev) != 0) 381 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 382 383 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 384 if (sc->exca[0].pccarddev == NULL) 385 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 386 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 387 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 388 389 /* Map and establish the interrupt. */ 390 rid = 0; 391 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 392 RF_SHAREABLE | RF_ACTIVE); 393 if (sc->irq_res == NULL) { 394 device_printf(brdev, "Unable to map IRQ...\n"); 395 goto err; 396 } 397 398 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 399 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 400 device_printf(brdev, "couldn't establish interrupt\n"); 401 goto err; 402 } 403 404 /* reset 16-bit pcmcia bus */ 405 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 406 407 /* turn off power */ 408 cbb_power(brdev, CARD_OFF); 409 410 /* CSC Interrupt: Card detect interrupt on */ 411 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 412 413 /* reset interrupt */ 414 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 415 416 if (bootverbose) 417 cbb_print_config(brdev); 418 419 /* Start the thread */ 420 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 421 "%s event thread", device_get_nameunit(brdev))) { 422 device_printf(brdev, "unable to create event thread.\n"); 423 panic("cbb_create_event_thread"); 424 } 425 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 426 return (0); 427 err: 428 if (sc->irq_res) 429 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 430 if (sc->base_res) { 431 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 432 sc->base_res); 433 } 434 mtx_destroy(&sc->mtx); 435 return (ENOMEM); 436 } 437 438 static void 439 cbb_chipinit(struct cbb_softc *sc) 440 { 441 uint32_t mux, sysctrl, reg; 442 443 /* Set CardBus latency timer */ 444 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) 445 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); 446 447 /* Set PCI latency timer */ 448 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 449 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 450 451 /* Enable DMA, memory access for this card and I/O acces for children */ 452 pci_enable_busmaster(sc->dev); 453 pci_enable_io(sc->dev, SYS_RES_IOPORT); 454 pci_enable_io(sc->dev, SYS_RES_MEMORY); 455 456 /* disable Legacy IO */ 457 switch (sc->chipset) { 458 case CB_RF5C46X: 459 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 460 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 461 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 462 break; 463 default: 464 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 465 break; 466 } 467 468 /* Use PCI interrupt for interrupt routing */ 469 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 470 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 471 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 472 | CBBM_BRIDGECTRL_WRITE_POST_EN, 473 2); 474 475 /* 476 * XXX this should be a function table, ala OLDCARD. This means 477 * that we could more easily support ISA interrupts for pccard 478 * cards if we had to. 479 */ 480 switch (sc->chipset) { 481 case CB_TI113X: 482 /* 483 * The TI 1031, TI 1130 and TI 1131 all require another bit 484 * be set to enable PCI routing of interrupts, and then 485 * a bit for each of the CSC and Function interrupts we 486 * want routed. 487 */ 488 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 489 | CBBM_CBCTRL_113X_PCI_INTR | 490 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 491 1); 492 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 493 & ~(CBBM_DEVCTRL_INT_SERIAL | 494 CBBM_DEVCTRL_INT_PCI), 1); 495 break; 496 case CB_TI12XX: 497 /* 498 * Some TI 12xx (and [14][45]xx) based pci cards 499 * sometimes have issues with the MFUNC register not 500 * being initialized due to a bad EEPROM on board. 501 * Laptops that this matters on have this register 502 * properly initialized. 503 * 504 * The TI125X parts have a different register. 505 * 506 * Note: Only the lower two nibbles matter. When set 507 * to 0, the MFUNC{0,1} pins are GPIO, which isn't 508 * going to work out too well because we specifically 509 * program these parts to parallel interrupt signalling 510 * elsewhere. We preserve the upper bits of this 511 * register since changing them have subtle side effects 512 * for different variants of the card and are 513 * extremely difficult to exaustively test. 514 * 515 * Also, the TI 1510/1520 changed the default for the MFUNC 516 * register from 0x0 to 0x1000 to enable IRQSER by default. 517 * We want to be careful to avoid overriding that, and the 518 * below test will do that. Should this check prove to be 519 * too permissive, we should just check against 0 and 0x1000 520 * and not touch it otherwise. 521 */ 522 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 523 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 524 if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { 525 mux = (mux & ~CBBM_MFUNC_PIN0) | 526 CBBM_MFUNC_PIN0_INTA; 527 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 528 mux = (mux & ~CBBM_MFUNC_PIN1) | 529 CBBM_MFUNC_PIN1_INTB; 530 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 531 } 532 /*FALLTHROUGH*/ 533 case CB_TI125X: 534 /* 535 * Disable zoom video. Some machines initialize this 536 * improperly and exerpience has shown that this helps 537 * prevent strange behavior. We don't support zoom 538 * video anyway, so no harm can come from this. 539 */ 540 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 541 break; 542 case CB_O2MICRO: 543 /* 544 * Issue #1: INT# generated at the same time as 545 * selected ISA IRQ. When IREQ# or STSCHG# is active, 546 * in addition to the ISA IRQ being generated, INT# 547 * will also be generated at the same time. 548 * 549 * Some of the older controllers have an issue in 550 * which the slot's PCI INT# will be asserted whenever 551 * IREQ# or STSCGH# is asserted even if ExCA registers 552 * 03h or 05h have an ISA IRQ selected. 553 * 554 * The fix for this issue, which will work for any 555 * controller (old or new), is to set ExCA registers 556 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 557 * These bits are undocumented. By setting this 558 * register (of each slot) to '1010xxxxb' a routing of 559 * IREQ# to INTC# and STSCHG# to INTC# is selected. 560 * Since INTC# isn't connected there will be no 561 * unexpected PCI INT when IREQ# or STSCHG# is active. 562 * However, INTA# (slot 0) or INTB# (slot 1) will 563 * still be correctly generated if NO ISA IRQ is 564 * selected (ExCA regs 03h or 05h are cleared). 565 */ 566 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 567 reg = (reg & 0x0f) | 568 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 569 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 570 break; 571 case CB_TOPIC97: 572 /* 573 * Disable Zoom Video, ToPIC 97, 100. 574 */ 575 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 576 /* 577 * ToPIC 97, 100 578 * At offset 0xa1: INTERRUPT CONTROL register 579 * 0x1: Turn on INT interrupts. 580 */ 581 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 582 | TOPIC97_INTCTRL_INTIRQSEL, 1); 583 /* 584 * ToPIC97, 100 585 * Need to assert support for low voltage cards 586 */ 587 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL, 588 EXCA_TOPIC97_CTRL_LV_MASK); 589 goto topic_common; 590 case CB_TOPIC95: 591 /* 592 * SOCKETCTRL appears to be TOPIC 95/B specific 593 */ 594 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 595 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 596 597 topic_common:; 598 /* 599 * At offset 0xa0: SLOT CONTROL 600 * 0x80 Enable CardBus Functionality 601 * 0x40 Enable CardBus and PC Card registers 602 * 0x20 Lock ID in exca regs 603 * 0x10 Write protect ID in config regs 604 * Clear the rest of the bits, which defaults the slot 605 * in legacy mode to 0x3e0 and offset 0. (legacy 606 * mode is determined elsewhere) 607 */ 608 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 609 TOPIC_SLOTCTRL_SLOTON | 610 TOPIC_SLOTCTRL_SLOTEN | 611 TOPIC_SLOTCTRL_ID_LOCK | 612 TOPIC_SLOTCTRL_ID_WP, 1); 613 614 /* 615 * At offset 0xa3 Card Detect Control Register 616 * 0x80 CARDBUS enbale 617 * 0x01 Cleared for hardware change detect 618 */ 619 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 620 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 621 break; 622 } 623 624 /* 625 * Need to tell ExCA registers to CSC interrupts route via PCI 626 * interrupts. There are two ways to do this. One is to set 627 * INTR_ENABLE and the other is to set CSC to 0. Since both 628 * methods are mutually compatible, we do both. 629 */ 630 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 631 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 632 633 cbb_disable_func_intr(sc); 634 635 /* close all memory and io windows */ 636 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 637 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 638 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 639 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 640 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 641 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 642 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 643 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 644 } 645 646 static int 647 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 648 { 649 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 650 651 return (rman_get_start(sc->irq_res)); 652 } 653 654 static int 655 cbb_pci_shutdown(device_t brdev) 656 { 657 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 658 659 /* 660 * We're about to pull the rug out from the card, so mark it as 661 * gone to prevent harm. 662 */ 663 sc->cardok = 0; 664 665 /* 666 * Place the cards in reset, turn off the interrupts and power 667 * down the socket. 668 */ 669 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 670 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 671 cbb_set(sc, CBB_SOCKET_MASK, 0); 672 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 673 cbb_power(brdev, CARD_OFF); 674 675 /* 676 * For paranoia, turn off all address decoding. Really not needed, 677 * it seems, but it can't hurt 678 */ 679 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 680 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 681 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 682 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 683 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 684 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 685 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 686 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 687 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 688 return (0); 689 } 690 691 static int 692 cbb_pci_filt(void *arg) 693 { 694 struct cbb_softc *sc = arg; 695 uint32_t sockevent; 696 uint8_t csc; 697 int retval = FILTER_STRAY; 698 699 /* 700 * Some chips also require us to read the old ExCA registe for card 701 * status change when we route CSC vis PCI. This isn't supposed to be 702 * required, but it clears the interrupt state on some chipsets. 703 * Maybe there's a setting that would obviate its need. Maybe we 704 * should test the status bits and deal with them, but so far we've 705 * not found any machines that don't also give us the socket status 706 * indication above. 707 * 708 * This call used to be unconditional. However, further research 709 * suggests that we hit this condition when the card READY interrupt 710 * fired. So now we only read it for 16-bit cards, and we only claim 711 * the interrupt if READY is set. If this still causes problems, then 712 * the next step would be to read this if we have a 16-bit card *OR* 713 * we have no card. We treat the READY signal as if it were the power 714 * completion signal. Some bridges may double signal things here, bit 715 * signalling twice should be OK since we only sleep on the powerintr 716 * in one place and a double wakeup would be benign there. 717 */ 718 if (sc->flags & CBB_16BIT_CARD) { 719 csc = exca_getb(&sc->exca[0], EXCA_CSC); 720 if (csc & EXCA_CSC_READY) { 721 atomic_add_int(&sc->powerintr, 1); 722 wakeup((void *)&sc->powerintr); 723 retval = FILTER_HANDLED; 724 } 725 } 726 727 /* 728 * Read the socket event. Sometimes, the theory goes, the PCI bus is 729 * so loaded that it cannot satisfy the read request, so we get 730 * garbage back from the following read. We have to filter out the 731 * garbage so that we don't spontaneously reset the card under high 732 * load. PCI isn't supposed to act like this. No doubt this is a bug 733 * in the PCI bridge chipset (or cbb brige) that's being used in 734 * certain amd64 laptops today. Work around the issue by assuming 735 * that any bits we don't know about being set means that we got 736 * garbage. 737 */ 738 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 739 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 740 /* 741 * If anything has happened to the socket, we assume that the 742 * card is no longer OK, and we shouldn't call its ISR. We 743 * set cardok as soon as we've attached the card. This helps 744 * in a noisy eject, which happens all too often when users 745 * are ejecting their PC Cards. 746 * 747 * We use this method in preference to checking to see if the 748 * card is still there because the check suffers from a race 749 * condition in the bouncing case. 750 */ 751 #define DELTA (CBB_SOCKET_MASK_CD) 752 if (sockevent & DELTA) { 753 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 754 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 755 sc->cardok = 0; 756 cbb_disable_func_intr(sc); 757 wakeup(&sc->intrhand); 758 } 759 #undef DELTA 760 761 /* 762 * Wakeup anybody waiting for a power interrupt. We have to 763 * use atomic_add_int for wakups on other cores. 764 */ 765 if (sockevent & CBB_SOCKET_EVENT_POWER) { 766 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 767 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 768 atomic_add_int(&sc->powerintr, 1); 769 wakeup((void *)&sc->powerintr); 770 } 771 772 /* 773 * Status change interrupts aren't presently used in the 774 * rest of the driver. For now, just ACK them. 775 */ 776 if (sockevent & CBB_SOCKET_EVENT_CSTS) 777 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 778 retval = FILTER_HANDLED; 779 } 780 return retval; 781 } 782 783 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 784 static struct resource * 785 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 786 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 787 { 788 struct cbb_softc *sc; 789 790 sc = device_get_softc(bus); 791 if (type == PCI_RES_BUS) 792 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 793 count, flags)); 794 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 795 flags)); 796 } 797 798 static int 799 cbb_pci_adjust_resource(device_t bus, device_t child, int type, 800 struct resource *r, rman_res_t start, rman_res_t end) 801 { 802 struct cbb_softc *sc; 803 804 sc = device_get_softc(bus); 805 if (type == PCI_RES_BUS) { 806 if (!rman_is_region_manager(r, &sc->bus.rman)) 807 return (EINVAL); 808 return (rman_adjust_resource(r, start, end)); 809 } 810 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 811 } 812 813 static int 814 cbb_pci_release_resource(device_t bus, device_t child, int type, int rid, 815 struct resource *r) 816 { 817 struct cbb_softc *sc; 818 int error; 819 820 sc = device_get_softc(bus); 821 if (type == PCI_RES_BUS) { 822 if (!rman_is_region_manager(r, &sc->bus.rman)) 823 return (EINVAL); 824 if (rman_get_flags(r) & RF_ACTIVE) { 825 error = bus_deactivate_resource(child, type, rid, r); 826 if (error) 827 return (error); 828 } 829 return (rman_release_resource(r)); 830 } 831 return (cbb_release_resource(bus, child, type, rid, r)); 832 } 833 #endif 834 835 /************************************************************************/ 836 /* PCI compat methods */ 837 /************************************************************************/ 838 839 static int 840 cbb_maxslots(device_t brdev) 841 { 842 return (0); 843 } 844 845 static uint32_t 846 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 847 { 848 /* 849 * Pass through to the next ppb up the chain (i.e. our grandparent). 850 */ 851 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 852 b, s, f, reg, width)); 853 } 854 855 static void 856 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 857 int width) 858 { 859 /* 860 * Pass through to the next ppb up the chain (i.e. our grandparent). 861 */ 862 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 863 b, s, f, reg, val, width); 864 } 865 866 static int 867 cbb_pci_suspend(device_t brdev) 868 { 869 int error = 0; 870 struct cbb_softc *sc = device_get_softc(brdev); 871 872 error = bus_generic_suspend(brdev); 873 if (error != 0) 874 return (error); 875 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 876 sc->cardok = 0; /* Card is bogus now */ 877 return (0); 878 } 879 880 static int 881 cbb_pci_resume(device_t brdev) 882 { 883 int error = 0; 884 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 885 uint32_t tmp; 886 887 /* 888 * In the APM and early ACPI era, BIOSes saved the PCI config 889 * registers. As chips became more complicated, that functionality moved 890 * into the ACPI code / tables. We must therefore, restore the settings 891 * we made here to make sure the device come back. Transitions to Dx 892 * from D0 and back to D0 cause the bridge to lose its config space, so 893 * all the bus mappings and such are preserved. 894 * 895 * The PCI layer handles standard PCI registers like the 896 * command register and BARs, but cbb-specific registers are 897 * handled here. 898 */ 899 sc->chipinit(sc); 900 901 /* reset interrupt -- Do we really need to do this? */ 902 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 903 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 904 905 /* CSC Interrupt: Card detect interrupt on */ 906 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 907 908 /* Signal the thread to wakeup. */ 909 wakeup(&sc->intrhand); 910 911 error = bus_generic_resume(brdev); 912 913 return (error); 914 } 915 916 static device_method_t cbb_methods[] = { 917 /* Device interface */ 918 DEVMETHOD(device_probe, cbb_pci_probe), 919 DEVMETHOD(device_attach, cbb_pci_attach), 920 DEVMETHOD(device_detach, cbb_detach), 921 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 922 DEVMETHOD(device_suspend, cbb_pci_suspend), 923 DEVMETHOD(device_resume, cbb_pci_resume), 924 925 /* bus methods */ 926 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 927 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 928 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 929 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 930 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 931 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 932 #else 933 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 934 DEVMETHOD(bus_release_resource, cbb_release_resource), 935 #endif 936 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 937 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 938 DEVMETHOD(bus_driver_added, cbb_driver_added), 939 DEVMETHOD(bus_child_detached, cbb_child_detached), 940 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 941 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 942 DEVMETHOD(bus_child_present, cbb_child_present), 943 944 /* 16-bit card interface */ 945 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 946 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 947 948 /* power interface */ 949 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 950 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 951 952 /* pcib compatibility interface */ 953 DEVMETHOD(pcib_maxslots, cbb_maxslots), 954 DEVMETHOD(pcib_read_config, cbb_read_config), 955 DEVMETHOD(pcib_write_config, cbb_write_config), 956 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 957 958 DEVMETHOD_END 959 }; 960 961 static driver_t cbb_driver = { 962 "cbb", 963 cbb_methods, 964 sizeof(struct cbb_softc) 965 }; 966 967 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 968 MODULE_DEPEND(cbb, exca, 1, 1, 1); 969