1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * 62 * References: 63 * TI Datasheets: 64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 65 * 66 * Written by Jonathan Chen <jon@freebsd.org> 67 * The author would like to acknowledge: 68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 71 * * David Cross: Author of the initial ugly hack for a specific cardbus card 72 */ 73 74 #include <sys/cdefs.h> 75 __FBSDID("$FreeBSD$"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 #include <sys/module.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <machine/clock.h> 97 98 #include <dev/pccard/pccardreg.h> 99 #include <dev/pccard/pccardvar.h> 100 101 #include <dev/exca/excareg.h> 102 #include <dev/exca/excavar.h> 103 104 #include <dev/pccbb/pccbbreg.h> 105 #include <dev/pccbb/pccbbvar.h> 106 107 #include "power_if.h" 108 #include "card_if.h" 109 #include "pcib_if.h" 110 111 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 112 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 113 114 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 116 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 117 pci_write_config(DEV, REG, ( \ 118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 119 120 static void cbb_chipinit(struct cbb_softc *sc); 121 122 static struct yenta_chipinfo { 123 uint32_t yc_id; 124 const char *yc_name; 125 int yc_chiptype; 126 } yc_chipsets[] = { 127 /* Texas Instruments chips */ 128 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 129 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 130 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 131 132 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 133 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 138 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 140 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 142 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 146 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 153 154 /* ENE */ 155 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 161 162 /* Ricoh chips */ 163 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 164 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 165 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 166 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 167 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 168 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 169 170 /* Toshiba products */ 171 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 172 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 173 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 174 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 175 176 /* Cirrus Logic */ 177 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 178 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 179 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 180 181 /* 02Micro */ 182 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 183 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 184 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 185 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 186 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 187 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 188 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 189 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 190 191 /* sentinel */ 192 {0 /* null id */, "unknown", CB_UNKNOWN}, 193 }; 194 195 /************************************************************************/ 196 /* Probe/Attach */ 197 /************************************************************************/ 198 199 static int 200 cbb_chipset(uint32_t pci_id, const char **namep) 201 { 202 struct yenta_chipinfo *ycp; 203 204 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 205 continue; 206 if (namep != NULL) 207 *namep = ycp->yc_name; 208 return (ycp->yc_chiptype); 209 } 210 211 static int 212 cbb_pci_probe(device_t brdev) 213 { 214 const char *name; 215 uint32_t progif; 216 uint32_t subclass; 217 218 /* 219 * Do we know that we support the chipset? If so, then we 220 * accept the device. 221 */ 222 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 223 device_set_desc(brdev, name); 224 return (BUS_PROBE_DEFAULT); 225 } 226 227 /* 228 * We do support generic CardBus bridges. All that we've seen 229 * to date have progif 0 (the Yenta spec, and successors mandate 230 * this). 231 */ 232 subclass = pci_get_subclass(brdev); 233 progif = pci_get_progif(brdev); 234 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 235 device_set_desc(brdev, "PCI-CardBus Bridge"); 236 return (BUS_PROBE_DEFAULT); 237 } 238 return (ENXIO); 239 } 240 241 #ifndef BURN_BRIDGES 242 /* 243 * Still need this because the pci code only does power for type 0 244 * header devices. 245 */ 246 static void 247 cbb_powerstate_d0(device_t dev) 248 { 249 u_int32_t membase, irq; 250 251 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 252 /* Save important PCI config data. */ 253 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 254 irq = pci_read_config(dev, PCIR_INTLINE, 4); 255 256 /* Reset the power state. */ 257 device_printf(dev, "chip is in D%d power mode " 258 "-- setting to D0\n", pci_get_powerstate(dev)); 259 260 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 261 262 /* Restore PCI config data. */ 263 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 264 pci_write_config(dev, PCIR_INTLINE, irq, 4); 265 } 266 } 267 #endif 268 269 /* 270 * Print out the config space 271 */ 272 static void 273 cbb_print_config(device_t dev) 274 { 275 int i; 276 277 device_printf(dev, "PCI Configuration space:"); 278 for (i = 0; i < 256; i += 4) { 279 if (i % 16 == 0) 280 printf("\n 0x%02x: ", i); 281 printf("0x%08x ", pci_read_config(dev, i, 4)); 282 } 283 printf("\n"); 284 } 285 286 static int 287 cbb_pci_attach(device_t brdev) 288 { 289 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 290 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 291 int rid, bus, pribus; 292 device_t parent; 293 294 parent = device_get_parent(brdev); 295 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 296 cv_init(&sc->cv, "cbb cv"); 297 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 298 sc->dev = brdev; 299 sc->cbdev = NULL; 300 sc->exca[0].pccarddev = NULL; 301 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 302 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 303 SLIST_INIT(&sc->rl); 304 STAILQ_INIT(&sc->intr_handlers); 305 #ifndef BURN_BRIDGES 306 cbb_powerstate_d0(brdev); 307 #endif 308 309 rid = CBBR_SOCKBASE; 310 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 311 RF_ACTIVE); 312 if (!sc->base_res) { 313 device_printf(brdev, "Could not map register memory\n"); 314 mtx_destroy(&sc->mtx); 315 cv_destroy(&sc->cv); 316 return (ENOMEM); 317 } else { 318 DEVPRINTF((brdev, "Found memory at %08lx\n", 319 rman_get_start(sc->base_res))); 320 } 321 322 sc->bst = rman_get_bustag(sc->base_res); 323 sc->bsh = rman_get_bushandle(sc->base_res); 324 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 325 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 326 sc->exca[0].chipset = EXCA_CARDBUS; 327 sc->chipinit = cbb_chipinit; 328 sc->chipinit(sc); 329 330 /* 331 * This is a gross hack. We should be scanning the entire pci 332 * tree, assigning bus numbers in a way such that we (1) can 333 * reserve 1 extra bus just in case and (2) all sub busses 334 * are in an appropriate range. 335 */ 336 bus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 337 pribus = pcib_get_bus(parent); 338 DEVPRINTF((brdev, "Secondary bus is %d\n", bus)); 339 if (bus == 0) { 340 if (curr_bus_number <= pribus) 341 curr_bus_number = pribus + 1; 342 if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) { 343 DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus)); 344 pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1); 345 } 346 bus = curr_bus_number; 347 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus, 348 bus + 1)); 349 sc->secbus = bus; 350 sc->subbus = bus + 1; 351 pci_write_config(brdev, PCIR_SECBUS_2, bus, 1); 352 pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1); 353 curr_bus_number += 2; 354 } 355 356 /* attach children */ 357 sc->cbdev = device_add_child(brdev, "cardbus", -1); 358 if (sc->cbdev == NULL) 359 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 360 else if (device_probe_and_attach(sc->cbdev) != 0) 361 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 362 363 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 364 if (sc->exca[0].pccarddev == NULL) 365 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 366 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 367 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 368 369 /* Map and establish the interrupt. */ 370 rid = 0; 371 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 372 RF_SHAREABLE | RF_ACTIVE); 373 if (sc->irq_res == NULL) { 374 printf("cbb: Unable to map IRQ...\n"); 375 goto err; 376 } 377 378 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 379 cbb_intr, sc, &sc->intrhand)) { 380 device_printf(brdev, "couldn't establish interrupt"); 381 goto err; 382 } 383 384 /* reset 16-bit pcmcia bus */ 385 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 386 387 /* turn off power */ 388 cbb_power(brdev, CARD_OFF); 389 390 /* CSC Interrupt: Card detect interrupt on */ 391 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 392 393 /* reset interrupt */ 394 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 395 396 if (bootverbose) 397 cbb_print_config(brdev); 398 399 /* Start the thread */ 400 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 401 "%s", device_get_nameunit(brdev))) { 402 device_printf(brdev, "unable to create event thread.\n"); 403 panic("cbb_create_event_thread"); 404 } 405 return (0); 406 err: 407 if (sc->irq_res) 408 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 409 if (sc->base_res) { 410 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 411 sc->base_res); 412 } 413 mtx_destroy(&sc->mtx); 414 cv_destroy(&sc->cv); 415 return (ENOMEM); 416 } 417 418 static void 419 cbb_chipinit(struct cbb_softc *sc) 420 { 421 uint32_t mux, sysctrl, reg; 422 423 /* Set CardBus latency timer */ 424 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 425 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 426 427 /* Set PCI latency timer */ 428 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 429 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 430 431 /* Enable memory access */ 432 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 433 | PCIM_CMD_MEMEN 434 | PCIM_CMD_PORTEN 435 | PCIM_CMD_BUSMASTEREN, 2); 436 437 /* disable Legacy IO */ 438 switch (sc->chipset) { 439 case CB_RF5C46X: 440 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 441 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 442 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 443 break; 444 default: 445 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 446 break; 447 } 448 449 /* Use PCI interrupt for interrupt routing */ 450 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 451 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 452 CBBM_BRIDGECTRL_INTR_IREQ_EN), 453 | CBBM_BRIDGECTRL_WRITE_POST_EN, 454 2); 455 456 /* 457 * XXX this should be a function table, ala OLDCARD. This means 458 * that we could more easily support ISA interrupts for pccard 459 * cards if we had to. 460 */ 461 switch (sc->chipset) { 462 case CB_TI113X: 463 /* 464 * The TI 1031, TI 1130 and TI 1131 all require another bit 465 * be set to enable PCI routing of interrupts, and then 466 * a bit for each of the CSC and Function interrupts we 467 * want routed. 468 */ 469 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 470 | CBBM_CBCTRL_113X_PCI_INTR | 471 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 472 1); 473 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 474 & ~(CBBM_DEVCTRL_INT_SERIAL | 475 CBBM_DEVCTRL_INT_PCI), 1); 476 break; 477 case CB_TI12XX: 478 /* 479 * Some TI 12xx (and [14][45]xx) based pci cards 480 * sometimes have issues with the MFUNC register not 481 * being initialized due to a bad EEPROM on board. 482 * Laptops that this matters on have this register 483 * properly initialized. 484 * 485 * The TI125X parts have a different register. 486 */ 487 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 488 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 489 if (mux == 0) { 490 mux = (mux & ~CBBM_MFUNC_PIN0) | 491 CBBM_MFUNC_PIN0_INTA; 492 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 493 mux = (mux & ~CBBM_MFUNC_PIN1) | 494 CBBM_MFUNC_PIN1_INTB; 495 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 496 } 497 /*FALLTHROUGH*/ 498 case CB_TI125X: 499 /* 500 * Disable zoom video. Some machines initialize this 501 * improperly and exerpience has shown that this helps 502 * prevent strange behavior. 503 */ 504 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 505 break; 506 case CB_O2MICRO: 507 /* 508 * Issue #1: INT# generated at the same time as 509 * selected ISA IRQ. When IREQ# or STSCHG# is active, 510 * in addition to the ISA IRQ being generated, INT# 511 * will also be generated at the same time. 512 * 513 * Some of the older controllers have an issue in 514 * which the slot's PCI INT# will be asserted whenever 515 * IREQ# or STSCGH# is asserted even if ExCA registers 516 * 03h or 05h have an ISA IRQ selected. 517 * 518 * The fix for this issue, which will work for any 519 * controller (old or new), is to set ExCA registers 520 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 521 * These bits are undocumented. By setting this 522 * register (of each slot) to '1010xxxxb' a routing of 523 * IREQ# to INTC# and STSCHG# to INTC# is selected. 524 * Since INTC# isn't connected there will be no 525 * unexpected PCI INT when IREQ# or STSCHG# is active. 526 * However, INTA# (slot 0) or INTB# (slot 1) will 527 * still be correctly generated if NO ISA IRQ is 528 * selected (ExCA regs 03h or 05h are cleared). 529 */ 530 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 531 reg = (reg & 0x0f) | 532 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 533 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 534 535 break; 536 case CB_TOPIC97: 537 /* 538 * Disable Zoom Video, ToPIC 97, 100. 539 */ 540 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 541 /* 542 * ToPIC 97, 100 543 * At offset 0xa1: INTERRUPT CONTROL register 544 * 0x1: Turn on INT interrupts. 545 */ 546 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 547 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 548 goto topic_common; 549 case CB_TOPIC95: 550 /* 551 * SOCKETCTRL appears to be TOPIC 95/B specific 552 */ 553 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 554 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 555 556 topic_common:; 557 /* 558 * At offset 0xa0: SLOT CONTROL 559 * 0x80 Enable CardBus Functionality 560 * 0x40 Enable CardBus and PC Card registers 561 * 0x20 Lock ID in exca regs 562 * 0x10 Write protect ID in config regs 563 * Clear the rest of the bits, which defaults the slot 564 * in legacy mode to 0x3e0 and offset 0. (legacy 565 * mode is determined elsewhere) 566 */ 567 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 568 CBBM_TOPIC_SLOTCTRL_SLOTON | 569 CBBM_TOPIC_SLOTCTRL_SLOTEN | 570 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 571 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 572 573 /* 574 * At offset 0xa3 Card Detect Control Register 575 * 0x80 CARDBUS enbale 576 * 0x01 Cleared for hardware change detect 577 */ 578 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 579 | CBBM_TOPIC_CDC_CARDBUS, 580 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 581 break; 582 } 583 584 /* 585 * Need to tell ExCA registers to CSC interrupts route via PCI 586 * interrupts. There are two ways to do this. Once is to set 587 * INTR_ENABLE and the other is to set CSC to 0. Since both 588 * methods are mutually compatible, we do both. 589 */ 590 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 591 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 592 593 cbb_disable_func_intr(sc); 594 595 /* close all memory and io windows */ 596 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 597 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 598 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 599 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 600 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 601 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 602 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 603 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 604 } 605 606 static int 607 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 608 { 609 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 610 611 return (rman_get_start(sc->irq_res)); 612 } 613 614 static device_method_t cbb_methods[] = { 615 /* Device interface */ 616 DEVMETHOD(device_probe, cbb_pci_probe), 617 DEVMETHOD(device_attach, cbb_pci_attach), 618 DEVMETHOD(device_detach, cbb_detach), 619 DEVMETHOD(device_shutdown, cbb_shutdown), 620 DEVMETHOD(device_suspend, cbb_suspend), 621 DEVMETHOD(device_resume, cbb_resume), 622 623 /* bus methods */ 624 DEVMETHOD(bus_print_child, bus_generic_print_child), 625 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 626 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 627 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 628 DEVMETHOD(bus_release_resource, cbb_release_resource), 629 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 630 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 631 DEVMETHOD(bus_driver_added, cbb_driver_added), 632 DEVMETHOD(bus_child_detached, cbb_child_detached), 633 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 634 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 635 DEVMETHOD(bus_child_present, cbb_child_present), 636 637 /* 16-bit card interface */ 638 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 639 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 640 641 /* power interface */ 642 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 643 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 644 645 /* pcib compatibility interface */ 646 DEVMETHOD(pcib_maxslots, cbb_maxslots), 647 DEVMETHOD(pcib_read_config, cbb_read_config), 648 DEVMETHOD(pcib_write_config, cbb_write_config), 649 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 650 651 {0,0} 652 }; 653 654 static driver_t cbb_driver = { 655 "cbb", 656 cbb_methods, 657 sizeof(struct cbb_softc) 658 }; 659 660 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 661 MODULE_DEPEND(cbb, exca, 1, 1, 1); 662