1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * 62 * References: 63 * TI Datasheets: 64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 65 * 66 * Written by Jonathan Chen <jon@freebsd.org> 67 * The author would like to acknowledge: 68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 71 * * David Cross: Author of the initial ugly hack for a specific cardbus card 72 */ 73 74 #include <sys/cdefs.h> 75 __FBSDID("$FreeBSD$"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 #include <sys/module.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 static void cbb_chipinit(struct cbb_softc *sc); 120 static int cbb_pci_filt(void *arg); 121 122 static struct yenta_chipinfo { 123 uint32_t yc_id; 124 const char *yc_name; 125 int yc_chiptype; 126 } yc_chipsets[] = { 127 /* Texas Instruments chips */ 128 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 129 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 130 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 131 132 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 133 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 138 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 140 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 142 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 146 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 163 /* ENE */ 164 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 170 171 /* Ricoh chips */ 172 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 173 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 174 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 175 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 177 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 178 179 /* Toshiba products */ 180 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 181 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 182 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 183 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 184 185 /* Cirrus Logic */ 186 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 187 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 188 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 189 190 /* 02Micro */ 191 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 203 204 /* SMC */ 205 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 206 207 /* sentinel */ 208 {0 /* null id */, "unknown", CB_UNKNOWN}, 209 }; 210 211 /************************************************************************/ 212 /* Probe/Attach */ 213 /************************************************************************/ 214 215 static int 216 cbb_chipset(uint32_t pci_id, const char **namep) 217 { 218 struct yenta_chipinfo *ycp; 219 220 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 221 continue; 222 if (namep != NULL) 223 *namep = ycp->yc_name; 224 return (ycp->yc_chiptype); 225 } 226 227 static int 228 cbb_pci_probe(device_t brdev) 229 { 230 const char *name; 231 uint32_t progif; 232 uint32_t baseclass; 233 uint32_t subclass; 234 235 /* 236 * Do we know that we support the chipset? If so, then we 237 * accept the device. 238 */ 239 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 240 device_set_desc(brdev, name); 241 return (BUS_PROBE_DEFAULT); 242 } 243 244 /* 245 * We do support generic CardBus bridges. All that we've seen 246 * to date have progif 0 (the Yenta spec, and successors mandate 247 * this). 248 */ 249 baseclass = pci_get_class(brdev); 250 subclass = pci_get_subclass(brdev); 251 progif = pci_get_progif(brdev); 252 if (baseclass == PCIC_BRIDGE && 253 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 254 device_set_desc(brdev, "PCI-CardBus Bridge"); 255 return (BUS_PROBE_GENERIC); 256 } 257 return (ENXIO); 258 } 259 260 /* 261 * Still need this because the pci code only does power for type 0 262 * header devices. 263 */ 264 static void 265 cbb_powerstate_d0(device_t dev) 266 { 267 u_int32_t membase, irq; 268 269 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 270 /* Save important PCI config data. */ 271 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 272 irq = pci_read_config(dev, PCIR_INTLINE, 4); 273 274 /* Reset the power state. */ 275 device_printf(dev, "chip is in D%d power mode " 276 "-- setting to D0\n", pci_get_powerstate(dev)); 277 278 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 279 280 /* Restore PCI config data. */ 281 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 282 pci_write_config(dev, PCIR_INTLINE, irq, 4); 283 } 284 } 285 286 /* 287 * Print out the config space 288 */ 289 static void 290 cbb_print_config(device_t dev) 291 { 292 int i; 293 294 device_printf(dev, "PCI Configuration space:"); 295 for (i = 0; i < 256; i += 4) { 296 if (i % 16 == 0) 297 printf("\n 0x%02x: ", i); 298 printf("0x%08x ", pci_read_config(dev, i, 4)); 299 } 300 printf("\n"); 301 } 302 303 static int 304 cbb_pci_attach(device_t brdev) 305 { 306 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 307 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 308 struct sysctl_ctx_list *sctx; 309 struct sysctl_oid *soid; 310 int rid; 311 device_t parent; 312 uint32_t pribus; 313 314 parent = device_get_parent(brdev); 315 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 316 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 317 sc->dev = brdev; 318 sc->cbdev = NULL; 319 sc->exca[0].pccarddev = NULL; 320 sc->domain = pci_get_domain(brdev); 321 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 322 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 323 sc->pribus = pcib_get_bus(parent); 324 SLIST_INIT(&sc->rl); 325 cbb_powerstate_d0(brdev); 326 327 rid = CBBR_SOCKBASE; 328 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 329 RF_ACTIVE); 330 if (!sc->base_res) { 331 device_printf(brdev, "Could not map register memory\n"); 332 mtx_destroy(&sc->mtx); 333 return (ENOMEM); 334 } else { 335 DEVPRINTF((brdev, "Found memory at %08lx\n", 336 rman_get_start(sc->base_res))); 337 } 338 339 sc->bst = rman_get_bustag(sc->base_res); 340 sc->bsh = rman_get_bushandle(sc->base_res); 341 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 342 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 343 sc->exca[0].chipset = EXCA_CARDBUS; 344 sc->chipinit = cbb_chipinit; 345 sc->chipinit(sc); 346 347 /*Sysctls*/ 348 sctx = device_get_sysctl_ctx(brdev); 349 soid = device_get_sysctl_tree(brdev); 350 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 351 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 352 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 353 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 354 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 355 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 356 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 357 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 358 #if 0 359 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 360 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 361 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 362 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memroy window open"); 363 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 364 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 365 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 366 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 367 #endif 368 369 /* 370 * This is a gross hack. We should be scanning the entire pci 371 * tree, assigning bus numbers in a way such that we (1) can 372 * reserve 1 extra bus just in case and (2) all sub busses 373 * are in an appropriate range. 374 */ 375 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->secbus)); 376 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 377 if (sc->secbus == 0 || sc->pribus != pribus) { 378 if (curr_bus_number <= sc->pribus) 379 curr_bus_number = sc->pribus + 1; 380 if (pribus != sc->pribus) { 381 DEVPRINTF((brdev, "Setting primary bus to %d\n", 382 sc->pribus)); 383 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 384 } 385 sc->secbus = curr_bus_number++; 386 sc->subbus = curr_bus_number++; 387 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 388 sc->secbus, sc->subbus)); 389 pci_write_config(brdev, PCIR_SECBUS_2, sc->secbus, 1); 390 pci_write_config(brdev, PCIR_SUBBUS_2, sc->subbus, 1); 391 } 392 393 /* attach children */ 394 sc->cbdev = device_add_child(brdev, "cardbus", -1); 395 if (sc->cbdev == NULL) 396 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 397 else if (device_probe_and_attach(sc->cbdev) != 0) 398 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 399 400 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 401 if (sc->exca[0].pccarddev == NULL) 402 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 403 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 404 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 405 406 /* Map and establish the interrupt. */ 407 rid = 0; 408 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 409 RF_SHAREABLE | RF_ACTIVE); 410 if (sc->irq_res == NULL) { 411 device_printf(brdev, "Unable to map IRQ...\n"); 412 goto err; 413 } 414 415 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 416 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 417 device_printf(brdev, "couldn't establish interrupt\n"); 418 goto err; 419 } 420 421 /* reset 16-bit pcmcia bus */ 422 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 423 424 /* turn off power */ 425 cbb_power(brdev, CARD_OFF); 426 427 /* CSC Interrupt: Card detect interrupt on */ 428 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 429 430 /* reset interrupt */ 431 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 432 433 if (bootverbose) 434 cbb_print_config(brdev); 435 436 /* Start the thread */ 437 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 438 "%s event thread", device_get_nameunit(brdev))) { 439 device_printf(brdev, "unable to create event thread.\n"); 440 panic("cbb_create_event_thread"); 441 } 442 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 443 return (0); 444 err: 445 if (sc->irq_res) 446 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 447 if (sc->base_res) { 448 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 449 sc->base_res); 450 } 451 mtx_destroy(&sc->mtx); 452 return (ENOMEM); 453 } 454 455 static void 456 cbb_chipinit(struct cbb_softc *sc) 457 { 458 uint32_t mux, sysctrl, reg; 459 460 /* Set CardBus latency timer */ 461 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 462 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 463 464 /* Set PCI latency timer */ 465 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 466 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 467 468 /* Restore bus configuration */ 469 pci_write_config(sc->dev, PCIR_PRIBUS_2, sc->pribus, 1); 470 pci_write_config(sc->dev, PCIR_SECBUS_2, sc->secbus, 1); 471 pci_write_config(sc->dev, PCIR_SUBBUS_2, sc->subbus, 1); 472 473 /* Enable memory access */ 474 pci_enable_busmaster(sc->dev); 475 476 /* disable Legacy IO */ 477 switch (sc->chipset) { 478 case CB_RF5C46X: 479 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 480 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 481 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 482 break; 483 default: 484 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 485 break; 486 } 487 488 /* Use PCI interrupt for interrupt routing */ 489 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 490 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 491 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 492 | CBBM_BRIDGECTRL_WRITE_POST_EN, 493 2); 494 495 /* 496 * XXX this should be a function table, ala OLDCARD. This means 497 * that we could more easily support ISA interrupts for pccard 498 * cards if we had to. 499 */ 500 switch (sc->chipset) { 501 case CB_TI113X: 502 /* 503 * The TI 1031, TI 1130 and TI 1131 all require another bit 504 * be set to enable PCI routing of interrupts, and then 505 * a bit for each of the CSC and Function interrupts we 506 * want routed. 507 */ 508 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 509 | CBBM_CBCTRL_113X_PCI_INTR | 510 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 511 1); 512 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 513 & ~(CBBM_DEVCTRL_INT_SERIAL | 514 CBBM_DEVCTRL_INT_PCI), 1); 515 break; 516 case CB_TI12XX: 517 /* 518 * Some TI 12xx (and [14][45]xx) based pci cards 519 * sometimes have issues with the MFUNC register not 520 * being initialized due to a bad EEPROM on board. 521 * Laptops that this matters on have this register 522 * properly initialized. 523 * 524 * The TI125X parts have a different register. 525 */ 526 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 527 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 528 if (mux == 0) { 529 mux = (mux & ~CBBM_MFUNC_PIN0) | 530 CBBM_MFUNC_PIN0_INTA; 531 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 532 mux = (mux & ~CBBM_MFUNC_PIN1) | 533 CBBM_MFUNC_PIN1_INTB; 534 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 535 } 536 /*FALLTHROUGH*/ 537 case CB_TI125X: 538 /* 539 * Disable zoom video. Some machines initialize this 540 * improperly and exerpience has shown that this helps 541 * prevent strange behavior. 542 */ 543 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 544 break; 545 case CB_O2MICRO: 546 /* 547 * Issue #1: INT# generated at the same time as 548 * selected ISA IRQ. When IREQ# or STSCHG# is active, 549 * in addition to the ISA IRQ being generated, INT# 550 * will also be generated at the same time. 551 * 552 * Some of the older controllers have an issue in 553 * which the slot's PCI INT# will be asserted whenever 554 * IREQ# or STSCGH# is asserted even if ExCA registers 555 * 03h or 05h have an ISA IRQ selected. 556 * 557 * The fix for this issue, which will work for any 558 * controller (old or new), is to set ExCA registers 559 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 560 * These bits are undocumented. By setting this 561 * register (of each slot) to '1010xxxxb' a routing of 562 * IREQ# to INTC# and STSCHG# to INTC# is selected. 563 * Since INTC# isn't connected there will be no 564 * unexpected PCI INT when IREQ# or STSCHG# is active. 565 * However, INTA# (slot 0) or INTB# (slot 1) will 566 * still be correctly generated if NO ISA IRQ is 567 * selected (ExCA regs 03h or 05h are cleared). 568 */ 569 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 570 reg = (reg & 0x0f) | 571 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 572 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 573 break; 574 case CB_TOPIC97: 575 /* 576 * Disable Zoom Video, ToPIC 97, 100. 577 */ 578 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 579 /* 580 * ToPIC 97, 100 581 * At offset 0xa1: INTERRUPT CONTROL register 582 * 0x1: Turn on INT interrupts. 583 */ 584 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 585 | TOPIC97_INTCTRL_INTIRQSEL, 1); 586 /* 587 * ToPIC97, 100 588 * Need to assert support for low voltage cards 589 */ 590 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL, 591 EXCA_TOPIC97_CTRL_LV_MASK); 592 goto topic_common; 593 case CB_TOPIC95: 594 /* 595 * SOCKETCTRL appears to be TOPIC 95/B specific 596 */ 597 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 598 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 599 600 topic_common:; 601 /* 602 * At offset 0xa0: SLOT CONTROL 603 * 0x80 Enable CardBus Functionality 604 * 0x40 Enable CardBus and PC Card registers 605 * 0x20 Lock ID in exca regs 606 * 0x10 Write protect ID in config regs 607 * Clear the rest of the bits, which defaults the slot 608 * in legacy mode to 0x3e0 and offset 0. (legacy 609 * mode is determined elsewhere) 610 */ 611 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 612 TOPIC_SLOTCTRL_SLOTON | 613 TOPIC_SLOTCTRL_SLOTEN | 614 TOPIC_SLOTCTRL_ID_LOCK | 615 TOPIC_SLOTCTRL_ID_WP, 1); 616 617 /* 618 * At offset 0xa3 Card Detect Control Register 619 * 0x80 CARDBUS enbale 620 * 0x01 Cleared for hardware change detect 621 */ 622 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 623 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 624 break; 625 } 626 627 /* 628 * Need to tell ExCA registers to CSC interrupts route via PCI 629 * interrupts. There are two ways to do this. One is to set 630 * INTR_ENABLE and the other is to set CSC to 0. Since both 631 * methods are mutually compatible, we do both. 632 */ 633 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 634 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 635 636 cbb_disable_func_intr(sc); 637 638 /* close all memory and io windows */ 639 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 640 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 641 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 642 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 643 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 644 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 645 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 646 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 647 } 648 649 static int 650 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 651 { 652 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 653 654 return (rman_get_start(sc->irq_res)); 655 } 656 657 static int 658 cbb_pci_shutdown(device_t brdev) 659 { 660 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 661 662 /* 663 * We're about to pull the rug out from the card, so mark it as 664 * gone to prevent harm. 665 */ 666 sc->cardok = 0; 667 668 /* 669 * Place the cards in reset, turn off the interrupts and power 670 * down the socket. 671 */ 672 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 673 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 674 cbb_set(sc, CBB_SOCKET_MASK, 0); 675 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 676 cbb_power(brdev, CARD_OFF); 677 678 /* 679 * For paranoia, turn off all address decoding. Really not needed, 680 * it seems, but it can't hurt 681 */ 682 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 683 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 684 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 685 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 686 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 687 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 688 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 689 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 690 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 691 return (0); 692 } 693 694 static int 695 cbb_pci_filt(void *arg) 696 { 697 struct cbb_softc *sc = arg; 698 uint32_t sockevent; 699 uint8_t csc; 700 int retval = FILTER_STRAY; 701 702 /* 703 * Some chips also require us to read the old ExCA registe for card 704 * status change when we route CSC vis PCI. This isn't supposed to be 705 * required, but it clears the interrupt state on some chipsets. 706 * Maybe there's a setting that would obviate its need. Maybe we 707 * should test the status bits and deal with them, but so far we've 708 * not found any machines that don't also give us the socket status 709 * indication above. 710 * 711 * This call used to be unconditional. However, further research 712 * suggests that we hit this condition when the card READY interrupt 713 * fired. So now we only read it for 16-bit cards, and we only claim 714 * the interrupt if READY is set. If this still causes problems, then 715 * the next step would be to read this if we have a 16-bit card *OR* 716 * we have no card. We treat the READY signal as if it were the power 717 * completion signal. Some bridges may double signal things here, bit 718 * signalling twice should be OK since we only sleep on the powerintr 719 * in one place and a double wakeup would be benign there. 720 */ 721 if (sc->flags & CBB_16BIT_CARD) { 722 csc = exca_getb(&sc->exca[0], EXCA_CSC); 723 if (csc & EXCA_CSC_READY) { 724 atomic_add_int(&sc->powerintr, 1); 725 wakeup((void *)&sc->powerintr); 726 retval = FILTER_HANDLED; 727 } 728 } 729 730 /* 731 * Read the socket event. Sometimes, the theory goes, the PCI bus is 732 * so loaded that it cannot satisfy the read request, so we get 733 * garbage back from the following read. We have to filter out the 734 * garbage so that we don't spontaneously reset the card under high 735 * load. PCI isn't supposed to act like this. No doubt this is a bug 736 * in the PCI bridge chipset (or cbb brige) that's being used in 737 * certain amd64 laptops today. Work around the issue by assuming 738 * that any bits we don't know about being set means that we got 739 * garbage. 740 */ 741 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 742 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 743 /* 744 * If anything has happened to the socket, we assume that the 745 * card is no longer OK, and we shouldn't call its ISR. We 746 * set cardok as soon as we've attached the card. This helps 747 * in a noisy eject, which happens all too often when users 748 * are ejecting their PC Cards. 749 * 750 * We use this method in preference to checking to see if the 751 * card is still there because the check suffers from a race 752 * condition in the bouncing case. 753 */ 754 #define DELTA (CBB_SOCKET_MASK_CD) 755 if (sockevent & DELTA) { 756 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 757 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 758 sc->cardok = 0; 759 cbb_disable_func_intr(sc); 760 wakeup(&sc->intrhand); 761 } 762 #undef DELTA 763 764 /* 765 * Wakeup anybody waiting for a power interrupt. We have to 766 * use atomic_add_int for wakups on other cores. 767 */ 768 if (sockevent & CBB_SOCKET_EVENT_POWER) { 769 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 770 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 771 atomic_add_int(&sc->powerintr, 1); 772 wakeup((void *)&sc->powerintr); 773 } 774 775 /* 776 * Status change interrupts aren't presently used in the 777 * rest of the driver. For now, just ACK them. 778 */ 779 if (sockevent & CBB_SOCKET_EVENT_CSTS) 780 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 781 retval = FILTER_HANDLED; 782 } 783 return retval; 784 } 785 786 /************************************************************************/ 787 /* PCI compat methods */ 788 /************************************************************************/ 789 790 static int 791 cbb_maxslots(device_t brdev) 792 { 793 return (0); 794 } 795 796 static uint32_t 797 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 798 { 799 /* 800 * Pass through to the next ppb up the chain (i.e. our grandparent). 801 */ 802 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 803 b, s, f, reg, width)); 804 } 805 806 static void 807 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 808 int width) 809 { 810 /* 811 * Pass through to the next ppb up the chain (i.e. our grandparent). 812 */ 813 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 814 b, s, f, reg, val, width); 815 } 816 817 static device_method_t cbb_methods[] = { 818 /* Device interface */ 819 DEVMETHOD(device_probe, cbb_pci_probe), 820 DEVMETHOD(device_attach, cbb_pci_attach), 821 DEVMETHOD(device_detach, cbb_detach), 822 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 823 DEVMETHOD(device_suspend, cbb_suspend), 824 DEVMETHOD(device_resume, cbb_resume), 825 826 /* bus methods */ 827 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 828 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 829 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 830 DEVMETHOD(bus_release_resource, cbb_release_resource), 831 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 832 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 833 DEVMETHOD(bus_driver_added, cbb_driver_added), 834 DEVMETHOD(bus_child_detached, cbb_child_detached), 835 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 836 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 837 DEVMETHOD(bus_child_present, cbb_child_present), 838 839 /* 16-bit card interface */ 840 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 841 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 842 843 /* power interface */ 844 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 845 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 846 847 /* pcib compatibility interface */ 848 DEVMETHOD(pcib_maxslots, cbb_maxslots), 849 DEVMETHOD(pcib_read_config, cbb_read_config), 850 DEVMETHOD(pcib_write_config, cbb_write_config), 851 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 852 853 DEVMETHOD_END 854 }; 855 856 static driver_t cbb_driver = { 857 "cbb", 858 cbb_methods, 859 sizeof(struct cbb_softc) 860 }; 861 862 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 863 MODULE_DEPEND(cbb, exca, 1, 1, 1); 864