1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000-2001 Jonathan Chen All rights reserved. 5 * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /*- 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 __FBSDID("$FreeBSD$"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/condvar.h> 82 #include <sys/errno.h> 83 #include <sys/kernel.h> 84 #include <sys/lock.h> 85 #include <sys/malloc.h> 86 #include <sys/mutex.h> 87 #include <sys/sysctl.h> 88 #include <sys/kthread.h> 89 #include <sys/bus.h> 90 #include <machine/bus.h> 91 #include <sys/rman.h> 92 #include <machine/resource.h> 93 #include <sys/module.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcib_private.h> 98 99 #include <dev/pccard/pccardreg.h> 100 #include <dev/pccard/pccardvar.h> 101 102 #include <dev/exca/excareg.h> 103 #include <dev/exca/excavar.h> 104 105 #include <dev/pccbb/pccbbreg.h> 106 #include <dev/pccbb/pccbbvar.h> 107 108 #include "power_if.h" 109 #include "card_if.h" 110 #include "pcib_if.h" 111 112 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 113 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 114 115 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 116 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 117 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 118 pci_write_config(DEV, REG, ( \ 119 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 120 121 static void cbb_chipinit(struct cbb_softc *sc); 122 static int cbb_pci_filt(void *arg); 123 124 static struct yenta_chipinfo { 125 uint32_t yc_id; 126 const char *yc_name; 127 int yc_chiptype; 128 } yc_chipsets[] = { 129 /* Texas Instruments chips */ 130 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 131 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 132 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 133 134 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 141 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 142 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 144 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 148 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 164 165 /* ENE */ 166 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 170 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 171 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 172 173 /* Ricoh chips */ 174 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 175 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 176 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 177 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 178 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 179 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 180 181 /* Toshiba products */ 182 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 183 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 184 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 185 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 186 187 /* Cirrus Logic */ 188 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 189 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 190 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 191 192 /* 02Micro */ 193 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 203 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 204 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 205 206 /* SMC */ 207 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 208 209 /* sentinel */ 210 {0 /* null id */, "unknown", CB_UNKNOWN}, 211 }; 212 213 /************************************************************************/ 214 /* Probe/Attach */ 215 /************************************************************************/ 216 217 static int 218 cbb_chipset(uint32_t pci_id, const char **namep) 219 { 220 struct yenta_chipinfo *ycp; 221 222 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 223 continue; 224 if (namep != NULL) 225 *namep = ycp->yc_name; 226 return (ycp->yc_chiptype); 227 } 228 229 static int 230 cbb_pci_probe(device_t brdev) 231 { 232 const char *name; 233 uint32_t progif; 234 uint32_t baseclass; 235 uint32_t subclass; 236 237 /* 238 * Do we know that we support the chipset? If so, then we 239 * accept the device. 240 */ 241 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 242 device_set_desc(brdev, name); 243 return (BUS_PROBE_DEFAULT); 244 } 245 246 /* 247 * We do support generic CardBus bridges. All that we've seen 248 * to date have progif 0 (the Yenta spec, and successors mandate 249 * this). 250 */ 251 baseclass = pci_get_class(brdev); 252 subclass = pci_get_subclass(brdev); 253 progif = pci_get_progif(brdev); 254 if (baseclass == PCIC_BRIDGE && 255 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 256 device_set_desc(brdev, "PCI-CardBus Bridge"); 257 return (BUS_PROBE_GENERIC); 258 } 259 return (ENXIO); 260 } 261 262 /* 263 * Print out the config space 264 */ 265 static void 266 cbb_print_config(device_t dev) 267 { 268 int i; 269 270 device_printf(dev, "PCI Configuration space:"); 271 for (i = 0; i < 256; i += 4) { 272 if (i % 16 == 0) 273 printf("\n 0x%02x: ", i); 274 printf("0x%08x ", pci_read_config(dev, i, 4)); 275 } 276 printf("\n"); 277 } 278 279 static int 280 cbb_pci_attach(device_t brdev) 281 { 282 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 283 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 284 uint32_t pribus; 285 #endif 286 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 287 struct sysctl_ctx_list *sctx; 288 struct sysctl_oid *soid; 289 int rid; 290 device_t parent; 291 292 parent = device_get_parent(brdev); 293 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 294 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 295 sc->dev = brdev; 296 sc->cbdev = NULL; 297 sc->exca[0].pccarddev = NULL; 298 sc->domain = pci_get_domain(brdev); 299 sc->pribus = pcib_get_bus(parent); 300 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 301 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 302 pcib_setup_secbus(brdev, &sc->bus, 1); 303 #else 304 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); 305 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 306 #endif 307 SLIST_INIT(&sc->rl); 308 309 rid = CBBR_SOCKBASE; 310 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 311 RF_ACTIVE); 312 if (!sc->base_res) { 313 device_printf(brdev, "Could not map register memory\n"); 314 mtx_destroy(&sc->mtx); 315 return (ENOMEM); 316 } else { 317 DEVPRINTF((brdev, "Found memory at %jx\n", 318 rman_get_start(sc->base_res))); 319 } 320 321 sc->bst = rman_get_bustag(sc->base_res); 322 sc->bsh = rman_get_bushandle(sc->base_res); 323 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 324 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 325 sc->exca[0].chipset = EXCA_CARDBUS; 326 sc->chipinit = cbb_chipinit; 327 sc->chipinit(sc); 328 329 /*Sysctls*/ 330 sctx = device_get_sysctl_ctx(brdev); 331 soid = device_get_sysctl_tree(brdev); 332 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 333 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 334 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 335 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 336 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 337 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 338 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 339 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 340 #if 0 341 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 342 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 343 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 344 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); 345 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 346 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 347 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 348 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 349 #endif 350 351 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 352 /* 353 * This is a gross hack. We should be scanning the entire pci 354 * tree, assigning bus numbers in a way such that we (1) can 355 * reserve 1 extra bus just in case and (2) all sub buses 356 * are in an appropriate range. 357 */ 358 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); 359 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 360 if (sc->bus.sec == 0 || sc->pribus != pribus) { 361 if (curr_bus_number <= sc->pribus) 362 curr_bus_number = sc->pribus + 1; 363 if (pribus != sc->pribus) { 364 DEVPRINTF((brdev, "Setting primary bus to %d\n", 365 sc->pribus)); 366 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 367 } 368 sc->bus.sec = curr_bus_number++; 369 sc->bus.sub = curr_bus_number++; 370 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 371 sc->bus.sec, sc->bus.sub)); 372 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); 373 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); 374 } 375 #endif 376 377 /* attach children */ 378 sc->cbdev = device_add_child(brdev, "cardbus", -1); 379 if (sc->cbdev == NULL) 380 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 381 else if (device_probe_and_attach(sc->cbdev) != 0) 382 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 383 384 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 385 if (sc->exca[0].pccarddev == NULL) 386 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 387 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 388 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 389 390 /* Map and establish the interrupt. */ 391 rid = 0; 392 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 393 RF_SHAREABLE | RF_ACTIVE); 394 if (sc->irq_res == NULL) { 395 device_printf(brdev, "Unable to map IRQ...\n"); 396 goto err; 397 } 398 399 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 400 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 401 device_printf(brdev, "couldn't establish interrupt\n"); 402 goto err; 403 } 404 405 /* reset 16-bit pcmcia bus */ 406 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 407 408 /* turn off power */ 409 cbb_power(brdev, CARD_OFF); 410 411 /* CSC Interrupt: Card detect interrupt on */ 412 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 413 414 /* reset interrupt */ 415 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 416 417 if (bootverbose) 418 cbb_print_config(brdev); 419 420 /* Start the thread */ 421 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 422 "%s event thread", device_get_nameunit(brdev))) { 423 device_printf(brdev, "unable to create event thread.\n"); 424 panic("cbb_create_event_thread"); 425 } 426 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 427 return (0); 428 err: 429 if (sc->irq_res) 430 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 431 if (sc->base_res) { 432 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 433 sc->base_res); 434 } 435 mtx_destroy(&sc->mtx); 436 return (ENOMEM); 437 } 438 439 static int 440 cbb_pci_detach(device_t brdev) 441 { 442 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 443 struct cbb_softc *sc = device_get_softc(brdev); 444 #endif 445 int error; 446 447 error = cbb_detach(brdev); 448 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 449 if (error == 0) 450 pcib_free_secbus(brdev, &sc->bus); 451 #endif 452 return (error); 453 } 454 455 static void 456 cbb_chipinit(struct cbb_softc *sc) 457 { 458 uint32_t mux, sysctrl, reg; 459 460 /* Set CardBus latency timer */ 461 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) 462 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); 463 464 /* Set PCI latency timer */ 465 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 466 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 467 468 /* Enable DMA, memory access for this card and I/O access for children */ 469 pci_enable_busmaster(sc->dev); 470 pci_enable_io(sc->dev, SYS_RES_IOPORT); 471 pci_enable_io(sc->dev, SYS_RES_MEMORY); 472 473 /* disable Legacy IO */ 474 switch (sc->chipset) { 475 case CB_RF5C46X: 476 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 477 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 478 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 479 break; 480 default: 481 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 482 break; 483 } 484 485 /* Use PCI interrupt for interrupt routing */ 486 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 487 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 488 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 489 | CBBM_BRIDGECTRL_WRITE_POST_EN, 490 2); 491 492 /* 493 * XXX this should be a function table, ala OLDCARD. This means 494 * that we could more easily support ISA interrupts for pccard 495 * cards if we had to. 496 */ 497 switch (sc->chipset) { 498 case CB_TI113X: 499 /* 500 * The TI 1031, TI 1130 and TI 1131 all require another bit 501 * be set to enable PCI routing of interrupts, and then 502 * a bit for each of the CSC and Function interrupts we 503 * want routed. 504 */ 505 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 506 | CBBM_CBCTRL_113X_PCI_INTR | 507 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 508 1); 509 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 510 & ~(CBBM_DEVCTRL_INT_SERIAL | 511 CBBM_DEVCTRL_INT_PCI), 1); 512 break; 513 case CB_TI12XX: 514 /* 515 * Some TI 12xx (and [14][45]xx) based pci cards 516 * sometimes have issues with the MFUNC register not 517 * being initialized due to a bad EEPROM on board. 518 * Laptops that this matters on have this register 519 * properly initialized. 520 * 521 * The TI125X parts have a different register. 522 * 523 * Note: Only the lower two nibbles matter. When set 524 * to 0, the MFUNC{0,1} pins are GPIO, which isn't 525 * going to work out too well because we specifically 526 * program these parts to parallel interrupt signalling 527 * elsewhere. We preserve the upper bits of this 528 * register since changing them have subtle side effects 529 * for different variants of the card and are 530 * extremely difficult to exaustively test. 531 * 532 * Also, the TI 1510/1520 changed the default for the MFUNC 533 * register from 0x0 to 0x1000 to enable IRQSER by default. 534 * We want to be careful to avoid overriding that, and the 535 * below test will do that. Should this check prove to be 536 * too permissive, we should just check against 0 and 0x1000 537 * and not touch it otherwise. 538 */ 539 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 540 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 541 if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { 542 mux = (mux & ~CBBM_MFUNC_PIN0) | 543 CBBM_MFUNC_PIN0_INTA; 544 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 545 mux = (mux & ~CBBM_MFUNC_PIN1) | 546 CBBM_MFUNC_PIN1_INTB; 547 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 548 } 549 /*FALLTHROUGH*/ 550 case CB_TI125X: 551 /* 552 * Disable zoom video. Some machines initialize this 553 * improperly and exerpience has shown that this helps 554 * prevent strange behavior. We don't support zoom 555 * video anyway, so no harm can come from this. 556 */ 557 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 558 break; 559 case CB_O2MICRO: 560 /* 561 * Issue #1: INT# generated at the same time as 562 * selected ISA IRQ. When IREQ# or STSCHG# is active, 563 * in addition to the ISA IRQ being generated, INT# 564 * will also be generated at the same time. 565 * 566 * Some of the older controllers have an issue in 567 * which the slot's PCI INT# will be asserted whenever 568 * IREQ# or STSCGH# is asserted even if ExCA registers 569 * 03h or 05h have an ISA IRQ selected. 570 * 571 * The fix for this issue, which will work for any 572 * controller (old or new), is to set ExCA registers 573 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 574 * These bits are undocumented. By setting this 575 * register (of each slot) to '1010xxxxb' a routing of 576 * IREQ# to INTC# and STSCHG# to INTC# is selected. 577 * Since INTC# isn't connected there will be no 578 * unexpected PCI INT when IREQ# or STSCHG# is active. 579 * However, INTA# (slot 0) or INTB# (slot 1) will 580 * still be correctly generated if NO ISA IRQ is 581 * selected (ExCA regs 03h or 05h are cleared). 582 */ 583 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 584 reg = (reg & 0x0f) | 585 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 586 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 587 break; 588 case CB_TOPIC97: 589 /* 590 * Disable Zoom Video, ToPIC 97, 100. 591 */ 592 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 593 /* 594 * ToPIC 97, 100 595 * At offset 0xa1: INTERRUPT CONTROL register 596 * 0x1: Turn on INT interrupts. 597 */ 598 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 599 | TOPIC97_INTCTRL_INTIRQSEL, 1); 600 /* 601 * ToPIC97, 100 602 * Need to assert support for low voltage cards 603 */ 604 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL, 605 EXCA_TOPIC97_CTRL_LV_MASK); 606 goto topic_common; 607 case CB_TOPIC95: 608 /* 609 * SOCKETCTRL appears to be TOPIC 95/B specific 610 */ 611 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 612 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 613 614 topic_common:; 615 /* 616 * At offset 0xa0: SLOT CONTROL 617 * 0x80 Enable CardBus Functionality 618 * 0x40 Enable CardBus and PC Card registers 619 * 0x20 Lock ID in exca regs 620 * 0x10 Write protect ID in config regs 621 * Clear the rest of the bits, which defaults the slot 622 * in legacy mode to 0x3e0 and offset 0. (legacy 623 * mode is determined elsewhere) 624 */ 625 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 626 TOPIC_SLOTCTRL_SLOTON | 627 TOPIC_SLOTCTRL_SLOTEN | 628 TOPIC_SLOTCTRL_ID_LOCK | 629 TOPIC_SLOTCTRL_ID_WP, 1); 630 631 /* 632 * At offset 0xa3 Card Detect Control Register 633 * 0x80 CARDBUS enbale 634 * 0x01 Cleared for hardware change detect 635 */ 636 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 637 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 638 break; 639 } 640 641 /* 642 * Need to tell ExCA registers to CSC interrupts route via PCI 643 * interrupts. There are two ways to do this. One is to set 644 * INTR_ENABLE and the other is to set CSC to 0. Since both 645 * methods are mutually compatible, we do both. 646 */ 647 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 648 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 649 650 cbb_disable_func_intr(sc); 651 652 /* close all memory and io windows */ 653 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 654 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 655 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 656 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 657 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 658 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 659 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 660 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 661 } 662 663 static int 664 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 665 { 666 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 667 668 return (rman_get_start(sc->irq_res)); 669 } 670 671 static int 672 cbb_pci_shutdown(device_t brdev) 673 { 674 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 675 676 /* 677 * We're about to pull the rug out from the card, so mark it as 678 * gone to prevent harm. 679 */ 680 sc->cardok = 0; 681 682 /* 683 * Place the cards in reset, turn off the interrupts and power 684 * down the socket. 685 */ 686 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 687 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 688 cbb_set(sc, CBB_SOCKET_MASK, 0); 689 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 690 cbb_power(brdev, CARD_OFF); 691 692 /* 693 * For paranoia, turn off all address decoding. Really not needed, 694 * it seems, but it can't hurt 695 */ 696 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 697 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 698 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 699 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 700 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 701 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 702 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 703 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 704 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 705 return (0); 706 } 707 708 static int 709 cbb_pci_filt(void *arg) 710 { 711 struct cbb_softc *sc = arg; 712 uint32_t sockevent; 713 uint8_t csc; 714 int retval = FILTER_STRAY; 715 716 /* 717 * Some chips also require us to read the old ExCA registe for card 718 * status change when we route CSC vis PCI. This isn't supposed to be 719 * required, but it clears the interrupt state on some chipsets. 720 * Maybe there's a setting that would obviate its need. Maybe we 721 * should test the status bits and deal with them, but so far we've 722 * not found any machines that don't also give us the socket status 723 * indication above. 724 * 725 * This call used to be unconditional. However, further research 726 * suggests that we hit this condition when the card READY interrupt 727 * fired. So now we only read it for 16-bit cards, and we only claim 728 * the interrupt if READY is set. If this still causes problems, then 729 * the next step would be to read this if we have a 16-bit card *OR* 730 * we have no card. We treat the READY signal as if it were the power 731 * completion signal. Some bridges may double signal things here, bit 732 * signalling twice should be OK since we only sleep on the powerintr 733 * in one place and a double wakeup would be benign there. 734 */ 735 if (sc->flags & CBB_16BIT_CARD) { 736 csc = exca_getb(&sc->exca[0], EXCA_CSC); 737 if (csc & EXCA_CSC_READY) { 738 atomic_add_int(&sc->powerintr, 1); 739 wakeup((void *)&sc->powerintr); 740 retval = FILTER_HANDLED; 741 } 742 } 743 744 /* 745 * Read the socket event. Sometimes, the theory goes, the PCI bus is 746 * so loaded that it cannot satisfy the read request, so we get 747 * garbage back from the following read. We have to filter out the 748 * garbage so that we don't spontaneously reset the card under high 749 * load. PCI isn't supposed to act like this. No doubt this is a bug 750 * in the PCI bridge chipset (or cbb brige) that's being used in 751 * certain amd64 laptops today. Work around the issue by assuming 752 * that any bits we don't know about being set means that we got 753 * garbage. 754 */ 755 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 756 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 757 /* 758 * If anything has happened to the socket, we assume that the 759 * card is no longer OK, and we shouldn't call its ISR. We 760 * set cardok as soon as we've attached the card. This helps 761 * in a noisy eject, which happens all too often when users 762 * are ejecting their PC Cards. 763 * 764 * We use this method in preference to checking to see if the 765 * card is still there because the check suffers from a race 766 * condition in the bouncing case. 767 */ 768 #define DELTA (CBB_SOCKET_MASK_CD) 769 if (sockevent & DELTA) { 770 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 771 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 772 sc->cardok = 0; 773 cbb_disable_func_intr(sc); 774 wakeup(&sc->intrhand); 775 } 776 #undef DELTA 777 778 /* 779 * Wakeup anybody waiting for a power interrupt. We have to 780 * use atomic_add_int for wakups on other cores. 781 */ 782 if (sockevent & CBB_SOCKET_EVENT_POWER) { 783 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 784 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 785 atomic_add_int(&sc->powerintr, 1); 786 wakeup((void *)&sc->powerintr); 787 } 788 789 /* 790 * Status change interrupts aren't presently used in the 791 * rest of the driver. For now, just ACK them. 792 */ 793 if (sockevent & CBB_SOCKET_EVENT_CSTS) 794 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 795 retval = FILTER_HANDLED; 796 } 797 return retval; 798 } 799 800 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 801 static struct resource * 802 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 803 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 804 { 805 struct cbb_softc *sc; 806 807 sc = device_get_softc(bus); 808 if (type == PCI_RES_BUS) 809 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 810 count, flags)); 811 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 812 flags)); 813 } 814 815 static int 816 cbb_pci_adjust_resource(device_t bus, device_t child, int type, 817 struct resource *r, rman_res_t start, rman_res_t end) 818 { 819 struct cbb_softc *sc; 820 821 sc = device_get_softc(bus); 822 if (type == PCI_RES_BUS) { 823 if (!rman_is_region_manager(r, &sc->bus.rman)) 824 return (EINVAL); 825 return (rman_adjust_resource(r, start, end)); 826 } 827 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 828 } 829 830 static int 831 cbb_pci_release_resource(device_t bus, device_t child, int type, int rid, 832 struct resource *r) 833 { 834 struct cbb_softc *sc; 835 int error; 836 837 sc = device_get_softc(bus); 838 if (type == PCI_RES_BUS) { 839 if (!rman_is_region_manager(r, &sc->bus.rman)) 840 return (EINVAL); 841 if (rman_get_flags(r) & RF_ACTIVE) { 842 error = bus_deactivate_resource(child, type, rid, r); 843 if (error) 844 return (error); 845 } 846 return (rman_release_resource(r)); 847 } 848 return (cbb_release_resource(bus, child, type, rid, r)); 849 } 850 #endif 851 852 /************************************************************************/ 853 /* PCI compat methods */ 854 /************************************************************************/ 855 856 static int 857 cbb_maxslots(device_t brdev) 858 { 859 return (0); 860 } 861 862 static uint32_t 863 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 864 { 865 /* 866 * Pass through to the next ppb up the chain (i.e. our grandparent). 867 */ 868 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 869 b, s, f, reg, width)); 870 } 871 872 static void 873 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 874 int width) 875 { 876 /* 877 * Pass through to the next ppb up the chain (i.e. our grandparent). 878 */ 879 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 880 b, s, f, reg, val, width); 881 } 882 883 static int 884 cbb_pci_suspend(device_t brdev) 885 { 886 int error = 0; 887 struct cbb_softc *sc = device_get_softc(brdev); 888 889 error = bus_generic_suspend(brdev); 890 if (error != 0) 891 return (error); 892 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 893 sc->cardok = 0; /* Card is bogus now */ 894 return (0); 895 } 896 897 static int 898 cbb_pci_resume(device_t brdev) 899 { 900 int error = 0; 901 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 902 uint32_t tmp; 903 904 /* 905 * In the APM and early ACPI era, BIOSes saved the PCI config 906 * registers. As chips became more complicated, that functionality moved 907 * into the ACPI code / tables. We must therefore, restore the settings 908 * we made here to make sure the device come back. Transitions to Dx 909 * from D0 and back to D0 cause the bridge to lose its config space, so 910 * all the bus mappings and such are preserved. 911 * 912 * The PCI layer handles standard PCI registers like the 913 * command register and BARs, but cbb-specific registers are 914 * handled here. 915 */ 916 sc->chipinit(sc); 917 918 /* reset interrupt -- Do we really need to do this? */ 919 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 920 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 921 922 /* CSC Interrupt: Card detect interrupt on */ 923 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 924 925 /* Signal the thread to wakeup. */ 926 wakeup(&sc->intrhand); 927 928 error = bus_generic_resume(brdev); 929 930 return (error); 931 } 932 933 static device_method_t cbb_methods[] = { 934 /* Device interface */ 935 DEVMETHOD(device_probe, cbb_pci_probe), 936 DEVMETHOD(device_attach, cbb_pci_attach), 937 DEVMETHOD(device_detach, cbb_pci_detach), 938 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 939 DEVMETHOD(device_suspend, cbb_pci_suspend), 940 DEVMETHOD(device_resume, cbb_pci_resume), 941 942 /* bus methods */ 943 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 944 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 945 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 946 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 947 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 948 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 949 #else 950 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 951 DEVMETHOD(bus_release_resource, cbb_release_resource), 952 #endif 953 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 954 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 955 DEVMETHOD(bus_driver_added, cbb_driver_added), 956 DEVMETHOD(bus_child_detached, cbb_child_detached), 957 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 958 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 959 DEVMETHOD(bus_child_present, cbb_child_present), 960 961 /* 16-bit card interface */ 962 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 963 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 964 965 /* power interface */ 966 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 967 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 968 969 /* pcib compatibility interface */ 970 DEVMETHOD(pcib_maxslots, cbb_maxslots), 971 DEVMETHOD(pcib_read_config, cbb_read_config), 972 DEVMETHOD(pcib_write_config, cbb_write_config), 973 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 974 975 DEVMETHOD_END 976 }; 977 978 static driver_t cbb_driver = { 979 "cbb", 980 cbb_methods, 981 sizeof(struct cbb_softc) 982 }; 983 984 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 985 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, cbb, yc_chipsets, 986 nitems(yc_chipsets) - 1); 987 MODULE_DEPEND(cbb, exca, 1, 1, 1); 988