1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2000-2001 Jonathan Chen All rights reserved. 5 * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /*- 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/condvar.h> 80 #include <sys/errno.h> 81 #include <sys/kernel.h> 82 #include <sys/lock.h> 83 #include <sys/malloc.h> 84 #include <sys/mutex.h> 85 #include <sys/sysctl.h> 86 #include <sys/kthread.h> 87 #include <sys/bus.h> 88 #include <machine/bus.h> 89 #include <sys/rman.h> 90 #include <machine/resource.h> 91 #include <sys/module.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/pcib_private.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 static void cbb_chipinit(struct cbb_softc *sc); 120 static int cbb_pci_filt(void *arg); 121 122 static struct yenta_chipinfo { 123 uint32_t yc_id; 124 const char *yc_name; 125 int yc_chiptype; 126 } yc_chipsets[] = { 127 /* Texas Instruments chips */ 128 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 129 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 130 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 131 132 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 133 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 138 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 140 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 142 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 146 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 163 /* ENE */ 164 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 170 171 /* Ricoh chips */ 172 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 173 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 174 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 175 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 177 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 178 179 /* Toshiba products */ 180 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 181 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 182 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 183 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 184 185 /* Cirrus Logic */ 186 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 187 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 188 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 189 190 /* 02Micro */ 191 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 203 204 /* SMC */ 205 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 206 207 /* sentinel */ 208 {0 /* null id */, "unknown", CB_UNKNOWN}, 209 }; 210 211 /************************************************************************/ 212 /* Probe/Attach */ 213 /************************************************************************/ 214 215 static int 216 cbb_chipset(uint32_t pci_id, const char **namep) 217 { 218 struct yenta_chipinfo *ycp; 219 220 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 221 continue; 222 if (namep != NULL) 223 *namep = ycp->yc_name; 224 return (ycp->yc_chiptype); 225 } 226 227 static int 228 cbb_pci_probe(device_t brdev) 229 { 230 const char *name; 231 uint32_t progif; 232 uint32_t baseclass; 233 uint32_t subclass; 234 235 /* 236 * Do we know that we support the chipset? If so, then we 237 * accept the device. 238 */ 239 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 240 device_set_desc(brdev, name); 241 return (BUS_PROBE_DEFAULT); 242 } 243 244 /* 245 * We do support generic CardBus bridges. All that we've seen 246 * to date have progif 0 (the Yenta spec, and successors mandate 247 * this). 248 */ 249 baseclass = pci_get_class(brdev); 250 subclass = pci_get_subclass(brdev); 251 progif = pci_get_progif(brdev); 252 if (baseclass == PCIC_BRIDGE && 253 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 254 device_set_desc(brdev, "PCI-CardBus Bridge"); 255 return (BUS_PROBE_GENERIC); 256 } 257 return (ENXIO); 258 } 259 260 /* 261 * Print out the config space 262 */ 263 static void 264 cbb_print_config(device_t dev) 265 { 266 int i; 267 268 device_printf(dev, "PCI Configuration space:"); 269 for (i = 0; i < 256; i += 4) { 270 if (i % 16 == 0) 271 printf("\n 0x%02x: ", i); 272 printf("0x%08x ", pci_read_config(dev, i, 4)); 273 } 274 printf("\n"); 275 } 276 277 static int 278 cbb_pci_attach(device_t brdev) 279 { 280 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 281 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 282 uint32_t pribus; 283 #endif 284 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 285 struct sysctl_ctx_list *sctx; 286 struct sysctl_oid *soid; 287 int rid; 288 device_t parent; 289 290 parent = device_get_parent(brdev); 291 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 292 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 293 sc->dev = brdev; 294 sc->cbdev = NULL; 295 sc->domain = pci_get_domain(brdev); 296 sc->pribus = pcib_get_bus(parent); 297 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 298 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 299 pcib_setup_secbus(brdev, &sc->bus, 1); 300 #else 301 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); 302 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 303 #endif 304 SLIST_INIT(&sc->rl); 305 306 rid = CBBR_SOCKBASE; 307 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 308 RF_ACTIVE); 309 if (!sc->base_res) { 310 device_printf(brdev, "Could not map register memory\n"); 311 mtx_destroy(&sc->mtx); 312 return (ENOMEM); 313 } else { 314 DEVPRINTF((brdev, "Found memory at %jx\n", 315 rman_get_start(sc->base_res))); 316 } 317 318 /* attach children */ 319 sc->cbdev = device_add_child(brdev, "cardbus", -1); 320 if (sc->cbdev == NULL) 321 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 322 else if (device_probe_and_attach(sc->cbdev) != 0) 323 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 324 325 sc->bst = rman_get_bustag(sc->base_res); 326 sc->bsh = rman_get_bushandle(sc->base_res); 327 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 328 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 329 sc->exca.chipset = EXCA_CARDBUS; 330 sc->chipinit = cbb_chipinit; 331 sc->chipinit(sc); 332 333 /*Sysctls*/ 334 sctx = device_get_sysctl_ctx(brdev); 335 soid = device_get_sysctl_tree(brdev); 336 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 337 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 338 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 339 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 340 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 341 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 342 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 343 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 344 #if 0 345 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 346 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 347 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 348 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); 349 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 350 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 351 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 352 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 353 #endif 354 355 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 356 /* 357 * This is a gross hack. We should be scanning the entire pci 358 * tree, assigning bus numbers in a way such that we (1) can 359 * reserve 1 extra bus just in case and (2) all sub buses 360 * are in an appropriate range. 361 */ 362 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); 363 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 364 if (sc->bus.sec == 0 || sc->pribus != pribus) { 365 if (curr_bus_number <= sc->pribus) 366 curr_bus_number = sc->pribus + 1; 367 if (pribus != sc->pribus) { 368 DEVPRINTF((brdev, "Setting primary bus to %d\n", 369 sc->pribus)); 370 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 371 } 372 sc->bus.sec = curr_bus_number++; 373 sc->bus.sub = curr_bus_number++; 374 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 375 sc->bus.sec, sc->bus.sub)); 376 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); 377 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); 378 } 379 #endif 380 381 /* Map and establish the interrupt. */ 382 rid = 0; 383 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 384 RF_SHAREABLE | RF_ACTIVE); 385 if (sc->irq_res == NULL) { 386 device_printf(brdev, "Unable to map IRQ...\n"); 387 goto err; 388 } 389 390 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 391 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 392 device_printf(brdev, "couldn't establish interrupt\n"); 393 goto err; 394 } 395 396 /* reset 16-bit pcmcia bus */ 397 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 398 399 /* turn off power */ 400 cbb_power(brdev, CARD_OFF); 401 402 /* CSC Interrupt: Card detect interrupt on */ 403 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 404 405 /* reset interrupt */ 406 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 407 408 if (bootverbose) 409 cbb_print_config(brdev); 410 411 /* Start the thread */ 412 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 413 "%s event thread", device_get_nameunit(brdev))) { 414 device_printf(brdev, "unable to create event thread.\n"); 415 panic("cbb_create_event_thread"); 416 } 417 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 418 return (0); 419 err: 420 if (sc->irq_res) 421 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 422 if (sc->base_res) { 423 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 424 sc->base_res); 425 } 426 mtx_destroy(&sc->mtx); 427 return (ENOMEM); 428 } 429 430 static int 431 cbb_pci_detach(device_t brdev) 432 { 433 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 434 struct cbb_softc *sc = device_get_softc(brdev); 435 #endif 436 int error; 437 438 error = cbb_detach(brdev); 439 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 440 if (error == 0) 441 pcib_free_secbus(brdev, &sc->bus); 442 #endif 443 return (error); 444 } 445 446 static void 447 cbb_chipinit(struct cbb_softc *sc) 448 { 449 uint32_t mux, sysctrl, reg; 450 451 /* Set CardBus latency timer */ 452 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) 453 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); 454 455 /* Set PCI latency timer */ 456 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 457 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 458 459 /* Enable DMA, memory access for this card and I/O access for children */ 460 pci_enable_busmaster(sc->dev); 461 pci_enable_io(sc->dev, SYS_RES_IOPORT); 462 pci_enable_io(sc->dev, SYS_RES_MEMORY); 463 464 /* disable Legacy IO */ 465 switch (sc->chipset) { 466 case CB_RF5C46X: 467 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 468 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 469 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 470 break; 471 default: 472 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 473 break; 474 } 475 476 /* Use PCI interrupt for interrupt routing */ 477 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 478 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 479 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 480 | CBBM_BRIDGECTRL_WRITE_POST_EN, 481 2); 482 483 /* 484 * XXX this should be a function table, ala OLDCARD. This means 485 * that we could more easily support ISA interrupts for pccard 486 * cards if we had to. 487 */ 488 switch (sc->chipset) { 489 case CB_TI113X: 490 /* 491 * The TI 1031, TI 1130 and TI 1131 all require another bit 492 * be set to enable PCI routing of interrupts, and then 493 * a bit for each of the CSC and Function interrupts we 494 * want routed. 495 */ 496 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 497 | CBBM_CBCTRL_113X_PCI_INTR | 498 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 499 1); 500 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 501 & ~(CBBM_DEVCTRL_INT_SERIAL | 502 CBBM_DEVCTRL_INT_PCI), 1); 503 break; 504 case CB_TI12XX: 505 /* 506 * Some TI 12xx (and [14][45]xx) based pci cards 507 * sometimes have issues with the MFUNC register not 508 * being initialized due to a bad EEPROM on board. 509 * Laptops that this matters on have this register 510 * properly initialized. 511 * 512 * The TI125X parts have a different register. 513 * 514 * Note: Only the lower two nibbles matter. When set 515 * to 0, the MFUNC{0,1} pins are GPIO, which isn't 516 * going to work out too well because we specifically 517 * program these parts to parallel interrupt signalling 518 * elsewhere. We preserve the upper bits of this 519 * register since changing them have subtle side effects 520 * for different variants of the card and are 521 * extremely difficult to exaustively test. 522 * 523 * Also, the TI 1510/1520 changed the default for the MFUNC 524 * register from 0x0 to 0x1000 to enable IRQSER by default. 525 * We want to be careful to avoid overriding that, and the 526 * below test will do that. Should this check prove to be 527 * too permissive, we should just check against 0 and 0x1000 528 * and not touch it otherwise. 529 */ 530 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 531 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 532 if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { 533 mux = (mux & ~CBBM_MFUNC_PIN0) | 534 CBBM_MFUNC_PIN0_INTA; 535 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 536 mux = (mux & ~CBBM_MFUNC_PIN1) | 537 CBBM_MFUNC_PIN1_INTB; 538 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 539 } 540 /*FALLTHROUGH*/ 541 case CB_TI125X: 542 /* 543 * Disable zoom video. Some machines initialize this 544 * improperly and exerpience has shown that this helps 545 * prevent strange behavior. We don't support zoom 546 * video anyway, so no harm can come from this. 547 */ 548 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 549 break; 550 case CB_O2MICRO: 551 /* 552 * Issue #1: INT# generated at the same time as 553 * selected ISA IRQ. When IREQ# or STSCHG# is active, 554 * in addition to the ISA IRQ being generated, INT# 555 * will also be generated at the same time. 556 * 557 * Some of the older controllers have an issue in 558 * which the slot's PCI INT# will be asserted whenever 559 * IREQ# or STSCGH# is asserted even if ExCA registers 560 * 03h or 05h have an ISA IRQ selected. 561 * 562 * The fix for this issue, which will work for any 563 * controller (old or new), is to set ExCA registers 564 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 565 * These bits are undocumented. By setting this 566 * register (of each slot) to '1010xxxxb' a routing of 567 * IREQ# to INTC# and STSCHG# to INTC# is selected. 568 * Since INTC# isn't connected there will be no 569 * unexpected PCI INT when IREQ# or STSCHG# is active. 570 * However, INTA# (slot 0) or INTB# (slot 1) will 571 * still be correctly generated if NO ISA IRQ is 572 * selected (ExCA regs 03h or 05h are cleared). 573 */ 574 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 575 reg = (reg & 0x0f) | 576 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 577 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 578 break; 579 case CB_TOPIC97: 580 /* 581 * Disable Zoom Video, ToPIC 97, 100. 582 */ 583 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 584 /* 585 * ToPIC 97, 100 586 * At offset 0xa1: INTERRUPT CONTROL register 587 * 0x1: Turn on INT interrupts. 588 */ 589 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 590 | TOPIC97_INTCTRL_INTIRQSEL, 1); 591 /* 592 * ToPIC97, 100 593 * Need to assert support for low voltage cards 594 */ 595 exca_setb(&sc->exca, EXCA_TOPIC97_CTRL, 596 EXCA_TOPIC97_CTRL_LV_MASK); 597 goto topic_common; 598 case CB_TOPIC95: 599 /* 600 * SOCKETCTRL appears to be TOPIC 95/B specific 601 */ 602 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 603 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 604 605 topic_common:; 606 /* 607 * At offset 0xa0: SLOT CONTROL 608 * 0x80 Enable CardBus Functionality 609 * 0x40 Enable CardBus and PC Card registers 610 * 0x20 Lock ID in exca regs 611 * 0x10 Write protect ID in config regs 612 * Clear the rest of the bits, which defaults the slot 613 * in legacy mode to 0x3e0 and offset 0. (legacy 614 * mode is determined elsewhere) 615 */ 616 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 617 TOPIC_SLOTCTRL_SLOTON | 618 TOPIC_SLOTCTRL_SLOTEN | 619 TOPIC_SLOTCTRL_ID_LOCK | 620 TOPIC_SLOTCTRL_ID_WP, 1); 621 622 /* 623 * At offset 0xa3 Card Detect Control Register 624 * 0x80 CARDBUS enbale 625 * 0x01 Cleared for hardware change detect 626 */ 627 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 628 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 629 break; 630 } 631 632 /* 633 * Need to tell ExCA registers to CSC interrupts route via PCI 634 * interrupts. There are two ways to do this. One is to set 635 * INTR_ENABLE and the other is to set CSC to 0. Since both 636 * methods are mutually compatible, we do both. 637 */ 638 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 639 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 640 641 cbb_disable_func_intr(sc); 642 643 /* close all memory and io windows */ 644 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 645 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 646 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 647 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 648 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 649 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 650 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 651 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 652 } 653 654 static int 655 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 656 { 657 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 658 659 return (rman_get_start(sc->irq_res)); 660 } 661 662 static int 663 cbb_pci_shutdown(device_t brdev) 664 { 665 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 666 667 /* 668 * We're about to pull the rug out from the card, so mark it as 669 * gone to prevent harm. 670 */ 671 sc->cardok = 0; 672 673 /* 674 * Place the cards in reset, turn off the interrupts and power 675 * down the socket. 676 */ 677 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 678 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 679 cbb_set(sc, CBB_SOCKET_MASK, 0); 680 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 681 cbb_power(brdev, CARD_OFF); 682 683 /* 684 * For paranoia, turn off all address decoding. Really not needed, 685 * it seems, but it can't hurt 686 */ 687 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 688 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 689 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 690 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 691 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 692 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 693 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 694 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 695 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 696 return (0); 697 } 698 699 static int 700 cbb_pci_filt(void *arg) 701 { 702 struct cbb_softc *sc = arg; 703 uint32_t sockevent; 704 uint8_t csc; 705 int retval = FILTER_STRAY; 706 707 /* 708 * Some chips also require us to read the old ExCA registe for card 709 * status change when we route CSC vis PCI. This isn't supposed to be 710 * required, but it clears the interrupt state on some chipsets. 711 * Maybe there's a setting that would obviate its need. Maybe we 712 * should test the status bits and deal with them, but so far we've 713 * not found any machines that don't also give us the socket status 714 * indication above. 715 * 716 * This call used to be unconditional. However, further research 717 * suggests that we hit this condition when the card READY interrupt 718 * fired. So now we only read it for 16-bit cards, and we only claim 719 * the interrupt if READY is set. If this still causes problems, then 720 * the next step would be to read this if we have a 16-bit card *OR* 721 * we have no card. We treat the READY signal as if it were the power 722 * completion signal. Some bridges may double signal things here, bit 723 * signalling twice should be OK since we only sleep on the powerintr 724 * in one place and a double wakeup would be benign there. 725 */ 726 if (sc->flags & CBB_16BIT_CARD) { 727 csc = exca_getb(&sc->exca, EXCA_CSC); 728 if (csc & EXCA_CSC_READY) { 729 atomic_add_int(&sc->powerintr, 1); 730 wakeup((void *)&sc->powerintr); 731 retval = FILTER_HANDLED; 732 } 733 } 734 735 /* 736 * Read the socket event. Sometimes, the theory goes, the PCI bus is 737 * so loaded that it cannot satisfy the read request, so we get 738 * garbage back from the following read. We have to filter out the 739 * garbage so that we don't spontaneously reset the card under high 740 * load. PCI isn't supposed to act like this. No doubt this is a bug 741 * in the PCI bridge chipset (or cbb brige) that's being used in 742 * certain amd64 laptops today. Work around the issue by assuming 743 * that any bits we don't know about being set means that we got 744 * garbage. 745 */ 746 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 747 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 748 /* 749 * If anything has happened to the socket, we assume that the 750 * card is no longer OK, and we shouldn't call its ISR. We 751 * set cardok as soon as we've attached the card. This helps 752 * in a noisy eject, which happens all too often when users 753 * are ejecting their PC Cards. 754 * 755 * We use this method in preference to checking to see if the 756 * card is still there because the check suffers from a race 757 * condition in the bouncing case. 758 */ 759 #define DELTA (CBB_SOCKET_MASK_CD) 760 if (sockevent & DELTA) { 761 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 762 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 763 sc->cardok = 0; 764 cbb_disable_func_intr(sc); 765 wakeup(&sc->intrhand); 766 } 767 #undef DELTA 768 769 /* 770 * Wakeup anybody waiting for a power interrupt. We have to 771 * use atomic_add_int for wakups on other cores. 772 */ 773 if (sockevent & CBB_SOCKET_EVENT_POWER) { 774 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 775 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 776 atomic_add_int(&sc->powerintr, 1); 777 wakeup((void *)&sc->powerintr); 778 } 779 780 /* 781 * Status change interrupts aren't presently used in the 782 * rest of the driver. For now, just ACK them. 783 */ 784 if (sockevent & CBB_SOCKET_EVENT_CSTS) 785 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 786 retval = FILTER_HANDLED; 787 } 788 return retval; 789 } 790 791 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 792 static struct resource * 793 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 794 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 795 { 796 struct cbb_softc *sc; 797 798 sc = device_get_softc(bus); 799 if (type == PCI_RES_BUS) 800 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 801 count, flags)); 802 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 803 flags)); 804 } 805 806 static int 807 cbb_pci_adjust_resource(device_t bus, device_t child, int type, 808 struct resource *r, rman_res_t start, rman_res_t end) 809 { 810 struct cbb_softc *sc; 811 812 sc = device_get_softc(bus); 813 if (type == PCI_RES_BUS) { 814 if (!rman_is_region_manager(r, &sc->bus.rman)) 815 return (EINVAL); 816 return (rman_adjust_resource(r, start, end)); 817 } 818 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 819 } 820 821 static int 822 cbb_pci_release_resource(device_t bus, device_t child, int type, int rid, 823 struct resource *r) 824 { 825 struct cbb_softc *sc; 826 int error; 827 828 sc = device_get_softc(bus); 829 if (type == PCI_RES_BUS) { 830 if (!rman_is_region_manager(r, &sc->bus.rman)) 831 return (EINVAL); 832 if (rman_get_flags(r) & RF_ACTIVE) { 833 error = bus_deactivate_resource(child, type, rid, r); 834 if (error) 835 return (error); 836 } 837 return (rman_release_resource(r)); 838 } 839 return (cbb_release_resource(bus, child, type, rid, r)); 840 } 841 #endif 842 843 /************************************************************************/ 844 /* PCI compat methods */ 845 /************************************************************************/ 846 847 static int 848 cbb_maxslots(device_t brdev) 849 { 850 return (0); 851 } 852 853 static uint32_t 854 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 855 { 856 /* 857 * Pass through to the next ppb up the chain (i.e. our grandparent). 858 */ 859 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 860 b, s, f, reg, width)); 861 } 862 863 static void 864 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 865 int width) 866 { 867 /* 868 * Pass through to the next ppb up the chain (i.e. our grandparent). 869 */ 870 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 871 b, s, f, reg, val, width); 872 } 873 874 static int 875 cbb_pci_suspend(device_t brdev) 876 { 877 int error = 0; 878 struct cbb_softc *sc = device_get_softc(brdev); 879 880 error = bus_generic_suspend(brdev); 881 if (error != 0) 882 return (error); 883 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 884 sc->cardok = 0; /* Card is bogus now */ 885 return (0); 886 } 887 888 static int 889 cbb_pci_resume(device_t brdev) 890 { 891 int error = 0; 892 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 893 uint32_t tmp; 894 895 /* 896 * In the APM and early ACPI era, BIOSes saved the PCI config 897 * registers. As chips became more complicated, that functionality moved 898 * into the ACPI code / tables. We must therefore, restore the settings 899 * we made here to make sure the device come back. Transitions to Dx 900 * from D0 and back to D0 cause the bridge to lose its config space, so 901 * all the bus mappings and such are preserved. 902 * 903 * The PCI layer handles standard PCI registers like the 904 * command register and BARs, but cbb-specific registers are 905 * handled here. 906 */ 907 sc->chipinit(sc); 908 909 /* reset interrupt -- Do we really need to do this? */ 910 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 911 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 912 913 /* CSC Interrupt: Card detect interrupt on */ 914 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 915 916 /* Signal the thread to wakeup. */ 917 wakeup(&sc->intrhand); 918 919 error = bus_generic_resume(brdev); 920 921 return (error); 922 } 923 924 static device_method_t cbb_methods[] = { 925 /* Device interface */ 926 DEVMETHOD(device_probe, cbb_pci_probe), 927 DEVMETHOD(device_attach, cbb_pci_attach), 928 DEVMETHOD(device_detach, cbb_pci_detach), 929 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 930 DEVMETHOD(device_suspend, cbb_pci_suspend), 931 DEVMETHOD(device_resume, cbb_pci_resume), 932 933 /* bus methods */ 934 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 935 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 936 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 937 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 938 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 939 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 940 #else 941 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 942 DEVMETHOD(bus_release_resource, cbb_release_resource), 943 #endif 944 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 945 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 946 DEVMETHOD(bus_driver_added, cbb_driver_added), 947 DEVMETHOD(bus_child_detached, cbb_child_detached), 948 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 949 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 950 DEVMETHOD(bus_child_present, cbb_child_present), 951 952 /* 16-bit card interface */ 953 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 954 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 955 956 /* power interface */ 957 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 958 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 959 960 /* pcib compatibility interface */ 961 DEVMETHOD(pcib_maxslots, cbb_maxslots), 962 DEVMETHOD(pcib_read_config, cbb_read_config), 963 DEVMETHOD(pcib_write_config, cbb_write_config), 964 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 965 966 DEVMETHOD_END 967 }; 968 969 static driver_t cbb_driver = { 970 "cbb", 971 cbb_methods, 972 sizeof(struct cbb_softc) 973 }; 974 975 DRIVER_MODULE(cbb, pci, cbb_driver, 0, 0); 976 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, cbb, yc_chipsets, 977 nitems(yc_chipsets) - 1); 978 MODULE_DEPEND(cbb, exca, 1, 1, 1); 979