1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 __FBSDID("$FreeBSD$"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/condvar.h> 82 #include <sys/errno.h> 83 #include <sys/kernel.h> 84 #include <sys/lock.h> 85 #include <sys/malloc.h> 86 #include <sys/mutex.h> 87 #include <sys/sysctl.h> 88 #include <sys/kthread.h> 89 #include <sys/bus.h> 90 #include <machine/bus.h> 91 #include <sys/rman.h> 92 #include <machine/resource.h> 93 #include <sys/module.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <machine/clock.h> 98 99 #include <dev/pccard/pccardreg.h> 100 #include <dev/pccard/pccardvar.h> 101 102 #include <dev/exca/excareg.h> 103 #include <dev/exca/excavar.h> 104 105 #include <dev/pccbb/pccbbreg.h> 106 #include <dev/pccbb/pccbbvar.h> 107 108 #include "power_if.h" 109 #include "card_if.h" 110 #include "pcib_if.h" 111 112 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 113 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 114 115 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 116 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 117 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 118 pci_write_config(DEV, REG, ( \ 119 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 120 121 static void cbb_chipinit(struct cbb_softc *sc); 122 123 static struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 155 /* ENE */ 156 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 162 163 /* Ricoh chips */ 164 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 165 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 166 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 167 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 168 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 169 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 170 171 /* Toshiba products */ 172 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 173 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 174 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 175 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 176 177 /* Cirrus Logic */ 178 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 179 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 180 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 181 182 /* 02Micro */ 183 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 184 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 185 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 186 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 187 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 188 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 189 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 190 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 191 192 /* sentinel */ 193 {0 /* null id */, "unknown", CB_UNKNOWN}, 194 }; 195 196 /************************************************************************/ 197 /* Probe/Attach */ 198 /************************************************************************/ 199 200 static int 201 cbb_chipset(uint32_t pci_id, const char **namep) 202 { 203 struct yenta_chipinfo *ycp; 204 205 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 206 continue; 207 if (namep != NULL) 208 *namep = ycp->yc_name; 209 return (ycp->yc_chiptype); 210 } 211 212 static int 213 cbb_pci_probe(device_t brdev) 214 { 215 const char *name; 216 uint32_t progif; 217 uint32_t subclass; 218 219 /* 220 * Do we know that we support the chipset? If so, then we 221 * accept the device. 222 */ 223 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 224 device_set_desc(brdev, name); 225 return (0); 226 } 227 228 /* 229 * We do support generic CardBus bridges. All that we've seen 230 * to date have progif 0 (the Yenta spec, and successors mandate 231 * this). We do not support PCI PCMCIA bridges (with one exception) 232 * with this driver since they generally are I/O mapped. Those 233 * are supported by the pcic driver. This should help us be more 234 * future proof. 235 */ 236 subclass = pci_get_subclass(brdev); 237 progif = pci_get_progif(brdev); 238 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 239 device_set_desc(brdev, "PCI-CardBus Bridge"); 240 return (0); 241 } 242 return (ENXIO); 243 } 244 245 #ifndef BURN_BRIDGES 246 /* 247 * Still need this because the pci code only does power for type 0 248 * header devices. 249 */ 250 static void 251 cbb_powerstate_d0(device_t dev) 252 { 253 u_int32_t membase, irq; 254 255 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 256 /* Save important PCI config data. */ 257 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 258 irq = pci_read_config(dev, PCIR_INTLINE, 4); 259 260 /* Reset the power state. */ 261 device_printf(dev, "chip is in D%d power mode " 262 "-- setting to D0\n", pci_get_powerstate(dev)); 263 264 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 265 266 /* Restore PCI config data. */ 267 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 268 pci_write_config(dev, PCIR_INTLINE, irq, 4); 269 } 270 } 271 #endif 272 273 /* 274 * Print out the config space 275 */ 276 static void 277 cbb_print_config(device_t dev) 278 { 279 int i; 280 281 device_printf(dev, "PCI Configuration space:"); 282 for (i = 0; i < 256; i += 4) { 283 if (i % 16 == 0) 284 printf("\n 0x%02x: ", i); 285 printf("0x%08x ", pci_read_config(dev, i, 4)); 286 } 287 printf("\n"); 288 } 289 290 static int 291 cbb_pci_attach(device_t brdev) 292 { 293 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 294 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 295 int rid, bus, pribus; 296 device_t parent; 297 298 parent = device_get_parent(brdev); 299 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 300 cv_init(&sc->cv, "cbb cv"); 301 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 302 sc->dev = brdev; 303 sc->cbdev = NULL; 304 sc->exca[0].pccarddev = NULL; 305 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 306 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 307 SLIST_INIT(&sc->rl); 308 STAILQ_INIT(&sc->intr_handlers); 309 #ifndef BURN_BRIDGES 310 cbb_powerstate_d0(brdev); 311 #endif 312 313 rid = CBBR_SOCKBASE; 314 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 315 RF_ACTIVE); 316 if (!sc->base_res) { 317 device_printf(brdev, "Could not map register memory\n"); 318 mtx_destroy(&sc->mtx); 319 cv_destroy(&sc->cv); 320 return (ENOMEM); 321 } else { 322 DEVPRINTF((brdev, "Found memory at %08lx\n", 323 rman_get_start(sc->base_res))); 324 } 325 326 sc->bst = rman_get_bustag(sc->base_res); 327 sc->bsh = rman_get_bushandle(sc->base_res); 328 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 329 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 330 sc->exca[0].chipset = EXCA_CARDBUS; 331 sc->chipinit = cbb_chipinit; 332 sc->chipinit(sc); 333 334 /* 335 * This is a gross hack. We should be scanning the entire pci 336 * tree, assigning bus numbers in a way such that we (1) can 337 * reserve 1 extra bus just in case and (2) all sub busses 338 * are in an appropriate range. 339 */ 340 bus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 341 pribus = pcib_get_bus(parent); 342 DEVPRINTF((brdev, "Secondary bus is %d\n", bus)); 343 if (bus == 0) { 344 if (curr_bus_number <= pribus) 345 curr_bus_number = pribus + 1; 346 if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) { 347 DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus)); 348 pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1); 349 } 350 bus = curr_bus_number; 351 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus, 352 bus + 1)); 353 sc->secbus = bus; 354 sc->subbus = bus + 1; 355 pci_write_config(brdev, PCIR_SECBUS_2, bus, 1); 356 pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1); 357 curr_bus_number += 2; 358 } 359 360 /* attach children */ 361 sc->cbdev = device_add_child(brdev, "cardbus", -1); 362 if (sc->cbdev == NULL) 363 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 364 else if (device_probe_and_attach(sc->cbdev) != 0) 365 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 366 367 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 368 if (sc->exca[0].pccarddev == NULL) 369 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 370 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 371 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 372 373 /* Map and establish the interrupt. */ 374 rid = 0; 375 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 376 RF_SHAREABLE | RF_ACTIVE); 377 if (sc->irq_res == NULL) { 378 printf("cbb: Unable to map IRQ...\n"); 379 goto err; 380 } 381 382 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 383 cbb_intr, sc, &sc->intrhand)) { 384 device_printf(brdev, "couldn't establish interrupt"); 385 goto err; 386 } 387 388 /* reset 16-bit pcmcia bus */ 389 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 390 391 /* turn off power */ 392 cbb_power(brdev, CARD_OFF); 393 394 /* CSC Interrupt: Card detect interrupt on */ 395 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 396 397 /* reset interrupt */ 398 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 399 400 if (bootverbose) 401 cbb_print_config(brdev); 402 403 /* Start the thread */ 404 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 405 "%s", device_get_nameunit(brdev))) { 406 device_printf(brdev, "unable to create event thread.\n"); 407 panic("cbb_create_event_thread"); 408 } 409 return (0); 410 err: 411 if (sc->irq_res) 412 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 413 if (sc->base_res) { 414 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 415 sc->base_res); 416 } 417 mtx_destroy(&sc->mtx); 418 cv_destroy(&sc->cv); 419 return (ENOMEM); 420 } 421 422 static void 423 cbb_chipinit(struct cbb_softc *sc) 424 { 425 uint32_t mux, sysctrl, reg; 426 427 /* Set CardBus latency timer */ 428 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 429 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 430 431 /* Set PCI latency timer */ 432 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 433 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 434 435 /* Enable memory access */ 436 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 437 | PCIM_CMD_MEMEN 438 | PCIM_CMD_PORTEN 439 | PCIM_CMD_BUSMASTEREN, 2); 440 441 /* disable Legacy IO */ 442 switch (sc->chipset) { 443 case CB_RF5C46X: 444 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 445 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 446 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 447 break; 448 default: 449 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 450 break; 451 } 452 453 /* Use PCI interrupt for interrupt routing */ 454 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 455 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 456 CBBM_BRIDGECTRL_INTR_IREQ_EN), 457 | CBBM_BRIDGECTRL_WRITE_POST_EN, 458 2); 459 460 /* 461 * XXX this should be a function table, ala OLDCARD. This means 462 * that we could more easily support ISA interrupts for pccard 463 * cards if we had to. 464 */ 465 switch (sc->chipset) { 466 case CB_TI113X: 467 /* 468 * The TI 1031, TI 1130 and TI 1131 all require another bit 469 * be set to enable PCI routing of interrupts, and then 470 * a bit for each of the CSC and Function interrupts we 471 * want routed. 472 */ 473 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 474 | CBBM_CBCTRL_113X_PCI_INTR | 475 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 476 1); 477 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 478 & ~(CBBM_DEVCTRL_INT_SERIAL | 479 CBBM_DEVCTRL_INT_PCI), 1); 480 break; 481 case CB_TI12XX: 482 /* 483 * Some TI 12xx (and [14][45]xx) based pci cards 484 * sometimes have issues with the MFUNC register not 485 * being initialized due to a bad EEPROM on board. 486 * Laptops that this matters on have this register 487 * properly initialized. 488 * 489 * The TI125X parts have a different register. 490 */ 491 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 492 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 493 if (mux == 0) { 494 mux = (mux & ~CBBM_MFUNC_PIN0) | 495 CBBM_MFUNC_PIN0_INTA; 496 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 497 mux = (mux & ~CBBM_MFUNC_PIN1) | 498 CBBM_MFUNC_PIN1_INTB; 499 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 500 } 501 /*FALLTHROUGH*/ 502 case CB_TI125X: 503 /* 504 * Disable zoom video. Some machines initialize this 505 * improperly and exerpience has shown that this helps 506 * prevent strange behavior. 507 */ 508 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 509 break; 510 case CB_O2MICRO: 511 /* 512 * Issue #1: INT# generated at the same time as 513 * selected ISA IRQ. When IREQ# or STSCHG# is active, 514 * in addition to the ISA IRQ being generated, INT# 515 * will also be generated at the same time. 516 * 517 * Some of the older controllers have an issue in 518 * which the slot's PCI INT# will be asserted whenever 519 * IREQ# or STSCGH# is asserted even if ExCA registers 520 * 03h or 05h have an ISA IRQ selected. 521 * 522 * The fix for this issue, which will work for any 523 * controller (old or new), is to set ExCA registers 524 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 525 * These bits are undocumented. By setting this 526 * register (of each slot) to '1010xxxxb' a routing of 527 * IREQ# to INTC# and STSCHG# to INTC# is selected. 528 * Since INTC# isn't connected there will be no 529 * unexpected PCI INT when IREQ# or STSCHG# is active. 530 * However, INTA# (slot 0) or INTB# (slot 1) will 531 * still be correctly generated if NO ISA IRQ is 532 * selected (ExCA regs 03h or 05h are cleared). 533 */ 534 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 535 reg = (reg & 0x0f) | 536 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 537 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 538 539 break; 540 case CB_TOPIC97: 541 /* 542 * Disable Zoom Video, ToPIC 97, 100. 543 */ 544 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 545 /* 546 * ToPIC 97, 100 547 * At offset 0xa1: INTERRUPT CONTROL register 548 * 0x1: Turn on INT interrupts. 549 */ 550 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 551 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 552 goto topic_common; 553 case CB_TOPIC95: 554 /* 555 * SOCKETCTRL appears to be TOPIC 95/B specific 556 */ 557 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 558 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 559 560 topic_common:; 561 /* 562 * At offset 0xa0: SLOT CONTROL 563 * 0x80 Enable CardBus Functionality 564 * 0x40 Enable CardBus and PC Card registers 565 * 0x20 Lock ID in exca regs 566 * 0x10 Write protect ID in config regs 567 * Clear the rest of the bits, which defaults the slot 568 * in legacy mode to 0x3e0 and offset 0. (legacy 569 * mode is determined elsewhere) 570 */ 571 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 572 CBBM_TOPIC_SLOTCTRL_SLOTON | 573 CBBM_TOPIC_SLOTCTRL_SLOTEN | 574 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 575 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 576 577 /* 578 * At offset 0xa3 Card Detect Control Register 579 * 0x80 CARDBUS enbale 580 * 0x01 Cleared for hardware change detect 581 */ 582 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 583 | CBBM_TOPIC_CDC_CARDBUS, 584 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 585 break; 586 } 587 588 /* 589 * Need to tell ExCA registers to CSC interrupts route via PCI 590 * interrupts. There are two ways to do this. Once is to set 591 * INTR_ENABLE and the other is to set CSC to 0. Since both 592 * methods are mutually compatible, we do both. 593 */ 594 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 595 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 596 597 cbb_disable_func_intr(sc); 598 599 /* close all memory and io windows */ 600 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 601 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 602 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 603 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 604 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 605 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 606 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 607 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 608 } 609 610 static device_method_t cbb_methods[] = { 611 /* Device interface */ 612 DEVMETHOD(device_probe, cbb_pci_probe), 613 DEVMETHOD(device_attach, cbb_pci_attach), 614 DEVMETHOD(device_detach, cbb_detach), 615 DEVMETHOD(device_shutdown, cbb_shutdown), 616 DEVMETHOD(device_suspend, cbb_suspend), 617 DEVMETHOD(device_resume, cbb_resume), 618 619 /* bus methods */ 620 DEVMETHOD(bus_print_child, bus_generic_print_child), 621 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 622 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 623 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 624 DEVMETHOD(bus_release_resource, cbb_release_resource), 625 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 626 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 627 DEVMETHOD(bus_driver_added, cbb_driver_added), 628 DEVMETHOD(bus_child_detached, cbb_child_detached), 629 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 630 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 631 DEVMETHOD(bus_child_present, cbb_child_present), 632 633 /* 16-bit card interface */ 634 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 635 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 636 637 /* power interface */ 638 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 639 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 640 641 /* pcib compatibility interface */ 642 DEVMETHOD(pcib_maxslots, cbb_maxslots), 643 DEVMETHOD(pcib_read_config, cbb_read_config), 644 DEVMETHOD(pcib_write_config, cbb_write_config), 645 {0,0} 646 }; 647 648 static driver_t cbb_driver = { 649 "cbb", 650 cbb_methods, 651 sizeof(struct cbb_softc) 652 }; 653 654 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 655 MODULE_DEPEND(cbb, exca, 1, 1, 1); 656