1 /* 2 * Copyright (c) 2002 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for PCI to CardBus Bridge chips 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 93 #include <pci/pcireg.h> 94 #include <pci/pcivar.h> 95 #include <machine/clock.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 #define CBB_START_MEM 0x88000000 120 #define CBB_START_32_IO 0x1000 121 #define CBB_START_16_IO 0x100 122 123 struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 155 /* Ricoh chips */ 156 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 157 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 158 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 159 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 160 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 161 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 162 163 /* Toshiba products */ 164 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 165 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 166 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 167 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 168 169 /* Cirrus Logic */ 170 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 171 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 172 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 173 174 /* 02Micro */ 175 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_CIRRUS}, 176 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_CIRRUS}, 177 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_CIRRUS}, 178 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_CIRRUS}, 179 {PCIC_ID_OZ6922, "O2Micro OZ6822 PCI-CardBus Bridge", CB_CIRRUS}, 180 {PCIC_ID_OZ6933, "O2Micro OZ6833 PCI-CardBus Bridge", CB_CIRRUS}, 181 182 /* sentinel */ 183 {0 /* null id */, "unknown", CB_UNKNOWN}, 184 }; 185 186 /* sysctl vars */ 187 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 188 189 /* There's no way to say TUNEABLE_LONG to get the right types */ 190 u_long cbb_start_mem = CBB_START_MEM; 191 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 192 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 193 &cbb_start_mem, CBB_START_MEM, 194 "Starting address for memory allocations"); 195 196 u_long cbb_start_16_io = CBB_START_16_IO; 197 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 198 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 199 &cbb_start_16_io, CBB_START_16_IO, 200 "Starting ioport for 16-bit cards"); 201 202 u_long cbb_start_32_io = CBB_START_32_IO; 203 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 205 &cbb_start_32_io, CBB_START_32_IO, 206 "Starting ioport for 32-bit cards"); 207 208 int cbb_debug = 0; 209 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 211 "Verbose cardbus bridge debugging"); 212 213 static int cbb_chipset(uint32_t pci_id, const char **namep); 214 static int cbb_probe(device_t brdev); 215 static void cbb_chipinit(struct cbb_softc *sc); 216 static int cbb_attach(device_t brdev); 217 static int cbb_detach(device_t brdev); 218 static int cbb_shutdown(device_t brdev); 219 static void cbb_driver_added(device_t brdev, driver_t *driver); 220 static void cbb_child_detached(device_t brdev, device_t child); 221 static void cbb_event_thread(void *arg); 222 static void cbb_insert(struct cbb_softc *sc); 223 static void cbb_removal(struct cbb_softc *sc); 224 static void cbb_intr(void *arg); 225 static int cbb_detect_voltage(device_t brdev); 226 static int cbb_power(device_t brdev, int volts); 227 static void cbb_cardbus_reset(device_t brdev); 228 static int cbb_cardbus_power_enable_socket(device_t brdev, 229 device_t child); 230 static void cbb_cardbus_power_disable_socket(device_t brdev, 231 device_t child); 232 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 233 uint32_t end); 234 static int cbb_cardbus_mem_open(device_t brdev, int win, 235 uint32_t start, uint32_t end); 236 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 237 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 238 int type, int rid, struct resource *res); 239 static int cbb_cardbus_deactivate_resource(device_t brdev, 240 device_t child, int type, int rid, struct resource *res); 241 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 242 device_t child, int type, int *rid, u_long start, 243 u_long end, u_long count, uint flags); 244 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 245 int type, int rid, struct resource *res); 246 static int cbb_power_enable_socket(device_t brdev, device_t child); 247 static void cbb_power_disable_socket(device_t brdev, device_t child); 248 static int cbb_activate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *r); 250 static int cbb_deactivate_resource(device_t brdev, device_t child, 251 int type, int rid, struct resource *r); 252 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 253 int type, int *rid, u_long start, u_long end, u_long count, 254 uint flags); 255 static int cbb_release_resource(device_t brdev, device_t child, 256 int type, int rid, struct resource *r); 257 static int cbb_read_ivar(device_t brdev, device_t child, int which, 258 uintptr_t *result); 259 static int cbb_write_ivar(device_t brdev, device_t child, int which, 260 uintptr_t value); 261 static int cbb_maxslots(device_t brdev); 262 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 263 int reg, int width); 264 static void cbb_write_config(device_t brdev, int b, int s, int f, 265 int reg, uint32_t val, int width); 266 267 /* 268 */ 269 static __inline void 270 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 271 { 272 bus_space_write_4(sc->bst, sc->bsh, reg, val); 273 } 274 275 static __inline uint32_t 276 cbb_get(struct cbb_softc *sc, uint32_t reg) 277 { 278 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 279 } 280 281 static __inline void 282 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 283 { 284 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 285 } 286 287 static __inline void 288 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 289 { 290 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 291 } 292 293 static void 294 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 295 { 296 struct cbb_reslist *rle; 297 298 SLIST_FOREACH(rle, &sc->rl, link) { 299 if (rle->res == res) { 300 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 301 free(rle, M_DEVBUF); 302 return; 303 } 304 } 305 } 306 307 static struct resource * 308 cbb_find_res(struct cbb_softc *sc, int type, int rid) 309 { 310 struct cbb_reslist *rle; 311 312 SLIST_FOREACH(rle, &sc->rl, link) 313 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 314 return (rle->res); 315 return (NULL); 316 } 317 318 static void 319 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 320 int rid) 321 { 322 struct cbb_reslist *rle; 323 324 /* 325 * Need to record allocated resource so we can iterate through 326 * it later. 327 */ 328 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 329 if (!res) 330 panic("cbb_cardbus_alloc_resource: can't record entry!"); 331 rle->res = res; 332 rle->type = type; 333 rle->rid = rid; 334 SLIST_INSERT_HEAD(&sc->rl, rle, link); 335 } 336 337 static void 338 cbb_destroy_res(struct cbb_softc *sc) 339 { 340 struct cbb_reslist *rle; 341 342 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 343 device_printf(sc->dev, "Danger Will Robinson: Resource " 344 "left allocated! This is a bug... " 345 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 346 rman_get_start(rle->res)); 347 SLIST_REMOVE_HEAD(&sc->rl, link); 348 free(rle, M_DEVBUF); 349 } 350 } 351 352 /************************************************************************/ 353 /* Probe/Attach */ 354 /************************************************************************/ 355 356 static int 357 cbb_chipset(uint32_t pci_id, const char **namep) 358 { 359 struct yenta_chipinfo *ycp; 360 361 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 362 continue; 363 if (namep != NULL) 364 *namep = ycp->yc_name; 365 return (ycp->yc_chiptype); 366 } 367 368 static int 369 cbb_probe(device_t brdev) 370 { 371 const char *name; 372 uint32_t progif; 373 uint32_t subclass; 374 375 /* 376 * Do we know that we support the chipset? If so, then we 377 * accept the device. 378 */ 379 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 380 device_set_desc(brdev, name); 381 return (0); 382 } 383 384 /* 385 * We do support generic CardBus bridges. All that we've seen 386 * to date have progif 0 (the Yenta spec, and successors mandate 387 * this). We do not support PCI PCMCIA bridges (with one exception) 388 * with this driver since they generally are I/O mapped. Those 389 * are supported by the pcic driver. This should help us be more 390 * future proof. 391 */ 392 subclass = pci_get_subclass(brdev); 393 progif = pci_get_progif(brdev); 394 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 395 device_set_desc(brdev, "PCI-CardBus Bridge"); 396 return (0); 397 } 398 return (ENXIO); 399 } 400 401 402 static void 403 cbb_chipinit(struct cbb_softc *sc) 404 { 405 uint32_t mux, sysctrl; 406 407 /* Set CardBus latency timer */ 408 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 409 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 410 411 /* Set PCI latency timer */ 412 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 413 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 414 415 /* Enable memory access */ 416 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 417 | PCIM_CMD_MEMEN 418 | PCIM_CMD_PORTEN 419 | PCIM_CMD_BUSMASTEREN, 2); 420 421 /* disable Legacy IO */ 422 switch (sc->chipset) { 423 case CB_RF5C46X: 424 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 425 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 426 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 427 break; 428 default: 429 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 430 break; 431 } 432 433 /* Use PCI interrupt for interrupt routing */ 434 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 435 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 436 CBBM_BRIDGECTRL_INTR_IREQ_EN), 437 | CBBM_BRIDGECTRL_WRITE_POST_EN, 438 2); 439 440 /* 441 * XXX this should be a function table, ala OLDCARD. This means 442 * that we could more easily support ISA interrupts for pccard 443 * cards if we had to. 444 */ 445 switch (sc->chipset) { 446 case CB_TI113X: 447 /* 448 * The TI 1031, TI 1130 and TI 1131 all require another bit 449 * be set to enable PCI routing of interrupts, and then 450 * a bit for each of the CSC and Function interrupts we 451 * want routed. 452 */ 453 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 454 | CBBM_CBCTRL_113X_PCI_INTR | 455 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 456 1); 457 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 458 & ~(CBBM_DEVCTRL_INT_SERIAL | 459 CBBM_DEVCTRL_INT_PCI), 1); 460 break; 461 case CB_TI12XX: 462 /* 463 * Some TI 12xx (and [14][45]xx) based pci cards 464 * sometimes have issues with the MFUNC register not 465 * being initialized due to a bad EEPROM on board. 466 * Laptops that this matters on have this register 467 * properly initialized. 468 * 469 * The TI125X parts have a different register. 470 */ 471 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 472 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 473 if (mux == 0) { 474 mux = (mux & ~CBBM_MFUNC_PIN0) | 475 CBBM_MFUNC_PIN0_INTA; 476 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 477 mux = (mux & ~CBBM_MFUNC_PIN1) | 478 CBBM_MFUNC_PIN1_INTB; 479 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 480 } 481 /*FALLTHROUGH*/ 482 case CB_TI125X: 483 /* 484 * Disable zoom video. Some machines initialize this 485 * improperly and exerpience has shown that this helps 486 * on some machines. 487 */ 488 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 489 break; 490 case CB_TOPIC97: 491 /* 492 * Disable Zoom Video, ToPIC 97, 100. 493 */ 494 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 495 /* 496 * ToPIC 97, 100 497 * At offset 0xa1: INTERRUPT CONTROL register 498 * 0x1: Turn on INT interrupts. 499 */ 500 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 501 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 502 goto topic_common; 503 case CB_TOPIC95: 504 /* 505 * SOCKETCTRL appears to be TOPIC 95/B specific 506 */ 507 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 508 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 509 510 topic_common:; 511 /* 512 * At offset 0xa0: SLOT CONTROL 513 * 0x80 Enable CardBus Functionality 514 * 0x40 Enable CardBus and PC Card registers 515 * 0x20 Lock ID in exca regs 516 * 0x10 Write protect ID in config regs 517 * Clear the rest of the bits, which defaults the slot 518 * in legacy mode to 0x3e0 and offset 0. (legacy 519 * mode is determined elsewhere) 520 */ 521 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 522 CBBM_TOPIC_SLOTCTRL_SLOTON | 523 CBBM_TOPIC_SLOTCTRL_SLOTEN | 524 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 525 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 526 527 /* 528 * At offset 0xa3 Card Detect Control Register 529 * 0x80 CARDBUS enbale 530 * 0x01 Cleared for hardware change detect 531 */ 532 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 533 | CBBM_TOPIC_CDC_CARDBUS, 534 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 535 break; 536 } 537 538 /* 539 * Need to tell ExCA registers to route via PCI interrupts. There 540 * are two ways to do this. Once is to set INTR_ENABLE and the 541 * other is to set CSC to 0. Since both methods are mutually 542 * compatible, we do both. 543 */ 544 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 545 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 546 547 /* close all memory and io windows */ 548 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 549 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 550 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 551 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 552 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 553 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 554 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 555 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 556 } 557 558 static int 559 cbb_attach(device_t brdev) 560 { 561 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 562 int rid; 563 564 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 565 cv_init(&sc->cv, "cbb cv"); 566 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 567 sc->dev = brdev; 568 sc->cbdev = NULL; 569 sc->pccarddev = NULL; 570 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 571 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 572 SLIST_INIT(&sc->rl); 573 STAILQ_INIT(&sc->intr_handlers); 574 575 #ifndef BURN_THE_BOATS 576 /* 577 * The PCI bus code should assign us memory in the absense 578 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 579 * up something here until the PCI/acpi code properly assigns the 580 * resource. 581 */ 582 #endif 583 rid = CBBR_SOCKBASE; 584 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 585 0, ~0, 1, RF_ACTIVE); 586 if (!sc->base_res) { 587 #ifdef BURN_THE_BOATS 588 device_printf(brdev, "Could not map register memory\n"); 589 mtx_destroy(&sc->mtx); 590 cv_destroy(&sc->cv); 591 return (ENOMEM); 592 #else 593 uint32_t sockbase; 594 /* 595 * Generally, the BIOS will assign this memory for us. 596 * However, newer BIOSes do not because the MS design 597 * documents have mandated that this is for the OS 598 * to assign rather than the BIOS. This driver shouldn't 599 * be doing this, but until the pci bus code (or acpi) 600 * does this, we allow CardBus bridges to work on more 601 * machines. 602 */ 603 sockbase = pci_read_config(brdev, rid, 4); 604 if (sockbase < 0x100000 || sockbase >= 0xfffffff0) { 605 pci_write_config(brdev, rid, 0xffffffff, 4); 606 sockbase = pci_read_config(brdev, rid, 4); 607 sockbase = (sockbase & 0xfffffff0) & 608 -(sockbase & 0xfffffff0); 609 sc->base_res = bus_generic_alloc_resource( 610 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 611 &rid, cbb_start_mem, ~0, sockbase, 612 RF_ACTIVE|rman_make_alignment_flags(sockbase)); 613 if (!sc->base_res) { 614 device_printf(brdev, 615 "Could not grab register memory\n"); 616 mtx_destroy(&sc->mtx); 617 cv_destroy(&sc->cv); 618 return (ENOMEM); 619 } 620 sc->flags |= CBB_KLUDGE_ALLOC; 621 pci_write_config(brdev, CBBR_SOCKBASE, 622 rman_get_start(sc->base_res), 4); 623 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 624 rman_get_start(sc->base_res))); 625 } else { 626 device_printf(brdev, "Could not map register memory\n"); 627 goto err; 628 } 629 #endif 630 } 631 632 sc->bst = rman_get_bustag(sc->base_res); 633 sc->bsh = rman_get_bushandle(sc->base_res); 634 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 635 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 636 sc->exca.chipset = EXCA_CARDBUS; 637 cbb_chipinit(sc); 638 639 /* attach children */ 640 sc->cbdev = device_add_child(brdev, "cardbus", -1); 641 if (sc->cbdev == NULL) 642 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 643 else if (device_probe_and_attach(sc->cbdev) != 0) { 644 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 645 sc->cbdev = NULL; 646 } 647 648 sc->pccarddev = device_add_child(brdev, "pccard", -1); 649 if (sc->pccarddev == NULL) 650 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 651 else if (device_probe_and_attach(sc->pccarddev) != 0) { 652 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 653 sc->pccarddev = NULL; 654 } 655 656 /* Map and establish the interrupt. */ 657 rid = 0; 658 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 659 RF_SHAREABLE | RF_ACTIVE); 660 if (sc->irq_res == NULL) { 661 printf("cbb: Unable to map IRQ...\n"); 662 goto err; 663 return (ENOMEM); 664 } 665 666 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 667 &sc->intrhand)) { 668 device_printf(brdev, "couldn't establish interrupt"); 669 goto err; 670 } 671 672 /* reset 16-bit pcmcia bus */ 673 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 674 675 /* turn off power */ 676 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 677 678 /* CSC Interrupt: Card detect interrupt on */ 679 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 680 681 /* reset interrupt */ 682 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 683 684 /* Start the thread */ 685 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 686 "%s%d", device_get_name(sc->dev), device_get_unit(sc->dev))) { 687 device_printf (sc->dev, "unable to create event thread.\n"); 688 panic ("cbb_create_event_thread"); 689 } 690 691 return (0); 692 err: 693 if (sc->irq_res) 694 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 695 if (sc->base_res) { 696 if (sc->flags & CBB_KLUDGE_ALLOC) 697 bus_generic_release_resource(device_get_parent(brdev), 698 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 699 sc->base_res); 700 else 701 bus_release_resource(brdev, SYS_RES_MEMORY, 702 CBBR_SOCKBASE, sc->base_res); 703 } 704 mtx_destroy(&sc->mtx); 705 cv_destroy(&sc->cv); 706 return (ENOMEM); 707 } 708 709 static int 710 cbb_detach(device_t brdev) 711 { 712 struct cbb_softc *sc = device_get_softc(brdev); 713 int numdevs; 714 device_t *devlist; 715 int tmp; 716 int error; 717 718 device_get_children(brdev, &devlist, &numdevs); 719 720 error = 0; 721 for (tmp = 0; tmp < numdevs; tmp++) { 722 if (device_detach(devlist[tmp]) == 0) 723 device_delete_child(brdev, devlist[tmp]); 724 else 725 error++; 726 } 727 free(devlist, M_TEMP); 728 if (error > 0) 729 return (ENXIO); 730 731 mtx_lock(&sc->mtx); 732 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 733 sc->flags |= CBB_KTHREAD_DONE; 734 if (sc->flags & CBB_KTHREAD_RUNNING) { 735 cv_broadcast(&sc->cv); 736 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 737 } 738 mtx_unlock(&sc->mtx); 739 740 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 741 if (sc->flags & CBB_KLUDGE_ALLOC) 742 bus_generic_release_resource(device_get_parent(brdev), 743 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 744 sc->base_res); 745 else 746 bus_release_resource(brdev, SYS_RES_MEMORY, 747 CBBR_SOCKBASE, sc->base_res); 748 mtx_destroy(&sc->mtx); 749 cv_destroy(&sc->cv); 750 return (0); 751 } 752 753 static int 754 cbb_shutdown(device_t brdev) 755 { 756 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 757 /* properly reset everything at shutdown */ 758 759 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 760 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 761 762 cbb_set(sc, CBB_SOCKET_MASK, 0); 763 764 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 765 766 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 767 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 768 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 769 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 770 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 771 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 772 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 773 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 774 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 775 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 776 return (0); 777 } 778 779 static int 780 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 781 int flags, driver_intr_t *intr, void *arg, void **cookiep) 782 { 783 struct cbb_intrhand *ih; 784 struct cbb_softc *sc = device_get_softc(dev); 785 786 /* 787 * You aren't allowed to have fast interrupts for pccard/cardbus 788 * things since those interrupts are PCI and shared. Since we use 789 * the PCI interrupt for the status change interrupts, it can't be 790 * free for use by the driver. Fast interrupts must not be shared. 791 */ 792 if ((flags & INTR_FAST) != 0) 793 return (EINVAL); 794 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 795 if (ih == NULL) 796 return (ENOMEM); 797 *cookiep = ih; 798 ih->intr = intr; 799 ih->arg = arg; 800 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 801 /* 802 * XXX need to turn on ISA interrupts, if we ever support them, but 803 * XXX for now that's all we need to do. 804 */ 805 return (0); 806 } 807 808 static int 809 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 810 void *cookie) 811 { 812 struct cbb_intrhand *ih; 813 struct cbb_softc *sc = device_get_softc(dev); 814 815 /* XXX Need to do different things for ISA interrupts. */ 816 ih = (struct cbb_intrhand *) cookie; 817 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 818 free(ih, M_DEVBUF); 819 return (0); 820 } 821 822 823 static void 824 cbb_driver_added(device_t brdev, driver_t *driver) 825 { 826 struct cbb_softc *sc = device_get_softc(brdev); 827 device_t *devlist; 828 int tmp; 829 int numdevs; 830 int wake; 831 uint32_t sockstate; 832 833 DEVICE_IDENTIFY(driver, brdev); 834 device_get_children(brdev, &devlist, &numdevs); 835 wake = 0; 836 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 837 for (tmp = 0; tmp < numdevs; tmp++) { 838 if (device_get_state(devlist[tmp]) == DS_NOTPRESENT && 839 device_probe_and_attach(devlist[tmp]) == 0) { 840 if (devlist[tmp] == NULL) 841 /* NOTHING */; 842 else if (strcmp(driver->name, "cardbus") == 0) { 843 sc->cbdev = devlist[tmp]; 844 if (((sockstate & CBB_SOCKET_STAT_CD) == 0) && 845 (sockstate & CBB_SOCKET_STAT_CB)) 846 wake++; 847 } else if (strcmp(driver->name, "pccard") == 0) { 848 sc->pccarddev = devlist[tmp]; 849 if (((sockstate & CBB_SOCKET_STAT_CD) == 0) && 850 (sockstate & CBB_SOCKET_STAT_16BIT)) 851 wake++; 852 } else 853 device_printf(brdev, 854 "Unsupported child bus: %s\n", 855 driver->name); 856 } 857 } 858 free(devlist, M_TEMP); 859 860 if (wake > 0) { 861 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) 862 == 0) { 863 mtx_lock(&sc->mtx); 864 wakeup(sc); 865 mtx_unlock(&sc->mtx); 866 } 867 } 868 } 869 870 static void 871 cbb_child_detached(device_t brdev, device_t child) 872 { 873 struct cbb_softc *sc = device_get_softc(brdev); 874 875 if (child == sc->cbdev) 876 sc->cbdev = NULL; 877 else if (child == sc->pccarddev) 878 sc->pccarddev = NULL; 879 else 880 device_printf(brdev, "Unknown child detached: %s %p/%p\n", 881 device_get_nameunit(child), sc->cbdev, sc->pccarddev); 882 } 883 884 /************************************************************************/ 885 /* Kthreads */ 886 /************************************************************************/ 887 888 static void 889 cbb_event_thread(void *arg) 890 { 891 struct cbb_softc *sc = arg; 892 uint32_t status; 893 int err; 894 895 /* 896 * We take out Giant here because we need it deep, down in 897 * the bowels of the vm system for mapping the memory we need 898 * to read the CIS. We also need it for kthread_exit, which 899 * drops it. 900 */ 901 sc->flags |= CBB_KTHREAD_RUNNING; 902 while (1) { 903 /* 904 * Check to see if we have anything first so that 905 * if there's a card already inserted, we do the 906 * right thing. 907 */ 908 if (sc->flags & CBB_KTHREAD_DONE) 909 break; 910 911 status = cbb_get(sc, CBB_SOCKET_STATE); 912 mtx_lock(&Giant); 913 if ((status & CBB_SOCKET_STAT_CD) == 0) 914 cbb_insert(sc); 915 else 916 cbb_removal(sc); 917 mtx_unlock(&Giant); 918 919 /* 920 * Wait until it has been 1s since the last time we 921 * get an interrupt. We handle the rest of the interrupt 922 * at the top of the loop. 923 */ 924 mtx_lock(&sc->mtx); 925 cv_wait(&sc->cv, &sc->mtx); 926 err = 0; 927 while (err != EWOULDBLOCK && 928 (sc->flags & CBB_KTHREAD_DONE) == 0) 929 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 930 mtx_unlock(&sc->mtx); 931 } 932 sc->flags &= ~CBB_KTHREAD_RUNNING; 933 mtx_lock(&Giant); 934 kthread_exit(0); 935 } 936 937 /************************************************************************/ 938 /* Insert/removal */ 939 /************************************************************************/ 940 941 static void 942 cbb_insert(struct cbb_softc *sc) 943 { 944 uint32_t sockevent, sockstate; 945 946 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 947 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 948 949 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 950 sockevent, sockstate)); 951 952 if (sockstate & CBB_SOCKET_STAT_16BIT) { 953 if (sc->pccarddev != NULL) { 954 sc->flags |= CBB_16BIT_CARD; 955 sc->flags |= CBB_CARD_OK; 956 if (CARD_ATTACH_CARD(sc->pccarddev) != 0) 957 device_printf(sc->dev, 958 "PC Card card activation failed\n"); 959 } else { 960 device_printf(sc->dev, 961 "PC Card inserted, but no pccard bus.\n"); 962 } 963 } else if (sockstate & CBB_SOCKET_STAT_CB) { 964 if (sc->cbdev != NULL) { 965 sc->flags &= ~CBB_16BIT_CARD; 966 sc->flags |= CBB_CARD_OK; 967 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 968 device_printf(sc->dev, 969 "CardBus card activation failed\n"); 970 } else { 971 device_printf(sc->dev, 972 "CardBus card inserted, but no cardbus bus.\n"); 973 } 974 } else { 975 /* 976 * We should power the card down, and try again a couple of 977 * times if this happens. XXX 978 */ 979 device_printf(sc->dev, "Unsupported card type detected\n"); 980 } 981 } 982 983 static void 984 cbb_removal(struct cbb_softc *sc) 985 { 986 if (sc->flags & CBB_16BIT_CARD) { 987 if (sc->pccarddev != NULL) 988 CARD_DETACH_CARD(sc->pccarddev); 989 } else { 990 if (sc->cbdev != NULL) 991 CARD_DETACH_CARD(sc->cbdev); 992 } 993 cbb_destroy_res(sc); 994 } 995 996 /************************************************************************/ 997 /* Interrupt Handler */ 998 /************************************************************************/ 999 1000 static void 1001 cbb_intr(void *arg) 1002 { 1003 struct cbb_softc *sc = arg; 1004 uint32_t sockevent; 1005 struct cbb_intrhand *ih; 1006 1007 /* 1008 * This ISR needs work XXX 1009 */ 1010 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1011 if (sockevent) { 1012 /* ack the interrupt */ 1013 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1014 1015 /* 1016 * If anything has happened to the socket, we assume that 1017 * the card is no longer OK, and we shouldn't call its 1018 * ISR. We set CARD_OK as soon as we've attached the 1019 * card. This helps in a noisy eject, which happens 1020 * all too often when users are ejecting their PC Cards. 1021 * 1022 * We use this method in preference to checking to see if 1023 * the card is still there because the check suffers from 1024 * a race condition in the bouncing case. Prior versions 1025 * of the pccard software used a similar trick and achieved 1026 * excellent results. 1027 */ 1028 if (sockevent & CBB_SOCKET_EVENT_CD) { 1029 mtx_lock(&sc->mtx); 1030 sc->flags &= ~CBB_CARD_OK; 1031 cv_signal(&sc->cv); 1032 mtx_unlock(&sc->mtx); 1033 } 1034 if (sockevent & CBB_SOCKET_EVENT_CSTS) { 1035 DPRINTF((" cstsevent occured: 0x%08x\n", 1036 cbb_get(sc, CBB_SOCKET_STATE))); 1037 } 1038 if (sockevent & CBB_SOCKET_EVENT_POWER) { 1039 DPRINTF((" pwrevent occured: 0x%08x\n", 1040 cbb_get(sc, CBB_SOCKET_STATE))); 1041 } 1042 /* Other bits? */ 1043 } 1044 if (sc->flags & CBB_CARD_OK) { 1045 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1046 (*ih->intr)(ih->arg); 1047 } 1048 } 1049 } 1050 1051 /************************************************************************/ 1052 /* Generic Power functions */ 1053 /************************************************************************/ 1054 1055 static int 1056 cbb_detect_voltage(device_t brdev) 1057 { 1058 struct cbb_softc *sc = device_get_softc(brdev); 1059 uint32_t psr; 1060 int vol = CARD_UKN_CARD; 1061 1062 psr = cbb_get(sc, CBB_SOCKET_STATE); 1063 1064 if (psr & CBB_SOCKET_STAT_5VCARD) 1065 vol |= CARD_5V_CARD; 1066 if (psr & CBB_SOCKET_STAT_3VCARD) 1067 vol |= CARD_3V_CARD; 1068 if (psr & CBB_SOCKET_STAT_XVCARD) 1069 vol |= CARD_XV_CARD; 1070 if (psr & CBB_SOCKET_STAT_YVCARD) 1071 vol |= CARD_YV_CARD; 1072 1073 return (vol); 1074 } 1075 1076 static int 1077 cbb_power(device_t brdev, int volts) 1078 { 1079 uint32_t status, sock_ctrl; 1080 struct cbb_softc *sc = device_get_softc(brdev); 1081 int timeout; 1082 uint32_t sockevent; 1083 1084 DEVPRINTF((sc->dev, "cbb_power: %s and %s [%x]\n", 1085 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 1086 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 1087 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 1088 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 1089 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 1090 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 1091 "VCC-UNKNOWN", 1092 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 1093 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V" : 1094 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC" : 1095 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1096 "VPP-UNKNOWN", 1097 volts)); 1098 1099 status = cbb_get(sc, CBB_SOCKET_STATE); 1100 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1101 1102 switch (volts & CARD_VCCMASK) { 1103 case CARD_VCC_UC: 1104 break; 1105 case CARD_VCC_5V: 1106 if (CBB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1107 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1108 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1109 } else { 1110 device_printf(sc->dev, 1111 "BAD voltage request: no 5 V card\n"); 1112 } 1113 break; 1114 case CARD_VCC_3V: 1115 if (CBB_SOCKET_STAT_3VCARD & status) { 1116 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1117 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1118 } else { 1119 device_printf(sc->dev, 1120 "BAD voltage request: no 3.3 V card\n"); 1121 } 1122 break; 1123 case CARD_VCC_0V: 1124 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1125 break; 1126 default: 1127 return (0); /* power NEVER changed */ 1128 break; 1129 } 1130 1131 switch (volts & CARD_VPPMASK) { 1132 case CARD_VPP_UC: 1133 break; 1134 case CARD_VPP_0V: 1135 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1136 break; 1137 case CARD_VPP_VCC: 1138 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1139 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1140 break; 1141 case CARD_VPP_12V: 1142 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1143 sock_ctrl |= CBB_SOCKET_CTRL_VPP_12V; 1144 break; 1145 } 1146 1147 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1148 return (1); /* no change necessary */ 1149 1150 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1151 status = cbb_get(sc, CBB_SOCKET_STATE); 1152 1153 /* 1154 * XXX This busy wait is bogus. We should wait for a power 1155 * interrupt and then whine if the status is bad. If we're 1156 * worried about the card not coming up, then we should also 1157 * schedule a timeout which we can cacel in the power interrupt. 1158 */ 1159 timeout = 20; 1160 do { 1161 DELAY(20*1000); 1162 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1163 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1164 /* reset event status */ 1165 /* XXX should only reset EVENT_POWER */ 1166 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1167 if (timeout < 0) { 1168 printf ("VCC supply failed.\n"); 1169 return (0); 1170 } 1171 1172 /* XXX 1173 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1174 * is 20 ms, some PC-Card bridge requires longer duration. 1175 * XXX Note: We should check the stutus AFTER the delay to give time 1176 * for things to stabilize. 1177 */ 1178 DELAY(400*1000); 1179 1180 if (status & CBB_SOCKET_STAT_BADVCC) { 1181 device_printf(sc->dev, 1182 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1183 sock_ctrl ,status); 1184 printf("cbb_power: %s and %s [%x]\n", 1185 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 1186 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 1187 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 1188 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 1189 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 1190 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 1191 "VCC-UNKNOWN", 1192 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 1193 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V": 1194 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC": 1195 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1196 "VPP-UNKNOWN", 1197 volts); 1198 return (0); 1199 } 1200 return (1); /* power changed correctly */ 1201 } 1202 1203 /* 1204 * detect the voltage for the card, and set it. Since the power 1205 * used is the square of the voltage, lower voltages is a big win 1206 * and what Windows does (and what Microsoft prefers). The MS paper 1207 * also talks about preferring the CIS entry as well. 1208 */ 1209 static int 1210 cbb_do_power(device_t brdev) 1211 { 1212 int voltage; 1213 1214 /* Prefer lowest voltage supported */ 1215 voltage = cbb_detect_voltage(brdev); 1216 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1217 if (voltage & CARD_YV_CARD) 1218 cbb_power(brdev, CARD_VCC_YV | CARD_VPP_VCC); 1219 else if (voltage & CARD_XV_CARD) 1220 cbb_power(brdev, CARD_VCC_XV | CARD_VPP_VCC); 1221 else if (voltage & CARD_3V_CARD) 1222 cbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1223 else if (voltage & CARD_5V_CARD) 1224 cbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1225 else { 1226 device_printf(brdev, "Unknown card voltage\n"); 1227 return (ENXIO); 1228 } 1229 return (0); 1230 } 1231 1232 /************************************************************************/ 1233 /* CardBus power functions */ 1234 /************************************************************************/ 1235 1236 static void 1237 cbb_cardbus_reset(device_t brdev) 1238 { 1239 struct cbb_softc *sc = device_get_softc(brdev); 1240 int delay_us; 1241 1242 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1243 1244 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1245 1246 DELAY(delay_us); 1247 1248 /* If a card exists, unreset it! */ 1249 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 0) { 1250 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1251 &~CBBM_BRIDGECTRL_RESET, 2); 1252 DELAY(delay_us); 1253 } 1254 } 1255 1256 static int 1257 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1258 { 1259 struct cbb_softc *sc = device_get_softc(brdev); 1260 int err; 1261 1262 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 1263 CBB_SOCKET_STAT_CD) 1264 return (ENODEV); 1265 1266 err = cbb_do_power(brdev); 1267 if (err) 1268 return (err); 1269 cbb_cardbus_reset(brdev); 1270 return (0); 1271 } 1272 1273 static void 1274 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1275 { 1276 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1277 cbb_cardbus_reset(brdev); 1278 } 1279 1280 /************************************************************************/ 1281 /* CardBus Resource */ 1282 /************************************************************************/ 1283 1284 static int 1285 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1286 { 1287 int basereg; 1288 int limitreg; 1289 1290 if ((win < 0) || (win > 1)) { 1291 DEVPRINTF((brdev, 1292 "cbb_cardbus_io_open: window out of range %d\n", win)); 1293 return (EINVAL); 1294 } 1295 1296 basereg = win * 8 + CBBR_IOBASE0; 1297 limitreg = win * 8 + CBBR_IOLIMIT0; 1298 1299 pci_write_config(brdev, basereg, start, 4); 1300 pci_write_config(brdev, limitreg, end, 4); 1301 return (0); 1302 } 1303 1304 static int 1305 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1306 { 1307 int basereg; 1308 int limitreg; 1309 1310 if ((win < 0) || (win > 1)) { 1311 DEVPRINTF((brdev, 1312 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1313 return (EINVAL); 1314 } 1315 1316 basereg = win*8 + CBBR_MEMBASE0; 1317 limitreg = win*8 + CBBR_MEMLIMIT0; 1318 1319 pci_write_config(brdev, basereg, start, 4); 1320 pci_write_config(brdev, limitreg, end, 4); 1321 return (0); 1322 } 1323 1324 /* 1325 * XXX The following function belongs in the pci bus layer. 1326 */ 1327 static void 1328 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1329 { 1330 uint32_t starts[2]; 1331 uint32_t ends[2]; 1332 struct cbb_reslist *rle; 1333 int align; 1334 int prefetchable[2]; 1335 uint32_t reg; 1336 1337 starts[0] = starts[1] = 0xffffffff; 1338 ends[0] = ends[1] = 0; 1339 1340 if (type == SYS_RES_MEMORY) 1341 align = CBB_MEMALIGN; 1342 else if (type == SYS_RES_IOPORT) 1343 align = CBB_IOALIGN; 1344 else 1345 align = 1; 1346 1347 SLIST_FOREACH(rle, &sc->rl, link) { 1348 if (rle->type != type) 1349 ; 1350 else if (rle->res == NULL) { 1351 device_printf(sc->dev, "WARNING: Resource not reserved? " 1352 "(type=%d, addr=%lx)\n", 1353 rle->type, rman_get_start(rle->res)); 1354 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1355 /* XXX */ 1356 } else if (starts[0] == 0xffffffff) { 1357 starts[0] = rman_get_start(rle->res); 1358 ends[0] = rman_get_end(rle->res); 1359 prefetchable[0] = 1360 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1361 } else if (rman_get_end(rle->res) > ends[0] && 1362 rman_get_start(rle->res) - ends[0] < 1363 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1364 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1365 ends[0] = rman_get_end(rle->res); 1366 } else if (rman_get_start(rle->res) < starts[0] && 1367 starts[0] - rman_get_end(rle->res) < 1368 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1369 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1370 starts[0] = rman_get_start(rle->res); 1371 } else if (starts[1] == 0xffffffff) { 1372 starts[1] = rman_get_start(rle->res); 1373 ends[1] = rman_get_end(rle->res); 1374 prefetchable[1] = 1375 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1376 } else if (rman_get_end(rle->res) > ends[1] && 1377 rman_get_start(rle->res) - ends[1] < 1378 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1379 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1380 ends[1] = rman_get_end(rle->res); 1381 } else if (rman_get_start(rle->res) < starts[1] && 1382 starts[1] - rman_get_end(rle->res) < 1383 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1384 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1385 starts[1] = rman_get_start(rle->res); 1386 } else { 1387 uint32_t diffs[2]; 1388 int win; 1389 1390 diffs[0] = diffs[1] = 0xffffffff; 1391 if (rman_get_start(rle->res) > ends[0]) 1392 diffs[0] = rman_get_start(rle->res) - ends[0]; 1393 else if (rman_get_end(rle->res) < starts[0]) 1394 diffs[0] = starts[0] - rman_get_end(rle->res); 1395 if (rman_get_start(rle->res) > ends[1]) 1396 diffs[1] = rman_get_start(rle->res) - ends[1]; 1397 else if (rman_get_end(rle->res) < starts[1]) 1398 diffs[1] = starts[1] - rman_get_end(rle->res); 1399 1400 win = (diffs[0] <= diffs[1])?0:1; 1401 if (rman_get_start(rle->res) > ends[win]) 1402 ends[win] = rman_get_end(rle->res); 1403 else if (rman_get_end(rle->res) < starts[win]) 1404 starts[win] = rman_get_start(rle->res); 1405 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1406 prefetchable[win] = 0; 1407 } 1408 1409 if (starts[0] != 0xffffffff) 1410 starts[0] -= starts[0] % align; 1411 if (starts[1] != 0xffffffff) 1412 starts[1] -= starts[1] % align; 1413 if (ends[0] % align != 0) 1414 ends[0] += align - ends[0]%align - 1; 1415 if (ends[1] % align != 0) 1416 ends[1] += align - ends[1]%align - 1; 1417 } 1418 1419 if (type == SYS_RES_MEMORY) { 1420 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1421 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1422 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1423 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1424 CBBM_BRIDGECTRL_PREFETCH_1); 1425 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1426 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1427 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1428 } else if (type == SYS_RES_IOPORT) { 1429 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1430 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1431 } 1432 } 1433 1434 static int 1435 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1436 int rid, struct resource *res) 1437 { 1438 int ret; 1439 1440 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1441 type, rid, res); 1442 if (ret != 0) 1443 return (ret); 1444 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1445 return (0); 1446 } 1447 1448 static int 1449 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1450 int rid, struct resource *res) 1451 { 1452 int ret; 1453 1454 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1455 type, rid, res); 1456 if (ret != 0) 1457 return (ret); 1458 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1459 return (0); 1460 } 1461 1462 static struct resource * 1463 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1464 int *rid, u_long start, u_long end, u_long count, uint flags) 1465 { 1466 struct cbb_softc *sc = device_get_softc(brdev); 1467 int tmp; 1468 struct resource *res; 1469 1470 switch (type) { 1471 case SYS_RES_IRQ: 1472 tmp = rman_get_start(sc->irq_res); 1473 if (start > tmp || end < tmp || count != 1) { 1474 device_printf(child, "requested interrupt %ld-%ld," 1475 "count = %ld not supported by cbb\n", 1476 start, end, count); 1477 return (NULL); 1478 } 1479 start = end = tmp; 1480 break; 1481 case SYS_RES_IOPORT: 1482 if (start <= cbb_start_32_io) 1483 start = cbb_start_32_io; 1484 if (end < start) 1485 end = start; 1486 break; 1487 case SYS_RES_MEMORY: 1488 if (start <= cbb_start_mem) 1489 start = cbb_start_mem; 1490 if (end < start) 1491 end = start; 1492 break; 1493 } 1494 1495 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1496 start, end, count, flags & ~RF_ACTIVE); 1497 if (res == NULL) { 1498 printf("cbb alloc res fail\n"); 1499 return (NULL); 1500 } 1501 cbb_insert_res(sc, res, type, *rid); 1502 if (flags & RF_ACTIVE) 1503 if (bus_activate_resource(child, type, *rid, res) != 0) { 1504 bus_release_resource(child, type, *rid, res); 1505 return (NULL); 1506 } 1507 1508 return (res); 1509 } 1510 1511 static int 1512 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1513 int rid, struct resource *res) 1514 { 1515 struct cbb_softc *sc = device_get_softc(brdev); 1516 int error; 1517 1518 if (rman_get_flags(res) & RF_ACTIVE) { 1519 error = bus_deactivate_resource(child, type, rid, res); 1520 if (error != 0) 1521 return (error); 1522 } 1523 cbb_remove_res(sc, res); 1524 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1525 type, rid, res)); 1526 } 1527 1528 /************************************************************************/ 1529 /* PC Card Power Functions */ 1530 /************************************************************************/ 1531 1532 static int 1533 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1534 { 1535 struct cbb_softc *sc = device_get_softc(brdev); 1536 int err; 1537 1538 DPRINTF(("cbb_pcic_socket_enable:\n")); 1539 1540 /* power down/up the socket to reset */ 1541 err = cbb_do_power(brdev); 1542 if (err) 1543 return (err); 1544 exca_reset(&sc->exca, child); 1545 1546 return (0); 1547 } 1548 1549 static void 1550 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1551 { 1552 struct cbb_softc *sc = device_get_softc(brdev); 1553 1554 DPRINTF(("cbb_pcic_socket_disable\n")); 1555 1556 /* reset signal asserting... */ 1557 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1558 DELAY(2*1000); 1559 1560 /* power down the socket */ 1561 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1562 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1563 1564 /* wait 300ms until power fails (Tpf). */ 1565 DELAY(300 * 1000); 1566 } 1567 1568 /************************************************************************/ 1569 /* POWER methods */ 1570 /************************************************************************/ 1571 1572 static int 1573 cbb_power_enable_socket(device_t brdev, device_t child) 1574 { 1575 struct cbb_softc *sc = device_get_softc(brdev); 1576 1577 if (sc->flags & CBB_16BIT_CARD) 1578 return (cbb_pcic_power_enable_socket(brdev, child)); 1579 else 1580 return (cbb_cardbus_power_enable_socket(brdev, child)); 1581 } 1582 1583 static void 1584 cbb_power_disable_socket(device_t brdev, device_t child) 1585 { 1586 struct cbb_softc *sc = device_get_softc(brdev); 1587 if (sc->flags & CBB_16BIT_CARD) 1588 cbb_pcic_power_disable_socket(brdev, child); 1589 else 1590 cbb_cardbus_power_disable_socket(brdev, child); 1591 } 1592 static int 1593 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1594 struct resource *res) 1595 { 1596 int err; 1597 struct cbb_softc *sc = device_get_softc(brdev); 1598 if (!(rman_get_flags(res) & RF_ACTIVE)) { /* not already activated */ 1599 switch (type) { 1600 case SYS_RES_IOPORT: 1601 err = exca_io_map(&sc->exca, 0, res); 1602 break; 1603 case SYS_RES_MEMORY: 1604 err = exca_mem_map(&sc->exca, 0, res); 1605 break; 1606 default: 1607 err = 0; 1608 break; 1609 } 1610 if (err) 1611 return (err); 1612 1613 } 1614 return (BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1615 type, rid, res)); 1616 } 1617 1618 static int 1619 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1620 int rid, struct resource *res) 1621 { 1622 struct cbb_softc *sc = device_get_softc(brdev); 1623 1624 if (rman_get_flags(res) & RF_ACTIVE) { /* if activated */ 1625 switch (type) { 1626 case SYS_RES_IOPORT: 1627 if (exca_io_unmap_res(&sc->exca, res)) 1628 return (ENOENT); 1629 break; 1630 case SYS_RES_MEMORY: 1631 if (exca_mem_unmap_res(&sc->exca, res)) 1632 return (ENOENT); 1633 break; 1634 } 1635 } 1636 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1637 type, rid, res)); 1638 } 1639 1640 static struct resource * 1641 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1642 u_long start, u_long end, u_long count, uint flags) 1643 { 1644 struct resource *res = NULL; 1645 struct cbb_softc *sc = device_get_softc(brdev); 1646 int tmp; 1647 1648 switch (type) { 1649 case SYS_RES_MEMORY: 1650 if (start < cbb_start_mem) 1651 start = cbb_start_mem; 1652 if (end < start) 1653 end = start; 1654 flags = (flags & ~RF_ALIGNMENT_MASK) | 1655 rman_make_alignment_flags(CBB_MEMALIGN); 1656 break; 1657 case SYS_RES_IOPORT: 1658 if (start < cbb_start_16_io) 1659 start = cbb_start_16_io; 1660 if (end < start) 1661 end = start; 1662 break; 1663 case SYS_RES_IRQ: 1664 tmp = rman_get_start(sc->irq_res); 1665 if (start > tmp || end < tmp || count != 1) { 1666 device_printf(child, "requested interrupt %ld-%ld," 1667 "count = %ld not supported by cbb\n", 1668 start, end, count); 1669 return (NULL); 1670 } 1671 flags |= RF_SHAREABLE; 1672 start = end = rman_get_start(sc->irq_res); 1673 break; 1674 } 1675 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1676 start, end, count, flags & ~RF_ACTIVE); 1677 if (res == NULL) 1678 return (NULL); 1679 cbb_insert_res(sc, res, type, *rid); 1680 if (flags & RF_ACTIVE) { 1681 if (bus_activate_resource(child, type, *rid, res) != 0) { 1682 bus_release_resource(child, type, *rid, res); 1683 return (NULL); 1684 } 1685 } 1686 1687 return (res); 1688 } 1689 1690 static int 1691 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1692 int rid, struct resource *res) 1693 { 1694 struct cbb_softc *sc = device_get_softc(brdev); 1695 int error; 1696 1697 if (rman_get_flags(res) & RF_ACTIVE) { 1698 error = bus_deactivate_resource(child, type, rid, res); 1699 if (error != 0) 1700 return (error); 1701 } 1702 cbb_remove_res(sc, res); 1703 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1704 type, rid, res)); 1705 } 1706 1707 /************************************************************************/ 1708 /* PC Card methods */ 1709 /************************************************************************/ 1710 1711 static int 1712 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1713 uint32_t flags) 1714 { 1715 struct cbb_softc *sc = device_get_softc(brdev); 1716 struct resource *res; 1717 1718 if (type != SYS_RES_MEMORY) 1719 return (EINVAL); 1720 res = cbb_find_res(sc, type, rid); 1721 if (res == NULL) { 1722 device_printf(brdev, 1723 "set_res_flags: specified rid not found\n"); 1724 return (ENOENT); 1725 } 1726 return (exca_mem_set_flags(&sc->exca, res, flags)); 1727 } 1728 1729 static int 1730 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1731 uint32_t cardaddr, uint32_t *deltap) 1732 { 1733 struct cbb_softc *sc = device_get_softc(brdev); 1734 struct resource *res; 1735 1736 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1737 if (res == NULL) { 1738 device_printf(brdev, 1739 "set_memory_offset: specified rid not found\n"); 1740 return (ENOENT); 1741 } 1742 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1743 } 1744 1745 /************************************************************************/ 1746 /* BUS Methods */ 1747 /************************************************************************/ 1748 1749 1750 static int 1751 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1752 struct resource *r) 1753 { 1754 struct cbb_softc *sc = device_get_softc(brdev); 1755 1756 if (sc->flags & CBB_16BIT_CARD) 1757 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1758 else 1759 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1760 r)); 1761 } 1762 1763 static int 1764 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1765 int rid, struct resource *r) 1766 { 1767 struct cbb_softc *sc = device_get_softc(brdev); 1768 1769 if (sc->flags & CBB_16BIT_CARD) 1770 return (cbb_pcic_deactivate_resource(brdev, child, type, 1771 rid, r)); 1772 else 1773 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1774 rid, r)); 1775 } 1776 1777 static struct resource * 1778 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1779 u_long start, u_long end, u_long count, uint flags) 1780 { 1781 struct cbb_softc *sc = device_get_softc(brdev); 1782 1783 if (sc->flags & CBB_16BIT_CARD) 1784 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1785 start, end, count, flags)); 1786 else 1787 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1788 start, end, count, flags)); 1789 } 1790 1791 static int 1792 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1793 struct resource *r) 1794 { 1795 struct cbb_softc *sc = device_get_softc(brdev); 1796 1797 if (sc->flags & CBB_16BIT_CARD) 1798 return (cbb_pcic_release_resource(brdev, child, type, 1799 rid, r)); 1800 else 1801 return (cbb_cardbus_release_resource(brdev, child, type, 1802 rid, r)); 1803 } 1804 1805 static int 1806 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1807 { 1808 struct cbb_softc *sc = device_get_softc(brdev); 1809 1810 switch (which) { 1811 case PCIB_IVAR_BUS: 1812 *result = sc->secbus; 1813 return (0); 1814 } 1815 return (ENOENT); 1816 } 1817 1818 static int 1819 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1820 { 1821 struct cbb_softc *sc = device_get_softc(brdev); 1822 1823 switch (which) { 1824 case PCIB_IVAR_BUS: 1825 sc->secbus = value; 1826 break; 1827 } 1828 return (ENOENT); 1829 } 1830 1831 /************************************************************************/ 1832 /* PCI compat methods */ 1833 /************************************************************************/ 1834 1835 static int 1836 cbb_maxslots(device_t brdev) 1837 { 1838 return (0); 1839 } 1840 1841 static uint32_t 1842 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1843 { 1844 /* 1845 * Pass through to the next ppb up the chain (i.e. our grandparent). 1846 */ 1847 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1848 b, s, f, reg, width)); 1849 } 1850 1851 static void 1852 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1853 int width) 1854 { 1855 /* 1856 * Pass through to the next ppb up the chain (i.e. our grandparent). 1857 */ 1858 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1859 b, s, f, reg, val, width); 1860 } 1861 1862 static int 1863 cbb_suspend(device_t self) 1864 { 1865 int error = 0; 1866 struct cbb_softc *sc = device_get_softc(self); 1867 1868 cbb_setb(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1869 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1870 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1871 error = bus_generic_suspend(self); 1872 return (error); 1873 } 1874 1875 static int 1876 cbb_resume(device_t self) 1877 { 1878 int error = 0; 1879 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1880 uint32_t tmp; 1881 1882 /* 1883 * Some BIOSes will not save the BARs for the pci chips, so we 1884 * must do it ourselves. If the BAR is reset to 0 for an I/O 1885 * device, it will read back as 0x1, so no explicit test for 1886 * memory devices are needed. 1887 * 1888 * Note: The PCI bus code should do this automatically for us on 1889 * suspend/resume, but until it does, we have to cope. 1890 */ 1891 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1892 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1893 rman_get_start(sc->base_res))); 1894 1895 cbb_chipinit(sc); 1896 1897 /* reset interrupt -- Do we really need to do this? */ 1898 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1899 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1900 1901 /* re-establish the interrupt. */ 1902 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 1903 &sc->intrhand)) { 1904 device_printf(self, "couldn't re-establish interrupt"); 1905 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1906 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1907 sc->base_res); 1908 sc->irq_res = NULL; 1909 sc->base_res = NULL; 1910 return (ENOMEM); 1911 } 1912 1913 /* CSC Interrupt: Card detect interrupt on */ 1914 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1915 1916 /* Signal the thread to wakeup. */ 1917 mtx_lock(&sc->mtx); 1918 cv_signal(&sc->cv); 1919 mtx_unlock(&sc->mtx); 1920 1921 error = bus_generic_resume(self); 1922 1923 return (error); 1924 } 1925 1926 static int 1927 cbb_child_present(device_t self) 1928 { 1929 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1930 uint32_t sockstate; 1931 1932 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1933 return ((sockstate & CBB_SOCKET_STAT_CD) != 0 && 1934 (sc->flags & CBB_CARD_OK) != 0); 1935 } 1936 1937 static device_method_t cbb_methods[] = { 1938 /* Device interface */ 1939 DEVMETHOD(device_probe, cbb_probe), 1940 DEVMETHOD(device_attach, cbb_attach), 1941 DEVMETHOD(device_detach, cbb_detach), 1942 DEVMETHOD(device_shutdown, cbb_shutdown), 1943 DEVMETHOD(device_suspend, cbb_suspend), 1944 DEVMETHOD(device_resume, cbb_resume), 1945 1946 /* bus methods */ 1947 DEVMETHOD(bus_print_child, bus_generic_print_child), 1948 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 1949 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 1950 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 1951 DEVMETHOD(bus_release_resource, cbb_release_resource), 1952 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 1953 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 1954 DEVMETHOD(bus_driver_added, cbb_driver_added), 1955 DEVMETHOD(bus_child_detached, cbb_child_detached), 1956 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 1957 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 1958 DEVMETHOD(bus_child_present, cbb_child_present), 1959 1960 /* 16-bit card interface */ 1961 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 1962 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 1963 1964 /* power interface */ 1965 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 1966 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 1967 1968 /* pcib compatibility interface */ 1969 DEVMETHOD(pcib_maxslots, cbb_maxslots), 1970 DEVMETHOD(pcib_read_config, cbb_read_config), 1971 DEVMETHOD(pcib_write_config, cbb_write_config), 1972 {0,0} 1973 }; 1974 1975 static driver_t cbb_driver = { 1976 "cbb", 1977 cbb_methods, 1978 sizeof(struct cbb_softc) 1979 }; 1980 1981 static devclass_t cbb_devclass; 1982 1983 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 1984 MODULE_VERSION(cbb, 1); 1985 MODULE_DEPEND(cbb, exca, 1, 1, 1); 1986