1 /* 2 * Copyright (c) 2002 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for PCI to CardBus Bridge chips 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 93 #include <pci/pcireg.h> 94 #include <pci/pcivar.h> 95 #include <machine/clock.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 #define CBB_START_MEM 0x88000000 120 #define CBB_START_32_IO 0x1000 121 #define CBB_START_16_IO 0x100 122 123 struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 155 /* Ricoh chips */ 156 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 157 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 158 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 159 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 160 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 161 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 162 163 /* Toshiba products */ 164 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 165 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 166 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 167 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 168 169 /* Cirrus Logic */ 170 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 171 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 172 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 173 174 /* 02Micro */ 175 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_CIRRUS}, 176 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_CIRRUS}, 177 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_CIRRUS}, 178 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_CIRRUS}, 179 {PCIC_ID_OZ6922, "O2Micro OZ6822 PCI-CardBus Bridge", CB_CIRRUS}, 180 {PCIC_ID_OZ6933, "O2Micro OZ6833 PCI-CardBus Bridge", CB_CIRRUS}, 181 182 /* sentinel */ 183 {0 /* null id */, "unknown", CB_UNKNOWN}, 184 }; 185 186 /* sysctl vars */ 187 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 188 189 /* There's no way to say TUNEABLE_LONG to get the right types */ 190 u_long cbb_start_mem = CBB_START_MEM; 191 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 192 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 193 &cbb_start_mem, CBB_START_MEM, 194 "Starting address for memory allocations"); 195 196 u_long cbb_start_16_io = CBB_START_16_IO; 197 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 198 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 199 &cbb_start_16_io, CBB_START_16_IO, 200 "Starting ioport for 16-bit cards"); 201 202 u_long cbb_start_32_io = CBB_START_32_IO; 203 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 205 &cbb_start_32_io, CBB_START_32_IO, 206 "Starting ioport for 32-bit cards"); 207 208 int cbb_debug = 0; 209 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 211 "Verbose cardbus bridge debugging"); 212 213 static int cbb_chipset(uint32_t pci_id, const char **namep); 214 static int cbb_probe(device_t brdev); 215 static void cbb_chipinit(struct cbb_softc *sc); 216 static int cbb_attach(device_t brdev); 217 static int cbb_detach(device_t brdev); 218 static int cbb_shutdown(device_t brdev); 219 static void cbb_driver_added(device_t brdev, driver_t *driver); 220 static void cbb_child_detached(device_t brdev, device_t child); 221 static void cbb_event_thread(void *arg); 222 static void cbb_insert(struct cbb_softc *sc); 223 static void cbb_removal(struct cbb_softc *sc); 224 static void cbb_intr(void *arg); 225 static int cbb_detect_voltage(device_t brdev); 226 static int cbb_power(device_t brdev, int volts); 227 static void cbb_cardbus_reset(device_t brdev); 228 static int cbb_cardbus_power_enable_socket(device_t brdev, 229 device_t child); 230 static void cbb_cardbus_power_disable_socket(device_t brdev, 231 device_t child); 232 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 233 uint32_t end); 234 static int cbb_cardbus_mem_open(device_t brdev, int win, 235 uint32_t start, uint32_t end); 236 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 237 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 238 int type, int rid, struct resource *res); 239 static int cbb_cardbus_deactivate_resource(device_t brdev, 240 device_t child, int type, int rid, struct resource *res); 241 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 242 device_t child, int type, int *rid, u_long start, 243 u_long end, u_long count, uint flags); 244 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 245 int type, int rid, struct resource *res); 246 static int cbb_power_enable_socket(device_t brdev, device_t child); 247 static void cbb_power_disable_socket(device_t brdev, device_t child); 248 static int cbb_activate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *r); 250 static int cbb_deactivate_resource(device_t brdev, device_t child, 251 int type, int rid, struct resource *r); 252 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 253 int type, int *rid, u_long start, u_long end, u_long count, 254 uint flags); 255 static int cbb_release_resource(device_t brdev, device_t child, 256 int type, int rid, struct resource *r); 257 static int cbb_read_ivar(device_t brdev, device_t child, int which, 258 uintptr_t *result); 259 static int cbb_write_ivar(device_t brdev, device_t child, int which, 260 uintptr_t value); 261 static int cbb_maxslots(device_t brdev); 262 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 263 int reg, int width); 264 static void cbb_write_config(device_t brdev, int b, int s, int f, 265 int reg, uint32_t val, int width); 266 267 /* 268 */ 269 static __inline void 270 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 271 { 272 bus_space_write_4(sc->bst, sc->bsh, reg, val); 273 } 274 275 static __inline uint32_t 276 cbb_get(struct cbb_softc *sc, uint32_t reg) 277 { 278 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 279 } 280 281 static __inline void 282 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 283 { 284 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 285 } 286 287 static __inline void 288 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 289 { 290 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 291 } 292 293 static void 294 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 295 { 296 struct cbb_reslist *rle; 297 298 SLIST_FOREACH(rle, &sc->rl, link) { 299 if (rle->res == res) { 300 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 301 free(rle, M_DEVBUF); 302 return; 303 } 304 } 305 } 306 307 static struct resource * 308 cbb_find_res(struct cbb_softc *sc, int type, int rid) 309 { 310 struct cbb_reslist *rle; 311 312 SLIST_FOREACH(rle, &sc->rl, link) 313 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 314 return (rle->res); 315 return (NULL); 316 } 317 318 static void 319 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 320 int rid) 321 { 322 struct cbb_reslist *rle; 323 324 /* 325 * Need to record allocated resource so we can iterate through 326 * it later. 327 */ 328 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 329 if (!res) 330 panic("cbb_cardbus_alloc_resource: can't record entry!"); 331 rle->res = res; 332 rle->type = type; 333 rle->rid = rid; 334 SLIST_INSERT_HEAD(&sc->rl, rle, link); 335 } 336 337 static void 338 cbb_destroy_res(struct cbb_softc *sc) 339 { 340 struct cbb_reslist *rle; 341 342 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 343 device_printf(sc->dev, "Danger Will Robinson: Resource " 344 "left allocated! This is a bug... " 345 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 346 rman_get_start(rle->res)); 347 SLIST_REMOVE_HEAD(&sc->rl, link); 348 free(rle, M_DEVBUF); 349 } 350 } 351 352 /************************************************************************/ 353 /* Probe/Attach */ 354 /************************************************************************/ 355 356 static int 357 cbb_chipset(uint32_t pci_id, const char **namep) 358 { 359 struct yenta_chipinfo *ycp; 360 361 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 362 continue; 363 if (namep != NULL) 364 *namep = ycp->yc_name; 365 return (ycp->yc_chiptype); 366 } 367 368 static int 369 cbb_probe(device_t brdev) 370 { 371 const char *name; 372 uint32_t progif; 373 uint32_t subclass; 374 375 /* 376 * Do we know that we support the chipset? If so, then we 377 * accept the device. 378 */ 379 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 380 device_set_desc(brdev, name); 381 return (0); 382 } 383 384 /* 385 * We do support generic CardBus bridges. All that we've seen 386 * to date have progif 0 (the Yenta spec, and successors mandate 387 * this). We do not support PCI PCMCIA bridges (with one exception) 388 * with this driver since they generally are I/O mapped. Those 389 * are supported by the pcic driver. This should help us be more 390 * future proof. 391 */ 392 subclass = pci_get_subclass(brdev); 393 progif = pci_get_progif(brdev); 394 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 395 device_set_desc(brdev, "PCI-CardBus Bridge"); 396 return (0); 397 } 398 return (ENXIO); 399 } 400 401 402 static void 403 cbb_chipinit(struct cbb_softc *sc) 404 { 405 uint32_t mux, sysctrl; 406 407 /* Set CardBus latency timer */ 408 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 409 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 410 411 /* Set PCI latency timer */ 412 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 413 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 414 415 /* Enable memory access */ 416 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 417 | PCIM_CMD_MEMEN 418 | PCIM_CMD_PORTEN 419 | PCIM_CMD_BUSMASTEREN, 2); 420 421 /* disable Legacy IO */ 422 switch (sc->chipset) { 423 case CB_RF5C46X: 424 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 425 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 426 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 427 break; 428 default: 429 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 430 break; 431 } 432 433 /* Use PCI interrupt for interrupt routing */ 434 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 435 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 436 CBBM_BRIDGECTRL_INTR_IREQ_EN), 437 | CBBM_BRIDGECTRL_WRITE_POST_EN, 438 2); 439 440 /* 441 * XXX this should be a function table, ala OLDCARD. This means 442 * that we could more easily support ISA interrupts for pccard 443 * cards if we had to. 444 */ 445 switch (sc->chipset) { 446 case CB_TI113X: 447 /* 448 * The TI 1031, TI 1130 and TI 1131 all require another bit 449 * be set to enable PCI routing of interrupts, and then 450 * a bit for each of the CSC and Function interrupts we 451 * want routed. 452 */ 453 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 454 | CBBM_CBCTRL_113X_PCI_INTR | 455 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 456 1); 457 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 458 & ~(CBBM_DEVCTRL_INT_SERIAL | 459 CBBM_DEVCTRL_INT_PCI), 1); 460 break; 461 case CB_TI12XX: 462 /* 463 * Some TI 12xx (and [14][45]xx) based pci cards 464 * sometimes have issues with the MFUNC register not 465 * being initialized due to a bad EEPROM on board. 466 * Laptops that this matters on have this register 467 * properly initialized. 468 * 469 * The TI125X parts have a different register. 470 */ 471 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 472 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 473 if (mux == 0) { 474 mux = (mux & ~CBBM_MFUNC_PIN0) | 475 CBBM_MFUNC_PIN0_INTA; 476 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 477 mux = (mux & ~CBBM_MFUNC_PIN1) | 478 CBBM_MFUNC_PIN1_INTB; 479 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 480 } 481 /*FALLTHROUGH*/ 482 case CB_TI125X: 483 /* 484 * Disable zoom video. Some machines initialize this 485 * improperly and exerpience has shown that this helps 486 * on some machines. 487 */ 488 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 489 break; 490 case CB_TOPIC97: 491 /* 492 * Disable Zoom Video, ToPIC 97, 100. 493 */ 494 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 495 /* 496 * ToPIC 97, 100 497 * At offset 0xa1: INTERRUPT CONTROL register 498 * 0x1: Turn on INT interrupts. 499 */ 500 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 501 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 502 goto topic_common; 503 case CB_TOPIC95: 504 /* 505 * SOCKETCTRL appears to be TOPIC 95/B specific 506 */ 507 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 508 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 509 510 topic_common:; 511 /* 512 * At offset 0xa0: SLOT CONTROL 513 * 0x80 Enable CardBus Functionality 514 * 0x40 Enable CardBus and PC Card registers 515 * 0x20 Lock ID in exca regs 516 * 0x10 Write protect ID in config regs 517 * Clear the rest of the bits, which defaults the slot 518 * in legacy mode to 0x3e0 and offset 0. (legacy 519 * mode is determined elsewhere) 520 */ 521 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 522 CBBM_TOPIC_SLOTCTRL_SLOTON | 523 CBBM_TOPIC_SLOTCTRL_SLOTEN | 524 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 525 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 526 527 /* 528 * At offset 0xa3 Card Detect Control Register 529 * 0x80 CARDBUS enbale 530 * 0x01 Cleared for hardware change detect 531 */ 532 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 533 | CBBM_TOPIC_CDC_CARDBUS, 534 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 535 break; 536 } 537 538 /* 539 * Need to tell ExCA registers to route via PCI interrupts. There 540 * are two ways to do this. Once is to set INTR_ENABLE and the 541 * other is to set CSC to 0. Since both methods are mutually 542 * compatible, we do both. 543 */ 544 exca_write(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 545 exca_write(&sc->exca, EXCA_CSC_INTR, 0); 546 547 /* close all memory and io windows */ 548 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 549 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 550 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 551 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 552 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 553 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 554 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 555 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 556 } 557 558 static int 559 cbb_attach(device_t brdev) 560 { 561 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 562 int rid; 563 564 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 565 cv_init(&sc->cv, "cbb cv"); 566 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 567 sc->dev = brdev; 568 sc->cbdev = NULL; 569 sc->pccarddev = NULL; 570 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 571 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 572 SLIST_INIT(&sc->rl); 573 STAILQ_INIT(&sc->intr_handlers); 574 575 #ifndef BURN_THE_BOATS 576 /* 577 * The PCI bus code should assign us memory in the absense 578 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 579 * up something here until the PCI/acpi code properly assigns the 580 * resource. 581 */ 582 #endif 583 rid = CBBR_SOCKBASE; 584 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 585 0, ~0, 1, RF_ACTIVE); 586 if (!sc->base_res) { 587 #ifdef BURN_THE_BOATS 588 device_printf(brdev, "Could not map register memory\n"); 589 mtx_destroy(&sc->mtx); 590 cv_destroy(&sc->cv); 591 return (ENOMEM); 592 #else 593 uint32_t sockbase; 594 /* 595 * Generally, the BIOS will assign this memory for us. 596 * However, newer BIOSes do not because the MS design 597 * documents have mandated that this is for the OS 598 * to assign rather than the BIOS. This driver shouldn't 599 * be doing this, but until the pci bus code (or acpi) 600 * does this, we allow CardBus bridges to work on more 601 * machines. 602 */ 603 sockbase = pci_read_config(brdev, rid, 4); 604 if (sockbase < 0x100000 || sockbase >= 0xfffffff0) { 605 pci_write_config(brdev, rid, 0xffffffff, 4); 606 sockbase = pci_read_config(brdev, rid, 4); 607 sockbase = (sockbase & 0xfffffff0) & 608 -(sockbase & 0xfffffff0); 609 sc->base_res = bus_generic_alloc_resource( 610 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 611 &rid, cbb_start_mem, ~0, sockbase, 612 RF_ACTIVE|rman_make_alignment_flags(sockbase)); 613 if (!sc->base_res) { 614 device_printf(brdev, 615 "Could not grab register memory\n"); 616 mtx_destroy(&sc->mtx); 617 cv_destroy(&sc->cv); 618 return (ENOMEM); 619 } 620 sc->flags |= CBB_KLUDGE_ALLOC; 621 pci_write_config(brdev, CBBR_SOCKBASE, 622 rman_get_start(sc->base_res), 4); 623 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 624 rman_get_start(sc->base_res))); 625 } else { 626 device_printf(brdev, "Could not map register memory\n"); 627 goto err; 628 } 629 #endif 630 } 631 632 sc->bst = rman_get_bustag(sc->base_res); 633 sc->bsh = rman_get_bushandle(sc->base_res); 634 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 635 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 636 cbb_chipinit(sc); 637 638 /* attach children */ 639 sc->cbdev = device_add_child(brdev, "cardbus", -1); 640 if (sc->cbdev == NULL) 641 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 642 else if (device_probe_and_attach(sc->cbdev) != 0) { 643 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 644 sc->cbdev = NULL; 645 } 646 647 sc->pccarddev = device_add_child(brdev, "pccard", -1); 648 if (sc->pccarddev == NULL) 649 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 650 else if (device_probe_and_attach(sc->pccarddev) != 0) { 651 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 652 sc->pccarddev = NULL; 653 } 654 655 /* Map and establish the interrupt. */ 656 rid = 0; 657 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 658 RF_SHAREABLE | RF_ACTIVE); 659 if (sc->irq_res == NULL) { 660 printf("cbb: Unable to map IRQ...\n"); 661 goto err; 662 return (ENOMEM); 663 } 664 665 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 666 &sc->intrhand)) { 667 device_printf(brdev, "couldn't establish interrupt"); 668 goto err; 669 } 670 671 /* reset 16-bit pcmcia bus */ 672 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 673 674 /* turn off power */ 675 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 676 677 /* CSC Interrupt: Card detect interrupt on */ 678 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 679 680 /* reset interrupt */ 681 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 682 683 /* Start the thread */ 684 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 685 "%s%d", device_get_name(sc->dev), device_get_unit(sc->dev))) { 686 device_printf (sc->dev, "unable to create event thread.\n"); 687 panic ("cbb_create_event_thread"); 688 } 689 690 return (0); 691 err: 692 if (sc->irq_res) 693 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 694 if (sc->base_res) { 695 if (sc->flags & CBB_KLUDGE_ALLOC) 696 bus_generic_release_resource(device_get_parent(brdev), 697 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 698 sc->base_res); 699 else 700 bus_release_resource(brdev, SYS_RES_MEMORY, 701 CBBR_SOCKBASE, sc->base_res); 702 } 703 mtx_destroy(&sc->mtx); 704 cv_destroy(&sc->cv); 705 return (ENOMEM); 706 } 707 708 static int 709 cbb_detach(device_t brdev) 710 { 711 struct cbb_softc *sc = device_get_softc(brdev); 712 int numdevs; 713 device_t *devlist; 714 int tmp; 715 int error; 716 717 device_get_children(brdev, &devlist, &numdevs); 718 719 error = 0; 720 for (tmp = 0; tmp < numdevs; tmp++) { 721 if (device_detach(devlist[tmp]) == 0) 722 device_delete_child(brdev, devlist[tmp]); 723 else 724 error++; 725 } 726 free(devlist, M_TEMP); 727 if (error > 0) 728 return (ENXIO); 729 730 mtx_lock(&sc->mtx); 731 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 732 sc->flags |= CBB_KTHREAD_DONE; 733 if (sc->flags & CBB_KTHREAD_RUNNING) { 734 cv_broadcast(&sc->cv); 735 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 736 } 737 mtx_unlock(&sc->mtx); 738 739 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 740 if (sc->flags & CBB_KLUDGE_ALLOC) 741 bus_generic_release_resource(device_get_parent(brdev), 742 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 743 sc->base_res); 744 else 745 bus_release_resource(brdev, SYS_RES_MEMORY, 746 CBBR_SOCKBASE, sc->base_res); 747 mtx_destroy(&sc->mtx); 748 cv_destroy(&sc->cv); 749 return (0); 750 } 751 752 static int 753 cbb_shutdown(device_t brdev) 754 { 755 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 756 /* properly reset everything at shutdown */ 757 758 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 759 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 760 761 cbb_set(sc, CBB_SOCKET_MASK, 0); 762 763 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 764 765 exca_write(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 766 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 767 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 768 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 769 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 770 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 771 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 772 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 773 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 774 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 775 return (0); 776 } 777 778 static int 779 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 780 int flags, driver_intr_t *intr, void *arg, void **cookiep) 781 { 782 struct cbb_intrhand *ih; 783 struct cbb_softc *sc = device_get_softc(dev); 784 785 /* 786 * You aren't allowed to have fast interrupts for pccard/cardbus 787 * things since those interrupts are PCI and shared. Since we use 788 * the PCI interrupt for the status change interrupts, it can't be 789 * free for use by the driver. Fast interrupts must not be shared. 790 */ 791 if ((flags & INTR_FAST) != 0) 792 return (EINVAL); 793 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 794 if (ih == NULL) 795 return (ENOMEM); 796 *cookiep = ih; 797 ih->intr = intr; 798 ih->arg = arg; 799 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 800 /* 801 * XXX we should do what old card does to ensure that we don't 802 * XXX call the function's interrupt routine(s). 803 */ 804 /* 805 * XXX need to turn on ISA interrupts, if we ever support them, but 806 * XXX for now that's all we need to do. 807 */ 808 return (0); 809 } 810 811 static int 812 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 813 void *cookie) 814 { 815 struct cbb_intrhand *ih; 816 struct cbb_softc *sc = device_get_softc(dev); 817 818 /* XXX Need to do different things for ISA interrupts. */ 819 ih = (struct cbb_intrhand *) cookie; 820 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 821 free(ih, M_DEVBUF); 822 return (0); 823 } 824 825 826 static void 827 cbb_driver_added(device_t brdev, driver_t *driver) 828 { 829 struct cbb_softc *sc = device_get_softc(brdev); 830 device_t *devlist; 831 int tmp; 832 int numdevs; 833 int wake; 834 uint32_t sockstate; 835 836 DEVICE_IDENTIFY(driver, brdev); 837 device_get_children(brdev, &devlist, &numdevs); 838 wake = 0; 839 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 840 for (tmp = 0; tmp < numdevs; tmp++) { 841 if (device_get_state(devlist[tmp]) == DS_NOTPRESENT && 842 device_probe_and_attach(devlist[tmp]) == 0) { 843 if (devlist[tmp] == NULL) 844 /* NOTHING */; 845 else if (strcmp(driver->name, "cardbus") == 0) { 846 printf("Adding cardbus\n"); 847 sc->cbdev = devlist[tmp]; 848 if (((sockstate & CBB_SOCKET_STAT_CD) == 0) && 849 (sockstate & CBB_SOCKET_STAT_CB)) 850 wake++; 851 } else if (strcmp(driver->name, "pccard") == 0) { 852 printf("Adding pccard\n"); 853 sc->pccarddev = devlist[tmp]; 854 if (((sockstate & CBB_SOCKET_STAT_CD) == 0) && 855 (sockstate & CBB_SOCKET_STAT_16BIT)) 856 wake++; 857 } else 858 device_printf(brdev, 859 "Unsupported child bus: %s\n", 860 driver->name); 861 } 862 } 863 free(devlist, M_TEMP); 864 865 if (wake > 0) { 866 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) 867 == 0) { 868 mtx_lock(&sc->mtx); 869 wakeup(sc); 870 mtx_unlock(&sc->mtx); 871 } 872 } 873 } 874 875 static void 876 cbb_child_detached(device_t brdev, device_t child) 877 { 878 struct cbb_softc *sc = device_get_softc(brdev); 879 880 if (child == sc->cbdev) 881 sc->cbdev = NULL; 882 else if (child == sc->pccarddev) 883 sc->pccarddev = NULL; 884 else 885 device_printf(brdev, "Unknown child detached: %s %p/%p\n", 886 device_get_nameunit(child), sc->cbdev, sc->pccarddev); 887 } 888 889 /************************************************************************/ 890 /* Kthreads */ 891 /************************************************************************/ 892 893 static void 894 cbb_event_thread(void *arg) 895 { 896 struct cbb_softc *sc = arg; 897 uint32_t status; 898 int err; 899 900 /* 901 * We take out Giant here because we need it deep, down in 902 * the bowels of the vm system for mapping the memory we need 903 * to read the CIS. We also need it for kthread_exit, which 904 * drops it. 905 */ 906 sc->flags |= CBB_KTHREAD_RUNNING; 907 while (1) { 908 /* 909 * Check to see if we have anything first so that 910 * if there's a card already inserted, we do the 911 * right thing. 912 */ 913 if (sc->flags & CBB_KTHREAD_DONE) 914 break; 915 916 status = cbb_get(sc, CBB_SOCKET_STATE); 917 mtx_lock(&Giant); 918 if ((status & CBB_SOCKET_STAT_CD) == 0) 919 cbb_insert(sc); 920 else 921 cbb_removal(sc); 922 mtx_unlock(&Giant); 923 924 /* 925 * Wait until it has been 1s since the last time we 926 * get an interrupt. We handle the rest of the interrupt 927 * at the top of the loop. 928 */ 929 mtx_lock(&sc->mtx); 930 cv_wait(&sc->cv, &sc->mtx); 931 err = 0; 932 while (err != EWOULDBLOCK && 933 (sc->flags & CBB_KTHREAD_DONE) == 0) 934 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 935 mtx_unlock(&sc->mtx); 936 } 937 sc->flags &= ~CBB_KTHREAD_RUNNING; 938 mtx_lock(&Giant); 939 kthread_exit(0); 940 } 941 942 /************************************************************************/ 943 /* Insert/removal */ 944 /************************************************************************/ 945 946 static void 947 cbb_insert(struct cbb_softc *sc) 948 { 949 uint32_t sockevent, sockstate; 950 951 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 952 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 953 954 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 955 sockevent, sockstate)); 956 957 if (sockstate & CBB_SOCKET_STAT_16BIT) { 958 if (sc->pccarddev != NULL) { 959 sc->flags |= CBB_16BIT_CARD; 960 sc->flags |= CBB_CARD_OK; 961 if (CARD_ATTACH_CARD(sc->pccarddev) != 0) { 962 device_printf(sc->dev, 963 "PC Card card activation failed\n"); 964 sc->flags &= ~CBB_CARD_OK; 965 } 966 } else { 967 device_printf(sc->dev, 968 "PC Card inserted, but no pccard bus.\n"); 969 } 970 } else if (sockstate & CBB_SOCKET_STAT_CB) { 971 if (sc->cbdev != NULL) { 972 sc->flags &= ~CBB_16BIT_CARD; 973 sc->flags |= CBB_CARD_OK; 974 if (CARD_ATTACH_CARD(sc->cbdev) != 0) { 975 device_printf(sc->dev, 976 "CardBus card activation failed\n"); 977 sc->flags &= ~CBB_CARD_OK; 978 } 979 } else { 980 device_printf(sc->dev, 981 "CardBus card inserted, but no cardbus bus.\n"); 982 } 983 } else { 984 /* 985 * We should power the card down, and try again a couple of 986 * times if this happens. XXX 987 */ 988 device_printf (sc->dev, "Unsupported card type detected\n"); 989 } 990 } 991 992 static void 993 cbb_removal(struct cbb_softc *sc) 994 { 995 if (sc->flags & CBB_16BIT_CARD && sc->pccarddev != NULL) 996 CARD_DETACH_CARD(sc->pccarddev); 997 else if ((!(sc->flags & CBB_16BIT_CARD)) && sc->cbdev != NULL) 998 CARD_DETACH_CARD(sc->cbdev); 999 cbb_destroy_res(sc); 1000 } 1001 1002 /************************************************************************/ 1003 /* Interrupt Handler */ 1004 /************************************************************************/ 1005 1006 static void 1007 cbb_intr(void *arg) 1008 { 1009 struct cbb_softc *sc = arg; 1010 uint32_t sockevent; 1011 struct cbb_intrhand *ih; 1012 1013 /* 1014 * This ISR needs work XXX 1015 */ 1016 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1017 if (sockevent) { 1018 /* ack the interrupt */ 1019 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1020 1021 /* 1022 * If anything has happened to the socket, we assume that 1023 * the card is no longer OK, and we shouldn't call its 1024 * ISR. We set CARD_OK as soon as we've attached the 1025 * card. This helps in a noisy eject, which happens 1026 * all too often when users are ejecting their PC Cards. 1027 * 1028 * We use this method in preference to checking to see if 1029 * the card is still there because the check suffers from 1030 * a race condition in the bouncing case. Prior versions 1031 * of the pccard software used a similar trick and achieved 1032 * excellent results. 1033 */ 1034 if (sockevent & CBB_SOCKET_EVENT_CD) { 1035 mtx_lock(&sc->mtx); 1036 sc->flags &= ~CBB_CARD_OK; 1037 cv_signal(&sc->cv); 1038 mtx_unlock(&sc->mtx); 1039 } 1040 if (sockevent & CBB_SOCKET_EVENT_CSTS) { 1041 DPRINTF((" cstsevent occured: 0x%08x\n", 1042 cbb_get(sc, CBB_SOCKET_STATE))); 1043 } 1044 if (sockevent & CBB_SOCKET_EVENT_POWER) { 1045 DPRINTF((" pwrevent occured: 0x%08x\n", 1046 cbb_get(sc, CBB_SOCKET_STATE))); 1047 } 1048 /* Other bits? */ 1049 } 1050 if (sc->flags & CBB_CARD_OK) { 1051 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1052 (*ih->intr)(ih->arg); 1053 } 1054 1055 } 1056 } 1057 1058 /************************************************************************/ 1059 /* Generic Power functions */ 1060 /************************************************************************/ 1061 1062 static int 1063 cbb_detect_voltage(device_t brdev) 1064 { 1065 struct cbb_softc *sc = device_get_softc(brdev); 1066 uint32_t psr; 1067 int vol = CARD_UKN_CARD; 1068 1069 psr = cbb_get(sc, CBB_SOCKET_STATE); 1070 1071 if (psr & CBB_SOCKET_STAT_5VCARD) 1072 vol |= CARD_5V_CARD; 1073 if (psr & CBB_SOCKET_STAT_3VCARD) 1074 vol |= CARD_3V_CARD; 1075 if (psr & CBB_SOCKET_STAT_XVCARD) 1076 vol |= CARD_XV_CARD; 1077 if (psr & CBB_SOCKET_STAT_YVCARD) 1078 vol |= CARD_YV_CARD; 1079 1080 return (vol); 1081 } 1082 1083 static int 1084 cbb_power(device_t brdev, int volts) 1085 { 1086 uint32_t status, sock_ctrl; 1087 struct cbb_softc *sc = device_get_softc(brdev); 1088 int timeout; 1089 uint32_t sockevent; 1090 1091 DEVPRINTF((sc->dev, "cbb_power: %s and %s [%x]\n", 1092 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 1093 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 1094 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 1095 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 1096 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 1097 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 1098 "VCC-UNKNOWN", 1099 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 1100 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V" : 1101 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC" : 1102 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1103 "VPP-UNKNOWN", 1104 volts)); 1105 1106 status = cbb_get(sc, CBB_SOCKET_STATE); 1107 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1108 1109 switch (volts & CARD_VCCMASK) { 1110 case CARD_VCC_UC: 1111 break; 1112 case CARD_VCC_5V: 1113 if (CBB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1114 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1115 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1116 } else { 1117 device_printf(sc->dev, 1118 "BAD voltage request: no 5 V card\n"); 1119 } 1120 break; 1121 case CARD_VCC_3V: 1122 if (CBB_SOCKET_STAT_3VCARD & status) { 1123 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1124 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1125 } else { 1126 device_printf(sc->dev, 1127 "BAD voltage request: no 3.3 V card\n"); 1128 } 1129 break; 1130 case CARD_VCC_0V: 1131 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1132 break; 1133 default: 1134 return (0); /* power NEVER changed */ 1135 break; 1136 } 1137 1138 switch (volts & CARD_VPPMASK) { 1139 case CARD_VPP_UC: 1140 break; 1141 case CARD_VPP_0V: 1142 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1143 break; 1144 case CARD_VPP_VCC: 1145 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1146 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1147 break; 1148 case CARD_VPP_12V: 1149 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1150 sock_ctrl |= CBB_SOCKET_CTRL_VPP_12V; 1151 break; 1152 } 1153 1154 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1155 return (1); /* no change necessary */ 1156 1157 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1158 status = cbb_get(sc, CBB_SOCKET_STATE); 1159 1160 /* 1161 * XXX This busy wait is bogus. We should wait for a power 1162 * interrupt and then whine if the status is bad. If we're 1163 * worried about the card not coming up, then we should also 1164 * schedule a timeout which we can cacel in the power interrupt. 1165 */ 1166 timeout = 20; 1167 do { 1168 DELAY(20*1000); 1169 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1170 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1171 /* reset event status */ 1172 /* XXX should only reset EVENT_POWER */ 1173 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1174 if (timeout < 0) { 1175 printf ("VCC supply failed.\n"); 1176 return (0); 1177 } 1178 1179 /* XXX 1180 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1181 * is 20 ms, some PC-Card bridge requires longer duration. 1182 * XXX Note: We should check the stutus AFTER the delay to give time 1183 * for things to stabilize. 1184 */ 1185 DELAY(400*1000); 1186 1187 if (status & CBB_SOCKET_STAT_BADVCC) { 1188 device_printf(sc->dev, 1189 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1190 sock_ctrl ,status); 1191 printf("cbb_power: %s and %s [%x]\n", 1192 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 1193 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 1194 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 1195 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 1196 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 1197 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 1198 "VCC-UNKNOWN", 1199 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 1200 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V": 1201 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC": 1202 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1203 "VPP-UNKNOWN", 1204 volts); 1205 return (0); 1206 } 1207 return (1); /* power changed correctly */ 1208 } 1209 1210 /* 1211 * detect the voltage for the card, and set it. Since the power 1212 * used is the square of the voltage, lower voltages is a big win 1213 * and what Windows does (and what Microsoft prefers). The MS paper 1214 * also talks about preferring the CIS entry as well. 1215 */ 1216 static int 1217 cbb_do_power(device_t brdev) 1218 { 1219 int voltage; 1220 1221 /* Prefer lowest voltage supported */ 1222 voltage = cbb_detect_voltage(brdev); 1223 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1224 if (voltage & CARD_YV_CARD) 1225 cbb_power(brdev, CARD_VCC_YV | CARD_VPP_VCC); 1226 else if (voltage & CARD_XV_CARD) 1227 cbb_power(brdev, CARD_VCC_XV | CARD_VPP_VCC); 1228 else if (voltage & CARD_3V_CARD) 1229 cbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1230 else if (voltage & CARD_5V_CARD) 1231 cbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1232 else { 1233 device_printf(brdev, "Unknown card voltage\n"); 1234 return (ENXIO); 1235 } 1236 return (0); 1237 } 1238 1239 /************************************************************************/ 1240 /* CardBus power functions */ 1241 /************************************************************************/ 1242 1243 static void 1244 cbb_cardbus_reset(device_t brdev) 1245 { 1246 struct cbb_softc *sc = device_get_softc(brdev); 1247 int delay_us; 1248 1249 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1250 1251 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1252 1253 DELAY(delay_us); 1254 1255 /* If a card exists, unreset it! */ 1256 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 0) { 1257 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1258 &~CBBM_BRIDGECTRL_RESET, 2); 1259 DELAY(delay_us); 1260 } 1261 } 1262 1263 static int 1264 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1265 { 1266 struct cbb_softc *sc = device_get_softc(brdev); 1267 int err; 1268 1269 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 1270 CBB_SOCKET_STAT_CD) 1271 return (ENODEV); 1272 1273 err = cbb_do_power(brdev); 1274 if (err) 1275 return (err); 1276 cbb_cardbus_reset(brdev); 1277 return (0); 1278 } 1279 1280 static void 1281 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1282 { 1283 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1284 cbb_cardbus_reset(brdev); 1285 } 1286 1287 /************************************************************************/ 1288 /* CardBus Resource */ 1289 /************************************************************************/ 1290 1291 static int 1292 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1293 { 1294 int basereg; 1295 int limitreg; 1296 1297 if ((win < 0) || (win > 1)) { 1298 DEVPRINTF((brdev, 1299 "cbb_cardbus_io_open: window out of range %d\n", win)); 1300 return (EINVAL); 1301 } 1302 1303 basereg = win * 8 + CBBR_IOBASE0; 1304 limitreg = win * 8 + CBBR_IOLIMIT0; 1305 1306 pci_write_config(brdev, basereg, start, 4); 1307 pci_write_config(brdev, limitreg, end, 4); 1308 return (0); 1309 } 1310 1311 static int 1312 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1313 { 1314 int basereg; 1315 int limitreg; 1316 1317 if ((win < 0) || (win > 1)) { 1318 DEVPRINTF((brdev, 1319 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1320 return (EINVAL); 1321 } 1322 1323 basereg = win*8 + CBBR_MEMBASE0; 1324 limitreg = win*8 + CBBR_MEMLIMIT0; 1325 1326 pci_write_config(brdev, basereg, start, 4); 1327 pci_write_config(brdev, limitreg, end, 4); 1328 return (0); 1329 } 1330 1331 /* 1332 * XXX The following function belongs in the pci bus layer. 1333 */ 1334 static void 1335 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1336 { 1337 uint32_t starts[2]; 1338 uint32_t ends[2]; 1339 struct cbb_reslist *rle; 1340 int align; 1341 int prefetchable[2]; 1342 uint32_t reg; 1343 1344 starts[0] = starts[1] = 0xffffffff; 1345 ends[0] = ends[1] = 0; 1346 1347 if (type == SYS_RES_MEMORY) 1348 align = CBB_MEMALIGN; 1349 else if (type == SYS_RES_IOPORT) 1350 align = CBB_IOALIGN; 1351 else 1352 align = 1; 1353 1354 SLIST_FOREACH(rle, &sc->rl, link) { 1355 if (rle->type != type) 1356 ; 1357 else if (rle->res == NULL) { 1358 device_printf(sc->dev, "WARNING: Resource not reserved? " 1359 "(type=%d, addr=%lx)\n", 1360 rle->type, rman_get_start(rle->res)); 1361 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1362 /* XXX */ 1363 } else if (starts[0] == 0xffffffff) { 1364 starts[0] = rman_get_start(rle->res); 1365 ends[0] = rman_get_end(rle->res); 1366 prefetchable[0] = 1367 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1368 } else if (rman_get_end(rle->res) > ends[0] && 1369 rman_get_start(rle->res) - ends[0] < 1370 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1371 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1372 ends[0] = rman_get_end(rle->res); 1373 } else if (rman_get_start(rle->res) < starts[0] && 1374 starts[0] - rman_get_end(rle->res) < 1375 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1376 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1377 starts[0] = rman_get_start(rle->res); 1378 } else if (starts[1] == 0xffffffff) { 1379 starts[1] = rman_get_start(rle->res); 1380 ends[1] = rman_get_end(rle->res); 1381 prefetchable[1] = 1382 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1383 } else if (rman_get_end(rle->res) > ends[1] && 1384 rman_get_start(rle->res) - ends[1] < 1385 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1386 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1387 ends[1] = rman_get_end(rle->res); 1388 } else if (rman_get_start(rle->res) < starts[1] && 1389 starts[1] - rman_get_end(rle->res) < 1390 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1391 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1392 starts[1] = rman_get_start(rle->res); 1393 } else { 1394 uint32_t diffs[2]; 1395 int win; 1396 1397 diffs[0] = diffs[1] = 0xffffffff; 1398 if (rman_get_start(rle->res) > ends[0]) 1399 diffs[0] = rman_get_start(rle->res) - ends[0]; 1400 else if (rman_get_end(rle->res) < starts[0]) 1401 diffs[0] = starts[0] - rman_get_end(rle->res); 1402 if (rman_get_start(rle->res) > ends[1]) 1403 diffs[1] = rman_get_start(rle->res) - ends[1]; 1404 else if (rman_get_end(rle->res) < starts[1]) 1405 diffs[1] = starts[1] - rman_get_end(rle->res); 1406 1407 win = (diffs[0] <= diffs[1])?0:1; 1408 if (rman_get_start(rle->res) > ends[win]) 1409 ends[win] = rman_get_end(rle->res); 1410 else if (rman_get_end(rle->res) < starts[win]) 1411 starts[win] = rman_get_start(rle->res); 1412 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1413 prefetchable[win] = 0; 1414 } 1415 1416 if (starts[0] != 0xffffffff) 1417 starts[0] -= starts[0] % align; 1418 if (starts[1] != 0xffffffff) 1419 starts[1] -= starts[1] % align; 1420 if (ends[0] % align != 0) 1421 ends[0] += align - ends[0]%align - 1; 1422 if (ends[1] % align != 0) 1423 ends[1] += align - ends[1]%align - 1; 1424 } 1425 1426 if (type == SYS_RES_MEMORY) { 1427 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1428 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1429 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1430 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1431 CBBM_BRIDGECTRL_PREFETCH_1); 1432 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1433 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1434 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1435 } else if (type == SYS_RES_IOPORT) { 1436 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1437 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1438 } 1439 } 1440 1441 static int 1442 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1443 int rid, struct resource *res) 1444 { 1445 int ret; 1446 1447 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1448 type, rid, res); 1449 if (ret != 0) 1450 return (ret); 1451 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1452 return (0); 1453 } 1454 1455 static int 1456 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1457 int rid, struct resource *res) 1458 { 1459 int ret; 1460 1461 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1462 type, rid, res); 1463 if (ret != 0) 1464 return (ret); 1465 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1466 return (0); 1467 } 1468 1469 static struct resource * 1470 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1471 int *rid, u_long start, u_long end, u_long count, uint flags) 1472 { 1473 struct cbb_softc *sc = device_get_softc(brdev); 1474 int tmp; 1475 struct resource *res; 1476 1477 switch (type) { 1478 case SYS_RES_IRQ: 1479 tmp = rman_get_start(sc->irq_res); 1480 if (start > tmp || end < tmp || count != 1) { 1481 device_printf(child, "requested interrupt %ld-%ld," 1482 "count = %ld not supported by cbb\n", 1483 start, end, count); 1484 return (NULL); 1485 } 1486 start = end = tmp; 1487 break; 1488 case SYS_RES_IOPORT: 1489 if (start <= cbb_start_32_io) 1490 start = cbb_start_32_io; 1491 if (end < start) 1492 end = start; 1493 break; 1494 case SYS_RES_MEMORY: 1495 if (start <= cbb_start_mem) 1496 start = cbb_start_mem; 1497 if (end < start) 1498 end = start; 1499 break; 1500 } 1501 1502 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1503 start, end, count, flags & ~RF_ACTIVE); 1504 if (res == NULL) { 1505 printf("cbb alloc res fail\n"); 1506 return (NULL); 1507 } 1508 cbb_insert_res(sc, res, type, *rid); 1509 if (flags & RF_ACTIVE) 1510 if (bus_activate_resource(child, type, *rid, res) != 0) { 1511 bus_release_resource(child, type, *rid, res); 1512 return (NULL); 1513 } 1514 1515 return (res); 1516 } 1517 1518 static int 1519 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1520 int rid, struct resource *res) 1521 { 1522 struct cbb_softc *sc = device_get_softc(brdev); 1523 int error; 1524 1525 if (rman_get_flags(res) & RF_ACTIVE) { 1526 error = bus_deactivate_resource(child, type, rid, res); 1527 if (error != 0) 1528 return (error); 1529 } 1530 cbb_remove_res(sc, res); 1531 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1532 type, rid, res)); 1533 } 1534 1535 /************************************************************************/ 1536 /* PC Card Power Functions */ 1537 /************************************************************************/ 1538 1539 static int 1540 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1541 { 1542 struct cbb_softc *sc = device_get_softc(brdev); 1543 int err; 1544 1545 DPRINTF(("cbb_pcic_socket_enable:\n")); 1546 1547 /* power down/up the socket to reset */ 1548 err = cbb_do_power(brdev); 1549 if (err) 1550 return (err); 1551 exca_reset(&sc->exca, child); 1552 1553 return (0); 1554 } 1555 1556 static void 1557 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1558 { 1559 struct cbb_softc *sc = device_get_softc(brdev); 1560 1561 DPRINTF(("cbb_pcic_socket_disable\n")); 1562 1563 /* reset signal asserting... */ 1564 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1565 DELAY(2*1000); 1566 1567 /* power down the socket */ 1568 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1569 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1570 1571 /* wait 300ms until power fails (Tpf). */ 1572 DELAY(300 * 1000); 1573 } 1574 1575 /************************************************************************/ 1576 /* POWER methods */ 1577 /************************************************************************/ 1578 1579 static int 1580 cbb_power_enable_socket(device_t brdev, device_t child) 1581 { 1582 struct cbb_softc *sc = device_get_softc(brdev); 1583 1584 if (sc->flags & CBB_16BIT_CARD) 1585 return (cbb_pcic_power_enable_socket(brdev, child)); 1586 else 1587 return (cbb_cardbus_power_enable_socket(brdev, child)); 1588 } 1589 1590 static void 1591 cbb_power_disable_socket(device_t brdev, device_t child) 1592 { 1593 struct cbb_softc *sc = device_get_softc(brdev); 1594 if (sc->flags & CBB_16BIT_CARD) 1595 cbb_pcic_power_disable_socket(brdev, child); 1596 else 1597 cbb_cardbus_power_disable_socket(brdev, child); 1598 } 1599 static int 1600 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1601 struct resource *res) 1602 { 1603 int err; 1604 struct cbb_softc *sc = device_get_softc(brdev); 1605 if (!(rman_get_flags(res) & RF_ACTIVE)) { /* not already activated */ 1606 switch (type) { 1607 case SYS_RES_IOPORT: 1608 err = exca_io_map(&sc->exca, 0, res); 1609 break; 1610 case SYS_RES_MEMORY: 1611 err = exca_mem_map(&sc->exca, 0, res); 1612 break; 1613 default: 1614 err = 0; 1615 break; 1616 } 1617 if (err) 1618 return (err); 1619 1620 } 1621 return (BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1622 type, rid, res)); 1623 } 1624 1625 static int 1626 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1627 int rid, struct resource *res) 1628 { 1629 struct cbb_softc *sc = device_get_softc(brdev); 1630 1631 if (rman_get_flags(res) & RF_ACTIVE) { /* if activated */ 1632 switch (type) { 1633 case SYS_RES_IOPORT: 1634 if (exca_io_unmap_res(&sc->exca, res)) 1635 return (ENOENT); 1636 break; 1637 case SYS_RES_MEMORY: 1638 if (exca_mem_unmap_res(&sc->exca, res)) 1639 return (ENOENT); 1640 break; 1641 } 1642 } 1643 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1644 type, rid, res)); 1645 } 1646 1647 static struct resource * 1648 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1649 u_long start, u_long end, u_long count, uint flags) 1650 { 1651 struct resource *res = NULL; 1652 struct cbb_softc *sc = device_get_softc(brdev); 1653 int tmp; 1654 1655 switch (type) { 1656 case SYS_RES_MEMORY: 1657 if (start < cbb_start_mem) 1658 start = cbb_start_mem; 1659 if (end < start) 1660 end = start; 1661 flags = (flags & ~RF_ALIGNMENT_MASK) | 1662 rman_make_alignment_flags(CBB_MEMALIGN); 1663 break; 1664 case SYS_RES_IOPORT: 1665 if (start < cbb_start_16_io) 1666 start = cbb_start_16_io; 1667 if (end < start) 1668 end = start; 1669 break; 1670 case SYS_RES_IRQ: 1671 tmp = rman_get_start(sc->irq_res); 1672 if (start > tmp || end < tmp || count != 1) { 1673 device_printf(child, "requested interrupt %ld-%ld," 1674 "count = %ld not supported by cbb\n", 1675 start, end, count); 1676 return (NULL); 1677 } 1678 flags |= RF_SHAREABLE; 1679 start = end = rman_get_start(sc->irq_res); 1680 break; 1681 } 1682 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1683 start, end, count, flags & ~RF_ACTIVE); 1684 if (res == NULL) 1685 return (NULL); 1686 cbb_insert_res(sc, res, type, *rid); 1687 if (flags & RF_ACTIVE) { 1688 if (bus_activate_resource(child, type, *rid, res) != 0) { 1689 bus_release_resource(child, type, *rid, res); 1690 return (NULL); 1691 } 1692 } 1693 1694 return (res); 1695 } 1696 1697 static int 1698 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1699 int rid, struct resource *res) 1700 { 1701 struct cbb_softc *sc = device_get_softc(brdev); 1702 int error; 1703 1704 if (rman_get_flags(res) & RF_ACTIVE) { 1705 error = bus_deactivate_resource(child, type, rid, res); 1706 if (error != 0) 1707 return (error); 1708 } 1709 cbb_remove_res(sc, res); 1710 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1711 type, rid, res)); 1712 } 1713 1714 /************************************************************************/ 1715 /* PC Card methods */ 1716 /************************************************************************/ 1717 1718 static int 1719 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1720 uint32_t flags) 1721 { 1722 struct cbb_softc *sc = device_get_softc(brdev); 1723 struct resource *res; 1724 1725 if (type != SYS_RES_MEMORY) 1726 return (EINVAL); 1727 res = cbb_find_res(sc, type, rid); 1728 if (res == NULL) { 1729 device_printf(brdev, 1730 "set_res_flags: specified rid not found\n"); 1731 return (ENOENT); 1732 } 1733 return (exca_mem_set_flags(&sc->exca, res, flags)); 1734 } 1735 1736 static int 1737 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1738 uint32_t cardaddr, uint32_t *deltap) 1739 { 1740 struct cbb_softc *sc = device_get_softc(brdev); 1741 struct resource *res; 1742 1743 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1744 if (res == NULL) { 1745 device_printf(brdev, 1746 "set_memory_offset: specified rid not found\n"); 1747 return (ENOENT); 1748 } 1749 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1750 } 1751 1752 /************************************************************************/ 1753 /* BUS Methods */ 1754 /************************************************************************/ 1755 1756 1757 static int 1758 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1759 struct resource *r) 1760 { 1761 struct cbb_softc *sc = device_get_softc(brdev); 1762 1763 if (sc->flags & CBB_16BIT_CARD) 1764 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1765 else 1766 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1767 r)); 1768 } 1769 1770 static int 1771 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1772 int rid, struct resource *r) 1773 { 1774 struct cbb_softc *sc = device_get_softc(brdev); 1775 1776 if (sc->flags & CBB_16BIT_CARD) 1777 return (cbb_pcic_deactivate_resource(brdev, child, type, 1778 rid, r)); 1779 else 1780 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1781 rid, r)); 1782 } 1783 1784 static struct resource * 1785 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1786 u_long start, u_long end, u_long count, uint flags) 1787 { 1788 struct cbb_softc *sc = device_get_softc(brdev); 1789 1790 if (sc->flags & CBB_16BIT_CARD) 1791 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1792 start, end, count, flags)); 1793 else 1794 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1795 start, end, count, flags)); 1796 } 1797 1798 static int 1799 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1800 struct resource *r) 1801 { 1802 struct cbb_softc *sc = device_get_softc(brdev); 1803 1804 if (sc->flags & CBB_16BIT_CARD) 1805 return (cbb_pcic_release_resource(brdev, child, type, 1806 rid, r)); 1807 else 1808 return (cbb_cardbus_release_resource(brdev, child, type, 1809 rid, r)); 1810 } 1811 1812 static int 1813 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1814 { 1815 struct cbb_softc *sc = device_get_softc(brdev); 1816 1817 switch (which) { 1818 case PCIB_IVAR_BUS: 1819 *result = sc->secbus; 1820 return (0); 1821 } 1822 return (ENOENT); 1823 } 1824 1825 static int 1826 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1827 { 1828 struct cbb_softc *sc = device_get_softc(brdev); 1829 1830 switch (which) { 1831 case PCIB_IVAR_BUS: 1832 sc->secbus = value; 1833 break; 1834 } 1835 return (ENOENT); 1836 } 1837 1838 /************************************************************************/ 1839 /* PCI compat methods */ 1840 /************************************************************************/ 1841 1842 static int 1843 cbb_maxslots(device_t brdev) 1844 { 1845 return (0); 1846 } 1847 1848 static uint32_t 1849 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1850 { 1851 /* 1852 * Pass through to the next ppb up the chain (i.e. our grandparent). 1853 */ 1854 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1855 b, s, f, reg, width)); 1856 } 1857 1858 static void 1859 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1860 int width) 1861 { 1862 /* 1863 * Pass through to the next ppb up the chain (i.e. our grandparent). 1864 */ 1865 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1866 b, s, f, reg, val, width); 1867 } 1868 1869 static int 1870 cbb_suspend(device_t self) 1871 { 1872 int error = 0; 1873 struct cbb_softc *sc = device_get_softc(self); 1874 1875 cbb_setb(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1876 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1877 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1878 error = bus_generic_suspend(self); 1879 return (error); 1880 } 1881 1882 static int 1883 cbb_resume(device_t self) 1884 { 1885 int error = 0; 1886 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1887 uint32_t tmp; 1888 1889 /* 1890 * Some BIOSes will not save the BARs for the pci chips, so we 1891 * must do it ourselves. If the BAR is reset to 0 for an I/O 1892 * device, it will read back as 0x1, so no explicit test for 1893 * memory devices are needed. 1894 * 1895 * Note: The PCI bus code should do this automatically for us on 1896 * suspend/resume, but until it does, we have to cope. 1897 */ 1898 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1899 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1900 rman_get_start(sc->base_res))); 1901 1902 cbb_chipinit(sc); 1903 1904 /* reset interrupt -- Do we really need to do this? */ 1905 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1906 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1907 1908 /* re-establish the interrupt. */ 1909 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 1910 &sc->intrhand)) { 1911 device_printf(self, "couldn't re-establish interrupt"); 1912 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1913 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1914 sc->base_res); 1915 sc->irq_res = NULL; 1916 sc->base_res = NULL; 1917 return (ENOMEM); 1918 } 1919 1920 /* CSC Interrupt: Card detect interrupt on */ 1921 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1922 1923 /* Signal the thread to wakeup. */ 1924 mtx_lock(&sc->mtx); 1925 cv_signal(&sc->cv); 1926 mtx_unlock(&sc->mtx); 1927 1928 error = bus_generic_resume(self); 1929 1930 return (error); 1931 } 1932 1933 static device_method_t cbb_methods[] = { 1934 /* Device interface */ 1935 DEVMETHOD(device_probe, cbb_probe), 1936 DEVMETHOD(device_attach, cbb_attach), 1937 DEVMETHOD(device_detach, cbb_detach), 1938 DEVMETHOD(device_shutdown, cbb_shutdown), 1939 DEVMETHOD(device_suspend, cbb_suspend), 1940 DEVMETHOD(device_resume, cbb_resume), 1941 1942 /* bus methods */ 1943 DEVMETHOD(bus_print_child, bus_generic_print_child), 1944 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 1945 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 1946 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 1947 DEVMETHOD(bus_release_resource, cbb_release_resource), 1948 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 1949 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 1950 DEVMETHOD(bus_driver_added, cbb_driver_added), 1951 DEVMETHOD(bus_child_detached, cbb_child_detached), 1952 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 1953 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 1954 1955 /* 16-bit card interface */ 1956 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 1957 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 1958 1959 /* power interface */ 1960 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 1961 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 1962 1963 /* pcib compatibility interface */ 1964 DEVMETHOD(pcib_maxslots, cbb_maxslots), 1965 DEVMETHOD(pcib_read_config, cbb_read_config), 1966 DEVMETHOD(pcib_write_config, cbb_write_config), 1967 {0,0} 1968 }; 1969 1970 static driver_t cbb_driver = { 1971 "cbb", 1972 cbb_methods, 1973 sizeof(struct cbb_softc) 1974 }; 1975 1976 static devclass_t cbb_devclass; 1977 1978 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 1979 MODULE_VERSION(cbb, 1); 1980 MODULE_DEPEND(cbb, exca, 1, 1, 1); 1981