1 /* 2 * Copyright (c) 2002 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for PCI to CardBus Bridge chips 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 93 #include <pci/pcireg.h> 94 #include <pci/pcivar.h> 95 #include <machine/clock.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 #define CBB_START_MEM 0x88000000 120 #define CBB_START_32_IO 0x1000 121 #define CBB_START_16_IO 0x100 122 123 struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 155 /* Ricoh chips */ 156 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 157 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 158 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 159 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 160 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 161 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 162 163 /* Toshiba products */ 164 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 165 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 166 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 167 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 168 169 /* Cirrus Logic */ 170 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 171 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 172 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 173 174 /* 02Micro */ 175 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 176 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 177 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 178 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 179 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 180 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 181 182 /* sentinel */ 183 {0 /* null id */, "unknown", CB_UNKNOWN}, 184 }; 185 186 /* sysctl vars */ 187 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 188 189 /* There's no way to say TUNEABLE_LONG to get the right types */ 190 u_long cbb_start_mem = CBB_START_MEM; 191 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 192 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 193 &cbb_start_mem, CBB_START_MEM, 194 "Starting address for memory allocations"); 195 196 u_long cbb_start_16_io = CBB_START_16_IO; 197 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 198 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 199 &cbb_start_16_io, CBB_START_16_IO, 200 "Starting ioport for 16-bit cards"); 201 202 u_long cbb_start_32_io = CBB_START_32_IO; 203 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 205 &cbb_start_32_io, CBB_START_32_IO, 206 "Starting ioport for 32-bit cards"); 207 208 int cbb_debug = 0; 209 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 211 "Verbose cardbus bridge debugging"); 212 213 static int cbb_chipset(uint32_t pci_id, const char **namep); 214 static int cbb_probe(device_t brdev); 215 static void cbb_chipinit(struct cbb_softc *sc); 216 static int cbb_attach(device_t brdev); 217 static int cbb_detach(device_t brdev); 218 static int cbb_shutdown(device_t brdev); 219 static void cbb_driver_added(device_t brdev, driver_t *driver); 220 static void cbb_child_detached(device_t brdev, device_t child); 221 static void cbb_event_thread(void *arg); 222 static void cbb_insert(struct cbb_softc *sc); 223 static void cbb_removal(struct cbb_softc *sc); 224 static void cbb_intr(void *arg); 225 static int cbb_detect_voltage(device_t brdev); 226 static int cbb_power(device_t brdev, int volts); 227 static void cbb_cardbus_reset(device_t brdev); 228 static int cbb_cardbus_power_enable_socket(device_t brdev, 229 device_t child); 230 static void cbb_cardbus_power_disable_socket(device_t brdev, 231 device_t child); 232 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 233 uint32_t end); 234 static int cbb_cardbus_mem_open(device_t brdev, int win, 235 uint32_t start, uint32_t end); 236 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 237 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 238 int type, int rid, struct resource *res); 239 static int cbb_cardbus_deactivate_resource(device_t brdev, 240 device_t child, int type, int rid, struct resource *res); 241 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 242 device_t child, int type, int *rid, u_long start, 243 u_long end, u_long count, uint flags); 244 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 245 int type, int rid, struct resource *res); 246 static int cbb_power_enable_socket(device_t brdev, device_t child); 247 static void cbb_power_disable_socket(device_t brdev, device_t child); 248 static int cbb_activate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *r); 250 static int cbb_deactivate_resource(device_t brdev, device_t child, 251 int type, int rid, struct resource *r); 252 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 253 int type, int *rid, u_long start, u_long end, u_long count, 254 uint flags); 255 static int cbb_release_resource(device_t brdev, device_t child, 256 int type, int rid, struct resource *r); 257 static int cbb_read_ivar(device_t brdev, device_t child, int which, 258 uintptr_t *result); 259 static int cbb_write_ivar(device_t brdev, device_t child, int which, 260 uintptr_t value); 261 static int cbb_maxslots(device_t brdev); 262 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 263 int reg, int width); 264 static void cbb_write_config(device_t brdev, int b, int s, int f, 265 int reg, uint32_t val, int width); 266 267 /* 268 */ 269 static __inline void 270 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 271 { 272 bus_space_write_4(sc->bst, sc->bsh, reg, val); 273 } 274 275 static __inline uint32_t 276 cbb_get(struct cbb_softc *sc, uint32_t reg) 277 { 278 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 279 } 280 281 static __inline void 282 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 283 { 284 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 285 } 286 287 static __inline void 288 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 289 { 290 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 291 } 292 293 static void 294 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 295 { 296 struct cbb_reslist *rle; 297 298 SLIST_FOREACH(rle, &sc->rl, link) { 299 if (rle->res == res) { 300 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 301 free(rle, M_DEVBUF); 302 return; 303 } 304 } 305 } 306 307 static struct resource * 308 cbb_find_res(struct cbb_softc *sc, int type, int rid) 309 { 310 struct cbb_reslist *rle; 311 312 SLIST_FOREACH(rle, &sc->rl, link) 313 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 314 return (rle->res); 315 return (NULL); 316 } 317 318 static void 319 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 320 int rid) 321 { 322 struct cbb_reslist *rle; 323 324 /* 325 * Need to record allocated resource so we can iterate through 326 * it later. 327 */ 328 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 329 if (!res) 330 panic("cbb_cardbus_alloc_resource: can't record entry!"); 331 rle->res = res; 332 rle->type = type; 333 rle->rid = rid; 334 SLIST_INSERT_HEAD(&sc->rl, rle, link); 335 } 336 337 static void 338 cbb_destroy_res(struct cbb_softc *sc) 339 { 340 struct cbb_reslist *rle; 341 342 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 343 device_printf(sc->dev, "Danger Will Robinson: Resource " 344 "left allocated! This is a bug... " 345 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 346 rman_get_start(rle->res)); 347 SLIST_REMOVE_HEAD(&sc->rl, link); 348 free(rle, M_DEVBUF); 349 } 350 } 351 352 /************************************************************************/ 353 /* Probe/Attach */ 354 /************************************************************************/ 355 356 static int 357 cbb_chipset(uint32_t pci_id, const char **namep) 358 { 359 struct yenta_chipinfo *ycp; 360 361 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 362 continue; 363 if (namep != NULL) 364 *namep = ycp->yc_name; 365 return (ycp->yc_chiptype); 366 } 367 368 static int 369 cbb_probe(device_t brdev) 370 { 371 const char *name; 372 uint32_t progif; 373 uint32_t subclass; 374 375 /* 376 * Do we know that we support the chipset? If so, then we 377 * accept the device. 378 */ 379 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 380 device_set_desc(brdev, name); 381 return (0); 382 } 383 384 /* 385 * We do support generic CardBus bridges. All that we've seen 386 * to date have progif 0 (the Yenta spec, and successors mandate 387 * this). We do not support PCI PCMCIA bridges (with one exception) 388 * with this driver since they generally are I/O mapped. Those 389 * are supported by the pcic driver. This should help us be more 390 * future proof. 391 */ 392 subclass = pci_get_subclass(brdev); 393 progif = pci_get_progif(brdev); 394 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 395 device_set_desc(brdev, "PCI-CardBus Bridge"); 396 return (0); 397 } 398 return (ENXIO); 399 } 400 401 402 static void 403 cbb_chipinit(struct cbb_softc *sc) 404 { 405 uint32_t mux, sysctrl, reg; 406 407 /* Set CardBus latency timer */ 408 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 409 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 410 411 /* Set PCI latency timer */ 412 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 413 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 414 415 /* Enable memory access */ 416 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 417 | PCIM_CMD_MEMEN 418 | PCIM_CMD_PORTEN 419 | PCIM_CMD_BUSMASTEREN, 2); 420 421 /* disable Legacy IO */ 422 switch (sc->chipset) { 423 case CB_RF5C46X: 424 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 425 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 426 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 427 break; 428 default: 429 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 430 break; 431 } 432 433 /* Use PCI interrupt for interrupt routing */ 434 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 435 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 436 CBBM_BRIDGECTRL_INTR_IREQ_EN), 437 | CBBM_BRIDGECTRL_WRITE_POST_EN, 438 2); 439 440 /* 441 * XXX this should be a function table, ala OLDCARD. This means 442 * that we could more easily support ISA interrupts for pccard 443 * cards if we had to. 444 */ 445 switch (sc->chipset) { 446 case CB_TI113X: 447 /* 448 * The TI 1031, TI 1130 and TI 1131 all require another bit 449 * be set to enable PCI routing of interrupts, and then 450 * a bit for each of the CSC and Function interrupts we 451 * want routed. 452 */ 453 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 454 | CBBM_CBCTRL_113X_PCI_INTR | 455 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 456 1); 457 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 458 & ~(CBBM_DEVCTRL_INT_SERIAL | 459 CBBM_DEVCTRL_INT_PCI), 1); 460 break; 461 case CB_TI12XX: 462 /* 463 * Some TI 12xx (and [14][45]xx) based pci cards 464 * sometimes have issues with the MFUNC register not 465 * being initialized due to a bad EEPROM on board. 466 * Laptops that this matters on have this register 467 * properly initialized. 468 * 469 * The TI125X parts have a different register. 470 */ 471 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 472 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 473 if (mux == 0) { 474 mux = (mux & ~CBBM_MFUNC_PIN0) | 475 CBBM_MFUNC_PIN0_INTA; 476 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 477 mux = (mux & ~CBBM_MFUNC_PIN1) | 478 CBBM_MFUNC_PIN1_INTB; 479 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 480 } 481 /*FALLTHROUGH*/ 482 case CB_TI125X: 483 /* 484 * Disable zoom video. Some machines initialize this 485 * improperly and exerpience has shown that this helps 486 * on some machines. 487 */ 488 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 489 break; 490 case CB_O2MICRO: 491 /* 492 * Issue #1: INT# generated at the same time as 493 * selected ISA IRQ. When IREQ# or STSCHG# is active, 494 * in addition to the ISA IRQ being generated, INT# 495 * will also be generated at the same time. 496 * 497 * Some of our older controllers have an issue in 498 * which the slot's PCI INT# will be asserted whenever 499 * IREQ# or STSCGH# is asserted even if ExCA registers 500 * 03h or 05h have an ISA IRQ selected. 501 * 502 * The fix for this issue, which will work for any 503 * controller (old or new), is to set ExCA registers 504 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 505 * These bits are undocumented. By setting this 506 * register (of each slot) to '1010xxxxb' a routing of 507 * IREQ# to INTC# and STSCHG# to INTC# is selected. 508 * Since INTC# isn't connected there will be no 509 * unexpected PCI INT when IREQ# or STSCHG# is active. 510 * However, INTA# (slot 0) or INTB# (slot 1) will 511 * still be correctly generated if NO ISA IRQ is 512 * selected (ExCA regs 03h or 05h are cleared). 513 */ 514 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 515 reg = (reg & 0x0f) | 516 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 517 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 518 519 break; 520 case CB_TOPIC97: 521 /* 522 * Disable Zoom Video, ToPIC 97, 100. 523 */ 524 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 525 /* 526 * ToPIC 97, 100 527 * At offset 0xa1: INTERRUPT CONTROL register 528 * 0x1: Turn on INT interrupts. 529 */ 530 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 531 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 532 goto topic_common; 533 case CB_TOPIC95: 534 /* 535 * SOCKETCTRL appears to be TOPIC 95/B specific 536 */ 537 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 538 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 539 540 topic_common:; 541 /* 542 * At offset 0xa0: SLOT CONTROL 543 * 0x80 Enable CardBus Functionality 544 * 0x40 Enable CardBus and PC Card registers 545 * 0x20 Lock ID in exca regs 546 * 0x10 Write protect ID in config regs 547 * Clear the rest of the bits, which defaults the slot 548 * in legacy mode to 0x3e0 and offset 0. (legacy 549 * mode is determined elsewhere) 550 */ 551 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 552 CBBM_TOPIC_SLOTCTRL_SLOTON | 553 CBBM_TOPIC_SLOTCTRL_SLOTEN | 554 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 555 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 556 557 /* 558 * At offset 0xa3 Card Detect Control Register 559 * 0x80 CARDBUS enbale 560 * 0x01 Cleared for hardware change detect 561 */ 562 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 563 | CBBM_TOPIC_CDC_CARDBUS, 564 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 565 break; 566 } 567 568 /* 569 * Need to tell ExCA registers to route via PCI interrupts. There 570 * are two ways to do this. Once is to set INTR_ENABLE and the 571 * other is to set CSC to 0. Since both methods are mutually 572 * compatible, we do both. 573 */ 574 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 575 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 576 577 /* close all memory and io windows */ 578 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 579 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 580 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 581 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 582 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 583 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 584 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 585 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 586 } 587 588 #ifndef BURN_BRIDGES 589 static void 590 cbb_powerstate_d0(device_t dev) 591 { 592 u_int32_t membase, irq; 593 594 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 595 /* Save important PCI config data. */ 596 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 597 irq = pci_read_config(dev, PCIR_INTLINE, 4); 598 599 /* Reset the power state. */ 600 device_printf(dev, "chip is in D%d power mode " 601 "-- setting to D0\n", pci_get_powerstate(dev)); 602 603 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 604 605 /* Restore PCI config data. */ 606 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 607 pci_write_config(dev, PCIR_INTLINE, irq, 4); 608 } 609 } 610 #endif 611 612 /* 613 * Print out the config space 614 */ 615 static void 616 cbb_print_config(device_t dev) 617 { 618 int i; 619 620 device_printf(dev, "PCI Configuration space:"); 621 for (i = 0; i < 256; i += 4) { 622 if (i % 16 == 0) 623 printf("\n 0x%02x: ", i); 624 printf("0x%08x ", pci_read_config(dev, i, 4)); 625 } 626 printf("\n"); 627 } 628 629 static int 630 cbb_attach(device_t brdev) 631 { 632 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 633 int rid; 634 635 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 636 cv_init(&sc->cv, "cbb cv"); 637 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 638 sc->dev = brdev; 639 sc->cbdev = NULL; 640 sc->exca.pccarddev = NULL; 641 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 642 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 643 SLIST_INIT(&sc->rl); 644 STAILQ_INIT(&sc->intr_handlers); 645 #ifndef BURN_BRIDGES 646 cbb_powerstate_d0(brdev); 647 648 /* 649 * The PCI bus code should assign us memory in the absense 650 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 651 * up something here until the PCI/acpi code properly assigns the 652 * resource. 653 */ 654 #endif 655 rid = CBBR_SOCKBASE; 656 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 657 0, ~0, 1, RF_ACTIVE); 658 if (!sc->base_res) { 659 #ifdef BURN_BRIDGES 660 device_printf(brdev, "Could not map register memory\n"); 661 mtx_destroy(&sc->mtx); 662 cv_destroy(&sc->cv); 663 return (ENOMEM); 664 #else 665 uint32_t sockbase; 666 /* 667 * Generally, the BIOS will assign this memory for us. 668 * However, newer BIOSes do not because the MS design 669 * documents have mandated that this is for the OS 670 * to assign rather than the BIOS. This driver shouldn't 671 * be doing this, but until the pci bus code (or acpi) 672 * does this, we allow CardBus bridges to work on more 673 * machines. 674 */ 675 pci_write_config(brdev, rid, 0xfffffffful, 4); 676 sockbase = pci_read_config(brdev, rid, 4); 677 sockbase = (sockbase & 0xfffffff0ul) & 678 -(sockbase & 0xfffffff0ul); 679 sc->base_res = bus_generic_alloc_resource( 680 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 681 &rid, cbb_start_mem, ~0, sockbase, 682 RF_ACTIVE | rman_make_alignment_flags(sockbase)); 683 if (!sc->base_res) { 684 device_printf(brdev, 685 "Could not grab register memory\n"); 686 mtx_destroy(&sc->mtx); 687 cv_destroy(&sc->cv); 688 return (ENOMEM); 689 } 690 sc->flags |= CBB_KLUDGE_ALLOC; 691 pci_write_config(brdev, CBBR_SOCKBASE, 692 rman_get_start(sc->base_res), 4); 693 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 694 rman_get_start(sc->base_res))); 695 #endif 696 } else { 697 DEVPRINTF((brdev, "Found memory at %08lx\n", 698 rman_get_start(sc->base_res))); 699 } 700 701 sc->bst = rman_get_bustag(sc->base_res); 702 sc->bsh = rman_get_bushandle(sc->base_res); 703 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 704 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 705 sc->exca.chipset = EXCA_CARDBUS; 706 cbb_chipinit(sc); 707 708 /* attach children */ 709 sc->cbdev = device_add_child(brdev, "cardbus", -1); 710 if (sc->cbdev == NULL) 711 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 712 else if (device_probe_and_attach(sc->cbdev) != 0) { 713 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 714 sc->cbdev = NULL; 715 } 716 717 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 718 if (sc->exca.pccarddev == NULL) 719 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 720 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) { 721 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 722 sc->exca.pccarddev = NULL; 723 } 724 725 /* Map and establish the interrupt. */ 726 rid = 0; 727 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 728 RF_SHAREABLE | RF_ACTIVE); 729 if (sc->irq_res == NULL) { 730 printf("cbb: Unable to map IRQ...\n"); 731 goto err; 732 } 733 734 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 735 cbb_intr, sc, &sc->intrhand)) { 736 device_printf(brdev, "couldn't establish interrupt"); 737 goto err; 738 } 739 740 /* reset 16-bit pcmcia bus */ 741 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 742 743 /* turn off power */ 744 cbb_power(brdev, CARD_OFF); 745 746 /* CSC Interrupt: Card detect interrupt on */ 747 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 748 749 /* reset interrupt */ 750 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 751 752 if (bootverbose) 753 cbb_print_config(brdev); 754 755 /* Start the thread */ 756 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 757 "%s%d", device_get_name(brdev), device_get_unit(brdev))) { 758 device_printf(brdev, "unable to create event thread.\n"); 759 panic("cbb_create_event_thread"); 760 } 761 762 return (0); 763 err: 764 if (sc->irq_res) 765 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 766 if (sc->base_res) { 767 if (sc->flags & CBB_KLUDGE_ALLOC) 768 bus_generic_release_resource(device_get_parent(brdev), 769 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 770 sc->base_res); 771 else 772 bus_release_resource(brdev, SYS_RES_MEMORY, 773 CBBR_SOCKBASE, sc->base_res); 774 } 775 mtx_destroy(&sc->mtx); 776 cv_destroy(&sc->cv); 777 return (ENOMEM); 778 } 779 780 static int 781 cbb_detach(device_t brdev) 782 { 783 struct cbb_softc *sc = device_get_softc(brdev); 784 int numdevs; 785 device_t *devlist; 786 int tmp; 787 int error; 788 789 device_get_children(brdev, &devlist, &numdevs); 790 791 error = 0; 792 for (tmp = 0; tmp < numdevs; tmp++) { 793 if (device_detach(devlist[tmp]) == 0) 794 device_delete_child(brdev, devlist[tmp]); 795 else 796 error++; 797 } 798 free(devlist, M_TEMP); 799 if (error > 0) 800 return (ENXIO); 801 802 mtx_lock(&sc->mtx); 803 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 804 sc->flags |= CBB_KTHREAD_DONE; 805 if (sc->flags & CBB_KTHREAD_RUNNING) { 806 cv_broadcast(&sc->cv); 807 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 808 } 809 mtx_unlock(&sc->mtx); 810 811 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 812 if (sc->flags & CBB_KLUDGE_ALLOC) 813 bus_generic_release_resource(device_get_parent(brdev), 814 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, sc->base_res); 815 else 816 bus_release_resource(brdev, SYS_RES_MEMORY, 817 CBBR_SOCKBASE, sc->base_res); 818 mtx_destroy(&sc->mtx); 819 cv_destroy(&sc->cv); 820 return (0); 821 } 822 823 static int 824 cbb_shutdown(device_t brdev) 825 { 826 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 827 /* properly reset everything at shutdown */ 828 829 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 830 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 831 832 cbb_set(sc, CBB_SOCKET_MASK, 0); 833 834 cbb_power(brdev, CARD_OFF); 835 836 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 837 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 838 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 839 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 840 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 841 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 842 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 843 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 844 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 845 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 846 return (0); 847 } 848 849 static int 850 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 851 int flags, driver_intr_t *intr, void *arg, void **cookiep) 852 { 853 struct cbb_intrhand *ih; 854 struct cbb_softc *sc = device_get_softc(dev); 855 856 /* 857 * You aren't allowed to have fast interrupts for pccard/cardbus 858 * things since those interrupts are PCI and shared. Since we use 859 * the PCI interrupt for the status change interrupts, it can't be 860 * free for use by the driver. Fast interrupts must not be shared. 861 */ 862 if ((flags & INTR_FAST) != 0) 863 return (EINVAL); 864 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 865 if (ih == NULL) 866 return (ENOMEM); 867 *cookiep = ih; 868 ih->intr = intr; 869 ih->arg = arg; 870 ih->flags = flags & INTR_MPSAFE; 871 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 872 /* 873 * XXX need to turn on ISA interrupts, if we ever support them, but 874 * XXX for now that's all we need to do. 875 */ 876 return (0); 877 } 878 879 static int 880 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 881 void *cookie) 882 { 883 struct cbb_intrhand *ih; 884 struct cbb_softc *sc = device_get_softc(dev); 885 886 /* XXX Need to do different things for ISA interrupts. */ 887 ih = (struct cbb_intrhand *) cookie; 888 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 889 free(ih, M_DEVBUF); 890 return (0); 891 } 892 893 894 static void 895 cbb_driver_added(device_t brdev, driver_t *driver) 896 { 897 struct cbb_softc *sc = device_get_softc(brdev); 898 device_t *devlist; 899 device_t dev; 900 int tmp; 901 int numdevs; 902 int wake = 0; 903 904 DEVICE_IDENTIFY(driver, brdev); 905 device_get_children(brdev, &devlist, &numdevs); 906 for (tmp = 0; tmp < numdevs; tmp++) { 907 dev = devlist[tmp]; 908 if (device_get_state(dev) == DS_NOTPRESENT && 909 device_probe_and_attach(dev) == 0) 910 wake++; 911 } 912 free(devlist, M_TEMP); 913 914 if (wake > 0) { 915 mtx_lock(&sc->mtx); 916 cv_signal(&sc->cv); 917 mtx_unlock(&sc->mtx); 918 } 919 } 920 921 static void 922 cbb_child_detached(device_t brdev, device_t child) 923 { 924 struct cbb_softc *sc = device_get_softc(brdev); 925 926 if (child != sc->cbdev && child != sc->exca.pccarddev) 927 device_printf(brdev, "Unknown child detached: %s\n", 928 device_get_nameunit(child)); 929 } 930 931 /************************************************************************/ 932 /* Kthreads */ 933 /************************************************************************/ 934 935 static void 936 cbb_event_thread(void *arg) 937 { 938 struct cbb_softc *sc = arg; 939 uint32_t status; 940 int err; 941 942 sc->flags |= CBB_KTHREAD_RUNNING; 943 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 944 /* 945 * We take out Giant here because we need it deep, 946 * down in the bowels of the vm system for mapping the 947 * memory we need to read the CIS. In addition, since 948 * we are adding/deleting devices from the dev tree, 949 * and that code isn't MP safe, we have to hold Giant. 950 */ 951 mtx_lock(&Giant); 952 status = cbb_get(sc, CBB_SOCKET_STATE); 953 if ((status & CBB_SOCKET_STAT_CD) == 0) 954 cbb_insert(sc); 955 else 956 cbb_removal(sc); 957 mtx_unlock(&Giant); 958 959 /* 960 * In our ISR, we turn off the card changed interrupt. Turn 961 * them back on here before we wait for them to happen. We 962 * turn them on/off so that we can tolerate a large latency 963 * between the time we signal cbb_event_thread and it gets 964 * a chance to run. 965 */ 966 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 967 968 /* 969 * Wait until it has been 1s since the last time we 970 * get an interrupt. We handle the rest of the interrupt 971 * at the top of the loop. Although we clear the bit in the 972 * ISR, we signal sc->cv from the detach path after we've 973 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 974 * 1s sleep here. 975 */ 976 mtx_lock(&sc->mtx); 977 cv_wait(&sc->cv, &sc->mtx); 978 err = 0; 979 while (err != EWOULDBLOCK && 980 (sc->flags & CBB_KTHREAD_DONE) == 0) 981 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 982 mtx_unlock(&sc->mtx); 983 } 984 sc->flags &= ~CBB_KTHREAD_RUNNING; 985 mtx_lock(&Giant); /* kthread_exit drops */ 986 kthread_exit(0); 987 } 988 989 /************************************************************************/ 990 /* Insert/removal */ 991 /************************************************************************/ 992 993 static void 994 cbb_insert(struct cbb_softc *sc) 995 { 996 uint32_t sockevent, sockstate; 997 998 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 999 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1000 1001 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1002 sockevent, sockstate)); 1003 1004 if (sockstate & CBB_SOCKET_STAT_16BIT) { 1005 if (sc->exca.pccarddev) 1006 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1007 exca_insert(&sc->exca); 1008 } else if (sockstate & CBB_SOCKET_STAT_CB) { 1009 if (sc->cbdev != NULL) { 1010 sc->flags &= ~CBB_16BIT_CARD; 1011 sc->flags |= CBB_CARD_OK; 1012 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1013 device_printf(sc->dev, 1014 "CardBus card activation failed\n"); 1015 } else { 1016 device_printf(sc->dev, 1017 "CardBus card inserted, but no cardbus bus.\n"); 1018 } 1019 } else { 1020 /* 1021 * We should power the card down, and try again a couple of 1022 * times if this happens. XXX 1023 */ 1024 device_printf(sc->dev, "Unsupported card type detected\n"); 1025 } 1026 } 1027 1028 static void 1029 cbb_removal(struct cbb_softc *sc) 1030 { 1031 if (sc->flags & CBB_16BIT_CARD) { 1032 exca_removal(&sc->exca); 1033 } else { 1034 if (sc->cbdev != NULL) 1035 CARD_DETACH_CARD(sc->cbdev); 1036 } 1037 cbb_destroy_res(sc); 1038 } 1039 1040 /************************************************************************/ 1041 /* Interrupt Handler */ 1042 /************************************************************************/ 1043 1044 static void 1045 cbb_intr(void *arg) 1046 { 1047 struct cbb_softc *sc = arg; 1048 uint32_t sockevent; 1049 struct cbb_intrhand *ih; 1050 1051 /* 1052 * This ISR needs work XXX 1053 */ 1054 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1055 if (sockevent) { 1056 /* ack the interrupt */ 1057 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1058 1059 /* 1060 * If anything has happened to the socket, we assume that 1061 * the card is no longer OK, and we shouldn't call its 1062 * ISR. We set CARD_OK as soon as we've attached the 1063 * card. This helps in a noisy eject, which happens 1064 * all too often when users are ejecting their PC Cards. 1065 * 1066 * We use this method in preference to checking to see if 1067 * the card is still there because the check suffers from 1068 * a race condition in the bouncing case. Prior versions 1069 * of the pccard software used a similar trick and achieved 1070 * excellent results. 1071 */ 1072 if (sockevent & CBB_SOCKET_EVENT_CD) { 1073 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1074 mtx_lock(&sc->mtx); 1075 sc->flags &= ~CBB_CARD_OK; 1076 cv_signal(&sc->cv); 1077 mtx_unlock(&sc->mtx); 1078 } 1079 if (sockevent & CBB_SOCKET_EVENT_CSTS) { 1080 DPRINTF((" cstsevent occured: 0x%08x\n", 1081 cbb_get(sc, CBB_SOCKET_STATE))); 1082 } 1083 if (sockevent & CBB_SOCKET_EVENT_POWER) { 1084 DPRINTF((" pwrevent occured: 0x%08x\n", 1085 cbb_get(sc, CBB_SOCKET_STATE))); 1086 } 1087 /* Other bits? */ 1088 } 1089 if (sc->flags & CBB_CARD_OK) { 1090 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1091 if ((ih->flags & INTR_MPSAFE) != 0) 1092 mtx_lock(&Giant); 1093 (*ih->intr)(ih->arg); 1094 if ((ih->flags & INTR_MPSAFE) != 0) 1095 mtx_unlock(&Giant); 1096 } 1097 } 1098 } 1099 1100 /************************************************************************/ 1101 /* Generic Power functions */ 1102 /************************************************************************/ 1103 1104 static int 1105 cbb_detect_voltage(device_t brdev) 1106 { 1107 struct cbb_softc *sc = device_get_softc(brdev); 1108 uint32_t psr; 1109 int vol = CARD_UKN_CARD; 1110 1111 psr = cbb_get(sc, CBB_SOCKET_STATE); 1112 1113 if (psr & CBB_SOCKET_STAT_5VCARD) 1114 vol |= CARD_5V_CARD; 1115 if (psr & CBB_SOCKET_STAT_3VCARD) 1116 vol |= CARD_3V_CARD; 1117 if (psr & CBB_SOCKET_STAT_XVCARD) 1118 vol |= CARD_XV_CARD; 1119 if (psr & CBB_SOCKET_STAT_YVCARD) 1120 vol |= CARD_YV_CARD; 1121 1122 return (vol); 1123 } 1124 1125 static uint8_t 1126 cbb_o2micro_power_hack(struct cbb_softc *sc) 1127 { 1128 uint8_t reg; 1129 1130 /* 1131 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1132 * unexpected PCI INT# may be generated during PC-Card 1133 * initialization even with the IRQ Routing Bit Set with some 1134 * PC-Cards. 1135 * 1136 * This is a two part issue. The first part is that some of 1137 * our older controllers have an issue in which the slot's PCI 1138 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1139 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1140 * is selected (ExCA register 03h bits 3:0, of the slot, are 1141 * cleared) we will generate INT# if IREQ# is asserted. The 1142 * second part is because some PC-Cards prematurally assert 1143 * IREQ# before the ExCA registers are fully programmed. This 1144 * in turn asserts INT# because ExCA register 03h bits 3:0 1145 * (ISA IRQ Select) are not yet programmed. 1146 * 1147 * The fix for this issue, which will work for any controller 1148 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1149 * (select IRQ1), of the slot, before turning on slot power. 1150 * Selecting IRQ1 will result in INT# NOT being asserted 1151 * (because IRQ1 is selected), and IRQ1 won't be asserted 1152 * because our controllers don't generate IRQ1. 1153 */ 1154 reg = exca_getb(&sc->exca, EXCA_INTR); 1155 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1156 return (reg); 1157 } 1158 1159 /* 1160 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1161 * we don't have an interrupt storm on power on. This has the efect of 1162 * disabling card status change interrupts for the duration of poweron. 1163 */ 1164 static void 1165 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1166 { 1167 exca_putb(&sc->exca, EXCA_INTR, reg); 1168 } 1169 1170 static int 1171 cbb_power(device_t brdev, int volts) 1172 { 1173 uint32_t status, sock_ctrl; 1174 struct cbb_softc *sc = device_get_softc(brdev); 1175 int timeout; 1176 int retval = 0; 1177 uint32_t sockevent; 1178 uint8_t reg = 0; 1179 1180 status = cbb_get(sc, CBB_SOCKET_STATE); 1181 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1182 1183 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1184 switch (volts & CARD_VCCMASK) { 1185 case 5: 1186 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1187 break; 1188 case 3: 1189 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1190 break; 1191 case XV: 1192 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1193 break; 1194 case YV: 1195 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1196 break; 1197 case 0: 1198 break; 1199 default: 1200 return (0); /* power NEVER changed */ 1201 } 1202 1203 /* VPP == VCC */ 1204 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1205 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1206 1207 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1208 return (1); /* no change necessary */ 1209 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1210 if (volts != 0 && sc->chipset == CB_O2MICRO) 1211 reg = cbb_o2micro_power_hack(sc); 1212 1213 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1214 status = cbb_get(sc, CBB_SOCKET_STATE); 1215 1216 /* 1217 * XXX This busy wait is bogus. We should wait for a power 1218 * interrupt and then whine if the status is bad. If we're 1219 * worried about the card not coming up, then we should also 1220 * schedule a timeout which we can cancel in the power interrupt. 1221 */ 1222 timeout = 20; 1223 do { 1224 DELAY(20*1000); 1225 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1226 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1227 /* reset event status */ 1228 /* XXX should only reset EVENT_POWER */ 1229 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1230 if (timeout < 0) { 1231 printf ("VCC supply failed.\n"); 1232 goto done; 1233 } 1234 1235 /* XXX 1236 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1237 * is 20 ms, some PC-Card bridge requires longer duration. 1238 * XXX Note: We should check the stutus AFTER the delay to give time 1239 * for things to stabilize. 1240 */ 1241 DELAY(400*1000); 1242 1243 if (status & CBB_SOCKET_STAT_BADVCC) { 1244 device_printf(sc->dev, 1245 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1246 sock_ctrl ,status); 1247 printf("cbb_power: %dV\n", volts); 1248 goto done; 1249 } 1250 retval = 1; 1251 done:; 1252 if (volts != 0 && sc->chipset == CB_O2MICRO) 1253 cbb_o2micro_power_hack2(sc, reg); 1254 return (retval); 1255 } 1256 1257 /* 1258 * detect the voltage for the card, and set it. Since the power 1259 * used is the square of the voltage, lower voltages is a big win 1260 * and what Windows does (and what Microsoft prefers). The MS paper 1261 * also talks about preferring the CIS entry as well. 1262 */ 1263 static int 1264 cbb_do_power(device_t brdev) 1265 { 1266 int voltage; 1267 1268 /* Prefer lowest voltage supported */ 1269 voltage = cbb_detect_voltage(brdev); 1270 cbb_power(brdev, CARD_OFF); 1271 if (voltage & CARD_YV_CARD) 1272 cbb_power(brdev, CARD_VCC(YV)); 1273 else if (voltage & CARD_XV_CARD) 1274 cbb_power(brdev, CARD_VCC(XV)); 1275 else if (voltage & CARD_3V_CARD) 1276 cbb_power(brdev, CARD_VCC(3)); 1277 else if (voltage & CARD_5V_CARD) 1278 cbb_power(brdev, CARD_VCC(5)); 1279 else { 1280 device_printf(brdev, "Unknown card voltage\n"); 1281 return (ENXIO); 1282 } 1283 return (0); 1284 } 1285 1286 /************************************************************************/ 1287 /* CardBus power functions */ 1288 /************************************************************************/ 1289 1290 static void 1291 cbb_cardbus_reset(device_t brdev) 1292 { 1293 struct cbb_softc *sc = device_get_softc(brdev); 1294 int delay_us; 1295 1296 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1297 1298 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1299 1300 DELAY(delay_us); 1301 1302 /* If a card exists, unreset it! */ 1303 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 0) { 1304 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1305 &~CBBM_BRIDGECTRL_RESET, 2); 1306 DELAY(delay_us); 1307 } 1308 } 1309 1310 static int 1311 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1312 { 1313 struct cbb_softc *sc = device_get_softc(brdev); 1314 int err; 1315 1316 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 1317 CBB_SOCKET_STAT_CD) 1318 return (ENODEV); 1319 1320 err = cbb_do_power(brdev); 1321 if (err) 1322 return (err); 1323 cbb_cardbus_reset(brdev); 1324 return (0); 1325 } 1326 1327 static void 1328 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1329 { 1330 cbb_power(brdev, CARD_OFF); 1331 cbb_cardbus_reset(brdev); 1332 } 1333 1334 /************************************************************************/ 1335 /* CardBus Resource */ 1336 /************************************************************************/ 1337 1338 static int 1339 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1340 { 1341 int basereg; 1342 int limitreg; 1343 1344 if ((win < 0) || (win > 1)) { 1345 DEVPRINTF((brdev, 1346 "cbb_cardbus_io_open: window out of range %d\n", win)); 1347 return (EINVAL); 1348 } 1349 1350 basereg = win * 8 + CBBR_IOBASE0; 1351 limitreg = win * 8 + CBBR_IOLIMIT0; 1352 1353 pci_write_config(brdev, basereg, start, 4); 1354 pci_write_config(brdev, limitreg, end, 4); 1355 return (0); 1356 } 1357 1358 static int 1359 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1360 { 1361 int basereg; 1362 int limitreg; 1363 1364 if ((win < 0) || (win > 1)) { 1365 DEVPRINTF((brdev, 1366 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1367 return (EINVAL); 1368 } 1369 1370 basereg = win*8 + CBBR_MEMBASE0; 1371 limitreg = win*8 + CBBR_MEMLIMIT0; 1372 1373 pci_write_config(brdev, basereg, start, 4); 1374 pci_write_config(brdev, limitreg, end, 4); 1375 return (0); 1376 } 1377 1378 /* 1379 * XXX The following function belongs in the pci bus layer. 1380 */ 1381 static void 1382 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1383 { 1384 uint32_t starts[2]; 1385 uint32_t ends[2]; 1386 struct cbb_reslist *rle; 1387 int align; 1388 int prefetchable[2]; 1389 uint32_t reg; 1390 1391 starts[0] = starts[1] = 0xffffffff; 1392 ends[0] = ends[1] = 0; 1393 1394 if (type == SYS_RES_MEMORY) 1395 align = CBB_MEMALIGN; 1396 else if (type == SYS_RES_IOPORT) 1397 align = CBB_IOALIGN; 1398 else 1399 align = 1; 1400 1401 SLIST_FOREACH(rle, &sc->rl, link) { 1402 if (rle->type != type) 1403 ; 1404 else if (rle->res == NULL) { 1405 device_printf(sc->dev, "WARNING: Resource not reserved? " 1406 "(type=%d, addr=%lx)\n", 1407 rle->type, rman_get_start(rle->res)); 1408 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1409 /* XXX */ 1410 } else if (starts[0] == 0xffffffff) { 1411 starts[0] = rman_get_start(rle->res); 1412 ends[0] = rman_get_end(rle->res); 1413 prefetchable[0] = 1414 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1415 } else if (rman_get_end(rle->res) > ends[0] && 1416 rman_get_start(rle->res) - ends[0] < 1417 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1418 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1419 ends[0] = rman_get_end(rle->res); 1420 } else if (rman_get_start(rle->res) < starts[0] && 1421 starts[0] - rman_get_end(rle->res) < 1422 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1423 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1424 starts[0] = rman_get_start(rle->res); 1425 } else if (starts[1] == 0xffffffff) { 1426 starts[1] = rman_get_start(rle->res); 1427 ends[1] = rman_get_end(rle->res); 1428 prefetchable[1] = 1429 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1430 } else if (rman_get_end(rle->res) > ends[1] && 1431 rman_get_start(rle->res) - ends[1] < 1432 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1433 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1434 ends[1] = rman_get_end(rle->res); 1435 } else if (rman_get_start(rle->res) < starts[1] && 1436 starts[1] - rman_get_end(rle->res) < 1437 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1438 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1439 starts[1] = rman_get_start(rle->res); 1440 } else { 1441 uint32_t diffs[2]; 1442 int win; 1443 1444 diffs[0] = diffs[1] = 0xffffffff; 1445 if (rman_get_start(rle->res) > ends[0]) 1446 diffs[0] = rman_get_start(rle->res) - ends[0]; 1447 else if (rman_get_end(rle->res) < starts[0]) 1448 diffs[0] = starts[0] - rman_get_end(rle->res); 1449 if (rman_get_start(rle->res) > ends[1]) 1450 diffs[1] = rman_get_start(rle->res) - ends[1]; 1451 else if (rman_get_end(rle->res) < starts[1]) 1452 diffs[1] = starts[1] - rman_get_end(rle->res); 1453 1454 win = (diffs[0] <= diffs[1])?0:1; 1455 if (rman_get_start(rle->res) > ends[win]) 1456 ends[win] = rman_get_end(rle->res); 1457 else if (rman_get_end(rle->res) < starts[win]) 1458 starts[win] = rman_get_start(rle->res); 1459 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1460 prefetchable[win] = 0; 1461 } 1462 1463 if (starts[0] != 0xffffffff) 1464 starts[0] -= starts[0] % align; 1465 if (starts[1] != 0xffffffff) 1466 starts[1] -= starts[1] % align; 1467 if (ends[0] % align != 0) 1468 ends[0] += align - ends[0]%align - 1; 1469 if (ends[1] % align != 0) 1470 ends[1] += align - ends[1]%align - 1; 1471 } 1472 1473 if (type == SYS_RES_MEMORY) { 1474 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1475 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1476 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1477 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1478 CBBM_BRIDGECTRL_PREFETCH_1); 1479 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1480 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1481 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1482 } else if (type == SYS_RES_IOPORT) { 1483 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1484 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1485 } 1486 } 1487 1488 static int 1489 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1490 int rid, struct resource *res) 1491 { 1492 int ret; 1493 1494 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1495 type, rid, res); 1496 if (ret != 0) 1497 return (ret); 1498 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1499 return (0); 1500 } 1501 1502 static int 1503 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1504 int rid, struct resource *res) 1505 { 1506 int ret; 1507 1508 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1509 type, rid, res); 1510 if (ret != 0) 1511 return (ret); 1512 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1513 return (0); 1514 } 1515 1516 static struct resource * 1517 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1518 int *rid, u_long start, u_long end, u_long count, uint flags) 1519 { 1520 struct cbb_softc *sc = device_get_softc(brdev); 1521 int tmp; 1522 struct resource *res; 1523 1524 switch (type) { 1525 case SYS_RES_IRQ: 1526 tmp = rman_get_start(sc->irq_res); 1527 if (start > tmp || end < tmp || count != 1) { 1528 device_printf(child, "requested interrupt %ld-%ld," 1529 "count = %ld not supported by cbb\n", 1530 start, end, count); 1531 return (NULL); 1532 } 1533 start = end = tmp; 1534 flags |= RF_SHAREABLE; 1535 break; 1536 case SYS_RES_IOPORT: 1537 if (start <= cbb_start_32_io) 1538 start = cbb_start_32_io; 1539 if (end < start) 1540 end = start; 1541 break; 1542 case SYS_RES_MEMORY: 1543 if (start <= cbb_start_mem) 1544 start = cbb_start_mem; 1545 if (end < start) 1546 end = start; 1547 break; 1548 } 1549 1550 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1551 start, end, count, flags & ~RF_ACTIVE); 1552 if (res == NULL) { 1553 printf("cbb alloc res fail\n"); 1554 return (NULL); 1555 } 1556 cbb_insert_res(sc, res, type, *rid); 1557 if (flags & RF_ACTIVE) 1558 if (bus_activate_resource(child, type, *rid, res) != 0) { 1559 bus_release_resource(child, type, *rid, res); 1560 return (NULL); 1561 } 1562 1563 return (res); 1564 } 1565 1566 static int 1567 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1568 int rid, struct resource *res) 1569 { 1570 struct cbb_softc *sc = device_get_softc(brdev); 1571 int error; 1572 1573 if (rman_get_flags(res) & RF_ACTIVE) { 1574 error = bus_deactivate_resource(child, type, rid, res); 1575 if (error != 0) 1576 return (error); 1577 } 1578 cbb_remove_res(sc, res); 1579 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1580 type, rid, res)); 1581 } 1582 1583 /************************************************************************/ 1584 /* PC Card Power Functions */ 1585 /************************************************************************/ 1586 1587 static int 1588 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1589 { 1590 struct cbb_softc *sc = device_get_softc(brdev); 1591 int err; 1592 1593 DPRINTF(("cbb_pcic_socket_enable:\n")); 1594 1595 /* power down/up the socket to reset */ 1596 err = cbb_do_power(brdev); 1597 if (err) 1598 return (err); 1599 exca_reset(&sc->exca, child); 1600 1601 return (0); 1602 } 1603 1604 static void 1605 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1606 { 1607 struct cbb_softc *sc = device_get_softc(brdev); 1608 1609 DPRINTF(("cbb_pcic_socket_disable\n")); 1610 1611 /* reset signal asserting... */ 1612 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1613 DELAY(2*1000); 1614 1615 /* power down the socket */ 1616 cbb_power(brdev, CARD_OFF); 1617 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1618 1619 /* wait 300ms until power fails (Tpf). */ 1620 DELAY(300 * 1000); 1621 } 1622 1623 /************************************************************************/ 1624 /* POWER methods */ 1625 /************************************************************************/ 1626 1627 static int 1628 cbb_power_enable_socket(device_t brdev, device_t child) 1629 { 1630 struct cbb_softc *sc = device_get_softc(brdev); 1631 1632 if (sc->flags & CBB_16BIT_CARD) 1633 return (cbb_pcic_power_enable_socket(brdev, child)); 1634 else 1635 return (cbb_cardbus_power_enable_socket(brdev, child)); 1636 } 1637 1638 static void 1639 cbb_power_disable_socket(device_t brdev, device_t child) 1640 { 1641 struct cbb_softc *sc = device_get_softc(brdev); 1642 if (sc->flags & CBB_16BIT_CARD) 1643 cbb_pcic_power_disable_socket(brdev, child); 1644 else 1645 cbb_cardbus_power_disable_socket(brdev, child); 1646 } 1647 1648 static int 1649 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1650 struct resource *res) 1651 { 1652 struct cbb_softc *sc = device_get_softc(brdev); 1653 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1654 } 1655 1656 static int 1657 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1658 int rid, struct resource *res) 1659 { 1660 struct cbb_softc *sc = device_get_softc(brdev); 1661 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1662 } 1663 1664 static struct resource * 1665 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1666 u_long start, u_long end, u_long count, uint flags) 1667 { 1668 struct resource *res = NULL; 1669 struct cbb_softc *sc = device_get_softc(brdev); 1670 int tmp; 1671 1672 switch (type) { 1673 case SYS_RES_MEMORY: 1674 if (start < cbb_start_mem) 1675 start = cbb_start_mem; 1676 if (end < start) 1677 end = start; 1678 flags = (flags & ~RF_ALIGNMENT_MASK) | 1679 rman_make_alignment_flags(CBB_MEMALIGN); 1680 break; 1681 case SYS_RES_IOPORT: 1682 if (start < cbb_start_16_io) 1683 start = cbb_start_16_io; 1684 if (end < start) 1685 end = start; 1686 break; 1687 case SYS_RES_IRQ: 1688 tmp = rman_get_start(sc->irq_res); 1689 if (start > tmp || end < tmp || count != 1) { 1690 device_printf(child, "requested interrupt %ld-%ld," 1691 "count = %ld not supported by cbb\n", 1692 start, end, count); 1693 return (NULL); 1694 } 1695 flags |= RF_SHAREABLE; 1696 start = end = rman_get_start(sc->irq_res); 1697 break; 1698 } 1699 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1700 start, end, count, flags & ~RF_ACTIVE); 1701 if (res == NULL) 1702 return (NULL); 1703 cbb_insert_res(sc, res, type, *rid); 1704 if (flags & RF_ACTIVE) { 1705 if (bus_activate_resource(child, type, *rid, res) != 0) { 1706 bus_release_resource(child, type, *rid, res); 1707 return (NULL); 1708 } 1709 } 1710 1711 return (res); 1712 } 1713 1714 static int 1715 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1716 int rid, struct resource *res) 1717 { 1718 struct cbb_softc *sc = device_get_softc(brdev); 1719 int error; 1720 1721 if (rman_get_flags(res) & RF_ACTIVE) { 1722 error = bus_deactivate_resource(child, type, rid, res); 1723 if (error != 0) 1724 return (error); 1725 } 1726 cbb_remove_res(sc, res); 1727 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1728 type, rid, res)); 1729 } 1730 1731 /************************************************************************/ 1732 /* PC Card methods */ 1733 /************************************************************************/ 1734 1735 static int 1736 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1737 uint32_t flags) 1738 { 1739 struct cbb_softc *sc = device_get_softc(brdev); 1740 struct resource *res; 1741 1742 if (type != SYS_RES_MEMORY) 1743 return (EINVAL); 1744 res = cbb_find_res(sc, type, rid); 1745 if (res == NULL) { 1746 device_printf(brdev, 1747 "set_res_flags: specified rid not found\n"); 1748 return (ENOENT); 1749 } 1750 return (exca_mem_set_flags(&sc->exca, res, flags)); 1751 } 1752 1753 static int 1754 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1755 uint32_t cardaddr, uint32_t *deltap) 1756 { 1757 struct cbb_softc *sc = device_get_softc(brdev); 1758 struct resource *res; 1759 1760 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1761 if (res == NULL) { 1762 device_printf(brdev, 1763 "set_memory_offset: specified rid not found\n"); 1764 return (ENOENT); 1765 } 1766 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1767 } 1768 1769 /************************************************************************/ 1770 /* BUS Methods */ 1771 /************************************************************************/ 1772 1773 1774 static int 1775 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1776 struct resource *r) 1777 { 1778 struct cbb_softc *sc = device_get_softc(brdev); 1779 1780 if (sc->flags & CBB_16BIT_CARD) 1781 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1782 else 1783 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1784 r)); 1785 } 1786 1787 static int 1788 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1789 int rid, struct resource *r) 1790 { 1791 struct cbb_softc *sc = device_get_softc(brdev); 1792 1793 if (sc->flags & CBB_16BIT_CARD) 1794 return (cbb_pcic_deactivate_resource(brdev, child, type, 1795 rid, r)); 1796 else 1797 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1798 rid, r)); 1799 } 1800 1801 static struct resource * 1802 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1803 u_long start, u_long end, u_long count, uint flags) 1804 { 1805 struct cbb_softc *sc = device_get_softc(brdev); 1806 1807 if (sc->flags & CBB_16BIT_CARD) 1808 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1809 start, end, count, flags)); 1810 else 1811 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1812 start, end, count, flags)); 1813 } 1814 1815 static int 1816 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1817 struct resource *r) 1818 { 1819 struct cbb_softc *sc = device_get_softc(brdev); 1820 1821 if (sc->flags & CBB_16BIT_CARD) 1822 return (cbb_pcic_release_resource(brdev, child, type, 1823 rid, r)); 1824 else 1825 return (cbb_cardbus_release_resource(brdev, child, type, 1826 rid, r)); 1827 } 1828 1829 static int 1830 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1831 { 1832 struct cbb_softc *sc = device_get_softc(brdev); 1833 1834 switch (which) { 1835 case PCIB_IVAR_BUS: 1836 *result = sc->secbus; 1837 return (0); 1838 } 1839 return (ENOENT); 1840 } 1841 1842 static int 1843 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1844 { 1845 struct cbb_softc *sc = device_get_softc(brdev); 1846 1847 switch (which) { 1848 case PCIB_IVAR_BUS: 1849 sc->secbus = value; 1850 break; 1851 } 1852 return (ENOENT); 1853 } 1854 1855 /************************************************************************/ 1856 /* PCI compat methods */ 1857 /************************************************************************/ 1858 1859 static int 1860 cbb_maxslots(device_t brdev) 1861 { 1862 return (0); 1863 } 1864 1865 static uint32_t 1866 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1867 { 1868 /* 1869 * Pass through to the next ppb up the chain (i.e. our grandparent). 1870 */ 1871 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1872 b, s, f, reg, width)); 1873 } 1874 1875 static void 1876 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1877 int width) 1878 { 1879 /* 1880 * Pass through to the next ppb up the chain (i.e. our grandparent). 1881 */ 1882 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1883 b, s, f, reg, val, width); 1884 } 1885 1886 static int 1887 cbb_suspend(device_t self) 1888 { 1889 int error = 0; 1890 struct cbb_softc *sc = device_get_softc(self); 1891 1892 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1893 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1894 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1895 error = bus_generic_suspend(self); 1896 return (error); 1897 } 1898 1899 static int 1900 cbb_resume(device_t self) 1901 { 1902 int error = 0; 1903 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1904 uint32_t tmp; 1905 1906 /* 1907 * Some BIOSes will not save the BARs for the pci chips, so we 1908 * must do it ourselves. If the BAR is reset to 0 for an I/O 1909 * device, it will read back as 0x1, so no explicit test for 1910 * memory devices are needed. 1911 * 1912 * Note: The PCI bus code should do this automatically for us on 1913 * suspend/resume, but until it does, we have to cope. 1914 */ 1915 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1916 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1917 rman_get_start(sc->base_res))); 1918 1919 cbb_chipinit(sc); 1920 1921 /* reset interrupt -- Do we really need to do this? */ 1922 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1923 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1924 1925 /* re-establish the interrupt. */ 1926 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 1927 &sc->intrhand)) { 1928 device_printf(self, "couldn't re-establish interrupt"); 1929 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1930 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1931 sc->base_res); 1932 sc->irq_res = NULL; 1933 sc->base_res = NULL; 1934 return (ENOMEM); 1935 } 1936 1937 /* CSC Interrupt: Card detect interrupt on */ 1938 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1939 1940 /* Signal the thread to wakeup. */ 1941 mtx_lock(&sc->mtx); 1942 cv_signal(&sc->cv); 1943 mtx_unlock(&sc->mtx); 1944 1945 error = bus_generic_resume(self); 1946 1947 return (error); 1948 } 1949 1950 static int 1951 cbb_child_present(device_t self) 1952 { 1953 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1954 uint32_t sockstate; 1955 1956 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1957 return ((sockstate & CBB_SOCKET_STAT_CD) != 0 && 1958 (sc->flags & CBB_CARD_OK) != 0); 1959 } 1960 1961 static device_method_t cbb_methods[] = { 1962 /* Device interface */ 1963 DEVMETHOD(device_probe, cbb_probe), 1964 DEVMETHOD(device_attach, cbb_attach), 1965 DEVMETHOD(device_detach, cbb_detach), 1966 DEVMETHOD(device_shutdown, cbb_shutdown), 1967 DEVMETHOD(device_suspend, cbb_suspend), 1968 DEVMETHOD(device_resume, cbb_resume), 1969 1970 /* bus methods */ 1971 DEVMETHOD(bus_print_child, bus_generic_print_child), 1972 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 1973 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 1974 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 1975 DEVMETHOD(bus_release_resource, cbb_release_resource), 1976 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 1977 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 1978 DEVMETHOD(bus_driver_added, cbb_driver_added), 1979 DEVMETHOD(bus_child_detached, cbb_child_detached), 1980 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 1981 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 1982 DEVMETHOD(bus_child_present, cbb_child_present), 1983 1984 /* 16-bit card interface */ 1985 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 1986 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 1987 1988 /* power interface */ 1989 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 1990 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 1991 1992 /* pcib compatibility interface */ 1993 DEVMETHOD(pcib_maxslots, cbb_maxslots), 1994 DEVMETHOD(pcib_read_config, cbb_read_config), 1995 DEVMETHOD(pcib_write_config, cbb_write_config), 1996 {0,0} 1997 }; 1998 1999 static driver_t cbb_driver = { 2000 "cbb", 2001 cbb_methods, 2002 sizeof(struct cbb_softc) 2003 }; 2004 2005 static devclass_t cbb_devclass; 2006 2007 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2008 MODULE_VERSION(cbb, 1); 2009 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2010