1 /* 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 __FBSDID("$FreeBSD$"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/condvar.h> 82 #include <sys/errno.h> 83 #include <sys/kernel.h> 84 #include <sys/lock.h> 85 #include <sys/malloc.h> 86 #include <sys/mutex.h> 87 #include <sys/sysctl.h> 88 #include <sys/kthread.h> 89 #include <sys/bus.h> 90 #include <machine/bus.h> 91 #include <sys/rman.h> 92 #include <machine/resource.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <machine/clock.h> 97 98 #include <dev/pccard/pccardreg.h> 99 #include <dev/pccard/pccardvar.h> 100 101 #include <dev/exca/excareg.h> 102 #include <dev/exca/excavar.h> 103 104 #include <dev/pccbb/pccbbreg.h> 105 #include <dev/pccbb/pccbbvar.h> 106 107 #include "power_if.h" 108 #include "card_if.h" 109 #include "pcib_if.h" 110 111 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 112 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 113 114 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 116 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 117 pci_write_config(DEV, REG, ( \ 118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 119 120 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 121 122 #define CBB_START_MEM 0x88000000 123 #define CBB_START_32_IO 0x1000 124 #define CBB_START_16_IO 0x100 125 126 struct yenta_chipinfo { 127 uint32_t yc_id; 128 const char *yc_name; 129 int yc_chiptype; 130 } yc_chipsets[] = { 131 /* Texas Instruments chips */ 132 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 133 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 134 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 135 136 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 142 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 143 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 144 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 146 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 150 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 157 158 /* ENE */ 159 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 165 166 /* Ricoh chips */ 167 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 168 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 169 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 170 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 171 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 172 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 173 174 /* Toshiba products */ 175 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 176 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 177 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 178 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 179 180 /* Cirrus Logic */ 181 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 182 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 183 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 184 185 /* 02Micro */ 186 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 187 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 188 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 189 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 190 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 191 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 193 194 /* sentinel */ 195 {0 /* null id */, "unknown", CB_UNKNOWN}, 196 }; 197 198 /* sysctl vars */ 199 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 200 201 /* There's no way to say TUNEABLE_LONG to get the right types */ 202 u_long cbb_start_mem = CBB_START_MEM; 203 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 205 &cbb_start_mem, CBB_START_MEM, 206 "Starting address for memory allocations"); 207 208 u_long cbb_start_16_io = CBB_START_16_IO; 209 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 211 &cbb_start_16_io, CBB_START_16_IO, 212 "Starting ioport for 16-bit cards"); 213 214 u_long cbb_start_32_io = CBB_START_32_IO; 215 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 216 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 217 &cbb_start_32_io, CBB_START_32_IO, 218 "Starting ioport for 32-bit cards"); 219 220 int cbb_debug = 0; 221 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 222 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 223 "Verbose cardbus bridge debugging"); 224 225 static int cbb_chipset(uint32_t pci_id, const char **namep); 226 static int cbb_probe(device_t brdev); 227 static void cbb_chipinit(struct cbb_softc *sc); 228 static int cbb_attach(device_t brdev); 229 static int cbb_detach(device_t brdev); 230 static int cbb_shutdown(device_t brdev); 231 static void cbb_driver_added(device_t brdev, driver_t *driver); 232 static void cbb_child_detached(device_t brdev, device_t child); 233 static void cbb_event_thread(void *arg); 234 static void cbb_insert(struct cbb_softc *sc); 235 static void cbb_removal(struct cbb_softc *sc); 236 static void cbb_intr(void *arg); 237 static int cbb_detect_voltage(device_t brdev); 238 static int cbb_power(device_t brdev, int volts); 239 static void cbb_cardbus_reset(device_t brdev); 240 static int cbb_cardbus_power_enable_socket(device_t brdev, 241 device_t child); 242 static void cbb_cardbus_power_disable_socket(device_t brdev, 243 device_t child); 244 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 245 uint32_t end); 246 static int cbb_cardbus_mem_open(device_t brdev, int win, 247 uint32_t start, uint32_t end); 248 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 249 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 250 int type, int rid, struct resource *res); 251 static int cbb_cardbus_deactivate_resource(device_t brdev, 252 device_t child, int type, int rid, struct resource *res); 253 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 254 device_t child, int type, int *rid, u_long start, 255 u_long end, u_long count, u_int flags); 256 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 257 int type, int rid, struct resource *res); 258 static int cbb_power_enable_socket(device_t brdev, device_t child); 259 static void cbb_power_disable_socket(device_t brdev, device_t child); 260 static int cbb_activate_resource(device_t brdev, device_t child, 261 int type, int rid, struct resource *r); 262 static int cbb_deactivate_resource(device_t brdev, device_t child, 263 int type, int rid, struct resource *r); 264 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 265 int type, int *rid, u_long start, u_long end, u_long count, 266 u_int flags); 267 static int cbb_release_resource(device_t brdev, device_t child, 268 int type, int rid, struct resource *r); 269 static int cbb_read_ivar(device_t brdev, device_t child, int which, 270 uintptr_t *result); 271 static int cbb_write_ivar(device_t brdev, device_t child, int which, 272 uintptr_t value); 273 static int cbb_maxslots(device_t brdev); 274 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 275 int reg, int width); 276 static void cbb_write_config(device_t brdev, int b, int s, int f, 277 int reg, uint32_t val, int width); 278 279 /* 280 */ 281 static __inline void 282 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 283 { 284 bus_space_write_4(sc->bst, sc->bsh, reg, val); 285 } 286 287 static __inline uint32_t 288 cbb_get(struct cbb_softc *sc, uint32_t reg) 289 { 290 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 291 } 292 293 static __inline void 294 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 295 { 296 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 297 } 298 299 static __inline void 300 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 301 { 302 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 303 } 304 305 static void 306 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 307 { 308 struct cbb_reslist *rle; 309 310 SLIST_FOREACH(rle, &sc->rl, link) { 311 if (rle->res == res) { 312 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 313 free(rle, M_DEVBUF); 314 return; 315 } 316 } 317 } 318 319 static struct resource * 320 cbb_find_res(struct cbb_softc *sc, int type, int rid) 321 { 322 struct cbb_reslist *rle; 323 324 SLIST_FOREACH(rle, &sc->rl, link) 325 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 326 return (rle->res); 327 return (NULL); 328 } 329 330 static void 331 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 332 int rid) 333 { 334 struct cbb_reslist *rle; 335 336 /* 337 * Need to record allocated resource so we can iterate through 338 * it later. 339 */ 340 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 341 if (rle == NULL) 342 panic("cbb_cardbus_alloc_resource: can't record entry!"); 343 rle->res = res; 344 rle->type = type; 345 rle->rid = rid; 346 SLIST_INSERT_HEAD(&sc->rl, rle, link); 347 } 348 349 static void 350 cbb_destroy_res(struct cbb_softc *sc) 351 { 352 struct cbb_reslist *rle; 353 354 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 355 device_printf(sc->dev, "Danger Will Robinson: Resource " 356 "left allocated! This is a bug... " 357 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 358 rman_get_start(rle->res)); 359 SLIST_REMOVE_HEAD(&sc->rl, link); 360 free(rle, M_DEVBUF); 361 } 362 } 363 364 /************************************************************************/ 365 /* Probe/Attach */ 366 /************************************************************************/ 367 368 static int 369 cbb_chipset(uint32_t pci_id, const char **namep) 370 { 371 struct yenta_chipinfo *ycp; 372 373 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 374 continue; 375 if (namep != NULL) 376 *namep = ycp->yc_name; 377 return (ycp->yc_chiptype); 378 } 379 380 static int 381 cbb_probe(device_t brdev) 382 { 383 const char *name; 384 uint32_t progif; 385 uint32_t subclass; 386 387 /* 388 * Do we know that we support the chipset? If so, then we 389 * accept the device. 390 */ 391 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 392 device_set_desc(brdev, name); 393 return (0); 394 } 395 396 /* 397 * We do support generic CardBus bridges. All that we've seen 398 * to date have progif 0 (the Yenta spec, and successors mandate 399 * this). We do not support PCI PCMCIA bridges (with one exception) 400 * with this driver since they generally are I/O mapped. Those 401 * are supported by the pcic driver. This should help us be more 402 * future proof. 403 */ 404 subclass = pci_get_subclass(brdev); 405 progif = pci_get_progif(brdev); 406 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 407 device_set_desc(brdev, "PCI-CardBus Bridge"); 408 return (0); 409 } 410 return (ENXIO); 411 } 412 413 414 /* 415 * Disable function interrupts by telling the bridge to generate IRQ1 416 * interrupts. These interrupts aren't really generated by the chip, since 417 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 418 * initialization, so this helps to work around the problem. 419 * 420 * XXX We can't do this workaround for all chipsets, because this 421 * XXX causes interference with the keyboard because somechipsets will 422 * XXX actually signal IRQ1 over their serial interrupt connections to 423 * XXX the south bridge. Disable it it for now. 424 */ 425 static void 426 cbb_disable_func_intr(struct cbb_softc *sc) 427 { 428 #if 0 429 uint8_t reg; 430 431 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 432 EXCA_INTR_IRQ_RESERVED1; 433 exca_putb(&sc->exca, EXCA_INTR, reg); 434 #endif 435 } 436 437 /* 438 * Enable function interrupts. We turn on function interrupts when the card 439 * requests an interrupt. The PCMCIA standard says that we should set 440 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 441 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 442 * cards. 443 */ 444 static void 445 cbb_enable_func_intr(struct cbb_softc *sc) 446 { 447 uint8_t reg; 448 449 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 450 EXCA_INTR_IRQ_NONE; 451 exca_putb(&sc->exca, EXCA_INTR, reg); 452 } 453 454 static void 455 cbb_chipinit(struct cbb_softc *sc) 456 { 457 uint32_t mux, sysctrl, reg; 458 459 /* Set CardBus latency timer */ 460 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 461 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 462 463 /* Set PCI latency timer */ 464 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 465 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 466 467 /* Enable memory access */ 468 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 469 | PCIM_CMD_MEMEN 470 | PCIM_CMD_PORTEN 471 | PCIM_CMD_BUSMASTEREN, 2); 472 473 /* disable Legacy IO */ 474 switch (sc->chipset) { 475 case CB_RF5C46X: 476 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 477 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 478 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 479 break; 480 default: 481 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 482 break; 483 } 484 485 /* Use PCI interrupt for interrupt routing */ 486 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 487 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 488 CBBM_BRIDGECTRL_INTR_IREQ_EN), 489 | CBBM_BRIDGECTRL_WRITE_POST_EN, 490 2); 491 492 /* 493 * XXX this should be a function table, ala OLDCARD. This means 494 * that we could more easily support ISA interrupts for pccard 495 * cards if we had to. 496 */ 497 switch (sc->chipset) { 498 case CB_TI113X: 499 /* 500 * The TI 1031, TI 1130 and TI 1131 all require another bit 501 * be set to enable PCI routing of interrupts, and then 502 * a bit for each of the CSC and Function interrupts we 503 * want routed. 504 */ 505 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 506 | CBBM_CBCTRL_113X_PCI_INTR | 507 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 508 1); 509 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 510 & ~(CBBM_DEVCTRL_INT_SERIAL | 511 CBBM_DEVCTRL_INT_PCI), 1); 512 break; 513 case CB_TI12XX: 514 /* 515 * Some TI 12xx (and [14][45]xx) based pci cards 516 * sometimes have issues with the MFUNC register not 517 * being initialized due to a bad EEPROM on board. 518 * Laptops that this matters on have this register 519 * properly initialized. 520 * 521 * The TI125X parts have a different register. 522 */ 523 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 524 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 525 if (mux == 0) { 526 mux = (mux & ~CBBM_MFUNC_PIN0) | 527 CBBM_MFUNC_PIN0_INTA; 528 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 529 mux = (mux & ~CBBM_MFUNC_PIN1) | 530 CBBM_MFUNC_PIN1_INTB; 531 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 532 } 533 /*FALLTHROUGH*/ 534 case CB_TI125X: 535 /* 536 * Disable zoom video. Some machines initialize this 537 * improperly and exerpience has shown that this helps 538 * prevent strange behavior. 539 */ 540 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 541 break; 542 case CB_O2MICRO: 543 /* 544 * Issue #1: INT# generated at the same time as 545 * selected ISA IRQ. When IREQ# or STSCHG# is active, 546 * in addition to the ISA IRQ being generated, INT# 547 * will also be generated at the same time. 548 * 549 * Some of the older controllers have an issue in 550 * which the slot's PCI INT# will be asserted whenever 551 * IREQ# or STSCGH# is asserted even if ExCA registers 552 * 03h or 05h have an ISA IRQ selected. 553 * 554 * The fix for this issue, which will work for any 555 * controller (old or new), is to set ExCA registers 556 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 557 * These bits are undocumented. By setting this 558 * register (of each slot) to '1010xxxxb' a routing of 559 * IREQ# to INTC# and STSCHG# to INTC# is selected. 560 * Since INTC# isn't connected there will be no 561 * unexpected PCI INT when IREQ# or STSCHG# is active. 562 * However, INTA# (slot 0) or INTB# (slot 1) will 563 * still be correctly generated if NO ISA IRQ is 564 * selected (ExCA regs 03h or 05h are cleared). 565 */ 566 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 567 reg = (reg & 0x0f) | 568 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 569 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 570 571 break; 572 case CB_TOPIC97: 573 /* 574 * Disable Zoom Video, ToPIC 97, 100. 575 */ 576 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 577 /* 578 * ToPIC 97, 100 579 * At offset 0xa1: INTERRUPT CONTROL register 580 * 0x1: Turn on INT interrupts. 581 */ 582 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 583 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 584 goto topic_common; 585 case CB_TOPIC95: 586 /* 587 * SOCKETCTRL appears to be TOPIC 95/B specific 588 */ 589 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 590 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 591 592 topic_common:; 593 /* 594 * At offset 0xa0: SLOT CONTROL 595 * 0x80 Enable CardBus Functionality 596 * 0x40 Enable CardBus and PC Card registers 597 * 0x20 Lock ID in exca regs 598 * 0x10 Write protect ID in config regs 599 * Clear the rest of the bits, which defaults the slot 600 * in legacy mode to 0x3e0 and offset 0. (legacy 601 * mode is determined elsewhere) 602 */ 603 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 604 CBBM_TOPIC_SLOTCTRL_SLOTON | 605 CBBM_TOPIC_SLOTCTRL_SLOTEN | 606 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 607 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 608 609 /* 610 * At offset 0xa3 Card Detect Control Register 611 * 0x80 CARDBUS enbale 612 * 0x01 Cleared for hardware change detect 613 */ 614 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 615 | CBBM_TOPIC_CDC_CARDBUS, 616 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 617 break; 618 } 619 620 /* 621 * Need to tell ExCA registers to CSC interrupts route via PCI 622 * interrupts. There are two ways to do this. Once is to set 623 * INTR_ENABLE and the other is to set CSC to 0. Since both 624 * methods are mutually compatible, we do both. 625 */ 626 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 627 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 628 629 cbb_disable_func_intr(sc); 630 631 /* close all memory and io windows */ 632 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 633 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 634 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 635 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 636 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 637 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 638 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 639 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 640 } 641 642 #ifndef BURN_BRIDGES 643 /* 644 * Still need this because the pci code only does power for type 0 645 * header devices. 646 */ 647 static void 648 cbb_powerstate_d0(device_t dev) 649 { 650 u_int32_t membase, irq; 651 652 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 653 /* Save important PCI config data. */ 654 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 655 irq = pci_read_config(dev, PCIR_INTLINE, 4); 656 657 /* Reset the power state. */ 658 device_printf(dev, "chip is in D%d power mode " 659 "-- setting to D0\n", pci_get_powerstate(dev)); 660 661 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 662 663 /* Restore PCI config data. */ 664 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 665 pci_write_config(dev, PCIR_INTLINE, irq, 4); 666 } 667 } 668 #endif 669 670 /* 671 * Print out the config space 672 */ 673 static void 674 cbb_print_config(device_t dev) 675 { 676 int i; 677 678 device_printf(dev, "PCI Configuration space:"); 679 for (i = 0; i < 256; i += 4) { 680 if (i % 16 == 0) 681 printf("\n 0x%02x: ", i); 682 printf("0x%08x ", pci_read_config(dev, i, 4)); 683 } 684 printf("\n"); 685 } 686 687 static int 688 cbb_attach(device_t brdev) 689 { 690 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 691 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 692 int rid, bus, pribus; 693 device_t parent; 694 695 parent = device_get_parent(brdev); 696 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 697 cv_init(&sc->cv, "cbb cv"); 698 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 699 sc->dev = brdev; 700 sc->cbdev = NULL; 701 sc->exca.pccarddev = NULL; 702 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 703 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 704 SLIST_INIT(&sc->rl); 705 STAILQ_INIT(&sc->intr_handlers); 706 #ifndef BURN_BRIDGES 707 cbb_powerstate_d0(brdev); 708 #endif 709 710 rid = CBBR_SOCKBASE; 711 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 712 RF_ACTIVE); 713 if (!sc->base_res) { 714 device_printf(brdev, "Could not map register memory\n"); 715 mtx_destroy(&sc->mtx); 716 cv_destroy(&sc->cv); 717 return (ENOMEM); 718 } else { 719 DEVPRINTF((brdev, "Found memory at %08lx\n", 720 rman_get_start(sc->base_res))); 721 } 722 723 sc->bst = rman_get_bustag(sc->base_res); 724 sc->bsh = rman_get_bushandle(sc->base_res); 725 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 726 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 727 sc->exca.chipset = EXCA_CARDBUS; 728 cbb_chipinit(sc); 729 730 /* 731 * This is a gross hack. We should be scanning the entire pci 732 * tree, assigning bus numbers in a way such that we (1) can 733 * reserve 1 extra bus just in case and (2) all sub busses 734 * are in an appropriate range. 735 */ 736 bus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 737 pribus = pcib_get_bus(parent); 738 DEVPRINTF((brdev, "Secondary bus is %d\n", bus)); 739 if (bus == 0) { 740 if (curr_bus_number < pribus) 741 curr_bus_number = pribus + 1; 742 if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) { 743 DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus)); 744 pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1); 745 } 746 bus = curr_bus_number; 747 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus, 748 bus + 1)); 749 sc->secbus = bus; 750 sc->subbus = bus + 1; 751 pci_write_config(brdev, PCIR_SECBUS_2, bus, 1); 752 pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1); 753 curr_bus_number += 2; 754 } 755 756 /* attach children */ 757 sc->cbdev = device_add_child(brdev, "cardbus", -1); 758 if (sc->cbdev == NULL) 759 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 760 else if (device_probe_and_attach(sc->cbdev) != 0) 761 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 762 763 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 764 if (sc->exca.pccarddev == NULL) 765 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 766 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) 767 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 768 769 /* Map and establish the interrupt. */ 770 rid = 0; 771 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 772 RF_SHAREABLE | RF_ACTIVE); 773 if (sc->irq_res == NULL) { 774 printf("cbb: Unable to map IRQ...\n"); 775 goto err; 776 } 777 778 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 779 cbb_intr, sc, &sc->intrhand)) { 780 device_printf(brdev, "couldn't establish interrupt"); 781 goto err; 782 } 783 784 /* reset 16-bit pcmcia bus */ 785 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 786 787 /* turn off power */ 788 cbb_power(brdev, CARD_OFF); 789 790 /* CSC Interrupt: Card detect interrupt on */ 791 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 792 793 /* reset interrupt */ 794 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 795 796 if (bootverbose) 797 cbb_print_config(brdev); 798 799 /* Start the thread */ 800 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 801 "%s", device_get_nameunit(brdev))) { 802 device_printf(brdev, "unable to create event thread.\n"); 803 panic("cbb_create_event_thread"); 804 } 805 return (0); 806 err: 807 if (sc->irq_res) 808 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 809 if (sc->base_res) { 810 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 811 sc->base_res); 812 } 813 mtx_destroy(&sc->mtx); 814 cv_destroy(&sc->cv); 815 return (ENOMEM); 816 } 817 818 static int 819 cbb_detach(device_t brdev) 820 { 821 struct cbb_softc *sc = device_get_softc(brdev); 822 int numdevs; 823 device_t *devlist; 824 int tmp; 825 int error; 826 827 device_get_children(brdev, &devlist, &numdevs); 828 829 error = 0; 830 for (tmp = 0; tmp < numdevs; tmp++) { 831 if (device_detach(devlist[tmp]) == 0) 832 device_delete_child(brdev, devlist[tmp]); 833 else 834 error++; 835 } 836 free(devlist, M_TEMP); 837 if (error > 0) 838 return (ENXIO); 839 840 mtx_lock(&sc->mtx); 841 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 842 sc->flags |= CBB_KTHREAD_DONE; 843 if (sc->flags & CBB_KTHREAD_RUNNING) { 844 cv_broadcast(&sc->cv); 845 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 846 } 847 mtx_unlock(&sc->mtx); 848 849 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 850 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 851 sc->base_res); 852 mtx_destroy(&sc->mtx); 853 cv_destroy(&sc->cv); 854 return (0); 855 } 856 857 static int 858 cbb_shutdown(device_t brdev) 859 { 860 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 861 /* properly reset everything at shutdown */ 862 863 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 864 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 865 866 cbb_set(sc, CBB_SOCKET_MASK, 0); 867 868 cbb_power(brdev, CARD_OFF); 869 870 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 871 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 872 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 873 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 874 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 875 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 876 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 877 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 878 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 879 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 880 return (0); 881 } 882 883 static int 884 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 885 int flags, driver_intr_t *intr, void *arg, void **cookiep) 886 { 887 struct cbb_intrhand *ih; 888 struct cbb_softc *sc = device_get_softc(dev); 889 890 /* 891 * You aren't allowed to have fast interrupts for pccard/cardbus 892 * things since those interrupts are PCI and shared. Since we use 893 * the PCI interrupt for the status change interrupts, it can't be 894 * free for use by the driver. Fast interrupts must not be shared. 895 */ 896 if ((flags & INTR_FAST) != 0) 897 return (EINVAL); 898 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 899 if (ih == NULL) 900 return (ENOMEM); 901 *cookiep = ih; 902 ih->intr = intr; 903 ih->arg = arg; 904 ih->flags = flags & INTR_MPSAFE; 905 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 906 cbb_enable_func_intr(sc); 907 /* 908 * XXX need to turn on ISA interrupts, if we ever support them, but 909 * XXX for now that's all we need to do. 910 */ 911 return (0); 912 } 913 914 static int 915 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 916 void *cookie) 917 { 918 struct cbb_intrhand *ih; 919 struct cbb_softc *sc = device_get_softc(dev); 920 921 /* XXX Need to do different things for ISA interrupts. */ 922 ih = (struct cbb_intrhand *) cookie; 923 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 924 free(ih, M_DEVBUF); 925 return (0); 926 } 927 928 929 static void 930 cbb_driver_added(device_t brdev, driver_t *driver) 931 { 932 struct cbb_softc *sc = device_get_softc(brdev); 933 device_t *devlist; 934 device_t dev; 935 int tmp; 936 int numdevs; 937 int wake = 0; 938 939 DEVICE_IDENTIFY(driver, brdev); 940 device_get_children(brdev, &devlist, &numdevs); 941 for (tmp = 0; tmp < numdevs; tmp++) { 942 dev = devlist[tmp]; 943 if (device_get_state(dev) == DS_NOTPRESENT && 944 device_probe_and_attach(dev) == 0) 945 wake++; 946 } 947 free(devlist, M_TEMP); 948 949 if (wake > 0) { 950 mtx_lock(&sc->mtx); 951 cv_signal(&sc->cv); 952 mtx_unlock(&sc->mtx); 953 } 954 } 955 956 static void 957 cbb_child_detached(device_t brdev, device_t child) 958 { 959 struct cbb_softc *sc = device_get_softc(brdev); 960 961 if (child != sc->cbdev && child != sc->exca.pccarddev) 962 device_printf(brdev, "Unknown child detached: %s\n", 963 device_get_nameunit(child)); 964 } 965 966 /************************************************************************/ 967 /* Kthreads */ 968 /************************************************************************/ 969 970 static void 971 cbb_event_thread(void *arg) 972 { 973 struct cbb_softc *sc = arg; 974 uint32_t status; 975 int err; 976 int not_a_card = 0; 977 978 sc->flags |= CBB_KTHREAD_RUNNING; 979 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 980 /* 981 * We take out Giant here because we need it deep, 982 * down in the bowels of the vm system for mapping the 983 * memory we need to read the CIS. In addition, since 984 * we are adding/deleting devices from the dev tree, 985 * and that code isn't MP safe, we have to hold Giant. 986 */ 987 mtx_lock(&Giant); 988 status = cbb_get(sc, CBB_SOCKET_STATE); 989 DPRINTF(("Status is 0x%x\n", status)); 990 if (!CBB_CARD_PRESENT(status)) { 991 not_a_card = 0; /* We know card type */ 992 cbb_removal(sc); 993 } else if (status & CBB_STATE_NOT_A_CARD) { 994 /* 995 * Up to 20 times, try to rescan the card when we 996 * see NOT_A_CARD. 997 */ 998 if (not_a_card++ < 20) { 999 DEVPRINTF((sc->dev, 1000 "Not a card bit set, rescanning\n")); 1001 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 1002 } else { 1003 device_printf(sc->dev, 1004 "Can't determine card type\n"); 1005 } 1006 } else { 1007 not_a_card = 0; /* We know card type */ 1008 cbb_insert(sc); 1009 } 1010 mtx_unlock(&Giant); 1011 1012 /* 1013 * Wait until it has been 1s since the last time we 1014 * get an interrupt. We handle the rest of the interrupt 1015 * at the top of the loop. Although we clear the bit in the 1016 * ISR, we signal sc->cv from the detach path after we've 1017 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 1018 * 1s sleep here. 1019 * 1020 * In our ISR, we turn off the card changed interrupt. Turn 1021 * them back on here before we wait for them to happen. We 1022 * turn them on/off so that we can tolerate a large latency 1023 * between the time we signal cbb_event_thread and it gets 1024 * a chance to run. 1025 */ 1026 mtx_lock(&sc->mtx); 1027 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1028 cv_wait(&sc->cv, &sc->mtx); 1029 err = 0; 1030 while (err != EWOULDBLOCK && 1031 (sc->flags & CBB_KTHREAD_DONE) == 0) 1032 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 1033 mtx_unlock(&sc->mtx); 1034 } 1035 sc->flags &= ~CBB_KTHREAD_RUNNING; 1036 kthread_exit(0); 1037 } 1038 1039 /************************************************************************/ 1040 /* Insert/removal */ 1041 /************************************************************************/ 1042 1043 static void 1044 cbb_insert(struct cbb_softc *sc) 1045 { 1046 uint32_t sockevent, sockstate; 1047 1048 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1049 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1050 1051 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1052 sockevent, sockstate)); 1053 1054 if (sockstate & CBB_STATE_R2_CARD) { 1055 if (sc->exca.pccarddev) 1056 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1057 exca_insert(&sc->exca); 1058 } else if (sockstate & CBB_STATE_CB_CARD) { 1059 if (sc->cbdev != NULL) { 1060 sc->flags &= ~CBB_16BIT_CARD; 1061 sc->flags |= CBB_CARD_OK; 1062 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1063 device_printf(sc->dev, 1064 "CardBus card activation failed\n"); 1065 } else { 1066 device_printf(sc->dev, 1067 "CardBus card inserted, but no cardbus bus.\n"); 1068 } 1069 } else { 1070 /* 1071 * We should power the card down, and try again a couple of 1072 * times if this happens. XXX 1073 */ 1074 device_printf(sc->dev, "Unsupported card type detected\n"); 1075 } 1076 } 1077 1078 static void 1079 cbb_removal(struct cbb_softc *sc) 1080 { 1081 if (sc->flags & CBB_16BIT_CARD) { 1082 exca_removal(&sc->exca); 1083 } else { 1084 if (sc->cbdev != NULL) 1085 CARD_DETACH_CARD(sc->cbdev); 1086 } 1087 cbb_destroy_res(sc); 1088 } 1089 1090 /************************************************************************/ 1091 /* Interrupt Handler */ 1092 /************************************************************************/ 1093 1094 static void 1095 cbb_intr(void *arg) 1096 { 1097 struct cbb_softc *sc = arg; 1098 uint32_t sockevent; 1099 struct cbb_intrhand *ih; 1100 1101 /* 1102 * This ISR needs work XXX 1103 */ 1104 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1105 if (sockevent != 0) { 1106 /* ack the interrupt */ 1107 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1108 1109 /* 1110 * If anything has happened to the socket, we assume that 1111 * the card is no longer OK, and we shouldn't call its 1112 * ISR. We set CARD_OK as soon as we've attached the 1113 * card. This helps in a noisy eject, which happens 1114 * all too often when users are ejecting their PC Cards. 1115 * 1116 * We use this method in preference to checking to see if 1117 * the card is still there because the check suffers from 1118 * a race condition in the bouncing case. Prior versions 1119 * of the pccard software used a similar trick and achieved 1120 * excellent results. 1121 */ 1122 if (sockevent & CBB_SOCKET_EVENT_CD) { 1123 mtx_lock(&sc->mtx); 1124 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1125 sc->flags &= ~CBB_CARD_OK; 1126 cbb_disable_func_intr(sc); 1127 cv_signal(&sc->cv); 1128 mtx_unlock(&sc->mtx); 1129 } 1130 } 1131 /* 1132 * Some chips also require us to read the old ExCA registe for 1133 * card status change when we route CSC vis PCI. This isn't supposed 1134 * to be required, but it clears the interrupt state on some chipsets. 1135 * Maybe there's a setting that would obviate its need. Maybe we 1136 * should test the status bits and deal with them, but so far we've 1137 * not found any machines that don't also give us the socket status 1138 * indication above. 1139 * 1140 * We have to call this unconditionally because some bridges deliver 1141 * the even independent of the CBB_SOCKET_EVENT_CD above. 1142 */ 1143 exca_getb(&sc->exca, EXCA_CSC); 1144 1145 /* 1146 * If the card is OK, call all the interrupt handlers. 1147 */ 1148 if (sc->flags & CBB_CARD_OK) { 1149 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1150 if ((ih->flags & INTR_MPSAFE) == 0) 1151 mtx_lock(&Giant); 1152 (*ih->intr)(ih->arg); 1153 if ((ih->flags & INTR_MPSAFE) == 0) 1154 mtx_unlock(&Giant); 1155 } 1156 } 1157 } 1158 1159 /************************************************************************/ 1160 /* Generic Power functions */ 1161 /************************************************************************/ 1162 1163 static int 1164 cbb_detect_voltage(device_t brdev) 1165 { 1166 struct cbb_softc *sc = device_get_softc(brdev); 1167 uint32_t psr; 1168 int vol = CARD_UKN_CARD; 1169 1170 psr = cbb_get(sc, CBB_SOCKET_STATE); 1171 1172 if (psr & CBB_STATE_5VCARD) 1173 vol |= CARD_5V_CARD; 1174 if (psr & CBB_STATE_3VCARD) 1175 vol |= CARD_3V_CARD; 1176 if (psr & CBB_STATE_XVCARD) 1177 vol |= CARD_XV_CARD; 1178 if (psr & CBB_STATE_YVCARD) 1179 vol |= CARD_YV_CARD; 1180 1181 return (vol); 1182 } 1183 1184 static uint8_t 1185 cbb_o2micro_power_hack(struct cbb_softc *sc) 1186 { 1187 uint8_t reg; 1188 1189 /* 1190 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1191 * unexpected PCI INT# may be generated during PC-Card 1192 * initialization even with the IRQ Routing Bit Set with some 1193 * PC-Cards. 1194 * 1195 * This is a two part issue. The first part is that some of 1196 * our older controllers have an issue in which the slot's PCI 1197 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1198 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1199 * is selected (ExCA register 03h bits 3:0, of the slot, are 1200 * cleared) we will generate INT# if IREQ# is asserted. The 1201 * second part is because some PC-Cards prematurally assert 1202 * IREQ# before the ExCA registers are fully programmed. This 1203 * in turn asserts INT# because ExCA register 03h bits 3:0 1204 * (ISA IRQ Select) are not yet programmed. 1205 * 1206 * The fix for this issue, which will work for any controller 1207 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1208 * (select IRQ1), of the slot, before turning on slot power. 1209 * Selecting IRQ1 will result in INT# NOT being asserted 1210 * (because IRQ1 is selected), and IRQ1 won't be asserted 1211 * because our controllers don't generate IRQ1. 1212 */ 1213 reg = exca_getb(&sc->exca, EXCA_INTR); 1214 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1215 return (reg); 1216 } 1217 1218 /* 1219 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1220 * we don't have an interrupt storm on power on. This has the efect of 1221 * disabling card status change interrupts for the duration of poweron. 1222 */ 1223 static void 1224 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1225 { 1226 exca_putb(&sc->exca, EXCA_INTR, reg); 1227 } 1228 1229 static int 1230 cbb_power(device_t brdev, int volts) 1231 { 1232 uint32_t status, sock_ctrl; 1233 struct cbb_softc *sc = device_get_softc(brdev); 1234 int timeout; 1235 int retval = 0; 1236 uint32_t sockevent; 1237 uint8_t reg = 0; 1238 1239 status = cbb_get(sc, CBB_SOCKET_STATE); 1240 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1241 1242 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1243 switch (volts & CARD_VCCMASK) { 1244 case 5: 1245 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1246 break; 1247 case 3: 1248 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1249 break; 1250 case XV: 1251 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1252 break; 1253 case YV: 1254 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1255 break; 1256 case 0: 1257 break; 1258 default: 1259 return (0); /* power NEVER changed */ 1260 } 1261 1262 /* VPP == VCC */ 1263 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1264 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1265 1266 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1267 return (1); /* no change necessary */ 1268 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1269 if (volts != 0 && sc->chipset == CB_O2MICRO) 1270 reg = cbb_o2micro_power_hack(sc); 1271 1272 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1273 status = cbb_get(sc, CBB_SOCKET_STATE); 1274 1275 /* 1276 * XXX This busy wait is bogus. We should wait for a power 1277 * interrupt and then whine if the status is bad. If we're 1278 * worried about the card not coming up, then we should also 1279 * schedule a timeout which we can cancel in the power interrupt. 1280 */ 1281 timeout = 20; 1282 do { 1283 DELAY(20*1000); 1284 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1285 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1286 /* reset event status */ 1287 /* XXX should only reset EVENT_POWER */ 1288 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1289 if (timeout < 0) { 1290 printf ("VCC supply failed.\n"); 1291 goto done; 1292 } 1293 1294 /* XXX 1295 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1296 * is 20 ms, some PC-Card bridge requires longer duration. 1297 * XXX Note: We should check the stutus AFTER the delay to give time 1298 * for things to stabilize. 1299 */ 1300 DELAY(400*1000); 1301 1302 if (status & CBB_STATE_BAD_VCC_REQ) { 1303 device_printf(sc->dev, 1304 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1305 sock_ctrl ,status); 1306 printf("cbb_power: %dV\n", volts); 1307 goto done; 1308 } 1309 retval = 1; 1310 done:; 1311 if (volts != 0 && sc->chipset == CB_O2MICRO) 1312 cbb_o2micro_power_hack2(sc, reg); 1313 return (retval); 1314 } 1315 1316 /* 1317 * detect the voltage for the card, and set it. Since the power 1318 * used is the square of the voltage, lower voltages is a big win 1319 * and what Windows does (and what Microsoft prefers). The MS paper 1320 * also talks about preferring the CIS entry as well. In addition, 1321 * we power up with OE disabled. We'll set it later in the power 1322 * up sequence. 1323 */ 1324 static int 1325 cbb_do_power(device_t brdev) 1326 { 1327 struct cbb_softc *sc = device_get_softc(brdev); 1328 int voltage; 1329 1330 /* Don't enable OE */ 1331 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1332 1333 /* Prefer lowest voltage supported */ 1334 voltage = cbb_detect_voltage(brdev); 1335 cbb_power(brdev, CARD_OFF); 1336 if (voltage & CARD_YV_CARD) 1337 cbb_power(brdev, CARD_VCC(YV)); 1338 else if (voltage & CARD_XV_CARD) 1339 cbb_power(brdev, CARD_VCC(XV)); 1340 else if (voltage & CARD_3V_CARD) 1341 cbb_power(brdev, CARD_VCC(3)); 1342 else if (voltage & CARD_5V_CARD) 1343 cbb_power(brdev, CARD_VCC(5)); 1344 else { 1345 device_printf(brdev, "Unknown card voltage\n"); 1346 return (ENXIO); 1347 } 1348 return (0); 1349 } 1350 1351 /************************************************************************/ 1352 /* CardBus power functions */ 1353 /************************************************************************/ 1354 1355 static void 1356 cbb_cardbus_reset(device_t brdev) 1357 { 1358 struct cbb_softc *sc = device_get_softc(brdev); 1359 int delay_us; 1360 1361 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1362 1363 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1364 1365 DELAY(delay_us); 1366 1367 /* If a card exists, unreset it! */ 1368 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 1369 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1370 &~CBBM_BRIDGECTRL_RESET, 2); 1371 DELAY(delay_us); 1372 } 1373 } 1374 1375 static int 1376 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1377 { 1378 struct cbb_softc *sc = device_get_softc(brdev); 1379 int err; 1380 1381 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 1382 return (ENODEV); 1383 1384 err = cbb_do_power(brdev); 1385 if (err) 1386 return (err); 1387 cbb_cardbus_reset(brdev); 1388 return (0); 1389 } 1390 1391 static void 1392 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1393 { 1394 cbb_power(brdev, CARD_OFF); 1395 cbb_cardbus_reset(brdev); 1396 } 1397 1398 /************************************************************************/ 1399 /* CardBus Resource */ 1400 /************************************************************************/ 1401 1402 static int 1403 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1404 { 1405 int basereg; 1406 int limitreg; 1407 1408 if ((win < 0) || (win > 1)) { 1409 DEVPRINTF((brdev, 1410 "cbb_cardbus_io_open: window out of range %d\n", win)); 1411 return (EINVAL); 1412 } 1413 1414 basereg = win * 8 + CBBR_IOBASE0; 1415 limitreg = win * 8 + CBBR_IOLIMIT0; 1416 1417 pci_write_config(brdev, basereg, start, 4); 1418 pci_write_config(brdev, limitreg, end, 4); 1419 return (0); 1420 } 1421 1422 static int 1423 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1424 { 1425 int basereg; 1426 int limitreg; 1427 1428 if ((win < 0) || (win > 1)) { 1429 DEVPRINTF((brdev, 1430 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1431 return (EINVAL); 1432 } 1433 1434 basereg = win*8 + CBBR_MEMBASE0; 1435 limitreg = win*8 + CBBR_MEMLIMIT0; 1436 1437 pci_write_config(brdev, basereg, start, 4); 1438 pci_write_config(brdev, limitreg, end, 4); 1439 return (0); 1440 } 1441 1442 /* 1443 * XXX The following function belongs in the pci bus layer. 1444 */ 1445 static void 1446 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1447 { 1448 uint32_t starts[2]; 1449 uint32_t ends[2]; 1450 struct cbb_reslist *rle; 1451 int align; 1452 int prefetchable[2]; 1453 uint32_t reg; 1454 1455 starts[0] = starts[1] = 0xffffffff; 1456 ends[0] = ends[1] = 0; 1457 1458 if (type == SYS_RES_MEMORY) 1459 align = CBB_MEMALIGN; 1460 else if (type == SYS_RES_IOPORT) 1461 align = CBB_IOALIGN; 1462 else 1463 align = 1; 1464 1465 /* 1466 * This looks somewhat bogus, and doesn't seem to really respect 1467 * alignment. The alignment stuff is happening too late (it 1468 * should happen at allocation time, not activation time) and 1469 * this code looks generally to be too complex for the purpose 1470 * it surves. 1471 */ 1472 SLIST_FOREACH(rle, &sc->rl, link) { 1473 if (rle->type != type) 1474 ; 1475 else if (rle->res == NULL) { 1476 device_printf(sc->dev, "WARNING: Resource not reserved? " 1477 "(type=%d, addr=%lx)\n", 1478 rle->type, rman_get_start(rle->res)); 1479 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1480 /* XXX */ 1481 } else if (starts[0] == 0xffffffff) { 1482 starts[0] = rman_get_start(rle->res); 1483 ends[0] = rman_get_end(rle->res); 1484 prefetchable[0] = 1485 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1486 } else if (rman_get_end(rle->res) > ends[0] && 1487 rman_get_start(rle->res) - ends[0] < 1488 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1489 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1490 ends[0] = rman_get_end(rle->res); 1491 } else if (rman_get_start(rle->res) < starts[0] && 1492 starts[0] - rman_get_end(rle->res) < 1493 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1494 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1495 starts[0] = rman_get_start(rle->res); 1496 } else if (starts[1] == 0xffffffff) { 1497 starts[1] = rman_get_start(rle->res); 1498 ends[1] = rman_get_end(rle->res); 1499 prefetchable[1] = 1500 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1501 } else if (rman_get_end(rle->res) > ends[1] && 1502 rman_get_start(rle->res) - ends[1] < 1503 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1504 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1505 ends[1] = rman_get_end(rle->res); 1506 } else if (rman_get_start(rle->res) < starts[1] && 1507 starts[1] - rman_get_end(rle->res) < 1508 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1509 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1510 starts[1] = rman_get_start(rle->res); 1511 } else { 1512 uint32_t diffs[2]; 1513 int win; 1514 1515 diffs[0] = diffs[1] = 0xffffffff; 1516 if (rman_get_start(rle->res) > ends[0]) 1517 diffs[0] = rman_get_start(rle->res) - ends[0]; 1518 else if (rman_get_end(rle->res) < starts[0]) 1519 diffs[0] = starts[0] - rman_get_end(rle->res); 1520 if (rman_get_start(rle->res) > ends[1]) 1521 diffs[1] = rman_get_start(rle->res) - ends[1]; 1522 else if (rman_get_end(rle->res) < starts[1]) 1523 diffs[1] = starts[1] - rman_get_end(rle->res); 1524 1525 win = (diffs[0] <= diffs[1])?0:1; 1526 if (rman_get_start(rle->res) > ends[win]) 1527 ends[win] = rman_get_end(rle->res); 1528 else if (rman_get_end(rle->res) < starts[win]) 1529 starts[win] = rman_get_start(rle->res); 1530 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1531 prefetchable[win] = 0; 1532 } 1533 1534 if (starts[0] != 0xffffffff) 1535 starts[0] -= starts[0] % align; 1536 if (starts[1] != 0xffffffff) 1537 starts[1] -= starts[1] % align; 1538 if (ends[0] % align != 0) 1539 ends[0] += align - ends[0] % align - 1; 1540 if (ends[1] % align != 0) 1541 ends[1] += align - ends[1] % align - 1; 1542 } 1543 1544 if (type == SYS_RES_MEMORY) { 1545 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1546 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1547 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1548 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1549 CBBM_BRIDGECTRL_PREFETCH_1); 1550 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1551 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1552 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1553 } else if (type == SYS_RES_IOPORT) { 1554 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1555 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1556 } 1557 } 1558 1559 static int 1560 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1561 int rid, struct resource *res) 1562 { 1563 int ret; 1564 1565 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1566 type, rid, res); 1567 if (ret != 0) 1568 return (ret); 1569 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1570 return (0); 1571 } 1572 1573 static int 1574 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1575 int rid, struct resource *res) 1576 { 1577 int ret; 1578 1579 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1580 type, rid, res); 1581 if (ret != 0) 1582 return (ret); 1583 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1584 return (0); 1585 } 1586 1587 static struct resource * 1588 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1589 int *rid, u_long start, u_long end, u_long count, u_int flags) 1590 { 1591 struct cbb_softc *sc = device_get_softc(brdev); 1592 int tmp; 1593 struct resource *res; 1594 u_long align; 1595 1596 switch (type) { 1597 case SYS_RES_IRQ: 1598 tmp = rman_get_start(sc->irq_res); 1599 if (start > tmp || end < tmp || count != 1) { 1600 device_printf(child, "requested interrupt %ld-%ld," 1601 "count = %ld not supported by cbb\n", 1602 start, end, count); 1603 return (NULL); 1604 } 1605 start = end = tmp; 1606 flags |= RF_SHAREABLE; 1607 break; 1608 case SYS_RES_IOPORT: 1609 if (start <= cbb_start_32_io) 1610 start = cbb_start_32_io; 1611 if (end < start) 1612 end = start; 1613 break; 1614 case SYS_RES_MEMORY: 1615 if (start <= cbb_start_mem) 1616 start = cbb_start_mem; 1617 if (end < start) 1618 end = start; 1619 if (count < CBB_MEMALIGN) 1620 align = CBB_MEMALIGN; 1621 else 1622 align = count; 1623 if (align > (1 << RF_ALIGNMENT(flags))) 1624 flags = (flags & ~RF_ALIGNMENT_MASK) | 1625 rman_make_alignment_flags(align); 1626 break; 1627 } 1628 1629 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1630 start, end, count, flags & ~RF_ACTIVE); 1631 if (res == NULL) { 1632 printf("cbb alloc res fail\n"); 1633 return (NULL); 1634 } 1635 cbb_insert_res(sc, res, type, *rid); 1636 if (flags & RF_ACTIVE) 1637 if (bus_activate_resource(child, type, *rid, res) != 0) { 1638 bus_release_resource(child, type, *rid, res); 1639 return (NULL); 1640 } 1641 1642 return (res); 1643 } 1644 1645 static int 1646 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1647 int rid, struct resource *res) 1648 { 1649 struct cbb_softc *sc = device_get_softc(brdev); 1650 int error; 1651 1652 if (rman_get_flags(res) & RF_ACTIVE) { 1653 error = bus_deactivate_resource(child, type, rid, res); 1654 if (error != 0) 1655 return (error); 1656 } 1657 cbb_remove_res(sc, res); 1658 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1659 type, rid, res)); 1660 } 1661 1662 /************************************************************************/ 1663 /* PC Card Power Functions */ 1664 /************************************************************************/ 1665 1666 static int 1667 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1668 { 1669 struct cbb_softc *sc = device_get_softc(brdev); 1670 int err; 1671 1672 DPRINTF(("cbb_pcic_socket_enable:\n")); 1673 1674 /* power down/up the socket to reset */ 1675 err = cbb_do_power(brdev); 1676 if (err) 1677 return (err); 1678 exca_reset(&sc->exca, child); 1679 1680 return (0); 1681 } 1682 1683 static void 1684 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1685 { 1686 struct cbb_softc *sc = device_get_softc(brdev); 1687 1688 DPRINTF(("cbb_pcic_socket_disable\n")); 1689 1690 /* reset signal asserting... */ 1691 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1692 DELAY(2*1000); 1693 1694 /* power down the socket */ 1695 cbb_power(brdev, CARD_OFF); 1696 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1697 1698 /* wait 300ms until power fails (Tpf). */ 1699 DELAY(300 * 1000); 1700 } 1701 1702 /************************************************************************/ 1703 /* POWER methods */ 1704 /************************************************************************/ 1705 1706 static int 1707 cbb_power_enable_socket(device_t brdev, device_t child) 1708 { 1709 struct cbb_softc *sc = device_get_softc(brdev); 1710 1711 if (sc->flags & CBB_16BIT_CARD) 1712 return (cbb_pcic_power_enable_socket(brdev, child)); 1713 else 1714 return (cbb_cardbus_power_enable_socket(brdev, child)); 1715 } 1716 1717 static void 1718 cbb_power_disable_socket(device_t brdev, device_t child) 1719 { 1720 struct cbb_softc *sc = device_get_softc(brdev); 1721 if (sc->flags & CBB_16BIT_CARD) 1722 cbb_pcic_power_disable_socket(brdev, child); 1723 else 1724 cbb_cardbus_power_disable_socket(brdev, child); 1725 } 1726 1727 static int 1728 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1729 struct resource *res) 1730 { 1731 struct cbb_softc *sc = device_get_softc(brdev); 1732 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1733 } 1734 1735 static int 1736 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1737 int rid, struct resource *res) 1738 { 1739 struct cbb_softc *sc = device_get_softc(brdev); 1740 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1741 } 1742 1743 static struct resource * 1744 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1745 u_long start, u_long end, u_long count, u_int flags) 1746 { 1747 struct resource *res = NULL; 1748 struct cbb_softc *sc = device_get_softc(brdev); 1749 int align; 1750 int tmp; 1751 1752 switch (type) { 1753 case SYS_RES_MEMORY: 1754 if (start < cbb_start_mem) 1755 start = cbb_start_mem; 1756 if (end < start) 1757 end = start; 1758 if (count < CBB_MEMALIGN) 1759 align = CBB_MEMALIGN; 1760 else 1761 align = count; 1762 if (align > (1 << RF_ALIGNMENT(flags))) 1763 flags = (flags & ~RF_ALIGNMENT_MASK) | 1764 rman_make_alignment_flags(align); 1765 break; 1766 case SYS_RES_IOPORT: 1767 if (start < cbb_start_16_io) 1768 start = cbb_start_16_io; 1769 if (end < start) 1770 end = start; 1771 break; 1772 case SYS_RES_IRQ: 1773 tmp = rman_get_start(sc->irq_res); 1774 if (start > tmp || end < tmp || count != 1) { 1775 device_printf(child, "requested interrupt %ld-%ld," 1776 "count = %ld not supported by cbb\n", 1777 start, end, count); 1778 return (NULL); 1779 } 1780 flags |= RF_SHAREABLE; 1781 start = end = rman_get_start(sc->irq_res); 1782 break; 1783 } 1784 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1785 start, end, count, flags & ~RF_ACTIVE); 1786 if (res == NULL) 1787 return (NULL); 1788 cbb_insert_res(sc, res, type, *rid); 1789 if (flags & RF_ACTIVE) { 1790 if (bus_activate_resource(child, type, *rid, res) != 0) { 1791 bus_release_resource(child, type, *rid, res); 1792 return (NULL); 1793 } 1794 } 1795 1796 return (res); 1797 } 1798 1799 static int 1800 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1801 int rid, struct resource *res) 1802 { 1803 struct cbb_softc *sc = device_get_softc(brdev); 1804 int error; 1805 1806 if (rman_get_flags(res) & RF_ACTIVE) { 1807 error = bus_deactivate_resource(child, type, rid, res); 1808 if (error != 0) 1809 return (error); 1810 } 1811 cbb_remove_res(sc, res); 1812 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1813 type, rid, res)); 1814 } 1815 1816 /************************************************************************/ 1817 /* PC Card methods */ 1818 /************************************************************************/ 1819 1820 static int 1821 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1822 uint32_t flags) 1823 { 1824 struct cbb_softc *sc = device_get_softc(brdev); 1825 struct resource *res; 1826 1827 if (type != SYS_RES_MEMORY) 1828 return (EINVAL); 1829 res = cbb_find_res(sc, type, rid); 1830 if (res == NULL) { 1831 device_printf(brdev, 1832 "set_res_flags: specified rid not found\n"); 1833 return (ENOENT); 1834 } 1835 return (exca_mem_set_flags(&sc->exca, res, flags)); 1836 } 1837 1838 static int 1839 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1840 uint32_t cardaddr, uint32_t *deltap) 1841 { 1842 struct cbb_softc *sc = device_get_softc(brdev); 1843 struct resource *res; 1844 1845 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1846 if (res == NULL) { 1847 device_printf(brdev, 1848 "set_memory_offset: specified rid not found\n"); 1849 return (ENOENT); 1850 } 1851 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1852 } 1853 1854 /************************************************************************/ 1855 /* BUS Methods */ 1856 /************************************************************************/ 1857 1858 1859 static int 1860 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1861 struct resource *r) 1862 { 1863 struct cbb_softc *sc = device_get_softc(brdev); 1864 1865 if (sc->flags & CBB_16BIT_CARD) 1866 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1867 else 1868 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1869 r)); 1870 } 1871 1872 static int 1873 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1874 int rid, struct resource *r) 1875 { 1876 struct cbb_softc *sc = device_get_softc(brdev); 1877 1878 if (sc->flags & CBB_16BIT_CARD) 1879 return (cbb_pcic_deactivate_resource(brdev, child, type, 1880 rid, r)); 1881 else 1882 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1883 rid, r)); 1884 } 1885 1886 static struct resource * 1887 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1888 u_long start, u_long end, u_long count, u_int flags) 1889 { 1890 struct cbb_softc *sc = device_get_softc(brdev); 1891 1892 if (sc->flags & CBB_16BIT_CARD) 1893 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1894 start, end, count, flags)); 1895 else 1896 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1897 start, end, count, flags)); 1898 } 1899 1900 static int 1901 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1902 struct resource *r) 1903 { 1904 struct cbb_softc *sc = device_get_softc(brdev); 1905 1906 if (sc->flags & CBB_16BIT_CARD) 1907 return (cbb_pcic_release_resource(brdev, child, type, 1908 rid, r)); 1909 else 1910 return (cbb_cardbus_release_resource(brdev, child, type, 1911 rid, r)); 1912 } 1913 1914 static int 1915 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1916 { 1917 struct cbb_softc *sc = device_get_softc(brdev); 1918 1919 switch (which) { 1920 case PCIB_IVAR_BUS: 1921 *result = sc->secbus; 1922 return (0); 1923 } 1924 return (ENOENT); 1925 } 1926 1927 static int 1928 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1929 { 1930 struct cbb_softc *sc = device_get_softc(brdev); 1931 1932 switch (which) { 1933 case PCIB_IVAR_BUS: 1934 sc->secbus = value; 1935 break; 1936 } 1937 return (ENOENT); 1938 } 1939 1940 /************************************************************************/ 1941 /* PCI compat methods */ 1942 /************************************************************************/ 1943 1944 static int 1945 cbb_maxslots(device_t brdev) 1946 { 1947 return (0); 1948 } 1949 1950 static uint32_t 1951 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1952 { 1953 /* 1954 * Pass through to the next ppb up the chain (i.e. our grandparent). 1955 */ 1956 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1957 b, s, f, reg, width)); 1958 } 1959 1960 static void 1961 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1962 int width) 1963 { 1964 /* 1965 * Pass through to the next ppb up the chain (i.e. our grandparent). 1966 */ 1967 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1968 b, s, f, reg, val, width); 1969 } 1970 1971 static int 1972 cbb_suspend(device_t self) 1973 { 1974 int error = 0; 1975 struct cbb_softc *sc = device_get_softc(self); 1976 1977 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1978 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1979 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1980 error = bus_generic_suspend(self); 1981 return (error); 1982 } 1983 1984 static int 1985 cbb_resume(device_t self) 1986 { 1987 int error = 0; 1988 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1989 uint32_t tmp; 1990 1991 /* 1992 * Some BIOSes will not save the BARs for the pci chips, so we 1993 * must do it ourselves. If the BAR is reset to 0 for an I/O 1994 * device, it will read back as 0x1, so no explicit test for 1995 * memory devices are needed. 1996 * 1997 * Note: The PCI bus code should do this automatically for us on 1998 * suspend/resume, but until it does, we have to cope. 1999 */ 2000 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 2001 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 2002 rman_get_start(sc->base_res))); 2003 2004 cbb_chipinit(sc); 2005 2006 /* reset interrupt -- Do we really need to do this? */ 2007 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 2008 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 2009 2010 /* re-establish the interrupt. */ 2011 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 2012 cbb_intr, sc, &sc->intrhand)) { 2013 device_printf(self, "couldn't re-establish interrupt"); 2014 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 2015 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 2016 sc->base_res); 2017 sc->irq_res = NULL; 2018 sc->base_res = NULL; 2019 return (ENOMEM); 2020 } 2021 2022 /* CSC Interrupt: Card detect interrupt on */ 2023 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 2024 2025 /* Signal the thread to wakeup. */ 2026 mtx_lock(&sc->mtx); 2027 cv_signal(&sc->cv); 2028 mtx_unlock(&sc->mtx); 2029 2030 error = bus_generic_resume(self); 2031 2032 return (error); 2033 } 2034 2035 static int 2036 cbb_child_present(device_t self) 2037 { 2038 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 2039 uint32_t sockstate; 2040 2041 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 2042 return (CBB_CARD_PRESENT(sockstate) && 2043 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 2044 } 2045 2046 static device_method_t cbb_methods[] = { 2047 /* Device interface */ 2048 DEVMETHOD(device_probe, cbb_probe), 2049 DEVMETHOD(device_attach, cbb_attach), 2050 DEVMETHOD(device_detach, cbb_detach), 2051 DEVMETHOD(device_shutdown, cbb_shutdown), 2052 DEVMETHOD(device_suspend, cbb_suspend), 2053 DEVMETHOD(device_resume, cbb_resume), 2054 2055 /* bus methods */ 2056 DEVMETHOD(bus_print_child, bus_generic_print_child), 2057 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 2058 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 2059 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 2060 DEVMETHOD(bus_release_resource, cbb_release_resource), 2061 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 2062 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 2063 DEVMETHOD(bus_driver_added, cbb_driver_added), 2064 DEVMETHOD(bus_child_detached, cbb_child_detached), 2065 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 2066 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 2067 DEVMETHOD(bus_child_present, cbb_child_present), 2068 2069 /* 16-bit card interface */ 2070 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 2071 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 2072 2073 /* power interface */ 2074 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 2075 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 2076 2077 /* pcib compatibility interface */ 2078 DEVMETHOD(pcib_maxslots, cbb_maxslots), 2079 DEVMETHOD(pcib_read_config, cbb_read_config), 2080 DEVMETHOD(pcib_write_config, cbb_write_config), 2081 {0,0} 2082 }; 2083 2084 static driver_t cbb_driver = { 2085 "cbb", 2086 cbb_methods, 2087 sizeof(struct cbb_softc) 2088 }; 2089 2090 static devclass_t cbb_devclass; 2091 2092 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2093 MODULE_VERSION(cbb, 1); 2094 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2095