1 /* 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 __FBSDID("$FreeBSD$"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/condvar.h> 82 #include <sys/errno.h> 83 #include <sys/kernel.h> 84 #include <sys/module.h> 85 #include <sys/lock.h> 86 #include <sys/malloc.h> 87 #include <sys/mutex.h> 88 #include <sys/sysctl.h> 89 #include <sys/kthread.h> 90 #include <sys/bus.h> 91 #include <machine/bus.h> 92 #include <sys/rman.h> 93 #include <machine/resource.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <machine/clock.h> 98 99 #include <dev/pccard/pccardreg.h> 100 #include <dev/pccard/pccardvar.h> 101 102 #include <dev/exca/excareg.h> 103 #include <dev/exca/excavar.h> 104 105 #include <dev/pccbb/pccbbreg.h> 106 #include <dev/pccbb/pccbbvar.h> 107 108 #include "power_if.h" 109 #include "card_if.h" 110 #include "pcib_if.h" 111 112 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 113 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 114 115 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 116 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 117 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 118 pci_write_config(DEV, REG, ( \ 119 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 120 121 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 122 123 #define CBB_START_MEM 0x88000000 124 #define CBB_START_32_IO 0x1000 125 #define CBB_START_16_IO 0x100 126 127 struct yenta_chipinfo { 128 uint32_t yc_id; 129 const char *yc_name; 130 int yc_chiptype; 131 } yc_chipsets[] = { 132 /* Texas Instruments chips */ 133 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 134 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 135 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 136 137 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 143 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 144 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 145 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 147 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 151 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 158 159 /* ENE */ 160 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 166 167 /* Ricoh chips */ 168 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 169 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 170 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 171 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 172 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 173 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 174 175 /* Toshiba products */ 176 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 177 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 178 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 179 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 180 181 /* Cirrus Logic */ 182 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 183 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 184 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 185 186 /* 02Micro */ 187 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 188 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 189 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 190 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 191 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 194 195 /* sentinel */ 196 {0 /* null id */, "unknown", CB_UNKNOWN}, 197 }; 198 199 /* sysctl vars */ 200 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 201 202 /* There's no way to say TUNEABLE_LONG to get the right types */ 203 u_long cbb_start_mem = CBB_START_MEM; 204 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 205 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 206 &cbb_start_mem, CBB_START_MEM, 207 "Starting address for memory allocations"); 208 209 u_long cbb_start_16_io = CBB_START_16_IO; 210 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 211 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 212 &cbb_start_16_io, CBB_START_16_IO, 213 "Starting ioport for 16-bit cards"); 214 215 u_long cbb_start_32_io = CBB_START_32_IO; 216 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 217 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 218 &cbb_start_32_io, CBB_START_32_IO, 219 "Starting ioport for 32-bit cards"); 220 221 int cbb_debug = 0; 222 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 223 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 224 "Verbose cardbus bridge debugging"); 225 226 static int cbb_chipset(uint32_t pci_id, const char **namep); 227 static int cbb_probe(device_t brdev); 228 static void cbb_chipinit(struct cbb_softc *sc); 229 static int cbb_attach(device_t brdev); 230 static int cbb_detach(device_t brdev); 231 static int cbb_shutdown(device_t brdev); 232 static void cbb_driver_added(device_t brdev, driver_t *driver); 233 static void cbb_child_detached(device_t brdev, device_t child); 234 static void cbb_event_thread(void *arg); 235 static void cbb_insert(struct cbb_softc *sc); 236 static void cbb_removal(struct cbb_softc *sc); 237 static void cbb_intr(void *arg); 238 static int cbb_detect_voltage(device_t brdev); 239 static int cbb_power(device_t brdev, int volts); 240 static void cbb_cardbus_reset(device_t brdev); 241 static int cbb_cardbus_power_enable_socket(device_t brdev, 242 device_t child); 243 static void cbb_cardbus_power_disable_socket(device_t brdev, 244 device_t child); 245 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 246 uint32_t end); 247 static int cbb_cardbus_mem_open(device_t brdev, int win, 248 uint32_t start, uint32_t end); 249 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 250 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 251 int type, int rid, struct resource *res); 252 static int cbb_cardbus_deactivate_resource(device_t brdev, 253 device_t child, int type, int rid, struct resource *res); 254 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 255 device_t child, int type, int *rid, u_long start, 256 u_long end, u_long count, u_int flags); 257 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 258 int type, int rid, struct resource *res); 259 static int cbb_power_enable_socket(device_t brdev, device_t child); 260 static void cbb_power_disable_socket(device_t brdev, device_t child); 261 static int cbb_activate_resource(device_t brdev, device_t child, 262 int type, int rid, struct resource *r); 263 static int cbb_deactivate_resource(device_t brdev, device_t child, 264 int type, int rid, struct resource *r); 265 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 266 int type, int *rid, u_long start, u_long end, u_long count, 267 u_int flags); 268 static int cbb_release_resource(device_t brdev, device_t child, 269 int type, int rid, struct resource *r); 270 static int cbb_read_ivar(device_t brdev, device_t child, int which, 271 uintptr_t *result); 272 static int cbb_write_ivar(device_t brdev, device_t child, int which, 273 uintptr_t value); 274 static int cbb_maxslots(device_t brdev); 275 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 276 int reg, int width); 277 static void cbb_write_config(device_t brdev, int b, int s, int f, 278 int reg, uint32_t val, int width); 279 280 /* 281 */ 282 static __inline void 283 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 284 { 285 bus_space_write_4(sc->bst, sc->bsh, reg, val); 286 } 287 288 static __inline uint32_t 289 cbb_get(struct cbb_softc *sc, uint32_t reg) 290 { 291 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 292 } 293 294 static __inline void 295 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 296 { 297 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 298 } 299 300 static __inline void 301 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 302 { 303 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 304 } 305 306 static void 307 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 308 { 309 struct cbb_reslist *rle; 310 311 SLIST_FOREACH(rle, &sc->rl, link) { 312 if (rle->res == res) { 313 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 314 free(rle, M_DEVBUF); 315 return; 316 } 317 } 318 } 319 320 static struct resource * 321 cbb_find_res(struct cbb_softc *sc, int type, int rid) 322 { 323 struct cbb_reslist *rle; 324 325 SLIST_FOREACH(rle, &sc->rl, link) 326 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 327 return (rle->res); 328 return (NULL); 329 } 330 331 static void 332 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 333 int rid) 334 { 335 struct cbb_reslist *rle; 336 337 /* 338 * Need to record allocated resource so we can iterate through 339 * it later. 340 */ 341 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 342 if (rle == NULL) 343 panic("cbb_cardbus_alloc_resource: can't record entry!"); 344 rle->res = res; 345 rle->type = type; 346 rle->rid = rid; 347 SLIST_INSERT_HEAD(&sc->rl, rle, link); 348 } 349 350 static void 351 cbb_destroy_res(struct cbb_softc *sc) 352 { 353 struct cbb_reslist *rle; 354 355 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 356 device_printf(sc->dev, "Danger Will Robinson: Resource " 357 "left allocated! This is a bug... " 358 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 359 rman_get_start(rle->res)); 360 SLIST_REMOVE_HEAD(&sc->rl, link); 361 free(rle, M_DEVBUF); 362 } 363 } 364 365 /************************************************************************/ 366 /* Probe/Attach */ 367 /************************************************************************/ 368 369 static int 370 cbb_chipset(uint32_t pci_id, const char **namep) 371 { 372 struct yenta_chipinfo *ycp; 373 374 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 375 continue; 376 if (namep != NULL) 377 *namep = ycp->yc_name; 378 return (ycp->yc_chiptype); 379 } 380 381 static int 382 cbb_probe(device_t brdev) 383 { 384 const char *name; 385 uint32_t progif; 386 uint32_t subclass; 387 388 /* 389 * Do we know that we support the chipset? If so, then we 390 * accept the device. 391 */ 392 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 393 device_set_desc(brdev, name); 394 return (0); 395 } 396 397 /* 398 * We do support generic CardBus bridges. All that we've seen 399 * to date have progif 0 (the Yenta spec, and successors mandate 400 * this). We do not support PCI PCMCIA bridges (with one exception) 401 * with this driver since they generally are I/O mapped. Those 402 * are supported by the pcic driver. This should help us be more 403 * future proof. 404 */ 405 subclass = pci_get_subclass(brdev); 406 progif = pci_get_progif(brdev); 407 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 408 device_set_desc(brdev, "PCI-CardBus Bridge"); 409 return (0); 410 } 411 return (ENXIO); 412 } 413 414 415 /* 416 * Disable function interrupts by telling the bridge to generate IRQ1 417 * interrupts. These interrupts aren't really generated by the chip, since 418 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 419 * initialization, so this helps to work around the problem. 420 * 421 * XXX We can't do this workaround for all chipsets, because this 422 * XXX causes interference with the keyboard because somechipsets will 423 * XXX actually signal IRQ1 over their serial interrupt connections to 424 * XXX the south bridge. Disable it it for now. 425 */ 426 static void 427 cbb_disable_func_intr(struct cbb_softc *sc) 428 { 429 #if 0 430 uint8_t reg; 431 432 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 433 EXCA_INTR_IRQ_RESERVED1; 434 exca_putb(&sc->exca, EXCA_INTR, reg); 435 #endif 436 } 437 438 /* 439 * Enable function interrupts. We turn on function interrupts when the card 440 * requests an interrupt. The PCMCIA standard says that we should set 441 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 442 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 443 * cards. 444 */ 445 static void 446 cbb_enable_func_intr(struct cbb_softc *sc) 447 { 448 uint8_t reg; 449 450 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 451 EXCA_INTR_IRQ_NONE; 452 exca_putb(&sc->exca, EXCA_INTR, reg); 453 } 454 455 static void 456 cbb_chipinit(struct cbb_softc *sc) 457 { 458 uint32_t mux, sysctrl, reg; 459 460 /* Set CardBus latency timer */ 461 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 462 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 463 464 /* Set PCI latency timer */ 465 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 466 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 467 468 /* Enable memory access */ 469 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 470 | PCIM_CMD_MEMEN 471 | PCIM_CMD_PORTEN 472 | PCIM_CMD_BUSMASTEREN, 2); 473 474 /* disable Legacy IO */ 475 switch (sc->chipset) { 476 case CB_RF5C46X: 477 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 478 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 479 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 480 break; 481 default: 482 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 483 break; 484 } 485 486 /* Use PCI interrupt for interrupt routing */ 487 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 488 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 489 CBBM_BRIDGECTRL_INTR_IREQ_EN), 490 | CBBM_BRIDGECTRL_WRITE_POST_EN, 491 2); 492 493 /* 494 * XXX this should be a function table, ala OLDCARD. This means 495 * that we could more easily support ISA interrupts for pccard 496 * cards if we had to. 497 */ 498 switch (sc->chipset) { 499 case CB_TI113X: 500 /* 501 * The TI 1031, TI 1130 and TI 1131 all require another bit 502 * be set to enable PCI routing of interrupts, and then 503 * a bit for each of the CSC and Function interrupts we 504 * want routed. 505 */ 506 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 507 | CBBM_CBCTRL_113X_PCI_INTR | 508 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 509 1); 510 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 511 & ~(CBBM_DEVCTRL_INT_SERIAL | 512 CBBM_DEVCTRL_INT_PCI), 1); 513 break; 514 case CB_TI12XX: 515 /* 516 * Some TI 12xx (and [14][45]xx) based pci cards 517 * sometimes have issues with the MFUNC register not 518 * being initialized due to a bad EEPROM on board. 519 * Laptops that this matters on have this register 520 * properly initialized. 521 * 522 * The TI125X parts have a different register. 523 */ 524 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 525 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 526 if (mux == 0) { 527 mux = (mux & ~CBBM_MFUNC_PIN0) | 528 CBBM_MFUNC_PIN0_INTA; 529 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 530 mux = (mux & ~CBBM_MFUNC_PIN1) | 531 CBBM_MFUNC_PIN1_INTB; 532 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 533 } 534 /*FALLTHROUGH*/ 535 case CB_TI125X: 536 /* 537 * Disable zoom video. Some machines initialize this 538 * improperly and exerpience has shown that this helps 539 * prevent strange behavior. 540 */ 541 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 542 break; 543 case CB_O2MICRO: 544 /* 545 * Issue #1: INT# generated at the same time as 546 * selected ISA IRQ. When IREQ# or STSCHG# is active, 547 * in addition to the ISA IRQ being generated, INT# 548 * will also be generated at the same time. 549 * 550 * Some of the older controllers have an issue in 551 * which the slot's PCI INT# will be asserted whenever 552 * IREQ# or STSCGH# is asserted even if ExCA registers 553 * 03h or 05h have an ISA IRQ selected. 554 * 555 * The fix for this issue, which will work for any 556 * controller (old or new), is to set ExCA registers 557 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 558 * These bits are undocumented. By setting this 559 * register (of each slot) to '1010xxxxb' a routing of 560 * IREQ# to INTC# and STSCHG# to INTC# is selected. 561 * Since INTC# isn't connected there will be no 562 * unexpected PCI INT when IREQ# or STSCHG# is active. 563 * However, INTA# (slot 0) or INTB# (slot 1) will 564 * still be correctly generated if NO ISA IRQ is 565 * selected (ExCA regs 03h or 05h are cleared). 566 */ 567 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 568 reg = (reg & 0x0f) | 569 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 570 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 571 572 break; 573 case CB_TOPIC97: 574 /* 575 * Disable Zoom Video, ToPIC 97, 100. 576 */ 577 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 578 /* 579 * ToPIC 97, 100 580 * At offset 0xa1: INTERRUPT CONTROL register 581 * 0x1: Turn on INT interrupts. 582 */ 583 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 584 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 585 goto topic_common; 586 case CB_TOPIC95: 587 /* 588 * SOCKETCTRL appears to be TOPIC 95/B specific 589 */ 590 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 591 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 592 593 topic_common:; 594 /* 595 * At offset 0xa0: SLOT CONTROL 596 * 0x80 Enable CardBus Functionality 597 * 0x40 Enable CardBus and PC Card registers 598 * 0x20 Lock ID in exca regs 599 * 0x10 Write protect ID in config regs 600 * Clear the rest of the bits, which defaults the slot 601 * in legacy mode to 0x3e0 and offset 0. (legacy 602 * mode is determined elsewhere) 603 */ 604 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 605 CBBM_TOPIC_SLOTCTRL_SLOTON | 606 CBBM_TOPIC_SLOTCTRL_SLOTEN | 607 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 608 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 609 610 /* 611 * At offset 0xa3 Card Detect Control Register 612 * 0x80 CARDBUS enbale 613 * 0x01 Cleared for hardware change detect 614 */ 615 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 616 | CBBM_TOPIC_CDC_CARDBUS, 617 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 618 break; 619 } 620 621 /* 622 * Need to tell ExCA registers to CSC interrupts route via PCI 623 * interrupts. There are two ways to do this. Once is to set 624 * INTR_ENABLE and the other is to set CSC to 0. Since both 625 * methods are mutually compatible, we do both. 626 */ 627 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 628 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 629 630 cbb_disable_func_intr(sc); 631 632 /* close all memory and io windows */ 633 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 634 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 635 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 636 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 637 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 638 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 639 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 640 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 641 } 642 643 #ifndef BURN_BRIDGES 644 /* 645 * Still need this because the pci code only does power for type 0 646 * header devices. 647 */ 648 static void 649 cbb_powerstate_d0(device_t dev) 650 { 651 u_int32_t membase, irq; 652 653 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 654 /* Save important PCI config data. */ 655 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 656 irq = pci_read_config(dev, PCIR_INTLINE, 4); 657 658 /* Reset the power state. */ 659 device_printf(dev, "chip is in D%d power mode " 660 "-- setting to D0\n", pci_get_powerstate(dev)); 661 662 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 663 664 /* Restore PCI config data. */ 665 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 666 pci_write_config(dev, PCIR_INTLINE, irq, 4); 667 } 668 } 669 #endif 670 671 /* 672 * Print out the config space 673 */ 674 static void 675 cbb_print_config(device_t dev) 676 { 677 int i; 678 679 device_printf(dev, "PCI Configuration space:"); 680 for (i = 0; i < 256; i += 4) { 681 if (i % 16 == 0) 682 printf("\n 0x%02x: ", i); 683 printf("0x%08x ", pci_read_config(dev, i, 4)); 684 } 685 printf("\n"); 686 } 687 688 static int 689 cbb_attach(device_t brdev) 690 { 691 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 692 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 693 int rid, bus, pribus; 694 device_t parent; 695 696 parent = device_get_parent(brdev); 697 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 698 cv_init(&sc->cv, "cbb cv"); 699 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 700 sc->dev = brdev; 701 sc->cbdev = NULL; 702 sc->exca.pccarddev = NULL; 703 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 704 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 705 SLIST_INIT(&sc->rl); 706 STAILQ_INIT(&sc->intr_handlers); 707 #ifndef BURN_BRIDGES 708 cbb_powerstate_d0(brdev); 709 #endif 710 711 rid = CBBR_SOCKBASE; 712 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 713 RF_ACTIVE); 714 if (!sc->base_res) { 715 device_printf(brdev, "Could not map register memory\n"); 716 mtx_destroy(&sc->mtx); 717 cv_destroy(&sc->cv); 718 return (ENOMEM); 719 } else { 720 DEVPRINTF((brdev, "Found memory at %08lx\n", 721 rman_get_start(sc->base_res))); 722 } 723 724 sc->bst = rman_get_bustag(sc->base_res); 725 sc->bsh = rman_get_bushandle(sc->base_res); 726 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 727 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 728 sc->exca.chipset = EXCA_CARDBUS; 729 cbb_chipinit(sc); 730 731 /* 732 * This is a gross hack. We should be scanning the entire pci 733 * tree, assigning bus numbers in a way such that we (1) can 734 * reserve 1 extra bus just in case and (2) all sub busses 735 * are in an appropriate range. 736 */ 737 bus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 738 pribus = pcib_get_bus(parent); 739 DEVPRINTF((brdev, "Secondary bus is %d\n", bus)); 740 if (bus == 0) { 741 if (curr_bus_number <= pribus) 742 curr_bus_number = pribus + 1; 743 if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) { 744 DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus)); 745 pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1); 746 } 747 bus = curr_bus_number; 748 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus, 749 bus + 1)); 750 sc->secbus = bus; 751 sc->subbus = bus + 1; 752 pci_write_config(brdev, PCIR_SECBUS_2, bus, 1); 753 pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1); 754 curr_bus_number += 2; 755 } 756 757 /* attach children */ 758 sc->cbdev = device_add_child(brdev, "cardbus", -1); 759 if (sc->cbdev == NULL) 760 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 761 else if (device_probe_and_attach(sc->cbdev) != 0) 762 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 763 764 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 765 if (sc->exca.pccarddev == NULL) 766 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 767 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) 768 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 769 770 /* Map and establish the interrupt. */ 771 rid = 0; 772 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 773 RF_SHAREABLE | RF_ACTIVE); 774 if (sc->irq_res == NULL) { 775 printf("cbb: Unable to map IRQ...\n"); 776 goto err; 777 } 778 779 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 780 cbb_intr, sc, &sc->intrhand)) { 781 device_printf(brdev, "couldn't establish interrupt"); 782 goto err; 783 } 784 785 /* reset 16-bit pcmcia bus */ 786 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 787 788 /* turn off power */ 789 cbb_power(brdev, CARD_OFF); 790 791 /* CSC Interrupt: Card detect interrupt on */ 792 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 793 794 /* reset interrupt */ 795 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 796 797 if (bootverbose) 798 cbb_print_config(brdev); 799 800 /* Start the thread */ 801 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 802 "%s", device_get_nameunit(brdev))) { 803 device_printf(brdev, "unable to create event thread.\n"); 804 panic("cbb_create_event_thread"); 805 } 806 return (0); 807 err: 808 if (sc->irq_res) 809 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 810 if (sc->base_res) { 811 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 812 sc->base_res); 813 } 814 mtx_destroy(&sc->mtx); 815 cv_destroy(&sc->cv); 816 return (ENOMEM); 817 } 818 819 static int 820 cbb_detach(device_t brdev) 821 { 822 struct cbb_softc *sc = device_get_softc(brdev); 823 int numdevs; 824 device_t *devlist; 825 int tmp; 826 int error; 827 828 device_get_children(brdev, &devlist, &numdevs); 829 830 error = 0; 831 for (tmp = 0; tmp < numdevs; tmp++) { 832 if (device_detach(devlist[tmp]) == 0) 833 device_delete_child(brdev, devlist[tmp]); 834 else 835 error++; 836 } 837 free(devlist, M_TEMP); 838 if (error > 0) 839 return (ENXIO); 840 841 mtx_lock(&sc->mtx); 842 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 843 sc->flags |= CBB_KTHREAD_DONE; 844 if (sc->flags & CBB_KTHREAD_RUNNING) { 845 cv_broadcast(&sc->cv); 846 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 847 } 848 mtx_unlock(&sc->mtx); 849 850 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 851 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 852 sc->base_res); 853 mtx_destroy(&sc->mtx); 854 cv_destroy(&sc->cv); 855 return (0); 856 } 857 858 static int 859 cbb_shutdown(device_t brdev) 860 { 861 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 862 /* properly reset everything at shutdown */ 863 864 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 865 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 866 867 cbb_set(sc, CBB_SOCKET_MASK, 0); 868 869 cbb_power(brdev, CARD_OFF); 870 871 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 872 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 873 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 874 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 875 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 876 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 877 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 878 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 879 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 880 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 881 return (0); 882 } 883 884 static int 885 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 886 int flags, driver_intr_t *intr, void *arg, void **cookiep) 887 { 888 struct cbb_intrhand *ih; 889 struct cbb_softc *sc = device_get_softc(dev); 890 891 /* 892 * You aren't allowed to have fast interrupts for pccard/cardbus 893 * things since those interrupts are PCI and shared. Since we use 894 * the PCI interrupt for the status change interrupts, it can't be 895 * free for use by the driver. Fast interrupts must not be shared. 896 */ 897 if ((flags & INTR_FAST) != 0) 898 return (EINVAL); 899 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 900 if (ih == NULL) 901 return (ENOMEM); 902 *cookiep = ih; 903 ih->intr = intr; 904 ih->arg = arg; 905 ih->flags = flags & INTR_MPSAFE; 906 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 907 cbb_enable_func_intr(sc); 908 /* 909 * XXX need to turn on ISA interrupts, if we ever support them, but 910 * XXX for now that's all we need to do. 911 */ 912 return (0); 913 } 914 915 static int 916 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 917 void *cookie) 918 { 919 struct cbb_intrhand *ih; 920 struct cbb_softc *sc = device_get_softc(dev); 921 922 /* XXX Need to do different things for ISA interrupts. */ 923 ih = (struct cbb_intrhand *) cookie; 924 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 925 free(ih, M_DEVBUF); 926 return (0); 927 } 928 929 930 static void 931 cbb_driver_added(device_t brdev, driver_t *driver) 932 { 933 struct cbb_softc *sc = device_get_softc(brdev); 934 device_t *devlist; 935 device_t dev; 936 int tmp; 937 int numdevs; 938 int wake = 0; 939 940 DEVICE_IDENTIFY(driver, brdev); 941 device_get_children(brdev, &devlist, &numdevs); 942 for (tmp = 0; tmp < numdevs; tmp++) { 943 dev = devlist[tmp]; 944 if (device_get_state(dev) == DS_NOTPRESENT && 945 device_probe_and_attach(dev) == 0) 946 wake++; 947 } 948 free(devlist, M_TEMP); 949 950 if (wake > 0) { 951 mtx_lock(&sc->mtx); 952 cv_signal(&sc->cv); 953 mtx_unlock(&sc->mtx); 954 } 955 } 956 957 static void 958 cbb_child_detached(device_t brdev, device_t child) 959 { 960 struct cbb_softc *sc = device_get_softc(brdev); 961 962 if (child != sc->cbdev && child != sc->exca.pccarddev) 963 device_printf(brdev, "Unknown child detached: %s\n", 964 device_get_nameunit(child)); 965 } 966 967 /************************************************************************/ 968 /* Kthreads */ 969 /************************************************************************/ 970 971 static void 972 cbb_event_thread(void *arg) 973 { 974 struct cbb_softc *sc = arg; 975 uint32_t status; 976 int err; 977 int not_a_card = 0; 978 979 sc->flags |= CBB_KTHREAD_RUNNING; 980 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 981 /* 982 * We take out Giant here because we need it deep, 983 * down in the bowels of the vm system for mapping the 984 * memory we need to read the CIS. In addition, since 985 * we are adding/deleting devices from the dev tree, 986 * and that code isn't MP safe, we have to hold Giant. 987 */ 988 mtx_lock(&Giant); 989 status = cbb_get(sc, CBB_SOCKET_STATE); 990 DPRINTF(("Status is 0x%x\n", status)); 991 if (!CBB_CARD_PRESENT(status)) { 992 not_a_card = 0; /* We know card type */ 993 cbb_removal(sc); 994 } else if (status & CBB_STATE_NOT_A_CARD) { 995 /* 996 * Up to 20 times, try to rescan the card when we 997 * see NOT_A_CARD. 998 */ 999 if (not_a_card++ < 20) { 1000 DEVPRINTF((sc->dev, 1001 "Not a card bit set, rescanning\n")); 1002 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 1003 } else { 1004 device_printf(sc->dev, 1005 "Can't determine card type\n"); 1006 } 1007 } else { 1008 not_a_card = 0; /* We know card type */ 1009 cbb_insert(sc); 1010 } 1011 mtx_unlock(&Giant); 1012 1013 /* 1014 * Wait until it has been 1s since the last time we 1015 * get an interrupt. We handle the rest of the interrupt 1016 * at the top of the loop. Although we clear the bit in the 1017 * ISR, we signal sc->cv from the detach path after we've 1018 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 1019 * 1s sleep here. 1020 * 1021 * In our ISR, we turn off the card changed interrupt. Turn 1022 * them back on here before we wait for them to happen. We 1023 * turn them on/off so that we can tolerate a large latency 1024 * between the time we signal cbb_event_thread and it gets 1025 * a chance to run. 1026 */ 1027 mtx_lock(&sc->mtx); 1028 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1029 cv_wait(&sc->cv, &sc->mtx); 1030 err = 0; 1031 while (err != EWOULDBLOCK && 1032 (sc->flags & CBB_KTHREAD_DONE) == 0) 1033 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 1034 mtx_unlock(&sc->mtx); 1035 } 1036 sc->flags &= ~CBB_KTHREAD_RUNNING; 1037 kthread_exit(0); 1038 } 1039 1040 /************************************************************************/ 1041 /* Insert/removal */ 1042 /************************************************************************/ 1043 1044 static void 1045 cbb_insert(struct cbb_softc *sc) 1046 { 1047 uint32_t sockevent, sockstate; 1048 1049 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1050 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1051 1052 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1053 sockevent, sockstate)); 1054 1055 if (sockstate & CBB_STATE_R2_CARD) { 1056 if (sc->exca.pccarddev) 1057 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1058 exca_insert(&sc->exca); 1059 } else if (sockstate & CBB_STATE_CB_CARD) { 1060 if (sc->cbdev != NULL) { 1061 sc->flags &= ~CBB_16BIT_CARD; 1062 sc->flags |= CBB_CARD_OK; 1063 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1064 device_printf(sc->dev, 1065 "CardBus card activation failed\n"); 1066 } else { 1067 device_printf(sc->dev, 1068 "CardBus card inserted, but no cardbus bus.\n"); 1069 } 1070 } else { 1071 /* 1072 * We should power the card down, and try again a couple of 1073 * times if this happens. XXX 1074 */ 1075 device_printf(sc->dev, "Unsupported card type detected\n"); 1076 } 1077 } 1078 1079 static void 1080 cbb_removal(struct cbb_softc *sc) 1081 { 1082 if (sc->flags & CBB_16BIT_CARD) { 1083 exca_removal(&sc->exca); 1084 } else { 1085 if (sc->cbdev != NULL) 1086 CARD_DETACH_CARD(sc->cbdev); 1087 } 1088 cbb_destroy_res(sc); 1089 } 1090 1091 /************************************************************************/ 1092 /* Interrupt Handler */ 1093 /************************************************************************/ 1094 1095 static void 1096 cbb_intr(void *arg) 1097 { 1098 struct cbb_softc *sc = arg; 1099 uint32_t sockevent; 1100 struct cbb_intrhand *ih; 1101 1102 /* 1103 * This ISR needs work XXX 1104 */ 1105 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1106 if (sockevent != 0) { 1107 /* ack the interrupt */ 1108 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1109 1110 /* 1111 * If anything has happened to the socket, we assume that 1112 * the card is no longer OK, and we shouldn't call its 1113 * ISR. We set CARD_OK as soon as we've attached the 1114 * card. This helps in a noisy eject, which happens 1115 * all too often when users are ejecting their PC Cards. 1116 * 1117 * We use this method in preference to checking to see if 1118 * the card is still there because the check suffers from 1119 * a race condition in the bouncing case. Prior versions 1120 * of the pccard software used a similar trick and achieved 1121 * excellent results. 1122 */ 1123 if (sockevent & CBB_SOCKET_EVENT_CD) { 1124 mtx_lock(&sc->mtx); 1125 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1126 sc->flags &= ~CBB_CARD_OK; 1127 cbb_disable_func_intr(sc); 1128 cv_signal(&sc->cv); 1129 mtx_unlock(&sc->mtx); 1130 } 1131 } 1132 /* 1133 * Some chips also require us to read the old ExCA registe for 1134 * card status change when we route CSC vis PCI. This isn't supposed 1135 * to be required, but it clears the interrupt state on some chipsets. 1136 * Maybe there's a setting that would obviate its need. Maybe we 1137 * should test the status bits and deal with them, but so far we've 1138 * not found any machines that don't also give us the socket status 1139 * indication above. 1140 * 1141 * We have to call this unconditionally because some bridges deliver 1142 * the even independent of the CBB_SOCKET_EVENT_CD above. 1143 */ 1144 exca_getb(&sc->exca, EXCA_CSC); 1145 1146 /* 1147 * If the card is OK, call all the interrupt handlers. 1148 */ 1149 if (sc->flags & CBB_CARD_OK) { 1150 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1151 if ((ih->flags & INTR_MPSAFE) == 0) 1152 mtx_lock(&Giant); 1153 (*ih->intr)(ih->arg); 1154 if ((ih->flags & INTR_MPSAFE) == 0) 1155 mtx_unlock(&Giant); 1156 } 1157 } 1158 } 1159 1160 /************************************************************************/ 1161 /* Generic Power functions */ 1162 /************************************************************************/ 1163 1164 static int 1165 cbb_detect_voltage(device_t brdev) 1166 { 1167 struct cbb_softc *sc = device_get_softc(brdev); 1168 uint32_t psr; 1169 int vol = CARD_UKN_CARD; 1170 1171 psr = cbb_get(sc, CBB_SOCKET_STATE); 1172 1173 if (psr & CBB_STATE_5VCARD) 1174 vol |= CARD_5V_CARD; 1175 if (psr & CBB_STATE_3VCARD) 1176 vol |= CARD_3V_CARD; 1177 if (psr & CBB_STATE_XVCARD) 1178 vol |= CARD_XV_CARD; 1179 if (psr & CBB_STATE_YVCARD) 1180 vol |= CARD_YV_CARD; 1181 1182 return (vol); 1183 } 1184 1185 static uint8_t 1186 cbb_o2micro_power_hack(struct cbb_softc *sc) 1187 { 1188 uint8_t reg; 1189 1190 /* 1191 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1192 * unexpected PCI INT# may be generated during PC-Card 1193 * initialization even with the IRQ Routing Bit Set with some 1194 * PC-Cards. 1195 * 1196 * This is a two part issue. The first part is that some of 1197 * our older controllers have an issue in which the slot's PCI 1198 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1199 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1200 * is selected (ExCA register 03h bits 3:0, of the slot, are 1201 * cleared) we will generate INT# if IREQ# is asserted. The 1202 * second part is because some PC-Cards prematurally assert 1203 * IREQ# before the ExCA registers are fully programmed. This 1204 * in turn asserts INT# because ExCA register 03h bits 3:0 1205 * (ISA IRQ Select) are not yet programmed. 1206 * 1207 * The fix for this issue, which will work for any controller 1208 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1209 * (select IRQ1), of the slot, before turning on slot power. 1210 * Selecting IRQ1 will result in INT# NOT being asserted 1211 * (because IRQ1 is selected), and IRQ1 won't be asserted 1212 * because our controllers don't generate IRQ1. 1213 */ 1214 reg = exca_getb(&sc->exca, EXCA_INTR); 1215 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1216 return (reg); 1217 } 1218 1219 /* 1220 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1221 * we don't have an interrupt storm on power on. This has the efect of 1222 * disabling card status change interrupts for the duration of poweron. 1223 */ 1224 static void 1225 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1226 { 1227 exca_putb(&sc->exca, EXCA_INTR, reg); 1228 } 1229 1230 static int 1231 cbb_power(device_t brdev, int volts) 1232 { 1233 uint32_t status, sock_ctrl; 1234 struct cbb_softc *sc = device_get_softc(brdev); 1235 int timeout; 1236 int retval = 0; 1237 uint32_t sockevent; 1238 uint8_t reg = 0; 1239 1240 status = cbb_get(sc, CBB_SOCKET_STATE); 1241 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1242 1243 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1244 switch (volts & CARD_VCCMASK) { 1245 case 5: 1246 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1247 break; 1248 case 3: 1249 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1250 break; 1251 case XV: 1252 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1253 break; 1254 case YV: 1255 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1256 break; 1257 case 0: 1258 break; 1259 default: 1260 return (0); /* power NEVER changed */ 1261 } 1262 1263 /* VPP == VCC */ 1264 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1265 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1266 1267 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1268 return (1); /* no change necessary */ 1269 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1270 if (volts != 0 && sc->chipset == CB_O2MICRO) 1271 reg = cbb_o2micro_power_hack(sc); 1272 1273 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1274 status = cbb_get(sc, CBB_SOCKET_STATE); 1275 1276 /* 1277 * XXX This busy wait is bogus. We should wait for a power 1278 * interrupt and then whine if the status is bad. If we're 1279 * worried about the card not coming up, then we should also 1280 * schedule a timeout which we can cancel in the power interrupt. 1281 */ 1282 timeout = 20; 1283 do { 1284 DELAY(20*1000); 1285 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1286 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1287 /* reset event status */ 1288 /* XXX should only reset EVENT_POWER */ 1289 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1290 if (timeout < 0) { 1291 printf ("VCC supply failed.\n"); 1292 goto done; 1293 } 1294 1295 /* XXX 1296 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1297 * is 20 ms, some PC-Card bridge requires longer duration. 1298 * XXX Note: We should check the stutus AFTER the delay to give time 1299 * for things to stabilize. 1300 */ 1301 DELAY(400*1000); 1302 1303 if (status & CBB_STATE_BAD_VCC_REQ) { 1304 device_printf(sc->dev, 1305 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1306 sock_ctrl ,status); 1307 printf("cbb_power: %dV\n", volts); 1308 goto done; 1309 } 1310 retval = 1; 1311 done:; 1312 if (volts != 0 && sc->chipset == CB_O2MICRO) 1313 cbb_o2micro_power_hack2(sc, reg); 1314 return (retval); 1315 } 1316 1317 /* 1318 * detect the voltage for the card, and set it. Since the power 1319 * used is the square of the voltage, lower voltages is a big win 1320 * and what Windows does (and what Microsoft prefers). The MS paper 1321 * also talks about preferring the CIS entry as well. In addition, 1322 * we power up with OE disabled. We'll set it later in the power 1323 * up sequence. 1324 */ 1325 static int 1326 cbb_do_power(device_t brdev) 1327 { 1328 struct cbb_softc *sc = device_get_softc(brdev); 1329 int voltage; 1330 1331 /* Don't enable OE */ 1332 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1333 1334 /* Prefer lowest voltage supported */ 1335 voltage = cbb_detect_voltage(brdev); 1336 cbb_power(brdev, CARD_OFF); 1337 if (voltage & CARD_YV_CARD) 1338 cbb_power(brdev, CARD_VCC(YV)); 1339 else if (voltage & CARD_XV_CARD) 1340 cbb_power(brdev, CARD_VCC(XV)); 1341 else if (voltage & CARD_3V_CARD) 1342 cbb_power(brdev, CARD_VCC(3)); 1343 else if (voltage & CARD_5V_CARD) 1344 cbb_power(brdev, CARD_VCC(5)); 1345 else { 1346 device_printf(brdev, "Unknown card voltage\n"); 1347 return (ENXIO); 1348 } 1349 return (0); 1350 } 1351 1352 /************************************************************************/ 1353 /* CardBus power functions */ 1354 /************************************************************************/ 1355 1356 static void 1357 cbb_cardbus_reset(device_t brdev) 1358 { 1359 struct cbb_softc *sc = device_get_softc(brdev); 1360 int delay_us; 1361 1362 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1363 1364 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1365 1366 DELAY(delay_us); 1367 1368 /* If a card exists, unreset it! */ 1369 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 1370 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1371 &~CBBM_BRIDGECTRL_RESET, 2); 1372 DELAY(delay_us); 1373 } 1374 } 1375 1376 static int 1377 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1378 { 1379 struct cbb_softc *sc = device_get_softc(brdev); 1380 int err; 1381 1382 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 1383 return (ENODEV); 1384 1385 err = cbb_do_power(brdev); 1386 if (err) 1387 return (err); 1388 cbb_cardbus_reset(brdev); 1389 return (0); 1390 } 1391 1392 static void 1393 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1394 { 1395 cbb_power(brdev, CARD_OFF); 1396 cbb_cardbus_reset(brdev); 1397 } 1398 1399 /************************************************************************/ 1400 /* CardBus Resource */ 1401 /************************************************************************/ 1402 1403 static int 1404 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1405 { 1406 int basereg; 1407 int limitreg; 1408 1409 if ((win < 0) || (win > 1)) { 1410 DEVPRINTF((brdev, 1411 "cbb_cardbus_io_open: window out of range %d\n", win)); 1412 return (EINVAL); 1413 } 1414 1415 basereg = win * 8 + CBBR_IOBASE0; 1416 limitreg = win * 8 + CBBR_IOLIMIT0; 1417 1418 pci_write_config(brdev, basereg, start, 4); 1419 pci_write_config(brdev, limitreg, end, 4); 1420 return (0); 1421 } 1422 1423 static int 1424 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1425 { 1426 int basereg; 1427 int limitreg; 1428 1429 if ((win < 0) || (win > 1)) { 1430 DEVPRINTF((brdev, 1431 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1432 return (EINVAL); 1433 } 1434 1435 basereg = win*8 + CBBR_MEMBASE0; 1436 limitreg = win*8 + CBBR_MEMLIMIT0; 1437 1438 pci_write_config(brdev, basereg, start, 4); 1439 pci_write_config(brdev, limitreg, end, 4); 1440 return (0); 1441 } 1442 1443 /* 1444 * XXX The following function belongs in the pci bus layer. 1445 */ 1446 static void 1447 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1448 { 1449 uint32_t starts[2]; 1450 uint32_t ends[2]; 1451 struct cbb_reslist *rle; 1452 int align; 1453 int prefetchable[2]; 1454 uint32_t reg; 1455 1456 starts[0] = starts[1] = 0xffffffff; 1457 ends[0] = ends[1] = 0; 1458 1459 if (type == SYS_RES_MEMORY) 1460 align = CBB_MEMALIGN; 1461 else if (type == SYS_RES_IOPORT) 1462 align = CBB_IOALIGN; 1463 else 1464 align = 1; 1465 1466 /* 1467 * This looks somewhat bogus, and doesn't seem to really respect 1468 * alignment. The alignment stuff is happening too late (it 1469 * should happen at allocation time, not activation time) and 1470 * this code looks generally to be too complex for the purpose 1471 * it surves. 1472 */ 1473 SLIST_FOREACH(rle, &sc->rl, link) { 1474 if (rle->type != type) 1475 ; 1476 else if (rle->res == NULL) { 1477 device_printf(sc->dev, "WARNING: Resource not reserved? " 1478 "(type=%d, addr=%lx)\n", 1479 rle->type, rman_get_start(rle->res)); 1480 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1481 /* XXX */ 1482 } else if (starts[0] == 0xffffffff) { 1483 starts[0] = rman_get_start(rle->res); 1484 ends[0] = rman_get_end(rle->res); 1485 prefetchable[0] = 1486 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1487 } else if (rman_get_end(rle->res) > ends[0] && 1488 rman_get_start(rle->res) - ends[0] < 1489 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1490 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1491 ends[0] = rman_get_end(rle->res); 1492 } else if (rman_get_start(rle->res) < starts[0] && 1493 starts[0] - rman_get_end(rle->res) < 1494 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1495 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1496 starts[0] = rman_get_start(rle->res); 1497 } else if (starts[1] == 0xffffffff) { 1498 starts[1] = rman_get_start(rle->res); 1499 ends[1] = rman_get_end(rle->res); 1500 prefetchable[1] = 1501 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1502 } else if (rman_get_end(rle->res) > ends[1] && 1503 rman_get_start(rle->res) - ends[1] < 1504 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1505 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1506 ends[1] = rman_get_end(rle->res); 1507 } else if (rman_get_start(rle->res) < starts[1] && 1508 starts[1] - rman_get_end(rle->res) < 1509 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1510 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1511 starts[1] = rman_get_start(rle->res); 1512 } else { 1513 uint32_t diffs[2]; 1514 int win; 1515 1516 diffs[0] = diffs[1] = 0xffffffff; 1517 if (rman_get_start(rle->res) > ends[0]) 1518 diffs[0] = rman_get_start(rle->res) - ends[0]; 1519 else if (rman_get_end(rle->res) < starts[0]) 1520 diffs[0] = starts[0] - rman_get_end(rle->res); 1521 if (rman_get_start(rle->res) > ends[1]) 1522 diffs[1] = rman_get_start(rle->res) - ends[1]; 1523 else if (rman_get_end(rle->res) < starts[1]) 1524 diffs[1] = starts[1] - rman_get_end(rle->res); 1525 1526 win = (diffs[0] <= diffs[1])?0:1; 1527 if (rman_get_start(rle->res) > ends[win]) 1528 ends[win] = rman_get_end(rle->res); 1529 else if (rman_get_end(rle->res) < starts[win]) 1530 starts[win] = rman_get_start(rle->res); 1531 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1532 prefetchable[win] = 0; 1533 } 1534 1535 if (starts[0] != 0xffffffff) 1536 starts[0] -= starts[0] % align; 1537 if (starts[1] != 0xffffffff) 1538 starts[1] -= starts[1] % align; 1539 if (ends[0] % align != 0) 1540 ends[0] += align - ends[0] % align - 1; 1541 if (ends[1] % align != 0) 1542 ends[1] += align - ends[1] % align - 1; 1543 } 1544 1545 if (type == SYS_RES_MEMORY) { 1546 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1547 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1548 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1549 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1550 CBBM_BRIDGECTRL_PREFETCH_1); 1551 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1552 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1553 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1554 } else if (type == SYS_RES_IOPORT) { 1555 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1556 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1557 } 1558 } 1559 1560 static int 1561 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1562 int rid, struct resource *res) 1563 { 1564 int ret; 1565 1566 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1567 type, rid, res); 1568 if (ret != 0) 1569 return (ret); 1570 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1571 return (0); 1572 } 1573 1574 static int 1575 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1576 int rid, struct resource *res) 1577 { 1578 int ret; 1579 1580 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1581 type, rid, res); 1582 if (ret != 0) 1583 return (ret); 1584 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1585 return (0); 1586 } 1587 1588 static struct resource * 1589 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1590 int *rid, u_long start, u_long end, u_long count, u_int flags) 1591 { 1592 struct cbb_softc *sc = device_get_softc(brdev); 1593 int tmp; 1594 struct resource *res; 1595 u_long align; 1596 1597 switch (type) { 1598 case SYS_RES_IRQ: 1599 tmp = rman_get_start(sc->irq_res); 1600 if (start > tmp || end < tmp || count != 1) { 1601 device_printf(child, "requested interrupt %ld-%ld," 1602 "count = %ld not supported by cbb\n", 1603 start, end, count); 1604 return (NULL); 1605 } 1606 start = end = tmp; 1607 flags |= RF_SHAREABLE; 1608 break; 1609 case SYS_RES_IOPORT: 1610 if (start <= cbb_start_32_io) 1611 start = cbb_start_32_io; 1612 if (end < start) 1613 end = start; 1614 break; 1615 case SYS_RES_MEMORY: 1616 if (start <= cbb_start_mem) 1617 start = cbb_start_mem; 1618 if (end < start) 1619 end = start; 1620 if (count < CBB_MEMALIGN) 1621 align = CBB_MEMALIGN; 1622 else 1623 align = count; 1624 if (align > (1 << RF_ALIGNMENT(flags))) 1625 flags = (flags & ~RF_ALIGNMENT_MASK) | 1626 rman_make_alignment_flags(align); 1627 break; 1628 } 1629 1630 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1631 start, end, count, flags & ~RF_ACTIVE); 1632 if (res == NULL) { 1633 printf("cbb alloc res fail\n"); 1634 return (NULL); 1635 } 1636 cbb_insert_res(sc, res, type, *rid); 1637 if (flags & RF_ACTIVE) 1638 if (bus_activate_resource(child, type, *rid, res) != 0) { 1639 bus_release_resource(child, type, *rid, res); 1640 return (NULL); 1641 } 1642 1643 return (res); 1644 } 1645 1646 static int 1647 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1648 int rid, struct resource *res) 1649 { 1650 struct cbb_softc *sc = device_get_softc(brdev); 1651 int error; 1652 1653 if (rman_get_flags(res) & RF_ACTIVE) { 1654 error = bus_deactivate_resource(child, type, rid, res); 1655 if (error != 0) 1656 return (error); 1657 } 1658 cbb_remove_res(sc, res); 1659 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1660 type, rid, res)); 1661 } 1662 1663 /************************************************************************/ 1664 /* PC Card Power Functions */ 1665 /************************************************************************/ 1666 1667 static int 1668 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1669 { 1670 struct cbb_softc *sc = device_get_softc(brdev); 1671 int err; 1672 1673 DPRINTF(("cbb_pcic_socket_enable:\n")); 1674 1675 /* power down/up the socket to reset */ 1676 err = cbb_do_power(brdev); 1677 if (err) 1678 return (err); 1679 exca_reset(&sc->exca, child); 1680 1681 return (0); 1682 } 1683 1684 static void 1685 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1686 { 1687 struct cbb_softc *sc = device_get_softc(brdev); 1688 1689 DPRINTF(("cbb_pcic_socket_disable\n")); 1690 1691 /* reset signal asserting... */ 1692 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1693 DELAY(2*1000); 1694 1695 /* power down the socket */ 1696 cbb_power(brdev, CARD_OFF); 1697 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1698 1699 /* wait 300ms until power fails (Tpf). */ 1700 DELAY(300 * 1000); 1701 } 1702 1703 /************************************************************************/ 1704 /* POWER methods */ 1705 /************************************************************************/ 1706 1707 static int 1708 cbb_power_enable_socket(device_t brdev, device_t child) 1709 { 1710 struct cbb_softc *sc = device_get_softc(brdev); 1711 1712 if (sc->flags & CBB_16BIT_CARD) 1713 return (cbb_pcic_power_enable_socket(brdev, child)); 1714 else 1715 return (cbb_cardbus_power_enable_socket(brdev, child)); 1716 } 1717 1718 static void 1719 cbb_power_disable_socket(device_t brdev, device_t child) 1720 { 1721 struct cbb_softc *sc = device_get_softc(brdev); 1722 if (sc->flags & CBB_16BIT_CARD) 1723 cbb_pcic_power_disable_socket(brdev, child); 1724 else 1725 cbb_cardbus_power_disable_socket(brdev, child); 1726 } 1727 1728 static int 1729 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1730 struct resource *res) 1731 { 1732 struct cbb_softc *sc = device_get_softc(brdev); 1733 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1734 } 1735 1736 static int 1737 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1738 int rid, struct resource *res) 1739 { 1740 struct cbb_softc *sc = device_get_softc(brdev); 1741 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1742 } 1743 1744 static struct resource * 1745 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1746 u_long start, u_long end, u_long count, u_int flags) 1747 { 1748 struct resource *res = NULL; 1749 struct cbb_softc *sc = device_get_softc(brdev); 1750 int align; 1751 int tmp; 1752 1753 switch (type) { 1754 case SYS_RES_MEMORY: 1755 if (start < cbb_start_mem) 1756 start = cbb_start_mem; 1757 if (end < start) 1758 end = start; 1759 if (count < CBB_MEMALIGN) 1760 align = CBB_MEMALIGN; 1761 else 1762 align = count; 1763 if (align > (1 << RF_ALIGNMENT(flags))) 1764 flags = (flags & ~RF_ALIGNMENT_MASK) | 1765 rman_make_alignment_flags(align); 1766 break; 1767 case SYS_RES_IOPORT: 1768 if (start < cbb_start_16_io) 1769 start = cbb_start_16_io; 1770 if (end < start) 1771 end = start; 1772 break; 1773 case SYS_RES_IRQ: 1774 tmp = rman_get_start(sc->irq_res); 1775 if (start > tmp || end < tmp || count != 1) { 1776 device_printf(child, "requested interrupt %ld-%ld," 1777 "count = %ld not supported by cbb\n", 1778 start, end, count); 1779 return (NULL); 1780 } 1781 flags |= RF_SHAREABLE; 1782 start = end = rman_get_start(sc->irq_res); 1783 break; 1784 } 1785 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1786 start, end, count, flags & ~RF_ACTIVE); 1787 if (res == NULL) 1788 return (NULL); 1789 cbb_insert_res(sc, res, type, *rid); 1790 if (flags & RF_ACTIVE) { 1791 if (bus_activate_resource(child, type, *rid, res) != 0) { 1792 bus_release_resource(child, type, *rid, res); 1793 return (NULL); 1794 } 1795 } 1796 1797 return (res); 1798 } 1799 1800 static int 1801 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1802 int rid, struct resource *res) 1803 { 1804 struct cbb_softc *sc = device_get_softc(brdev); 1805 int error; 1806 1807 if (rman_get_flags(res) & RF_ACTIVE) { 1808 error = bus_deactivate_resource(child, type, rid, res); 1809 if (error != 0) 1810 return (error); 1811 } 1812 cbb_remove_res(sc, res); 1813 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1814 type, rid, res)); 1815 } 1816 1817 /************************************************************************/ 1818 /* PC Card methods */ 1819 /************************************************************************/ 1820 1821 static int 1822 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1823 uint32_t flags) 1824 { 1825 struct cbb_softc *sc = device_get_softc(brdev); 1826 struct resource *res; 1827 1828 if (type != SYS_RES_MEMORY) 1829 return (EINVAL); 1830 res = cbb_find_res(sc, type, rid); 1831 if (res == NULL) { 1832 device_printf(brdev, 1833 "set_res_flags: specified rid not found\n"); 1834 return (ENOENT); 1835 } 1836 return (exca_mem_set_flags(&sc->exca, res, flags)); 1837 } 1838 1839 static int 1840 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1841 uint32_t cardaddr, uint32_t *deltap) 1842 { 1843 struct cbb_softc *sc = device_get_softc(brdev); 1844 struct resource *res; 1845 1846 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1847 if (res == NULL) { 1848 device_printf(brdev, 1849 "set_memory_offset: specified rid not found\n"); 1850 return (ENOENT); 1851 } 1852 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1853 } 1854 1855 /************************************************************************/ 1856 /* BUS Methods */ 1857 /************************************************************************/ 1858 1859 1860 static int 1861 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1862 struct resource *r) 1863 { 1864 struct cbb_softc *sc = device_get_softc(brdev); 1865 1866 if (sc->flags & CBB_16BIT_CARD) 1867 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1868 else 1869 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1870 r)); 1871 } 1872 1873 static int 1874 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1875 int rid, struct resource *r) 1876 { 1877 struct cbb_softc *sc = device_get_softc(brdev); 1878 1879 if (sc->flags & CBB_16BIT_CARD) 1880 return (cbb_pcic_deactivate_resource(brdev, child, type, 1881 rid, r)); 1882 else 1883 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1884 rid, r)); 1885 } 1886 1887 static struct resource * 1888 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1889 u_long start, u_long end, u_long count, u_int flags) 1890 { 1891 struct cbb_softc *sc = device_get_softc(brdev); 1892 1893 if (sc->flags & CBB_16BIT_CARD) 1894 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1895 start, end, count, flags)); 1896 else 1897 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1898 start, end, count, flags)); 1899 } 1900 1901 static int 1902 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1903 struct resource *r) 1904 { 1905 struct cbb_softc *sc = device_get_softc(brdev); 1906 1907 if (sc->flags & CBB_16BIT_CARD) 1908 return (cbb_pcic_release_resource(brdev, child, type, 1909 rid, r)); 1910 else 1911 return (cbb_cardbus_release_resource(brdev, child, type, 1912 rid, r)); 1913 } 1914 1915 static int 1916 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1917 { 1918 struct cbb_softc *sc = device_get_softc(brdev); 1919 1920 switch (which) { 1921 case PCIB_IVAR_BUS: 1922 *result = sc->secbus; 1923 return (0); 1924 } 1925 return (ENOENT); 1926 } 1927 1928 static int 1929 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1930 { 1931 struct cbb_softc *sc = device_get_softc(brdev); 1932 1933 switch (which) { 1934 case PCIB_IVAR_BUS: 1935 sc->secbus = value; 1936 break; 1937 } 1938 return (ENOENT); 1939 } 1940 1941 /************************************************************************/ 1942 /* PCI compat methods */ 1943 /************************************************************************/ 1944 1945 static int 1946 cbb_maxslots(device_t brdev) 1947 { 1948 return (0); 1949 } 1950 1951 static uint32_t 1952 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1953 { 1954 /* 1955 * Pass through to the next ppb up the chain (i.e. our grandparent). 1956 */ 1957 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1958 b, s, f, reg, width)); 1959 } 1960 1961 static void 1962 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1963 int width) 1964 { 1965 /* 1966 * Pass through to the next ppb up the chain (i.e. our grandparent). 1967 */ 1968 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1969 b, s, f, reg, val, width); 1970 } 1971 1972 static int 1973 cbb_suspend(device_t self) 1974 { 1975 int error = 0; 1976 struct cbb_softc *sc = device_get_softc(self); 1977 1978 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1979 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1980 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1981 error = bus_generic_suspend(self); 1982 return (error); 1983 } 1984 1985 static int 1986 cbb_resume(device_t self) 1987 { 1988 int error = 0; 1989 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1990 uint32_t tmp; 1991 1992 /* 1993 * Some BIOSes will not save the BARs for the pci chips, so we 1994 * must do it ourselves. If the BAR is reset to 0 for an I/O 1995 * device, it will read back as 0x1, so no explicit test for 1996 * memory devices are needed. 1997 * 1998 * Note: The PCI bus code should do this automatically for us on 1999 * suspend/resume, but until it does, we have to cope. 2000 */ 2001 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 2002 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 2003 rman_get_start(sc->base_res))); 2004 2005 cbb_chipinit(sc); 2006 2007 /* reset interrupt -- Do we really need to do this? */ 2008 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 2009 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 2010 2011 /* re-establish the interrupt. */ 2012 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 2013 cbb_intr, sc, &sc->intrhand)) { 2014 device_printf(self, "couldn't re-establish interrupt"); 2015 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 2016 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 2017 sc->base_res); 2018 sc->irq_res = NULL; 2019 sc->base_res = NULL; 2020 return (ENOMEM); 2021 } 2022 2023 /* CSC Interrupt: Card detect interrupt on */ 2024 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 2025 2026 /* Signal the thread to wakeup. */ 2027 mtx_lock(&sc->mtx); 2028 cv_signal(&sc->cv); 2029 mtx_unlock(&sc->mtx); 2030 2031 error = bus_generic_resume(self); 2032 2033 return (error); 2034 } 2035 2036 static int 2037 cbb_child_present(device_t self) 2038 { 2039 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 2040 uint32_t sockstate; 2041 2042 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 2043 return (CBB_CARD_PRESENT(sockstate) && 2044 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 2045 } 2046 2047 static device_method_t cbb_methods[] = { 2048 /* Device interface */ 2049 DEVMETHOD(device_probe, cbb_probe), 2050 DEVMETHOD(device_attach, cbb_attach), 2051 DEVMETHOD(device_detach, cbb_detach), 2052 DEVMETHOD(device_shutdown, cbb_shutdown), 2053 DEVMETHOD(device_suspend, cbb_suspend), 2054 DEVMETHOD(device_resume, cbb_resume), 2055 2056 /* bus methods */ 2057 DEVMETHOD(bus_print_child, bus_generic_print_child), 2058 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 2059 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 2060 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 2061 DEVMETHOD(bus_release_resource, cbb_release_resource), 2062 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 2063 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 2064 DEVMETHOD(bus_driver_added, cbb_driver_added), 2065 DEVMETHOD(bus_child_detached, cbb_child_detached), 2066 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 2067 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 2068 DEVMETHOD(bus_child_present, cbb_child_present), 2069 2070 /* 16-bit card interface */ 2071 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 2072 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 2073 2074 /* power interface */ 2075 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 2076 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 2077 2078 /* pcib compatibility interface */ 2079 DEVMETHOD(pcib_maxslots, cbb_maxslots), 2080 DEVMETHOD(pcib_read_config, cbb_read_config), 2081 DEVMETHOD(pcib_write_config, cbb_write_config), 2082 {0,0} 2083 }; 2084 2085 static driver_t cbb_driver = { 2086 "cbb", 2087 cbb_methods, 2088 sizeof(struct cbb_softc) 2089 }; 2090 2091 static devclass_t cbb_devclass; 2092 2093 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2094 MODULE_VERSION(cbb, 1); 2095 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2096