1 /* 2 * Copyright (c) 2002 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for PCI to CardBus Bridge chips 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 93 #include <pci/pcireg.h> 94 #include <pci/pcivar.h> 95 #include <machine/clock.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 #define CBB_START_MEM 0x88000000 120 #define CBB_START_32_IO 0x1000 121 #define CBB_START_16_IO 0x100 122 123 struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 155 /* Ricoh chips */ 156 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 157 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 158 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 159 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 160 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 161 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 162 163 /* Toshiba products */ 164 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 165 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 166 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 167 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 168 169 /* Cirrus Logic */ 170 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 171 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 172 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 173 174 /* 02Micro */ 175 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 176 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 177 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 178 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 179 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 180 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 181 182 /* sentinel */ 183 {0 /* null id */, "unknown", CB_UNKNOWN}, 184 }; 185 186 /* sysctl vars */ 187 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 188 189 /* There's no way to say TUNEABLE_LONG to get the right types */ 190 u_long cbb_start_mem = CBB_START_MEM; 191 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 192 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 193 &cbb_start_mem, CBB_START_MEM, 194 "Starting address for memory allocations"); 195 196 u_long cbb_start_16_io = CBB_START_16_IO; 197 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 198 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 199 &cbb_start_16_io, CBB_START_16_IO, 200 "Starting ioport for 16-bit cards"); 201 202 u_long cbb_start_32_io = CBB_START_32_IO; 203 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 205 &cbb_start_32_io, CBB_START_32_IO, 206 "Starting ioport for 32-bit cards"); 207 208 int cbb_debug = 0; 209 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 211 "Verbose cardbus bridge debugging"); 212 213 static int cbb_chipset(uint32_t pci_id, const char **namep); 214 static int cbb_probe(device_t brdev); 215 static void cbb_chipinit(struct cbb_softc *sc); 216 static int cbb_attach(device_t brdev); 217 static int cbb_detach(device_t brdev); 218 static int cbb_shutdown(device_t brdev); 219 static void cbb_driver_added(device_t brdev, driver_t *driver); 220 static void cbb_child_detached(device_t brdev, device_t child); 221 static void cbb_event_thread(void *arg); 222 static void cbb_insert(struct cbb_softc *sc); 223 static void cbb_removal(struct cbb_softc *sc); 224 static void cbb_intr(void *arg); 225 static int cbb_detect_voltage(device_t brdev); 226 static int cbb_power(device_t brdev, int volts); 227 static void cbb_cardbus_reset(device_t brdev); 228 static int cbb_cardbus_power_enable_socket(device_t brdev, 229 device_t child); 230 static void cbb_cardbus_power_disable_socket(device_t brdev, 231 device_t child); 232 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 233 uint32_t end); 234 static int cbb_cardbus_mem_open(device_t brdev, int win, 235 uint32_t start, uint32_t end); 236 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 237 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 238 int type, int rid, struct resource *res); 239 static int cbb_cardbus_deactivate_resource(device_t brdev, 240 device_t child, int type, int rid, struct resource *res); 241 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 242 device_t child, int type, int *rid, u_long start, 243 u_long end, u_long count, uint flags); 244 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 245 int type, int rid, struct resource *res); 246 static int cbb_power_enable_socket(device_t brdev, device_t child); 247 static void cbb_power_disable_socket(device_t brdev, device_t child); 248 static int cbb_activate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *r); 250 static int cbb_deactivate_resource(device_t brdev, device_t child, 251 int type, int rid, struct resource *r); 252 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 253 int type, int *rid, u_long start, u_long end, u_long count, 254 uint flags); 255 static int cbb_release_resource(device_t brdev, device_t child, 256 int type, int rid, struct resource *r); 257 static int cbb_read_ivar(device_t brdev, device_t child, int which, 258 uintptr_t *result); 259 static int cbb_write_ivar(device_t brdev, device_t child, int which, 260 uintptr_t value); 261 static int cbb_maxslots(device_t brdev); 262 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 263 int reg, int width); 264 static void cbb_write_config(device_t brdev, int b, int s, int f, 265 int reg, uint32_t val, int width); 266 267 /* 268 */ 269 static __inline void 270 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 271 { 272 bus_space_write_4(sc->bst, sc->bsh, reg, val); 273 } 274 275 static __inline uint32_t 276 cbb_get(struct cbb_softc *sc, uint32_t reg) 277 { 278 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 279 } 280 281 static __inline void 282 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 283 { 284 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 285 } 286 287 static __inline void 288 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 289 { 290 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 291 } 292 293 static void 294 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 295 { 296 struct cbb_reslist *rle; 297 298 SLIST_FOREACH(rle, &sc->rl, link) { 299 if (rle->res == res) { 300 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 301 free(rle, M_DEVBUF); 302 return; 303 } 304 } 305 } 306 307 static struct resource * 308 cbb_find_res(struct cbb_softc *sc, int type, int rid) 309 { 310 struct cbb_reslist *rle; 311 312 SLIST_FOREACH(rle, &sc->rl, link) 313 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 314 return (rle->res); 315 return (NULL); 316 } 317 318 static void 319 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 320 int rid) 321 { 322 struct cbb_reslist *rle; 323 324 /* 325 * Need to record allocated resource so we can iterate through 326 * it later. 327 */ 328 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 329 if (!res) 330 panic("cbb_cardbus_alloc_resource: can't record entry!"); 331 rle->res = res; 332 rle->type = type; 333 rle->rid = rid; 334 SLIST_INSERT_HEAD(&sc->rl, rle, link); 335 } 336 337 static void 338 cbb_destroy_res(struct cbb_softc *sc) 339 { 340 struct cbb_reslist *rle; 341 342 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 343 device_printf(sc->dev, "Danger Will Robinson: Resource " 344 "left allocated! This is a bug... " 345 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 346 rman_get_start(rle->res)); 347 SLIST_REMOVE_HEAD(&sc->rl, link); 348 free(rle, M_DEVBUF); 349 } 350 } 351 352 /************************************************************************/ 353 /* Probe/Attach */ 354 /************************************************************************/ 355 356 static int 357 cbb_chipset(uint32_t pci_id, const char **namep) 358 { 359 struct yenta_chipinfo *ycp; 360 361 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 362 continue; 363 if (namep != NULL) 364 *namep = ycp->yc_name; 365 return (ycp->yc_chiptype); 366 } 367 368 static int 369 cbb_probe(device_t brdev) 370 { 371 const char *name; 372 uint32_t progif; 373 uint32_t subclass; 374 375 /* 376 * Do we know that we support the chipset? If so, then we 377 * accept the device. 378 */ 379 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 380 device_set_desc(brdev, name); 381 return (0); 382 } 383 384 /* 385 * We do support generic CardBus bridges. All that we've seen 386 * to date have progif 0 (the Yenta spec, and successors mandate 387 * this). We do not support PCI PCMCIA bridges (with one exception) 388 * with this driver since they generally are I/O mapped. Those 389 * are supported by the pcic driver. This should help us be more 390 * future proof. 391 */ 392 subclass = pci_get_subclass(brdev); 393 progif = pci_get_progif(brdev); 394 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 395 device_set_desc(brdev, "PCI-CardBus Bridge"); 396 return (0); 397 } 398 return (ENXIO); 399 } 400 401 402 static void 403 cbb_chipinit(struct cbb_softc *sc) 404 { 405 uint32_t mux, sysctrl, reg; 406 407 /* Set CardBus latency timer */ 408 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 409 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 410 411 /* Set PCI latency timer */ 412 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 413 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 414 415 /* Enable memory access */ 416 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 417 | PCIM_CMD_MEMEN 418 | PCIM_CMD_PORTEN 419 | PCIM_CMD_BUSMASTEREN, 2); 420 421 /* disable Legacy IO */ 422 switch (sc->chipset) { 423 case CB_RF5C46X: 424 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 425 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 426 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 427 break; 428 default: 429 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 430 break; 431 } 432 433 /* Use PCI interrupt for interrupt routing */ 434 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 435 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 436 CBBM_BRIDGECTRL_INTR_IREQ_EN), 437 | CBBM_BRIDGECTRL_WRITE_POST_EN, 438 2); 439 440 /* 441 * XXX this should be a function table, ala OLDCARD. This means 442 * that we could more easily support ISA interrupts for pccard 443 * cards if we had to. 444 */ 445 switch (sc->chipset) { 446 case CB_TI113X: 447 /* 448 * The TI 1031, TI 1130 and TI 1131 all require another bit 449 * be set to enable PCI routing of interrupts, and then 450 * a bit for each of the CSC and Function interrupts we 451 * want routed. 452 */ 453 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 454 | CBBM_CBCTRL_113X_PCI_INTR | 455 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 456 1); 457 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 458 & ~(CBBM_DEVCTRL_INT_SERIAL | 459 CBBM_DEVCTRL_INT_PCI), 1); 460 break; 461 case CB_TI12XX: 462 /* 463 * Some TI 12xx (and [14][45]xx) based pci cards 464 * sometimes have issues with the MFUNC register not 465 * being initialized due to a bad EEPROM on board. 466 * Laptops that this matters on have this register 467 * properly initialized. 468 * 469 * The TI125X parts have a different register. 470 */ 471 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 472 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 473 if (mux == 0) { 474 mux = (mux & ~CBBM_MFUNC_PIN0) | 475 CBBM_MFUNC_PIN0_INTA; 476 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 477 mux = (mux & ~CBBM_MFUNC_PIN1) | 478 CBBM_MFUNC_PIN1_INTB; 479 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 480 } 481 /*FALLTHROUGH*/ 482 case CB_TI125X: 483 /* 484 * Disable zoom video. Some machines initialize this 485 * improperly and exerpience has shown that this helps 486 * on some machines. 487 */ 488 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 489 break; 490 case CB_O2MICRO: 491 /* 492 * Issue #1: INT# generated at the same time as 493 * selected ISA IRQ. When IREQ# or STSCHG# is active, 494 * in addition to the ISA IRQ being generated, INT# 495 * will also be generated at the same time. 496 * 497 * Some of our older controllers have an issue in 498 * which the slot's PCI INT# will be asserted whenever 499 * IREQ# or STSCGH# is asserted even if ExCA registers 500 * 03h or 05h have an ISA IRQ selected. 501 * 502 * The fix for this issue, which will work for any 503 * controller (old or new), is to set ExCA registers 504 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 505 * These bits are undocumented. By setting this 506 * register (of each slot) to '1010xxxxb' a routing of 507 * IREQ# to INTC# and STSCHG# to INTC# is selected. 508 * Since INTC# isn't connected there will be no 509 * unexpected PCI INT when IREQ# or STSCHG# is active. 510 * However, INTA# (slot 0) or INTB# (slot 1) will 511 * still be correctly generated if NO ISA IRQ is 512 * selected (ExCA regs 03h or 05h are cleared). 513 */ 514 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 515 reg = (reg & 0x0f) | 516 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 517 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 518 519 break; 520 case CB_TOPIC97: 521 /* 522 * Disable Zoom Video, ToPIC 97, 100. 523 */ 524 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 525 /* 526 * ToPIC 97, 100 527 * At offset 0xa1: INTERRUPT CONTROL register 528 * 0x1: Turn on INT interrupts. 529 */ 530 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 531 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 532 goto topic_common; 533 case CB_TOPIC95: 534 /* 535 * SOCKETCTRL appears to be TOPIC 95/B specific 536 */ 537 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 538 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 539 540 topic_common:; 541 /* 542 * At offset 0xa0: SLOT CONTROL 543 * 0x80 Enable CardBus Functionality 544 * 0x40 Enable CardBus and PC Card registers 545 * 0x20 Lock ID in exca regs 546 * 0x10 Write protect ID in config regs 547 * Clear the rest of the bits, which defaults the slot 548 * in legacy mode to 0x3e0 and offset 0. (legacy 549 * mode is determined elsewhere) 550 */ 551 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 552 CBBM_TOPIC_SLOTCTRL_SLOTON | 553 CBBM_TOPIC_SLOTCTRL_SLOTEN | 554 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 555 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 556 557 /* 558 * At offset 0xa3 Card Detect Control Register 559 * 0x80 CARDBUS enbale 560 * 0x01 Cleared for hardware change detect 561 */ 562 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 563 | CBBM_TOPIC_CDC_CARDBUS, 564 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 565 break; 566 } 567 568 /* 569 * Need to tell ExCA registers to route via PCI interrupts. There 570 * are two ways to do this. Once is to set INTR_ENABLE and the 571 * other is to set CSC to 0. Since both methods are mutually 572 * compatible, we do both. 573 */ 574 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 575 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 576 577 /* close all memory and io windows */ 578 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 579 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 580 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 581 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 582 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 583 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 584 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 585 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 586 } 587 588 static void 589 cbb_powerstate_d0(device_t dev) 590 { 591 u_int32_t membase, irq; 592 593 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 594 /* Save important PCI config data. */ 595 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 596 irq = pci_read_config(dev, PCIR_INTLINE, 4); 597 598 /* Reset the power state. */ 599 device_printf(dev, "chip is in D%d power mode " 600 "-- setting to D0\n", pci_get_powerstate(dev)); 601 602 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 603 604 /* Restore PCI config data. */ 605 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 606 pci_write_config(dev, PCIR_INTLINE, irq, 4); 607 } 608 } 609 610 /* 611 * Print out the config space 612 */ 613 static void 614 cbb_print_config(device_t dev) 615 { 616 int i; 617 618 device_printf(dev, "PCI Configuration space:"); 619 for (i = 0; i < 256; i += 4) { 620 if (i % 16 == 0) 621 printf("\n 0x%02x: ", i); 622 printf("0x%08x ", pci_read_config(dev, i, 4)); 623 } 624 printf("\n"); 625 } 626 627 static int 628 cbb_attach(device_t brdev) 629 { 630 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 631 int rid; 632 633 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 634 cv_init(&sc->cv, "cbb cv"); 635 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 636 sc->dev = brdev; 637 sc->cbdev = NULL; 638 sc->exca.pccarddev = NULL; 639 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 640 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 641 SLIST_INIT(&sc->rl); 642 STAILQ_INIT(&sc->intr_handlers); 643 644 cbb_powerstate_d0(brdev); 645 646 #ifndef BURN_BRIDGES 647 /* 648 * The PCI bus code should assign us memory in the absense 649 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 650 * up something here until the PCI/acpi code properly assigns the 651 * resource. 652 */ 653 #endif 654 rid = CBBR_SOCKBASE; 655 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 656 0, ~0, 1, RF_ACTIVE); 657 if (!sc->base_res) { 658 #ifdef BURN_BRIDGES 659 device_printf(brdev, "Could not map register memory\n"); 660 mtx_destroy(&sc->mtx); 661 cv_destroy(&sc->cv); 662 return (ENOMEM); 663 #else 664 uint32_t sockbase; 665 /* 666 * Generally, the BIOS will assign this memory for us. 667 * However, newer BIOSes do not because the MS design 668 * documents have mandated that this is for the OS 669 * to assign rather than the BIOS. This driver shouldn't 670 * be doing this, but until the pci bus code (or acpi) 671 * does this, we allow CardBus bridges to work on more 672 * machines. 673 */ 674 pci_write_config(brdev, rid, 0xfffffffful, 4); 675 sockbase = pci_read_config(brdev, rid, 4); 676 sockbase = (sockbase & 0xfffffff0ul) & 677 -(sockbase & 0xfffffff0ul); 678 sc->base_res = bus_generic_alloc_resource( 679 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 680 &rid, cbb_start_mem, ~0, sockbase, 681 RF_ACTIVE | rman_make_alignment_flags(sockbase)); 682 if (!sc->base_res) { 683 device_printf(brdev, 684 "Could not grab register memory\n"); 685 mtx_destroy(&sc->mtx); 686 cv_destroy(&sc->cv); 687 return (ENOMEM); 688 } 689 sc->flags |= CBB_KLUDGE_ALLOC; 690 pci_write_config(brdev, CBBR_SOCKBASE, 691 rman_get_start(sc->base_res), 4); 692 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 693 rman_get_start(sc->base_res))); 694 #endif 695 } else { 696 DEVPRINTF((brdev, "Found memory at %08lx\n", 697 rman_get_start(sc->base_res))); 698 } 699 700 sc->bst = rman_get_bustag(sc->base_res); 701 sc->bsh = rman_get_bushandle(sc->base_res); 702 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 703 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 704 sc->exca.chipset = EXCA_CARDBUS; 705 cbb_chipinit(sc); 706 707 /* attach children */ 708 sc->cbdev = device_add_child(brdev, "cardbus", -1); 709 if (sc->cbdev == NULL) 710 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 711 else if (device_probe_and_attach(sc->cbdev) != 0) { 712 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 713 sc->cbdev = NULL; 714 } 715 716 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 717 if (sc->exca.pccarddev == NULL) 718 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 719 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) { 720 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 721 sc->exca.pccarddev = NULL; 722 } 723 724 /* Map and establish the interrupt. */ 725 rid = 0; 726 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 727 RF_SHAREABLE | RF_ACTIVE); 728 if (sc->irq_res == NULL) { 729 printf("cbb: Unable to map IRQ...\n"); 730 goto err; 731 } 732 733 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 734 cbb_intr, sc, &sc->intrhand)) { 735 device_printf(brdev, "couldn't establish interrupt"); 736 goto err; 737 } 738 739 /* reset 16-bit pcmcia bus */ 740 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 741 742 /* turn off power */ 743 cbb_power(brdev, CARD_OFF); 744 745 /* CSC Interrupt: Card detect interrupt on */ 746 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 747 748 /* reset interrupt */ 749 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 750 751 if (bootverbose) 752 cbb_print_config(brdev); 753 754 /* Start the thread */ 755 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 756 "%s%d", device_get_name(brdev), device_get_unit(brdev))) { 757 device_printf(brdev, "unable to create event thread.\n"); 758 panic("cbb_create_event_thread"); 759 } 760 761 return (0); 762 err: 763 if (sc->irq_res) 764 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 765 if (sc->base_res) { 766 if (sc->flags & CBB_KLUDGE_ALLOC) 767 bus_generic_release_resource(device_get_parent(brdev), 768 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 769 sc->base_res); 770 else 771 bus_release_resource(brdev, SYS_RES_MEMORY, 772 CBBR_SOCKBASE, sc->base_res); 773 } 774 mtx_destroy(&sc->mtx); 775 cv_destroy(&sc->cv); 776 return (ENOMEM); 777 } 778 779 static int 780 cbb_detach(device_t brdev) 781 { 782 struct cbb_softc *sc = device_get_softc(brdev); 783 int numdevs; 784 device_t *devlist; 785 int tmp; 786 int error; 787 788 device_get_children(brdev, &devlist, &numdevs); 789 790 error = 0; 791 for (tmp = 0; tmp < numdevs; tmp++) { 792 if (device_detach(devlist[tmp]) == 0) 793 device_delete_child(brdev, devlist[tmp]); 794 else 795 error++; 796 } 797 free(devlist, M_TEMP); 798 if (error > 0) 799 return (ENXIO); 800 801 mtx_lock(&sc->mtx); 802 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 803 sc->flags |= CBB_KTHREAD_DONE; 804 if (sc->flags & CBB_KTHREAD_RUNNING) { 805 cv_broadcast(&sc->cv); 806 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 807 } 808 mtx_unlock(&sc->mtx); 809 810 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 811 if (sc->flags & CBB_KLUDGE_ALLOC) 812 bus_generic_release_resource(device_get_parent(brdev), 813 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, sc->base_res); 814 else 815 bus_release_resource(brdev, SYS_RES_MEMORY, 816 CBBR_SOCKBASE, sc->base_res); 817 mtx_destroy(&sc->mtx); 818 cv_destroy(&sc->cv); 819 return (0); 820 } 821 822 static int 823 cbb_shutdown(device_t brdev) 824 { 825 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 826 /* properly reset everything at shutdown */ 827 828 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 829 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 830 831 cbb_set(sc, CBB_SOCKET_MASK, 0); 832 833 cbb_power(brdev, CARD_OFF); 834 835 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 836 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 837 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 838 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 839 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 840 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 841 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 842 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 843 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 844 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 845 return (0); 846 } 847 848 static int 849 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 850 int flags, driver_intr_t *intr, void *arg, void **cookiep) 851 { 852 struct cbb_intrhand *ih; 853 struct cbb_softc *sc = device_get_softc(dev); 854 855 /* 856 * You aren't allowed to have fast interrupts for pccard/cardbus 857 * things since those interrupts are PCI and shared. Since we use 858 * the PCI interrupt for the status change interrupts, it can't be 859 * free for use by the driver. Fast interrupts must not be shared. 860 */ 861 if ((flags & INTR_FAST) != 0) 862 return (EINVAL); 863 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 864 if (ih == NULL) 865 return (ENOMEM); 866 *cookiep = ih; 867 ih->intr = intr; 868 ih->arg = arg; 869 ih->flags = flags & INTR_MPSAFE; 870 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 871 /* 872 * XXX need to turn on ISA interrupts, if we ever support them, but 873 * XXX for now that's all we need to do. 874 */ 875 return (0); 876 } 877 878 static int 879 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 880 void *cookie) 881 { 882 struct cbb_intrhand *ih; 883 struct cbb_softc *sc = device_get_softc(dev); 884 885 /* XXX Need to do different things for ISA interrupts. */ 886 ih = (struct cbb_intrhand *) cookie; 887 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 888 free(ih, M_DEVBUF); 889 return (0); 890 } 891 892 893 static void 894 cbb_driver_added(device_t brdev, driver_t *driver) 895 { 896 struct cbb_softc *sc = device_get_softc(brdev); 897 device_t *devlist; 898 device_t dev; 899 int tmp; 900 int numdevs; 901 int wake = 0; 902 903 DEVICE_IDENTIFY(driver, brdev); 904 device_get_children(brdev, &devlist, &numdevs); 905 for (tmp = 0; tmp < numdevs; tmp++) { 906 dev = devlist[tmp]; 907 if (device_get_state(dev) == DS_NOTPRESENT && 908 device_probe_and_attach(dev) == 0) 909 wake++; 910 } 911 free(devlist, M_TEMP); 912 913 if (wake > 0) { 914 mtx_lock(&sc->mtx); 915 cv_signal(&sc->cv); 916 mtx_unlock(&sc->mtx); 917 } 918 } 919 920 static void 921 cbb_child_detached(device_t brdev, device_t child) 922 { 923 struct cbb_softc *sc = device_get_softc(brdev); 924 925 if (child != sc->cbdev && child != sc->exca.pccarddev) 926 device_printf(brdev, "Unknown child detached: %s\n", 927 device_get_nameunit(child)); 928 } 929 930 /************************************************************************/ 931 /* Kthreads */ 932 /************************************************************************/ 933 934 static void 935 cbb_event_thread(void *arg) 936 { 937 struct cbb_softc *sc = arg; 938 uint32_t status; 939 int err; 940 941 sc->flags |= CBB_KTHREAD_RUNNING; 942 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 943 /* 944 * We take out Giant here because we need it deep, 945 * down in the bowels of the vm system for mapping the 946 * memory we need to read the CIS. In addition, since 947 * we are adding/deleting devices from the dev tree, 948 * and that code isn't MP safe, we have to hold Giant. 949 */ 950 mtx_lock(&Giant); 951 status = cbb_get(sc, CBB_SOCKET_STATE); 952 if ((status & CBB_SOCKET_STAT_CD) == 0) 953 cbb_insert(sc); 954 else 955 cbb_removal(sc); 956 mtx_unlock(&Giant); 957 958 /* 959 * In our ISR, we turn off the card changed interrupt. Turn 960 * them back on here before we wait for them to happen. We 961 * turn them on/off so that we can tolerate a large latency 962 * between the time we signal cbb_event_thread and it gets 963 * a chance to run. 964 */ 965 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 966 967 /* 968 * Wait until it has been 1s since the last time we 969 * get an interrupt. We handle the rest of the interrupt 970 * at the top of the loop. Although we clear the bit in the 971 * ISR, we signal sc->cv from the detach path after we've 972 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 973 * 1s sleep here. 974 */ 975 mtx_lock(&sc->mtx); 976 cv_wait(&sc->cv, &sc->mtx); 977 err = 0; 978 while (err != EWOULDBLOCK && 979 (sc->flags & CBB_KTHREAD_DONE) == 0) 980 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 981 mtx_unlock(&sc->mtx); 982 } 983 sc->flags &= ~CBB_KTHREAD_RUNNING; 984 mtx_lock(&Giant); /* kthread_exit drops */ 985 kthread_exit(0); 986 } 987 988 /************************************************************************/ 989 /* Insert/removal */ 990 /************************************************************************/ 991 992 static void 993 cbb_insert(struct cbb_softc *sc) 994 { 995 uint32_t sockevent, sockstate; 996 997 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 998 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 999 1000 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1001 sockevent, sockstate)); 1002 1003 if (sockstate & CBB_SOCKET_STAT_16BIT) { 1004 if (sc->exca.pccarddev) 1005 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1006 exca_insert(&sc->exca); 1007 } else if (sockstate & CBB_SOCKET_STAT_CB) { 1008 if (sc->cbdev != NULL) { 1009 sc->flags &= ~CBB_16BIT_CARD; 1010 sc->flags |= CBB_CARD_OK; 1011 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1012 device_printf(sc->dev, 1013 "CardBus card activation failed\n"); 1014 } else { 1015 device_printf(sc->dev, 1016 "CardBus card inserted, but no cardbus bus.\n"); 1017 } 1018 } else { 1019 /* 1020 * We should power the card down, and try again a couple of 1021 * times if this happens. XXX 1022 */ 1023 device_printf(sc->dev, "Unsupported card type detected\n"); 1024 } 1025 } 1026 1027 static void 1028 cbb_removal(struct cbb_softc *sc) 1029 { 1030 if (sc->flags & CBB_16BIT_CARD) { 1031 exca_removal(&sc->exca); 1032 } else { 1033 if (sc->cbdev != NULL) 1034 CARD_DETACH_CARD(sc->cbdev); 1035 } 1036 cbb_destroy_res(sc); 1037 } 1038 1039 /************************************************************************/ 1040 /* Interrupt Handler */ 1041 /************************************************************************/ 1042 1043 static void 1044 cbb_intr(void *arg) 1045 { 1046 struct cbb_softc *sc = arg; 1047 uint32_t sockevent; 1048 struct cbb_intrhand *ih; 1049 1050 /* 1051 * This ISR needs work XXX 1052 */ 1053 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1054 if (sockevent) { 1055 /* ack the interrupt */ 1056 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1057 1058 /* 1059 * If anything has happened to the socket, we assume that 1060 * the card is no longer OK, and we shouldn't call its 1061 * ISR. We set CARD_OK as soon as we've attached the 1062 * card. This helps in a noisy eject, which happens 1063 * all too often when users are ejecting their PC Cards. 1064 * 1065 * We use this method in preference to checking to see if 1066 * the card is still there because the check suffers from 1067 * a race condition in the bouncing case. Prior versions 1068 * of the pccard software used a similar trick and achieved 1069 * excellent results. 1070 */ 1071 if (sockevent & CBB_SOCKET_EVENT_CD) { 1072 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1073 mtx_lock(&sc->mtx); 1074 sc->flags &= ~CBB_CARD_OK; 1075 cv_signal(&sc->cv); 1076 mtx_unlock(&sc->mtx); 1077 } 1078 if (sockevent & CBB_SOCKET_EVENT_CSTS) { 1079 DPRINTF((" cstsevent occured: 0x%08x\n", 1080 cbb_get(sc, CBB_SOCKET_STATE))); 1081 } 1082 if (sockevent & CBB_SOCKET_EVENT_POWER) { 1083 DPRINTF((" pwrevent occured: 0x%08x\n", 1084 cbb_get(sc, CBB_SOCKET_STATE))); 1085 } 1086 /* Other bits? */ 1087 } 1088 if (sc->flags & CBB_CARD_OK) { 1089 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1090 if ((ih->flags & INTR_MPSAFE) != 0) 1091 mtx_lock(&Giant); 1092 (*ih->intr)(ih->arg); 1093 if ((ih->flags & INTR_MPSAFE) != 0) 1094 mtx_unlock(&Giant); 1095 } 1096 } 1097 } 1098 1099 /************************************************************************/ 1100 /* Generic Power functions */ 1101 /************************************************************************/ 1102 1103 static int 1104 cbb_detect_voltage(device_t brdev) 1105 { 1106 struct cbb_softc *sc = device_get_softc(brdev); 1107 uint32_t psr; 1108 int vol = CARD_UKN_CARD; 1109 1110 psr = cbb_get(sc, CBB_SOCKET_STATE); 1111 1112 if (psr & CBB_SOCKET_STAT_5VCARD) 1113 vol |= CARD_5V_CARD; 1114 if (psr & CBB_SOCKET_STAT_3VCARD) 1115 vol |= CARD_3V_CARD; 1116 if (psr & CBB_SOCKET_STAT_XVCARD) 1117 vol |= CARD_XV_CARD; 1118 if (psr & CBB_SOCKET_STAT_YVCARD) 1119 vol |= CARD_YV_CARD; 1120 1121 return (vol); 1122 } 1123 1124 static uint8_t 1125 cbb_o2micro_power_hack(struct cbb_softc *sc) 1126 { 1127 uint8_t reg; 1128 1129 /* 1130 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1131 * unexpected PCI INT# may be generated during PC-Card 1132 * initialization even with the IRQ Routing Bit Set with some 1133 * PC-Cards. 1134 * 1135 * This is a two part issue. The first part is that some of 1136 * our older controllers have an issue in which the slot's PCI 1137 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1138 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1139 * is selected (ExCA register 03h bits 3:0, of the slot, are 1140 * cleared) we will generate INT# if IREQ# is asserted. The 1141 * second part is because some PC-Cards prematurally assert 1142 * IREQ# before the ExCA registers are fully programmed. This 1143 * in turn asserts INT# because ExCA register 03h bits 3:0 1144 * (ISA IRQ Select) are not yet programmed. 1145 * 1146 * The fix for this issue, which will work for any controller 1147 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1148 * (select IRQ1), of the slot, before turning on slot power. 1149 * Selecting IRQ1 will result in INT# NOT being asserted 1150 * (because IRQ1 is selected), and IRQ1 won't be asserted 1151 * because our controllers don't generate IRQ1. 1152 */ 1153 reg = exca_getb(&sc->exca, EXCA_INTR); 1154 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1155 return (reg); 1156 } 1157 1158 /* 1159 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1160 * we don't have an interrupt storm on power on. This has the efect of 1161 * disabling card status change interrupts for the duration of poweron. 1162 */ 1163 static void 1164 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1165 { 1166 exca_putb(&sc->exca, EXCA_INTR, reg); 1167 } 1168 1169 static int 1170 cbb_power(device_t brdev, int volts) 1171 { 1172 uint32_t status, sock_ctrl; 1173 struct cbb_softc *sc = device_get_softc(brdev); 1174 int timeout; 1175 int retval = 0; 1176 uint32_t sockevent; 1177 uint8_t reg = 0; 1178 1179 status = cbb_get(sc, CBB_SOCKET_STATE); 1180 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1181 1182 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1183 switch (volts & CARD_VCCMASK) { 1184 case 5: 1185 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1186 break; 1187 case 3: 1188 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1189 break; 1190 case XV: 1191 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1192 break; 1193 case YV: 1194 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1195 break; 1196 case 0: 1197 break; 1198 default: 1199 return (0); /* power NEVER changed */ 1200 } 1201 1202 /* VPP == VCC */ 1203 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1204 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1205 1206 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1207 return (1); /* no change necessary */ 1208 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1209 if (volts != 0 && sc->chipset == CB_O2MICRO) 1210 reg = cbb_o2micro_power_hack(sc); 1211 1212 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1213 status = cbb_get(sc, CBB_SOCKET_STATE); 1214 1215 /* 1216 * XXX This busy wait is bogus. We should wait for a power 1217 * interrupt and then whine if the status is bad. If we're 1218 * worried about the card not coming up, then we should also 1219 * schedule a timeout which we can cancel in the power interrupt. 1220 */ 1221 timeout = 20; 1222 do { 1223 DELAY(20*1000); 1224 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1225 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1226 /* reset event status */ 1227 /* XXX should only reset EVENT_POWER */ 1228 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1229 if (timeout < 0) { 1230 printf ("VCC supply failed.\n"); 1231 goto done; 1232 } 1233 1234 /* XXX 1235 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1236 * is 20 ms, some PC-Card bridge requires longer duration. 1237 * XXX Note: We should check the stutus AFTER the delay to give time 1238 * for things to stabilize. 1239 */ 1240 DELAY(400*1000); 1241 1242 if (status & CBB_SOCKET_STAT_BADVCC) { 1243 device_printf(sc->dev, 1244 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1245 sock_ctrl ,status); 1246 printf("cbb_power: %dV\n", volts); 1247 goto done; 1248 } 1249 retval = 1; 1250 done:; 1251 if (volts != 0 && sc->chipset == CB_O2MICRO) 1252 cbb_o2micro_power_hack2(sc, reg); 1253 return (retval); 1254 } 1255 1256 /* 1257 * detect the voltage for the card, and set it. Since the power 1258 * used is the square of the voltage, lower voltages is a big win 1259 * and what Windows does (and what Microsoft prefers). The MS paper 1260 * also talks about preferring the CIS entry as well. 1261 */ 1262 static int 1263 cbb_do_power(device_t brdev) 1264 { 1265 int voltage; 1266 1267 /* Prefer lowest voltage supported */ 1268 voltage = cbb_detect_voltage(brdev); 1269 cbb_power(brdev, CARD_OFF); 1270 if (voltage & CARD_YV_CARD) 1271 cbb_power(brdev, CARD_VCC(YV)); 1272 else if (voltage & CARD_XV_CARD) 1273 cbb_power(brdev, CARD_VCC(XV)); 1274 else if (voltage & CARD_3V_CARD) 1275 cbb_power(brdev, CARD_VCC(3)); 1276 else if (voltage & CARD_5V_CARD) 1277 cbb_power(brdev, CARD_VCC(5)); 1278 else { 1279 device_printf(brdev, "Unknown card voltage\n"); 1280 return (ENXIO); 1281 } 1282 return (0); 1283 } 1284 1285 /************************************************************************/ 1286 /* CardBus power functions */ 1287 /************************************************************************/ 1288 1289 static void 1290 cbb_cardbus_reset(device_t brdev) 1291 { 1292 struct cbb_softc *sc = device_get_softc(brdev); 1293 int delay_us; 1294 1295 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1296 1297 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1298 1299 DELAY(delay_us); 1300 1301 /* If a card exists, unreset it! */ 1302 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 0) { 1303 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1304 &~CBBM_BRIDGECTRL_RESET, 2); 1305 DELAY(delay_us); 1306 } 1307 } 1308 1309 static int 1310 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1311 { 1312 struct cbb_softc *sc = device_get_softc(brdev); 1313 int err; 1314 1315 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 1316 CBB_SOCKET_STAT_CD) 1317 return (ENODEV); 1318 1319 err = cbb_do_power(brdev); 1320 if (err) 1321 return (err); 1322 cbb_cardbus_reset(brdev); 1323 return (0); 1324 } 1325 1326 static void 1327 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1328 { 1329 cbb_power(brdev, CARD_OFF); 1330 cbb_cardbus_reset(brdev); 1331 } 1332 1333 /************************************************************************/ 1334 /* CardBus Resource */ 1335 /************************************************************************/ 1336 1337 static int 1338 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1339 { 1340 int basereg; 1341 int limitreg; 1342 1343 if ((win < 0) || (win > 1)) { 1344 DEVPRINTF((brdev, 1345 "cbb_cardbus_io_open: window out of range %d\n", win)); 1346 return (EINVAL); 1347 } 1348 1349 basereg = win * 8 + CBBR_IOBASE0; 1350 limitreg = win * 8 + CBBR_IOLIMIT0; 1351 1352 pci_write_config(brdev, basereg, start, 4); 1353 pci_write_config(brdev, limitreg, end, 4); 1354 return (0); 1355 } 1356 1357 static int 1358 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1359 { 1360 int basereg; 1361 int limitreg; 1362 1363 if ((win < 0) || (win > 1)) { 1364 DEVPRINTF((brdev, 1365 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1366 return (EINVAL); 1367 } 1368 1369 basereg = win*8 + CBBR_MEMBASE0; 1370 limitreg = win*8 + CBBR_MEMLIMIT0; 1371 1372 pci_write_config(brdev, basereg, start, 4); 1373 pci_write_config(brdev, limitreg, end, 4); 1374 return (0); 1375 } 1376 1377 /* 1378 * XXX The following function belongs in the pci bus layer. 1379 */ 1380 static void 1381 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1382 { 1383 uint32_t starts[2]; 1384 uint32_t ends[2]; 1385 struct cbb_reslist *rle; 1386 int align; 1387 int prefetchable[2]; 1388 uint32_t reg; 1389 1390 starts[0] = starts[1] = 0xffffffff; 1391 ends[0] = ends[1] = 0; 1392 1393 if (type == SYS_RES_MEMORY) 1394 align = CBB_MEMALIGN; 1395 else if (type == SYS_RES_IOPORT) 1396 align = CBB_IOALIGN; 1397 else 1398 align = 1; 1399 1400 SLIST_FOREACH(rle, &sc->rl, link) { 1401 if (rle->type != type) 1402 ; 1403 else if (rle->res == NULL) { 1404 device_printf(sc->dev, "WARNING: Resource not reserved? " 1405 "(type=%d, addr=%lx)\n", 1406 rle->type, rman_get_start(rle->res)); 1407 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1408 /* XXX */ 1409 } else if (starts[0] == 0xffffffff) { 1410 starts[0] = rman_get_start(rle->res); 1411 ends[0] = rman_get_end(rle->res); 1412 prefetchable[0] = 1413 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1414 } else if (rman_get_end(rle->res) > ends[0] && 1415 rman_get_start(rle->res) - ends[0] < 1416 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1417 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1418 ends[0] = rman_get_end(rle->res); 1419 } else if (rman_get_start(rle->res) < starts[0] && 1420 starts[0] - rman_get_end(rle->res) < 1421 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1422 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1423 starts[0] = rman_get_start(rle->res); 1424 } else if (starts[1] == 0xffffffff) { 1425 starts[1] = rman_get_start(rle->res); 1426 ends[1] = rman_get_end(rle->res); 1427 prefetchable[1] = 1428 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1429 } else if (rman_get_end(rle->res) > ends[1] && 1430 rman_get_start(rle->res) - ends[1] < 1431 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1432 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1433 ends[1] = rman_get_end(rle->res); 1434 } else if (rman_get_start(rle->res) < starts[1] && 1435 starts[1] - rman_get_end(rle->res) < 1436 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1437 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1438 starts[1] = rman_get_start(rle->res); 1439 } else { 1440 uint32_t diffs[2]; 1441 int win; 1442 1443 diffs[0] = diffs[1] = 0xffffffff; 1444 if (rman_get_start(rle->res) > ends[0]) 1445 diffs[0] = rman_get_start(rle->res) - ends[0]; 1446 else if (rman_get_end(rle->res) < starts[0]) 1447 diffs[0] = starts[0] - rman_get_end(rle->res); 1448 if (rman_get_start(rle->res) > ends[1]) 1449 diffs[1] = rman_get_start(rle->res) - ends[1]; 1450 else if (rman_get_end(rle->res) < starts[1]) 1451 diffs[1] = starts[1] - rman_get_end(rle->res); 1452 1453 win = (diffs[0] <= diffs[1])?0:1; 1454 if (rman_get_start(rle->res) > ends[win]) 1455 ends[win] = rman_get_end(rle->res); 1456 else if (rman_get_end(rle->res) < starts[win]) 1457 starts[win] = rman_get_start(rle->res); 1458 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1459 prefetchable[win] = 0; 1460 } 1461 1462 if (starts[0] != 0xffffffff) 1463 starts[0] -= starts[0] % align; 1464 if (starts[1] != 0xffffffff) 1465 starts[1] -= starts[1] % align; 1466 if (ends[0] % align != 0) 1467 ends[0] += align - ends[0]%align - 1; 1468 if (ends[1] % align != 0) 1469 ends[1] += align - ends[1]%align - 1; 1470 } 1471 1472 if (type == SYS_RES_MEMORY) { 1473 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1474 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1475 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1476 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1477 CBBM_BRIDGECTRL_PREFETCH_1); 1478 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1479 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1480 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1481 } else if (type == SYS_RES_IOPORT) { 1482 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1483 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1484 } 1485 } 1486 1487 static int 1488 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1489 int rid, struct resource *res) 1490 { 1491 int ret; 1492 1493 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1494 type, rid, res); 1495 if (ret != 0) 1496 return (ret); 1497 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1498 return (0); 1499 } 1500 1501 static int 1502 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1503 int rid, struct resource *res) 1504 { 1505 int ret; 1506 1507 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1508 type, rid, res); 1509 if (ret != 0) 1510 return (ret); 1511 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1512 return (0); 1513 } 1514 1515 static struct resource * 1516 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1517 int *rid, u_long start, u_long end, u_long count, uint flags) 1518 { 1519 struct cbb_softc *sc = device_get_softc(brdev); 1520 int tmp; 1521 struct resource *res; 1522 1523 switch (type) { 1524 case SYS_RES_IRQ: 1525 tmp = rman_get_start(sc->irq_res); 1526 if (start > tmp || end < tmp || count != 1) { 1527 device_printf(child, "requested interrupt %ld-%ld," 1528 "count = %ld not supported by cbb\n", 1529 start, end, count); 1530 return (NULL); 1531 } 1532 start = end = tmp; 1533 flags |= RF_SHAREABLE; 1534 break; 1535 case SYS_RES_IOPORT: 1536 if (start <= cbb_start_32_io) 1537 start = cbb_start_32_io; 1538 if (end < start) 1539 end = start; 1540 break; 1541 case SYS_RES_MEMORY: 1542 if (start <= cbb_start_mem) 1543 start = cbb_start_mem; 1544 if (end < start) 1545 end = start; 1546 break; 1547 } 1548 1549 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1550 start, end, count, flags & ~RF_ACTIVE); 1551 if (res == NULL) { 1552 printf("cbb alloc res fail\n"); 1553 return (NULL); 1554 } 1555 cbb_insert_res(sc, res, type, *rid); 1556 if (flags & RF_ACTIVE) 1557 if (bus_activate_resource(child, type, *rid, res) != 0) { 1558 bus_release_resource(child, type, *rid, res); 1559 return (NULL); 1560 } 1561 1562 return (res); 1563 } 1564 1565 static int 1566 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1567 int rid, struct resource *res) 1568 { 1569 struct cbb_softc *sc = device_get_softc(brdev); 1570 int error; 1571 1572 if (rman_get_flags(res) & RF_ACTIVE) { 1573 error = bus_deactivate_resource(child, type, rid, res); 1574 if (error != 0) 1575 return (error); 1576 } 1577 cbb_remove_res(sc, res); 1578 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1579 type, rid, res)); 1580 } 1581 1582 /************************************************************************/ 1583 /* PC Card Power Functions */ 1584 /************************************************************************/ 1585 1586 static int 1587 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1588 { 1589 struct cbb_softc *sc = device_get_softc(brdev); 1590 int err; 1591 1592 DPRINTF(("cbb_pcic_socket_enable:\n")); 1593 1594 /* power down/up the socket to reset */ 1595 err = cbb_do_power(brdev); 1596 if (err) 1597 return (err); 1598 exca_reset(&sc->exca, child); 1599 1600 return (0); 1601 } 1602 1603 static void 1604 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1605 { 1606 struct cbb_softc *sc = device_get_softc(brdev); 1607 1608 DPRINTF(("cbb_pcic_socket_disable\n")); 1609 1610 /* reset signal asserting... */ 1611 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1612 DELAY(2*1000); 1613 1614 /* power down the socket */ 1615 cbb_power(brdev, CARD_OFF); 1616 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1617 1618 /* wait 300ms until power fails (Tpf). */ 1619 DELAY(300 * 1000); 1620 } 1621 1622 /************************************************************************/ 1623 /* POWER methods */ 1624 /************************************************************************/ 1625 1626 static int 1627 cbb_power_enable_socket(device_t brdev, device_t child) 1628 { 1629 struct cbb_softc *sc = device_get_softc(brdev); 1630 1631 if (sc->flags & CBB_16BIT_CARD) 1632 return (cbb_pcic_power_enable_socket(brdev, child)); 1633 else 1634 return (cbb_cardbus_power_enable_socket(brdev, child)); 1635 } 1636 1637 static void 1638 cbb_power_disable_socket(device_t brdev, device_t child) 1639 { 1640 struct cbb_softc *sc = device_get_softc(brdev); 1641 if (sc->flags & CBB_16BIT_CARD) 1642 cbb_pcic_power_disable_socket(brdev, child); 1643 else 1644 cbb_cardbus_power_disable_socket(brdev, child); 1645 } 1646 1647 static int 1648 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1649 struct resource *res) 1650 { 1651 struct cbb_softc *sc = device_get_softc(brdev); 1652 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1653 } 1654 1655 static int 1656 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1657 int rid, struct resource *res) 1658 { 1659 struct cbb_softc *sc = device_get_softc(brdev); 1660 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1661 } 1662 1663 static struct resource * 1664 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1665 u_long start, u_long end, u_long count, uint flags) 1666 { 1667 struct resource *res = NULL; 1668 struct cbb_softc *sc = device_get_softc(brdev); 1669 int tmp; 1670 1671 switch (type) { 1672 case SYS_RES_MEMORY: 1673 if (start < cbb_start_mem) 1674 start = cbb_start_mem; 1675 if (end < start) 1676 end = start; 1677 flags = (flags & ~RF_ALIGNMENT_MASK) | 1678 rman_make_alignment_flags(CBB_MEMALIGN); 1679 break; 1680 case SYS_RES_IOPORT: 1681 if (start < cbb_start_16_io) 1682 start = cbb_start_16_io; 1683 if (end < start) 1684 end = start; 1685 break; 1686 case SYS_RES_IRQ: 1687 tmp = rman_get_start(sc->irq_res); 1688 if (start > tmp || end < tmp || count != 1) { 1689 device_printf(child, "requested interrupt %ld-%ld," 1690 "count = %ld not supported by cbb\n", 1691 start, end, count); 1692 return (NULL); 1693 } 1694 flags |= RF_SHAREABLE; 1695 start = end = rman_get_start(sc->irq_res); 1696 break; 1697 } 1698 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1699 start, end, count, flags & ~RF_ACTIVE); 1700 if (res == NULL) 1701 return (NULL); 1702 cbb_insert_res(sc, res, type, *rid); 1703 if (flags & RF_ACTIVE) { 1704 if (bus_activate_resource(child, type, *rid, res) != 0) { 1705 bus_release_resource(child, type, *rid, res); 1706 return (NULL); 1707 } 1708 } 1709 1710 return (res); 1711 } 1712 1713 static int 1714 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1715 int rid, struct resource *res) 1716 { 1717 struct cbb_softc *sc = device_get_softc(brdev); 1718 int error; 1719 1720 if (rman_get_flags(res) & RF_ACTIVE) { 1721 error = bus_deactivate_resource(child, type, rid, res); 1722 if (error != 0) 1723 return (error); 1724 } 1725 cbb_remove_res(sc, res); 1726 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1727 type, rid, res)); 1728 } 1729 1730 /************************************************************************/ 1731 /* PC Card methods */ 1732 /************************************************************************/ 1733 1734 static int 1735 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1736 uint32_t flags) 1737 { 1738 struct cbb_softc *sc = device_get_softc(brdev); 1739 struct resource *res; 1740 1741 if (type != SYS_RES_MEMORY) 1742 return (EINVAL); 1743 res = cbb_find_res(sc, type, rid); 1744 if (res == NULL) { 1745 device_printf(brdev, 1746 "set_res_flags: specified rid not found\n"); 1747 return (ENOENT); 1748 } 1749 return (exca_mem_set_flags(&sc->exca, res, flags)); 1750 } 1751 1752 static int 1753 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1754 uint32_t cardaddr, uint32_t *deltap) 1755 { 1756 struct cbb_softc *sc = device_get_softc(brdev); 1757 struct resource *res; 1758 1759 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1760 if (res == NULL) { 1761 device_printf(brdev, 1762 "set_memory_offset: specified rid not found\n"); 1763 return (ENOENT); 1764 } 1765 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1766 } 1767 1768 /************************************************************************/ 1769 /* BUS Methods */ 1770 /************************************************************************/ 1771 1772 1773 static int 1774 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1775 struct resource *r) 1776 { 1777 struct cbb_softc *sc = device_get_softc(brdev); 1778 1779 if (sc->flags & CBB_16BIT_CARD) 1780 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1781 else 1782 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1783 r)); 1784 } 1785 1786 static int 1787 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1788 int rid, struct resource *r) 1789 { 1790 struct cbb_softc *sc = device_get_softc(brdev); 1791 1792 if (sc->flags & CBB_16BIT_CARD) 1793 return (cbb_pcic_deactivate_resource(brdev, child, type, 1794 rid, r)); 1795 else 1796 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1797 rid, r)); 1798 } 1799 1800 static struct resource * 1801 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1802 u_long start, u_long end, u_long count, uint flags) 1803 { 1804 struct cbb_softc *sc = device_get_softc(brdev); 1805 1806 if (sc->flags & CBB_16BIT_CARD) 1807 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1808 start, end, count, flags)); 1809 else 1810 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1811 start, end, count, flags)); 1812 } 1813 1814 static int 1815 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1816 struct resource *r) 1817 { 1818 struct cbb_softc *sc = device_get_softc(brdev); 1819 1820 if (sc->flags & CBB_16BIT_CARD) 1821 return (cbb_pcic_release_resource(brdev, child, type, 1822 rid, r)); 1823 else 1824 return (cbb_cardbus_release_resource(brdev, child, type, 1825 rid, r)); 1826 } 1827 1828 static int 1829 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1830 { 1831 struct cbb_softc *sc = device_get_softc(brdev); 1832 1833 switch (which) { 1834 case PCIB_IVAR_BUS: 1835 *result = sc->secbus; 1836 return (0); 1837 } 1838 return (ENOENT); 1839 } 1840 1841 static int 1842 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1843 { 1844 struct cbb_softc *sc = device_get_softc(brdev); 1845 1846 switch (which) { 1847 case PCIB_IVAR_BUS: 1848 sc->secbus = value; 1849 break; 1850 } 1851 return (ENOENT); 1852 } 1853 1854 /************************************************************************/ 1855 /* PCI compat methods */ 1856 /************************************************************************/ 1857 1858 static int 1859 cbb_maxslots(device_t brdev) 1860 { 1861 return (0); 1862 } 1863 1864 static uint32_t 1865 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1866 { 1867 /* 1868 * Pass through to the next ppb up the chain (i.e. our grandparent). 1869 */ 1870 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1871 b, s, f, reg, width)); 1872 } 1873 1874 static void 1875 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1876 int width) 1877 { 1878 /* 1879 * Pass through to the next ppb up the chain (i.e. our grandparent). 1880 */ 1881 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1882 b, s, f, reg, val, width); 1883 } 1884 1885 static int 1886 cbb_suspend(device_t self) 1887 { 1888 int error = 0; 1889 struct cbb_softc *sc = device_get_softc(self); 1890 1891 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1892 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1893 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1894 error = bus_generic_suspend(self); 1895 return (error); 1896 } 1897 1898 static int 1899 cbb_resume(device_t self) 1900 { 1901 int error = 0; 1902 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1903 uint32_t tmp; 1904 1905 /* 1906 * Some BIOSes will not save the BARs for the pci chips, so we 1907 * must do it ourselves. If the BAR is reset to 0 for an I/O 1908 * device, it will read back as 0x1, so no explicit test for 1909 * memory devices are needed. 1910 * 1911 * Note: The PCI bus code should do this automatically for us on 1912 * suspend/resume, but until it does, we have to cope. 1913 */ 1914 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1915 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1916 rman_get_start(sc->base_res))); 1917 1918 cbb_chipinit(sc); 1919 1920 /* reset interrupt -- Do we really need to do this? */ 1921 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1922 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1923 1924 /* re-establish the interrupt. */ 1925 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 1926 &sc->intrhand)) { 1927 device_printf(self, "couldn't re-establish interrupt"); 1928 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1929 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1930 sc->base_res); 1931 sc->irq_res = NULL; 1932 sc->base_res = NULL; 1933 return (ENOMEM); 1934 } 1935 1936 /* CSC Interrupt: Card detect interrupt on */ 1937 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1938 1939 /* Signal the thread to wakeup. */ 1940 mtx_lock(&sc->mtx); 1941 cv_signal(&sc->cv); 1942 mtx_unlock(&sc->mtx); 1943 1944 error = bus_generic_resume(self); 1945 1946 return (error); 1947 } 1948 1949 static int 1950 cbb_child_present(device_t self) 1951 { 1952 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1953 uint32_t sockstate; 1954 1955 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1956 return ((sockstate & CBB_SOCKET_STAT_CD) != 0 && 1957 (sc->flags & CBB_CARD_OK) != 0); 1958 } 1959 1960 static device_method_t cbb_methods[] = { 1961 /* Device interface */ 1962 DEVMETHOD(device_probe, cbb_probe), 1963 DEVMETHOD(device_attach, cbb_attach), 1964 DEVMETHOD(device_detach, cbb_detach), 1965 DEVMETHOD(device_shutdown, cbb_shutdown), 1966 DEVMETHOD(device_suspend, cbb_suspend), 1967 DEVMETHOD(device_resume, cbb_resume), 1968 1969 /* bus methods */ 1970 DEVMETHOD(bus_print_child, bus_generic_print_child), 1971 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 1972 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 1973 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 1974 DEVMETHOD(bus_release_resource, cbb_release_resource), 1975 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 1976 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 1977 DEVMETHOD(bus_driver_added, cbb_driver_added), 1978 DEVMETHOD(bus_child_detached, cbb_child_detached), 1979 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 1980 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 1981 DEVMETHOD(bus_child_present, cbb_child_present), 1982 1983 /* 16-bit card interface */ 1984 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 1985 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 1986 1987 /* power interface */ 1988 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 1989 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 1990 1991 /* pcib compatibility interface */ 1992 DEVMETHOD(pcib_maxslots, cbb_maxslots), 1993 DEVMETHOD(pcib_read_config, cbb_read_config), 1994 DEVMETHOD(pcib_write_config, cbb_write_config), 1995 {0,0} 1996 }; 1997 1998 static driver_t cbb_driver = { 1999 "cbb", 2000 cbb_methods, 2001 sizeof(struct cbb_softc) 2002 }; 2003 2004 static devclass_t cbb_devclass; 2005 2006 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2007 MODULE_VERSION(cbb, 1); 2008 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2009