1 /* 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 __FBSDID("$FreeBSD$"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/condvar.h> 82 #include <sys/errno.h> 83 #include <sys/kernel.h> 84 #include <sys/module.h> 85 #include <sys/lock.h> 86 #include <sys/malloc.h> 87 #include <sys/mutex.h> 88 #include <sys/sysctl.h> 89 #include <sys/kthread.h> 90 #include <sys/bus.h> 91 #include <machine/bus.h> 92 #include <sys/rman.h> 93 #include <machine/resource.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <machine/clock.h> 98 99 #include <dev/pccard/pccardreg.h> 100 #include <dev/pccard/pccardvar.h> 101 102 #include <dev/exca/excareg.h> 103 #include <dev/exca/excavar.h> 104 105 #include <dev/pccbb/pccbbreg.h> 106 #include <dev/pccbb/pccbbvar.h> 107 108 #include "power_if.h" 109 #include "card_if.h" 110 #include "pcib_if.h" 111 112 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 113 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 114 115 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 116 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 117 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 118 pci_write_config(DEV, REG, ( \ 119 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 120 121 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 122 123 #define CBB_START_MEM 0x88000000 124 #define CBB_START_32_IO 0x1000 125 #define CBB_START_16_IO 0x100 126 127 struct yenta_chipinfo { 128 uint32_t yc_id; 129 const char *yc_name; 130 int yc_chiptype; 131 } yc_chipsets[] = { 132 /* Texas Instruments chips */ 133 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 134 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 135 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 136 137 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 143 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 144 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 145 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 147 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 151 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI1515, "TI1515 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI1530, "TI1530 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI1620, "TI1620 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI4520, "TI4520 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_TI6411, "TI[67]x[12]1 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_TI6420, "TI[67]x20 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_TI6420SC, "TI[67]x20 (SC) PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_TI7610M, "TI7610 (M) PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_TI7610SD, "TI7610 (SD) PCI-CardBus Bridge", CB_TI12XX}, 170 {PCIC_ID_TI7610MS, "TI7610 (MS) PCI-CardBus Bridge", CB_TI12XX}, 171 172 /* ENE */ 173 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 174 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 175 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 176 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 177 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 178 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 179 180 /* Ricoh chips */ 181 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 182 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 183 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 184 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 185 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 186 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 187 188 /* Toshiba products */ 189 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 190 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 191 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 192 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 193 194 /* Cirrus Logic */ 195 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 196 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 197 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 198 199 /* 02Micro */ 200 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 203 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 204 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 205 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 206 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 207 208 /* sentinel */ 209 {0 /* null id */, "unknown", CB_UNKNOWN}, 210 }; 211 212 /* sysctl vars */ 213 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 214 215 /* There's no way to say TUNEABLE_LONG to get the right types */ 216 u_long cbb_start_mem = CBB_START_MEM; 217 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 218 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 219 &cbb_start_mem, CBB_START_MEM, 220 "Starting address for memory allocations"); 221 222 u_long cbb_start_16_io = CBB_START_16_IO; 223 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 224 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 225 &cbb_start_16_io, CBB_START_16_IO, 226 "Starting ioport for 16-bit cards"); 227 228 u_long cbb_start_32_io = CBB_START_32_IO; 229 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 230 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 231 &cbb_start_32_io, CBB_START_32_IO, 232 "Starting ioport for 32-bit cards"); 233 234 int cbb_debug = 0; 235 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 236 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 237 "Verbose cardbus bridge debugging"); 238 239 static int cbb_chipset(uint32_t pci_id, const char **namep); 240 static int cbb_probe(device_t brdev); 241 static void cbb_chipinit(struct cbb_softc *sc); 242 static int cbb_attach(device_t brdev); 243 static int cbb_detach(device_t brdev); 244 static int cbb_shutdown(device_t brdev); 245 static void cbb_driver_added(device_t brdev, driver_t *driver); 246 static void cbb_child_detached(device_t brdev, device_t child); 247 static void cbb_event_thread(void *arg); 248 static void cbb_insert(struct cbb_softc *sc); 249 static void cbb_removal(struct cbb_softc *sc); 250 static void cbb_intr(void *arg); 251 static int cbb_detect_voltage(device_t brdev); 252 static int cbb_power(device_t brdev, int volts); 253 static void cbb_cardbus_reset(device_t brdev); 254 static int cbb_cardbus_power_enable_socket(device_t brdev, 255 device_t child); 256 static void cbb_cardbus_power_disable_socket(device_t brdev, 257 device_t child); 258 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 259 uint32_t end); 260 static int cbb_cardbus_mem_open(device_t brdev, int win, 261 uint32_t start, uint32_t end); 262 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 263 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 264 int type, int rid, struct resource *res); 265 static int cbb_cardbus_deactivate_resource(device_t brdev, 266 device_t child, int type, int rid, struct resource *res); 267 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 268 device_t child, int type, int *rid, u_long start, 269 u_long end, u_long count, u_int flags); 270 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 271 int type, int rid, struct resource *res); 272 static int cbb_power_enable_socket(device_t brdev, device_t child); 273 static void cbb_power_disable_socket(device_t brdev, device_t child); 274 static int cbb_activate_resource(device_t brdev, device_t child, 275 int type, int rid, struct resource *r); 276 static int cbb_deactivate_resource(device_t brdev, device_t child, 277 int type, int rid, struct resource *r); 278 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 279 int type, int *rid, u_long start, u_long end, u_long count, 280 u_int flags); 281 static int cbb_release_resource(device_t brdev, device_t child, 282 int type, int rid, struct resource *r); 283 static int cbb_read_ivar(device_t brdev, device_t child, int which, 284 uintptr_t *result); 285 static int cbb_write_ivar(device_t brdev, device_t child, int which, 286 uintptr_t value); 287 static int cbb_maxslots(device_t brdev); 288 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 289 int reg, int width); 290 static void cbb_write_config(device_t brdev, int b, int s, int f, 291 int reg, uint32_t val, int width); 292 293 /* 294 */ 295 static __inline void 296 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 297 { 298 bus_space_write_4(sc->bst, sc->bsh, reg, val); 299 } 300 301 static __inline uint32_t 302 cbb_get(struct cbb_softc *sc, uint32_t reg) 303 { 304 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 305 } 306 307 static __inline void 308 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 309 { 310 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 311 } 312 313 static __inline void 314 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 315 { 316 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 317 } 318 319 static void 320 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 321 { 322 struct cbb_reslist *rle; 323 324 SLIST_FOREACH(rle, &sc->rl, link) { 325 if (rle->res == res) { 326 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 327 free(rle, M_DEVBUF); 328 return; 329 } 330 } 331 } 332 333 static struct resource * 334 cbb_find_res(struct cbb_softc *sc, int type, int rid) 335 { 336 struct cbb_reslist *rle; 337 338 SLIST_FOREACH(rle, &sc->rl, link) 339 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 340 return (rle->res); 341 return (NULL); 342 } 343 344 static void 345 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 346 int rid) 347 { 348 struct cbb_reslist *rle; 349 350 /* 351 * Need to record allocated resource so we can iterate through 352 * it later. 353 */ 354 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 355 if (rle == NULL) 356 panic("cbb_cardbus_alloc_resource: can't record entry!"); 357 rle->res = res; 358 rle->type = type; 359 rle->rid = rid; 360 SLIST_INSERT_HEAD(&sc->rl, rle, link); 361 } 362 363 static void 364 cbb_destroy_res(struct cbb_softc *sc) 365 { 366 struct cbb_reslist *rle; 367 368 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 369 device_printf(sc->dev, "Danger Will Robinson: Resource " 370 "left allocated! This is a bug... " 371 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 372 rman_get_start(rle->res)); 373 SLIST_REMOVE_HEAD(&sc->rl, link); 374 free(rle, M_DEVBUF); 375 } 376 } 377 378 /************************************************************************/ 379 /* Probe/Attach */ 380 /************************************************************************/ 381 382 static int 383 cbb_chipset(uint32_t pci_id, const char **namep) 384 { 385 struct yenta_chipinfo *ycp; 386 387 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 388 continue; 389 if (namep != NULL) 390 *namep = ycp->yc_name; 391 return (ycp->yc_chiptype); 392 } 393 394 static int 395 cbb_probe(device_t brdev) 396 { 397 const char *name; 398 uint32_t progif; 399 uint32_t subclass; 400 401 /* 402 * Do we know that we support the chipset? If so, then we 403 * accept the device. 404 */ 405 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 406 device_set_desc(brdev, name); 407 return (0); 408 } 409 410 /* 411 * We do support generic CardBus bridges. All that we've seen 412 * to date have progif 0 (the Yenta spec, and successors mandate 413 * this). We do not support PCI PCMCIA bridges (with one exception) 414 * with this driver since they generally are I/O mapped. Those 415 * are supported by the pcic driver. This should help us be more 416 * future proof. 417 */ 418 subclass = pci_get_subclass(brdev); 419 progif = pci_get_progif(brdev); 420 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 421 device_set_desc(brdev, "PCI-CardBus Bridge"); 422 return (0); 423 } 424 return (ENXIO); 425 } 426 427 428 /* 429 * Disable function interrupts by telling the bridge to generate IRQ1 430 * interrupts. These interrupts aren't really generated by the chip, since 431 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 432 * initialization, so this helps to work around the problem. 433 * 434 * XXX We can't do this workaround for all chipsets, because this 435 * XXX causes interference with the keyboard because somechipsets will 436 * XXX actually signal IRQ1 over their serial interrupt connections to 437 * XXX the south bridge. Disable it it for now. 438 */ 439 static void 440 cbb_disable_func_intr(struct cbb_softc *sc) 441 { 442 #if 0 443 uint8_t reg; 444 445 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 446 EXCA_INTR_IRQ_RESERVED1; 447 exca_putb(&sc->exca, EXCA_INTR, reg); 448 #endif 449 } 450 451 /* 452 * Enable function interrupts. We turn on function interrupts when the card 453 * requests an interrupt. The PCMCIA standard says that we should set 454 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 455 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 456 * cards. 457 */ 458 static void 459 cbb_enable_func_intr(struct cbb_softc *sc) 460 { 461 uint8_t reg; 462 463 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 464 EXCA_INTR_IRQ_NONE; 465 exca_putb(&sc->exca, EXCA_INTR, reg); 466 } 467 468 static void 469 cbb_chipinit(struct cbb_softc *sc) 470 { 471 uint32_t mux, sysctrl, reg; 472 473 /* Set CardBus latency timer */ 474 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 475 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 476 477 /* Set PCI latency timer */ 478 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 479 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 480 481 /* Enable memory access */ 482 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 483 | PCIM_CMD_MEMEN 484 | PCIM_CMD_PORTEN 485 | PCIM_CMD_BUSMASTEREN, 2); 486 487 /* disable Legacy IO */ 488 switch (sc->chipset) { 489 case CB_RF5C46X: 490 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 491 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 492 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 493 break; 494 default: 495 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 496 break; 497 } 498 499 /* Use PCI interrupt for interrupt routing */ 500 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 501 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 502 CBBM_BRIDGECTRL_INTR_IREQ_EN), 503 | CBBM_BRIDGECTRL_WRITE_POST_EN, 504 2); 505 506 /* 507 * XXX this should be a function table, ala OLDCARD. This means 508 * that we could more easily support ISA interrupts for pccard 509 * cards if we had to. 510 */ 511 switch (sc->chipset) { 512 case CB_TI113X: 513 /* 514 * The TI 1031, TI 1130 and TI 1131 all require another bit 515 * be set to enable PCI routing of interrupts, and then 516 * a bit for each of the CSC and Function interrupts we 517 * want routed. 518 */ 519 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 520 | CBBM_CBCTRL_113X_PCI_INTR | 521 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 522 1); 523 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 524 & ~(CBBM_DEVCTRL_INT_SERIAL | 525 CBBM_DEVCTRL_INT_PCI), 1); 526 break; 527 case CB_TI12XX: 528 /* 529 * Some TI 12xx (and [14][45]xx) based pci cards 530 * sometimes have issues with the MFUNC register not 531 * being initialized due to a bad EEPROM on board. 532 * Laptops that this matters on have this register 533 * properly initialized. 534 * 535 * The TI125X parts have a different register. 536 */ 537 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 538 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 539 if (mux == 0) { 540 mux = (mux & ~CBBM_MFUNC_PIN0) | 541 CBBM_MFUNC_PIN0_INTA; 542 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 543 mux = (mux & ~CBBM_MFUNC_PIN1) | 544 CBBM_MFUNC_PIN1_INTB; 545 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 546 } 547 /*FALLTHROUGH*/ 548 case CB_TI125X: 549 /* 550 * Disable zoom video. Some machines initialize this 551 * improperly and exerpience has shown that this helps 552 * prevent strange behavior. 553 */ 554 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 555 break; 556 case CB_O2MICRO: 557 /* 558 * Issue #1: INT# generated at the same time as 559 * selected ISA IRQ. When IREQ# or STSCHG# is active, 560 * in addition to the ISA IRQ being generated, INT# 561 * will also be generated at the same time. 562 * 563 * Some of the older controllers have an issue in 564 * which the slot's PCI INT# will be asserted whenever 565 * IREQ# or STSCGH# is asserted even if ExCA registers 566 * 03h or 05h have an ISA IRQ selected. 567 * 568 * The fix for this issue, which will work for any 569 * controller (old or new), is to set ExCA registers 570 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 571 * These bits are undocumented. By setting this 572 * register (of each slot) to '1010xxxxb' a routing of 573 * IREQ# to INTC# and STSCHG# to INTC# is selected. 574 * Since INTC# isn't connected there will be no 575 * unexpected PCI INT when IREQ# or STSCHG# is active. 576 * However, INTA# (slot 0) or INTB# (slot 1) will 577 * still be correctly generated if NO ISA IRQ is 578 * selected (ExCA regs 03h or 05h are cleared). 579 */ 580 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 581 reg = (reg & 0x0f) | 582 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 583 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 584 585 break; 586 case CB_TOPIC97: 587 /* 588 * Disable Zoom Video, ToPIC 97, 100. 589 */ 590 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 591 /* 592 * ToPIC 97, 100 593 * At offset 0xa1: INTERRUPT CONTROL register 594 * 0x1: Turn on INT interrupts. 595 */ 596 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 597 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 598 goto topic_common; 599 case CB_TOPIC95: 600 /* 601 * SOCKETCTRL appears to be TOPIC 95/B specific 602 */ 603 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 604 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 605 606 topic_common:; 607 /* 608 * At offset 0xa0: SLOT CONTROL 609 * 0x80 Enable CardBus Functionality 610 * 0x40 Enable CardBus and PC Card registers 611 * 0x20 Lock ID in exca regs 612 * 0x10 Write protect ID in config regs 613 * Clear the rest of the bits, which defaults the slot 614 * in legacy mode to 0x3e0 and offset 0. (legacy 615 * mode is determined elsewhere) 616 */ 617 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 618 CBBM_TOPIC_SLOTCTRL_SLOTON | 619 CBBM_TOPIC_SLOTCTRL_SLOTEN | 620 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 621 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 622 623 /* 624 * At offset 0xa3 Card Detect Control Register 625 * 0x80 CARDBUS enbale 626 * 0x01 Cleared for hardware change detect 627 */ 628 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 629 | CBBM_TOPIC_CDC_CARDBUS, 630 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 631 break; 632 } 633 634 /* 635 * Need to tell ExCA registers to CSC interrupts route via PCI 636 * interrupts. There are two ways to do this. Once is to set 637 * INTR_ENABLE and the other is to set CSC to 0. Since both 638 * methods are mutually compatible, we do both. 639 */ 640 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 641 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 642 643 cbb_disable_func_intr(sc); 644 645 /* close all memory and io windows */ 646 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 647 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 648 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 649 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 650 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 651 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 652 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 653 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 654 } 655 656 #ifndef BURN_BRIDGES 657 /* 658 * Still need this because the pci code only does power for type 0 659 * header devices. 660 */ 661 static void 662 cbb_powerstate_d0(device_t dev) 663 { 664 u_int32_t membase, irq; 665 666 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 667 /* Save important PCI config data. */ 668 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 669 irq = pci_read_config(dev, PCIR_INTLINE, 4); 670 671 /* Reset the power state. */ 672 device_printf(dev, "chip is in D%d power mode " 673 "-- setting to D0\n", pci_get_powerstate(dev)); 674 675 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 676 677 /* Restore PCI config data. */ 678 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 679 pci_write_config(dev, PCIR_INTLINE, irq, 4); 680 } 681 } 682 #endif 683 684 /* 685 * Print out the config space 686 */ 687 static void 688 cbb_print_config(device_t dev) 689 { 690 int i; 691 692 device_printf(dev, "PCI Configuration space:"); 693 for (i = 0; i < 256; i += 4) { 694 if (i % 16 == 0) 695 printf("\n 0x%02x: ", i); 696 printf("0x%08x ", pci_read_config(dev, i, 4)); 697 } 698 printf("\n"); 699 } 700 701 static int 702 cbb_attach(device_t brdev) 703 { 704 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 705 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 706 int rid, bus, pribus; 707 device_t parent; 708 709 parent = device_get_parent(brdev); 710 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 711 cv_init(&sc->cv, "cbb cv"); 712 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 713 sc->dev = brdev; 714 sc->cbdev = NULL; 715 sc->exca.pccarddev = NULL; 716 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 717 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 718 SLIST_INIT(&sc->rl); 719 STAILQ_INIT(&sc->intr_handlers); 720 #ifndef BURN_BRIDGES 721 cbb_powerstate_d0(brdev); 722 #endif 723 724 rid = CBBR_SOCKBASE; 725 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 726 RF_ACTIVE); 727 if (!sc->base_res) { 728 device_printf(brdev, "Could not map register memory\n"); 729 mtx_destroy(&sc->mtx); 730 cv_destroy(&sc->cv); 731 return (ENOMEM); 732 } else { 733 DEVPRINTF((brdev, "Found memory at %08lx\n", 734 rman_get_start(sc->base_res))); 735 } 736 737 sc->bst = rman_get_bustag(sc->base_res); 738 sc->bsh = rman_get_bushandle(sc->base_res); 739 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 740 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 741 sc->exca.chipset = EXCA_CARDBUS; 742 cbb_chipinit(sc); 743 744 /* 745 * This is a gross hack. We should be scanning the entire pci 746 * tree, assigning bus numbers in a way such that we (1) can 747 * reserve 1 extra bus just in case and (2) all sub busses 748 * are in an appropriate range. 749 */ 750 bus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 751 pribus = pcib_get_bus(parent); 752 DEVPRINTF((brdev, "Secondary bus is %d\n", bus)); 753 if (bus == 0) { 754 if (curr_bus_number <= pribus) 755 curr_bus_number = pribus + 1; 756 if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) { 757 DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus)); 758 pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1); 759 } 760 bus = curr_bus_number; 761 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus, 762 bus + 1)); 763 sc->secbus = bus; 764 sc->subbus = bus + 1; 765 pci_write_config(brdev, PCIR_SECBUS_2, bus, 1); 766 pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1); 767 curr_bus_number += 2; 768 } 769 770 /* attach children */ 771 sc->cbdev = device_add_child(brdev, "cardbus", -1); 772 if (sc->cbdev == NULL) 773 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 774 else if (device_probe_and_attach(sc->cbdev) != 0) 775 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 776 777 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 778 if (sc->exca.pccarddev == NULL) 779 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 780 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) 781 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 782 783 /* Map and establish the interrupt. */ 784 rid = 0; 785 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 786 RF_SHAREABLE | RF_ACTIVE); 787 if (sc->irq_res == NULL) { 788 printf("cbb: Unable to map IRQ...\n"); 789 goto err; 790 } 791 792 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 793 cbb_intr, sc, &sc->intrhand)) { 794 device_printf(brdev, "couldn't establish interrupt"); 795 goto err; 796 } 797 798 /* reset 16-bit pcmcia bus */ 799 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 800 801 /* turn off power */ 802 cbb_power(brdev, CARD_OFF); 803 804 /* CSC Interrupt: Card detect interrupt on */ 805 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 806 807 /* reset interrupt */ 808 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 809 810 if (bootverbose) 811 cbb_print_config(brdev); 812 813 /* Start the thread */ 814 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 815 "%s", device_get_nameunit(brdev))) { 816 device_printf(brdev, "unable to create event thread.\n"); 817 panic("cbb_create_event_thread"); 818 } 819 return (0); 820 err: 821 if (sc->irq_res) 822 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 823 if (sc->base_res) { 824 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 825 sc->base_res); 826 } 827 mtx_destroy(&sc->mtx); 828 cv_destroy(&sc->cv); 829 return (ENOMEM); 830 } 831 832 static int 833 cbb_detach(device_t brdev) 834 { 835 struct cbb_softc *sc = device_get_softc(brdev); 836 int numdevs; 837 device_t *devlist; 838 int tmp; 839 int error; 840 841 device_get_children(brdev, &devlist, &numdevs); 842 843 error = 0; 844 for (tmp = 0; tmp < numdevs; tmp++) { 845 if (device_detach(devlist[tmp]) == 0) 846 device_delete_child(brdev, devlist[tmp]); 847 else 848 error++; 849 } 850 free(devlist, M_TEMP); 851 if (error > 0) 852 return (ENXIO); 853 854 mtx_lock(&sc->mtx); 855 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 856 sc->flags |= CBB_KTHREAD_DONE; 857 if (sc->flags & CBB_KTHREAD_RUNNING) { 858 cv_broadcast(&sc->cv); 859 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 860 } 861 mtx_unlock(&sc->mtx); 862 863 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 864 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 865 sc->base_res); 866 mtx_destroy(&sc->mtx); 867 cv_destroy(&sc->cv); 868 return (0); 869 } 870 871 static int 872 cbb_shutdown(device_t brdev) 873 { 874 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 875 /* properly reset everything at shutdown */ 876 877 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 878 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 879 880 cbb_set(sc, CBB_SOCKET_MASK, 0); 881 882 cbb_power(brdev, CARD_OFF); 883 884 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 885 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 886 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 887 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 888 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 889 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 890 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 891 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 892 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 893 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 894 return (0); 895 } 896 897 static int 898 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 899 int flags, driver_intr_t *intr, void *arg, void **cookiep) 900 { 901 struct cbb_intrhand *ih; 902 struct cbb_softc *sc = device_get_softc(dev); 903 904 /* 905 * You aren't allowed to have fast interrupts for pccard/cardbus 906 * things since those interrupts are PCI and shared. Since we use 907 * the PCI interrupt for the status change interrupts, it can't be 908 * free for use by the driver. Fast interrupts must not be shared. 909 * Well, this is no longer strictly true. You can have multiple 910 * FAST ISRs, but can't mix fast and slow, so we have to assume 911 * least common denominator until the base system supports mixing 912 * and matching better. 913 */ 914 if ((flags & INTR_FAST) != 0) 915 return (EINVAL); 916 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 917 if (ih == NULL) 918 return (ENOMEM); 919 *cookiep = ih; 920 ih->intr = intr; 921 ih->arg = arg; 922 ih->flags = flags & INTR_MPSAFE; 923 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 924 cbb_enable_func_intr(sc); 925 /* 926 * XXX need to turn on ISA interrupts, if we ever support them, but 927 * XXX for now that's all we need to do. 928 */ 929 return (0); 930 } 931 932 static int 933 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 934 void *cookie) 935 { 936 struct cbb_intrhand *ih; 937 struct cbb_softc *sc = device_get_softc(dev); 938 939 /* XXX Need to do different things for ISA interrupts. */ 940 ih = (struct cbb_intrhand *) cookie; 941 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 942 free(ih, M_DEVBUF); 943 return (0); 944 } 945 946 947 static void 948 cbb_driver_added(device_t brdev, driver_t *driver) 949 { 950 struct cbb_softc *sc = device_get_softc(brdev); 951 device_t *devlist; 952 device_t dev; 953 int tmp; 954 int numdevs; 955 int wake = 0; 956 957 DEVICE_IDENTIFY(driver, brdev); 958 device_get_children(brdev, &devlist, &numdevs); 959 for (tmp = 0; tmp < numdevs; tmp++) { 960 dev = devlist[tmp]; 961 if (device_get_state(dev) == DS_NOTPRESENT && 962 device_probe_and_attach(dev) == 0) 963 wake++; 964 } 965 free(devlist, M_TEMP); 966 967 if (wake > 0) { 968 mtx_lock(&sc->mtx); 969 cv_signal(&sc->cv); 970 mtx_unlock(&sc->mtx); 971 } 972 } 973 974 static void 975 cbb_child_detached(device_t brdev, device_t child) 976 { 977 struct cbb_softc *sc = device_get_softc(brdev); 978 979 if (child != sc->cbdev && child != sc->exca.pccarddev) 980 device_printf(brdev, "Unknown child detached: %s\n", 981 device_get_nameunit(child)); 982 } 983 984 /************************************************************************/ 985 /* Kthreads */ 986 /************************************************************************/ 987 988 static void 989 cbb_event_thread(void *arg) 990 { 991 struct cbb_softc *sc = arg; 992 uint32_t status; 993 int err; 994 int not_a_card = 0; 995 996 sc->flags |= CBB_KTHREAD_RUNNING; 997 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 998 /* 999 * We take out Giant here because we need it deep, 1000 * down in the bowels of the vm system for mapping the 1001 * memory we need to read the CIS. In addition, since 1002 * we are adding/deleting devices from the dev tree, 1003 * and that code isn't MP safe, we have to hold Giant. 1004 */ 1005 mtx_lock(&Giant); 1006 status = cbb_get(sc, CBB_SOCKET_STATE); 1007 DPRINTF(("Status is 0x%x\n", status)); 1008 if (!CBB_CARD_PRESENT(status)) { 1009 not_a_card = 0; /* We know card type */ 1010 cbb_removal(sc); 1011 } else if (status & CBB_STATE_NOT_A_CARD) { 1012 /* 1013 * Up to 20 times, try to rescan the card when we 1014 * see NOT_A_CARD. 1015 */ 1016 if (not_a_card++ < 20) { 1017 DEVPRINTF((sc->dev, 1018 "Not a card bit set, rescanning\n")); 1019 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 1020 } else { 1021 device_printf(sc->dev, 1022 "Can't determine card type\n"); 1023 } 1024 } else { 1025 not_a_card = 0; /* We know card type */ 1026 cbb_insert(sc); 1027 } 1028 mtx_unlock(&Giant); 1029 1030 /* 1031 * Wait until it has been 1s since the last time we 1032 * get an interrupt. We handle the rest of the interrupt 1033 * at the top of the loop. Although we clear the bit in the 1034 * ISR, we signal sc->cv from the detach path after we've 1035 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 1036 * 1s sleep here. 1037 * 1038 * In our ISR, we turn off the card changed interrupt. Turn 1039 * them back on here before we wait for them to happen. We 1040 * turn them on/off so that we can tolerate a large latency 1041 * between the time we signal cbb_event_thread and it gets 1042 * a chance to run. 1043 */ 1044 mtx_lock(&sc->mtx); 1045 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1046 cv_wait(&sc->cv, &sc->mtx); 1047 err = 0; 1048 while (err != EWOULDBLOCK && 1049 (sc->flags & CBB_KTHREAD_DONE) == 0) 1050 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 1051 mtx_unlock(&sc->mtx); 1052 } 1053 sc->flags &= ~CBB_KTHREAD_RUNNING; 1054 kthread_exit(0); 1055 } 1056 1057 /************************************************************************/ 1058 /* Insert/removal */ 1059 /************************************************************************/ 1060 1061 static void 1062 cbb_insert(struct cbb_softc *sc) 1063 { 1064 uint32_t sockevent, sockstate; 1065 1066 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1067 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1068 1069 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1070 sockevent, sockstate)); 1071 1072 if (sockstate & CBB_STATE_R2_CARD) { 1073 if (sc->exca.pccarddev) 1074 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1075 exca_insert(&sc->exca); 1076 } else if (sockstate & CBB_STATE_CB_CARD) { 1077 if (sc->cbdev != NULL) { 1078 sc->flags &= ~CBB_16BIT_CARD; 1079 sc->flags |= CBB_CARD_OK; 1080 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1081 device_printf(sc->dev, 1082 "CardBus card activation failed\n"); 1083 } else { 1084 device_printf(sc->dev, 1085 "CardBus card inserted, but no cardbus bus.\n"); 1086 } 1087 } else { 1088 /* 1089 * We should power the card down, and try again a couple of 1090 * times if this happens. XXX 1091 */ 1092 device_printf(sc->dev, "Unsupported card type detected\n"); 1093 } 1094 } 1095 1096 static void 1097 cbb_removal(struct cbb_softc *sc) 1098 { 1099 if (sc->flags & CBB_16BIT_CARD) { 1100 exca_removal(&sc->exca); 1101 } else { 1102 if (sc->cbdev != NULL) 1103 CARD_DETACH_CARD(sc->cbdev); 1104 } 1105 cbb_destroy_res(sc); 1106 } 1107 1108 /************************************************************************/ 1109 /* Interrupt Handler */ 1110 /************************************************************************/ 1111 1112 static void 1113 cbb_intr(void *arg) 1114 { 1115 struct cbb_softc *sc = arg; 1116 uint32_t sockevent; 1117 struct cbb_intrhand *ih; 1118 1119 /* 1120 * This ISR needs work XXX 1121 */ 1122 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1123 if (sockevent != 0) { 1124 /* ack the interrupt */ 1125 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1126 1127 /* 1128 * If anything has happened to the socket, we assume that 1129 * the card is no longer OK, and we shouldn't call its 1130 * ISR. We set CARD_OK as soon as we've attached the 1131 * card. This helps in a noisy eject, which happens 1132 * all too often when users are ejecting their PC Cards. 1133 * 1134 * We use this method in preference to checking to see if 1135 * the card is still there because the check suffers from 1136 * a race condition in the bouncing case. Prior versions 1137 * of the pccard software used a similar trick and achieved 1138 * excellent results. 1139 */ 1140 if (sockevent & CBB_SOCKET_EVENT_CD) { 1141 mtx_lock(&sc->mtx); 1142 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1143 sc->flags &= ~CBB_CARD_OK; 1144 cbb_disable_func_intr(sc); 1145 cv_signal(&sc->cv); 1146 mtx_unlock(&sc->mtx); 1147 } 1148 } 1149 /* 1150 * Some chips also require us to read the old ExCA registe for 1151 * card status change when we route CSC vis PCI. This isn't supposed 1152 * to be required, but it clears the interrupt state on some chipsets. 1153 * Maybe there's a setting that would obviate its need. Maybe we 1154 * should test the status bits and deal with them, but so far we've 1155 * not found any machines that don't also give us the socket status 1156 * indication above. 1157 * 1158 * We have to call this unconditionally because some bridges deliver 1159 * the even independent of the CBB_SOCKET_EVENT_CD above. 1160 */ 1161 exca_getb(&sc->exca, EXCA_CSC); 1162 1163 /* 1164 * If the card is OK, call all the interrupt handlers. 1165 */ 1166 if (sc->flags & CBB_CARD_OK) { 1167 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1168 if ((ih->flags & INTR_MPSAFE) == 0) 1169 mtx_lock(&Giant); 1170 (*ih->intr)(ih->arg); 1171 if ((ih->flags & INTR_MPSAFE) == 0) 1172 mtx_unlock(&Giant); 1173 } 1174 } 1175 } 1176 1177 /************************************************************************/ 1178 /* Generic Power functions */ 1179 /************************************************************************/ 1180 1181 static int 1182 cbb_detect_voltage(device_t brdev) 1183 { 1184 struct cbb_softc *sc = device_get_softc(brdev); 1185 uint32_t psr; 1186 int vol = CARD_UKN_CARD; 1187 1188 psr = cbb_get(sc, CBB_SOCKET_STATE); 1189 1190 if (psr & CBB_STATE_5VCARD) 1191 vol |= CARD_5V_CARD; 1192 if (psr & CBB_STATE_3VCARD) 1193 vol |= CARD_3V_CARD; 1194 if (psr & CBB_STATE_XVCARD) 1195 vol |= CARD_XV_CARD; 1196 if (psr & CBB_STATE_YVCARD) 1197 vol |= CARD_YV_CARD; 1198 1199 return (vol); 1200 } 1201 1202 static uint8_t 1203 cbb_o2micro_power_hack(struct cbb_softc *sc) 1204 { 1205 uint8_t reg; 1206 1207 /* 1208 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1209 * unexpected PCI INT# may be generated during PC-Card 1210 * initialization even with the IRQ Routing Bit Set with some 1211 * PC-Cards. 1212 * 1213 * This is a two part issue. The first part is that some of 1214 * our older controllers have an issue in which the slot's PCI 1215 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1216 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1217 * is selected (ExCA register 03h bits 3:0, of the slot, are 1218 * cleared) we will generate INT# if IREQ# is asserted. The 1219 * second part is because some PC-Cards prematurally assert 1220 * IREQ# before the ExCA registers are fully programmed. This 1221 * in turn asserts INT# because ExCA register 03h bits 3:0 1222 * (ISA IRQ Select) are not yet programmed. 1223 * 1224 * The fix for this issue, which will work for any controller 1225 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1226 * (select IRQ1), of the slot, before turning on slot power. 1227 * Selecting IRQ1 will result in INT# NOT being asserted 1228 * (because IRQ1 is selected), and IRQ1 won't be asserted 1229 * because our controllers don't generate IRQ1. 1230 */ 1231 reg = exca_getb(&sc->exca, EXCA_INTR); 1232 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1233 return (reg); 1234 } 1235 1236 /* 1237 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1238 * we don't have an interrupt storm on power on. This has the efect of 1239 * disabling card status change interrupts for the duration of poweron. 1240 */ 1241 static void 1242 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1243 { 1244 exca_putb(&sc->exca, EXCA_INTR, reg); 1245 } 1246 1247 static int 1248 cbb_power(device_t brdev, int volts) 1249 { 1250 uint32_t status, sock_ctrl; 1251 struct cbb_softc *sc = device_get_softc(brdev); 1252 int timeout; 1253 int retval = 0; 1254 uint32_t sockevent; 1255 uint8_t reg = 0; 1256 1257 status = cbb_get(sc, CBB_SOCKET_STATE); 1258 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1259 1260 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1261 switch (volts & CARD_VCCMASK) { 1262 case 5: 1263 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1264 break; 1265 case 3: 1266 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1267 break; 1268 case XV: 1269 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1270 break; 1271 case YV: 1272 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1273 break; 1274 case 0: 1275 break; 1276 default: 1277 return (0); /* power NEVER changed */ 1278 } 1279 1280 /* VPP == VCC */ 1281 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1282 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1283 1284 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1285 return (1); /* no change necessary */ 1286 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1287 if (volts != 0 && sc->chipset == CB_O2MICRO) 1288 reg = cbb_o2micro_power_hack(sc); 1289 1290 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1291 status = cbb_get(sc, CBB_SOCKET_STATE); 1292 1293 /* 1294 * XXX This busy wait is bogus. We should wait for a power 1295 * interrupt and then whine if the status is bad. If we're 1296 * worried about the card not coming up, then we should also 1297 * schedule a timeout which we can cancel in the power interrupt. 1298 */ 1299 timeout = 20; 1300 do { 1301 DELAY(20*1000); 1302 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1303 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1304 /* reset event status */ 1305 /* XXX should only reset EVENT_POWER */ 1306 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1307 if (timeout < 0) { 1308 printf ("VCC supply failed.\n"); 1309 goto done; 1310 } 1311 1312 /* XXX 1313 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1314 * is 20 ms, some PC-Card bridge requires longer duration. 1315 * XXX Note: We should check the stutus AFTER the delay to give time 1316 * for things to stabilize. 1317 */ 1318 DELAY(400*1000); 1319 1320 if (status & CBB_STATE_BAD_VCC_REQ) { 1321 device_printf(sc->dev, 1322 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1323 sock_ctrl ,status); 1324 printf("cbb_power: %dV\n", volts); 1325 goto done; 1326 } 1327 retval = 1; 1328 done:; 1329 if (volts != 0 && sc->chipset == CB_O2MICRO) 1330 cbb_o2micro_power_hack2(sc, reg); 1331 return (retval); 1332 } 1333 1334 /* 1335 * detect the voltage for the card, and set it. Since the power 1336 * used is the square of the voltage, lower voltages is a big win 1337 * and what Windows does (and what Microsoft prefers). The MS paper 1338 * also talks about preferring the CIS entry as well. In addition, 1339 * we power up with OE disabled. We'll set it later in the power 1340 * up sequence. 1341 */ 1342 static int 1343 cbb_do_power(device_t brdev) 1344 { 1345 struct cbb_softc *sc = device_get_softc(brdev); 1346 int voltage; 1347 1348 /* Don't enable OE */ 1349 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1350 1351 /* Prefer lowest voltage supported */ 1352 voltage = cbb_detect_voltage(brdev); 1353 cbb_power(brdev, CARD_OFF); 1354 if (voltage & CARD_YV_CARD) 1355 cbb_power(brdev, CARD_VCC(YV)); 1356 else if (voltage & CARD_XV_CARD) 1357 cbb_power(brdev, CARD_VCC(XV)); 1358 else if (voltage & CARD_3V_CARD) 1359 cbb_power(brdev, CARD_VCC(3)); 1360 else if (voltage & CARD_5V_CARD) 1361 cbb_power(brdev, CARD_VCC(5)); 1362 else { 1363 device_printf(brdev, "Unknown card voltage\n"); 1364 return (ENXIO); 1365 } 1366 return (0); 1367 } 1368 1369 /************************************************************************/ 1370 /* CardBus power functions */ 1371 /************************************************************************/ 1372 1373 static void 1374 cbb_cardbus_reset(device_t brdev) 1375 { 1376 struct cbb_softc *sc = device_get_softc(brdev); 1377 int delay_us; 1378 1379 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1380 1381 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1382 1383 DELAY(delay_us); 1384 1385 /* If a card exists, unreset it! */ 1386 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 1387 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1388 &~CBBM_BRIDGECTRL_RESET, 2); 1389 DELAY(delay_us); 1390 } 1391 } 1392 1393 static int 1394 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1395 { 1396 struct cbb_softc *sc = device_get_softc(brdev); 1397 int err; 1398 1399 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 1400 return (ENODEV); 1401 1402 err = cbb_do_power(brdev); 1403 if (err) 1404 return (err); 1405 cbb_cardbus_reset(brdev); 1406 return (0); 1407 } 1408 1409 static void 1410 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1411 { 1412 cbb_power(brdev, CARD_OFF); 1413 cbb_cardbus_reset(brdev); 1414 } 1415 1416 /************************************************************************/ 1417 /* CardBus Resource */ 1418 /************************************************************************/ 1419 1420 static int 1421 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1422 { 1423 int basereg; 1424 int limitreg; 1425 1426 if ((win < 0) || (win > 1)) { 1427 DEVPRINTF((brdev, 1428 "cbb_cardbus_io_open: window out of range %d\n", win)); 1429 return (EINVAL); 1430 } 1431 1432 basereg = win * 8 + CBBR_IOBASE0; 1433 limitreg = win * 8 + CBBR_IOLIMIT0; 1434 1435 pci_write_config(brdev, basereg, start, 4); 1436 pci_write_config(brdev, limitreg, end, 4); 1437 return (0); 1438 } 1439 1440 static int 1441 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1442 { 1443 int basereg; 1444 int limitreg; 1445 1446 if ((win < 0) || (win > 1)) { 1447 DEVPRINTF((brdev, 1448 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1449 return (EINVAL); 1450 } 1451 1452 basereg = win*8 + CBBR_MEMBASE0; 1453 limitreg = win*8 + CBBR_MEMLIMIT0; 1454 1455 pci_write_config(brdev, basereg, start, 4); 1456 pci_write_config(brdev, limitreg, end, 4); 1457 return (0); 1458 } 1459 1460 /* 1461 * XXX The following function belongs in the pci bus layer. 1462 */ 1463 static void 1464 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1465 { 1466 uint32_t starts[2]; 1467 uint32_t ends[2]; 1468 struct cbb_reslist *rle; 1469 int align; 1470 int prefetchable[2]; 1471 uint32_t reg; 1472 1473 starts[0] = starts[1] = 0xffffffff; 1474 ends[0] = ends[1] = 0; 1475 1476 if (type == SYS_RES_MEMORY) 1477 align = CBB_MEMALIGN; 1478 else if (type == SYS_RES_IOPORT) 1479 align = CBB_IOALIGN; 1480 else 1481 align = 1; 1482 1483 /* 1484 * This looks somewhat bogus, and doesn't seem to really respect 1485 * alignment. The alignment stuff is happening too late (it 1486 * should happen at allocation time, not activation time) and 1487 * this code looks generally to be too complex for the purpose 1488 * it surves. 1489 */ 1490 SLIST_FOREACH(rle, &sc->rl, link) { 1491 if (rle->type != type) 1492 ; 1493 else if (rle->res == NULL) { 1494 device_printf(sc->dev, "WARNING: Resource not reserved? " 1495 "(type=%d, addr=%lx)\n", 1496 rle->type, rman_get_start(rle->res)); 1497 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1498 /* XXX */ 1499 } else if (starts[0] == 0xffffffff) { 1500 starts[0] = rman_get_start(rle->res); 1501 ends[0] = rman_get_end(rle->res); 1502 prefetchable[0] = 1503 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1504 } else if (rman_get_end(rle->res) > ends[0] && 1505 rman_get_start(rle->res) - ends[0] < 1506 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1507 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1508 ends[0] = rman_get_end(rle->res); 1509 } else if (rman_get_start(rle->res) < starts[0] && 1510 starts[0] - rman_get_end(rle->res) < 1511 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1512 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1513 starts[0] = rman_get_start(rle->res); 1514 } else if (starts[1] == 0xffffffff) { 1515 starts[1] = rman_get_start(rle->res); 1516 ends[1] = rman_get_end(rle->res); 1517 prefetchable[1] = 1518 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1519 } else if (rman_get_end(rle->res) > ends[1] && 1520 rman_get_start(rle->res) - ends[1] < 1521 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1522 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1523 ends[1] = rman_get_end(rle->res); 1524 } else if (rman_get_start(rle->res) < starts[1] && 1525 starts[1] - rman_get_end(rle->res) < 1526 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1527 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1528 starts[1] = rman_get_start(rle->res); 1529 } else { 1530 uint32_t diffs[2]; 1531 int win; 1532 1533 diffs[0] = diffs[1] = 0xffffffff; 1534 if (rman_get_start(rle->res) > ends[0]) 1535 diffs[0] = rman_get_start(rle->res) - ends[0]; 1536 else if (rman_get_end(rle->res) < starts[0]) 1537 diffs[0] = starts[0] - rman_get_end(rle->res); 1538 if (rman_get_start(rle->res) > ends[1]) 1539 diffs[1] = rman_get_start(rle->res) - ends[1]; 1540 else if (rman_get_end(rle->res) < starts[1]) 1541 diffs[1] = starts[1] - rman_get_end(rle->res); 1542 1543 win = (diffs[0] <= diffs[1])?0:1; 1544 if (rman_get_start(rle->res) > ends[win]) 1545 ends[win] = rman_get_end(rle->res); 1546 else if (rman_get_end(rle->res) < starts[win]) 1547 starts[win] = rman_get_start(rle->res); 1548 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1549 prefetchable[win] = 0; 1550 } 1551 1552 if (starts[0] != 0xffffffff) 1553 starts[0] -= starts[0] % align; 1554 if (starts[1] != 0xffffffff) 1555 starts[1] -= starts[1] % align; 1556 if (ends[0] % align != 0) 1557 ends[0] += align - ends[0] % align - 1; 1558 if (ends[1] % align != 0) 1559 ends[1] += align - ends[1] % align - 1; 1560 } 1561 1562 if (type == SYS_RES_MEMORY) { 1563 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1564 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1565 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1566 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1567 CBBM_BRIDGECTRL_PREFETCH_1); 1568 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1569 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1570 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1571 } else if (type == SYS_RES_IOPORT) { 1572 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1573 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1574 } 1575 } 1576 1577 static int 1578 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1579 int rid, struct resource *res) 1580 { 1581 int ret; 1582 1583 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1584 type, rid, res); 1585 if (ret != 0) 1586 return (ret); 1587 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1588 return (0); 1589 } 1590 1591 static int 1592 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1593 int rid, struct resource *res) 1594 { 1595 int ret; 1596 1597 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1598 type, rid, res); 1599 if (ret != 0) 1600 return (ret); 1601 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1602 return (0); 1603 } 1604 1605 static struct resource * 1606 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1607 int *rid, u_long start, u_long end, u_long count, u_int flags) 1608 { 1609 struct cbb_softc *sc = device_get_softc(brdev); 1610 int tmp; 1611 struct resource *res; 1612 u_long align; 1613 1614 switch (type) { 1615 case SYS_RES_IRQ: 1616 tmp = rman_get_start(sc->irq_res); 1617 if (start > tmp || end < tmp || count != 1) { 1618 device_printf(child, "requested interrupt %ld-%ld," 1619 "count = %ld not supported by cbb\n", 1620 start, end, count); 1621 return (NULL); 1622 } 1623 start = end = tmp; 1624 flags |= RF_SHAREABLE; 1625 break; 1626 case SYS_RES_IOPORT: 1627 if (start <= cbb_start_32_io) 1628 start = cbb_start_32_io; 1629 if (end < start) 1630 end = start; 1631 break; 1632 case SYS_RES_MEMORY: 1633 if (start <= cbb_start_mem) 1634 start = cbb_start_mem; 1635 if (end < start) 1636 end = start; 1637 if (count < CBB_MEMALIGN) 1638 align = CBB_MEMALIGN; 1639 else 1640 align = count; 1641 if (align > (1 << RF_ALIGNMENT(flags))) 1642 flags = (flags & ~RF_ALIGNMENT_MASK) | 1643 rman_make_alignment_flags(align); 1644 break; 1645 } 1646 1647 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1648 start, end, count, flags & ~RF_ACTIVE); 1649 if (res == NULL) { 1650 printf("cbb alloc res fail\n"); 1651 return (NULL); 1652 } 1653 cbb_insert_res(sc, res, type, *rid); 1654 if (flags & RF_ACTIVE) 1655 if (bus_activate_resource(child, type, *rid, res) != 0) { 1656 bus_release_resource(child, type, *rid, res); 1657 return (NULL); 1658 } 1659 1660 return (res); 1661 } 1662 1663 static int 1664 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1665 int rid, struct resource *res) 1666 { 1667 struct cbb_softc *sc = device_get_softc(brdev); 1668 int error; 1669 1670 if (rman_get_flags(res) & RF_ACTIVE) { 1671 error = bus_deactivate_resource(child, type, rid, res); 1672 if (error != 0) 1673 return (error); 1674 } 1675 cbb_remove_res(sc, res); 1676 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1677 type, rid, res)); 1678 } 1679 1680 /************************************************************************/ 1681 /* PC Card Power Functions */ 1682 /************************************************************************/ 1683 1684 static int 1685 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1686 { 1687 struct cbb_softc *sc = device_get_softc(brdev); 1688 int err; 1689 1690 DPRINTF(("cbb_pcic_socket_enable:\n")); 1691 1692 /* power down/up the socket to reset */ 1693 err = cbb_do_power(brdev); 1694 if (err) 1695 return (err); 1696 exca_reset(&sc->exca, child); 1697 1698 return (0); 1699 } 1700 1701 static void 1702 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1703 { 1704 struct cbb_softc *sc = device_get_softc(brdev); 1705 1706 DPRINTF(("cbb_pcic_socket_disable\n")); 1707 1708 /* reset signal asserting... */ 1709 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1710 DELAY(2*1000); 1711 1712 /* power down the socket */ 1713 cbb_power(brdev, CARD_OFF); 1714 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1715 1716 /* wait 300ms until power fails (Tpf). */ 1717 DELAY(300 * 1000); 1718 } 1719 1720 /************************************************************************/ 1721 /* POWER methods */ 1722 /************************************************************************/ 1723 1724 static int 1725 cbb_power_enable_socket(device_t brdev, device_t child) 1726 { 1727 struct cbb_softc *sc = device_get_softc(brdev); 1728 1729 if (sc->flags & CBB_16BIT_CARD) 1730 return (cbb_pcic_power_enable_socket(brdev, child)); 1731 else 1732 return (cbb_cardbus_power_enable_socket(brdev, child)); 1733 } 1734 1735 static void 1736 cbb_power_disable_socket(device_t brdev, device_t child) 1737 { 1738 struct cbb_softc *sc = device_get_softc(brdev); 1739 if (sc->flags & CBB_16BIT_CARD) 1740 cbb_pcic_power_disable_socket(brdev, child); 1741 else 1742 cbb_cardbus_power_disable_socket(brdev, child); 1743 } 1744 1745 static int 1746 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1747 struct resource *res) 1748 { 1749 struct cbb_softc *sc = device_get_softc(brdev); 1750 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1751 } 1752 1753 static int 1754 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1755 int rid, struct resource *res) 1756 { 1757 struct cbb_softc *sc = device_get_softc(brdev); 1758 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1759 } 1760 1761 static struct resource * 1762 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1763 u_long start, u_long end, u_long count, u_int flags) 1764 { 1765 struct resource *res = NULL; 1766 struct cbb_softc *sc = device_get_softc(brdev); 1767 int align; 1768 int tmp; 1769 1770 switch (type) { 1771 case SYS_RES_MEMORY: 1772 if (start < cbb_start_mem) 1773 start = cbb_start_mem; 1774 if (end < start) 1775 end = start; 1776 if (count < CBB_MEMALIGN) 1777 align = CBB_MEMALIGN; 1778 else 1779 align = count; 1780 if (align > (1 << RF_ALIGNMENT(flags))) 1781 flags = (flags & ~RF_ALIGNMENT_MASK) | 1782 rman_make_alignment_flags(align); 1783 break; 1784 case SYS_RES_IOPORT: 1785 if (start < cbb_start_16_io) 1786 start = cbb_start_16_io; 1787 if (end < start) 1788 end = start; 1789 break; 1790 case SYS_RES_IRQ: 1791 tmp = rman_get_start(sc->irq_res); 1792 if (start > tmp || end < tmp || count != 1) { 1793 device_printf(child, "requested interrupt %ld-%ld," 1794 "count = %ld not supported by cbb\n", 1795 start, end, count); 1796 return (NULL); 1797 } 1798 flags |= RF_SHAREABLE; 1799 start = end = rman_get_start(sc->irq_res); 1800 break; 1801 } 1802 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1803 start, end, count, flags & ~RF_ACTIVE); 1804 if (res == NULL) 1805 return (NULL); 1806 cbb_insert_res(sc, res, type, *rid); 1807 if (flags & RF_ACTIVE) { 1808 if (bus_activate_resource(child, type, *rid, res) != 0) { 1809 bus_release_resource(child, type, *rid, res); 1810 return (NULL); 1811 } 1812 } 1813 1814 return (res); 1815 } 1816 1817 static int 1818 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1819 int rid, struct resource *res) 1820 { 1821 struct cbb_softc *sc = device_get_softc(brdev); 1822 int error; 1823 1824 if (rman_get_flags(res) & RF_ACTIVE) { 1825 error = bus_deactivate_resource(child, type, rid, res); 1826 if (error != 0) 1827 return (error); 1828 } 1829 cbb_remove_res(sc, res); 1830 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1831 type, rid, res)); 1832 } 1833 1834 /************************************************************************/ 1835 /* PC Card methods */ 1836 /************************************************************************/ 1837 1838 static int 1839 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1840 uint32_t flags) 1841 { 1842 struct cbb_softc *sc = device_get_softc(brdev); 1843 struct resource *res; 1844 1845 if (type != SYS_RES_MEMORY) 1846 return (EINVAL); 1847 res = cbb_find_res(sc, type, rid); 1848 if (res == NULL) { 1849 device_printf(brdev, 1850 "set_res_flags: specified rid not found\n"); 1851 return (ENOENT); 1852 } 1853 return (exca_mem_set_flags(&sc->exca, res, flags)); 1854 } 1855 1856 static int 1857 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1858 uint32_t cardaddr, uint32_t *deltap) 1859 { 1860 struct cbb_softc *sc = device_get_softc(brdev); 1861 struct resource *res; 1862 1863 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1864 if (res == NULL) { 1865 device_printf(brdev, 1866 "set_memory_offset: specified rid not found\n"); 1867 return (ENOENT); 1868 } 1869 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1870 } 1871 1872 /************************************************************************/ 1873 /* BUS Methods */ 1874 /************************************************************************/ 1875 1876 1877 static int 1878 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1879 struct resource *r) 1880 { 1881 struct cbb_softc *sc = device_get_softc(brdev); 1882 1883 if (sc->flags & CBB_16BIT_CARD) 1884 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1885 else 1886 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1887 r)); 1888 } 1889 1890 static int 1891 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1892 int rid, struct resource *r) 1893 { 1894 struct cbb_softc *sc = device_get_softc(brdev); 1895 1896 if (sc->flags & CBB_16BIT_CARD) 1897 return (cbb_pcic_deactivate_resource(brdev, child, type, 1898 rid, r)); 1899 else 1900 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1901 rid, r)); 1902 } 1903 1904 static struct resource * 1905 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1906 u_long start, u_long end, u_long count, u_int flags) 1907 { 1908 struct cbb_softc *sc = device_get_softc(brdev); 1909 1910 if (sc->flags & CBB_16BIT_CARD) 1911 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1912 start, end, count, flags)); 1913 else 1914 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1915 start, end, count, flags)); 1916 } 1917 1918 static int 1919 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1920 struct resource *r) 1921 { 1922 struct cbb_softc *sc = device_get_softc(brdev); 1923 1924 if (sc->flags & CBB_16BIT_CARD) 1925 return (cbb_pcic_release_resource(brdev, child, type, 1926 rid, r)); 1927 else 1928 return (cbb_cardbus_release_resource(brdev, child, type, 1929 rid, r)); 1930 } 1931 1932 static int 1933 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1934 { 1935 struct cbb_softc *sc = device_get_softc(brdev); 1936 1937 switch (which) { 1938 case PCIB_IVAR_BUS: 1939 *result = sc->secbus; 1940 return (0); 1941 } 1942 return (ENOENT); 1943 } 1944 1945 static int 1946 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1947 { 1948 struct cbb_softc *sc = device_get_softc(brdev); 1949 1950 switch (which) { 1951 case PCIB_IVAR_BUS: 1952 sc->secbus = value; 1953 break; 1954 } 1955 return (ENOENT); 1956 } 1957 1958 /************************************************************************/ 1959 /* PCI compat methods */ 1960 /************************************************************************/ 1961 1962 static int 1963 cbb_maxslots(device_t brdev) 1964 { 1965 return (0); 1966 } 1967 1968 static uint32_t 1969 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1970 { 1971 /* 1972 * Pass through to the next ppb up the chain (i.e. our grandparent). 1973 */ 1974 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1975 b, s, f, reg, width)); 1976 } 1977 1978 static void 1979 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1980 int width) 1981 { 1982 /* 1983 * Pass through to the next ppb up the chain (i.e. our grandparent). 1984 */ 1985 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1986 b, s, f, reg, val, width); 1987 } 1988 1989 static int 1990 cbb_suspend(device_t self) 1991 { 1992 int error = 0; 1993 struct cbb_softc *sc = device_get_softc(self); 1994 1995 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1996 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1997 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1998 error = bus_generic_suspend(self); 1999 return (error); 2000 } 2001 2002 static int 2003 cbb_resume(device_t self) 2004 { 2005 int error = 0; 2006 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 2007 uint32_t tmp; 2008 2009 /* 2010 * Some BIOSes will not save the BARs for the pci chips, so we 2011 * must do it ourselves. If the BAR is reset to 0 for an I/O 2012 * device, it will read back as 0x1, so no explicit test for 2013 * memory devices are needed. 2014 * 2015 * Note: The PCI bus code should do this automatically for us on 2016 * suspend/resume, but until it does, we have to cope. 2017 */ 2018 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 2019 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 2020 rman_get_start(sc->base_res))); 2021 2022 cbb_chipinit(sc); 2023 2024 /* reset interrupt -- Do we really need to do this? */ 2025 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 2026 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 2027 2028 /* re-establish the interrupt. */ 2029 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 2030 cbb_intr, sc, &sc->intrhand)) { 2031 device_printf(self, "couldn't re-establish interrupt"); 2032 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 2033 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 2034 sc->base_res); 2035 sc->irq_res = NULL; 2036 sc->base_res = NULL; 2037 return (ENOMEM); 2038 } 2039 2040 /* CSC Interrupt: Card detect interrupt on */ 2041 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 2042 2043 /* Signal the thread to wakeup. */ 2044 mtx_lock(&sc->mtx); 2045 cv_signal(&sc->cv); 2046 mtx_unlock(&sc->mtx); 2047 2048 error = bus_generic_resume(self); 2049 2050 return (error); 2051 } 2052 2053 static int 2054 cbb_child_present(device_t self) 2055 { 2056 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 2057 uint32_t sockstate; 2058 2059 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 2060 return (CBB_CARD_PRESENT(sockstate) && 2061 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 2062 } 2063 2064 static device_method_t cbb_methods[] = { 2065 /* Device interface */ 2066 DEVMETHOD(device_probe, cbb_probe), 2067 DEVMETHOD(device_attach, cbb_attach), 2068 DEVMETHOD(device_detach, cbb_detach), 2069 DEVMETHOD(device_shutdown, cbb_shutdown), 2070 DEVMETHOD(device_suspend, cbb_suspend), 2071 DEVMETHOD(device_resume, cbb_resume), 2072 2073 /* bus methods */ 2074 DEVMETHOD(bus_print_child, bus_generic_print_child), 2075 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 2076 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 2077 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 2078 DEVMETHOD(bus_release_resource, cbb_release_resource), 2079 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 2080 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 2081 DEVMETHOD(bus_driver_added, cbb_driver_added), 2082 DEVMETHOD(bus_child_detached, cbb_child_detached), 2083 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 2084 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 2085 DEVMETHOD(bus_child_present, cbb_child_present), 2086 2087 /* 16-bit card interface */ 2088 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 2089 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 2090 2091 /* power interface */ 2092 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 2093 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 2094 2095 /* pcib compatibility interface */ 2096 DEVMETHOD(pcib_maxslots, cbb_maxslots), 2097 DEVMETHOD(pcib_read_config, cbb_read_config), 2098 DEVMETHOD(pcib_write_config, cbb_write_config), 2099 {0,0} 2100 }; 2101 2102 static driver_t cbb_driver = { 2103 "cbb", 2104 cbb_methods, 2105 sizeof(struct cbb_softc) 2106 }; 2107 2108 static devclass_t cbb_devclass; 2109 2110 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2111 MODULE_VERSION(cbb, 1); 2112 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2113