1 /* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Driver for PCI to Cardbus Bridge chips 33 * 34 * References: 35 * TI Datasheets: 36 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 37 * Much of the 16-bit PC Card compatibility code stolen from dev/pcic/i82365.c 38 * XXX and should be cleaned up to share as much as possible. 39 * 40 * Written by Jonathan Chen <jon@freebsd.org> 41 * The author would like to acknowledge: 42 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 43 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 44 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 45 * * David Cross: Author of the initial ugly hack for a specific cardbus card 46 */ 47 48 #define CBB_DEBUG 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/kernel.h> 54 #include <sys/kthread.h> 55 #include <sys/lock.h> 56 #include <sys/malloc.h> 57 #include <sys/mutex.h> 58 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 64 #include <pci/pcireg.h> 65 #include <pci/pcivar.h> 66 #include <machine/clock.h> 67 68 #include <dev/pccard/pccardreg.h> 69 #include <dev/pccard/pccardvar.h> 70 #include <dev/pcic/i82365reg.h> 71 72 #include <dev/pccbb/pccbbreg.h> 73 #include <dev/pccbb/pccbbvar.h> 74 75 #include "power_if.h" 76 #include "card_if.h" 77 #include "pcib_if.h" 78 79 #if defined CBB_DEBUG 80 #define DPRINTF(x) printf x 81 #define DEVPRINTF(x) device_printf x 82 #else 83 #define DPRINTF(x) 84 #define DEVPRINTF(x) 85 #endif 86 87 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 88 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 89 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 90 pci_write_config(DEV, REG, ( \ 91 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 92 93 /* 94 * XXX all the pcic code really doesn't belong here and needs to be 95 * XXX migrated to its own file, shared with the 16-bit code 96 */ 97 #define PCIC_READ(SC,REG) \ 98 (((u_int8_t*)((SC)->sc_socketreg))[0x800+(REG)]) 99 #define PCIC_WRITE(SC,REG,val) \ 100 (((u_int8_t*)((SC)->sc_socketreg))[0x800+(REG)]) = (val) 101 #define PCIC_MASK(SC,REG,MASK) \ 102 PCIC_WRITE(SC,REG,PCIC_READ(SC,REG) MASK) 103 #define PCIC_MASK2(SC,REG,MASK,MASK2) \ 104 PCIC_WRITE(SC,REG,(PCIC_READ(SC,REG) MASK) MASK2) 105 106 struct pccbb_sclist { 107 struct pccbb_softc *sc; 108 STAILQ_ENTRY(pccbb_sclist) entries; 109 }; 110 111 static STAILQ_HEAD(, pccbb_sclist) softcs; 112 static int softcs_init = 0; 113 114 115 struct yenta_chipinfo { 116 u_int32_t yc_id; 117 const char *yc_name; 118 int yc_chiptype; 119 int yc_flags; 120 } yc_chipsets[] = { 121 /* Texas Instruments chips */ 122 {PCI_DEVICE_ID_PCIC_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X, 123 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 124 {PCI_DEVICE_ID_PCIC_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X, 125 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 126 127 {PCI_DEVICE_ID_PCIC_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX, 128 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 129 {PCI_DEVICE_ID_PCIC_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX, 130 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 131 {PCI_DEVICE_ID_PCIC_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX, 132 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 133 {PCI_DEVICE_ID_PCIC_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX, 134 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 135 {PCI_DEVICE_ID_PCIC_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI12XX, 136 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 137 {PCI_DEVICE_ID_PCIC_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI12XX, 138 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 139 {PCI_DEVICE_ID_PCIC_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI12XX, 140 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 141 {PCI_DEVICE_ID_PCIC_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX, 142 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 143 {PCI_DEVICE_ID_PCIC_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX, 144 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 145 {PCI_DEVICE_ID_PCIC_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI12XX, 146 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 147 {PCI_DEVICE_ID_PCIC_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX, 148 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 149 {PCI_DEVICE_ID_PCIC_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX, 150 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 151 {PCI_DEVICE_ID_PCIC_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX, 152 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 153 154 /* Ricoh chips */ 155 {PCI_DEVICE_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", 156 CB_RF5C46X, PCCBB_PCIC_MEM_32}, 157 {PCI_DEVICE_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", 158 CB_RF5C46X, PCCBB_PCIC_MEM_32}, 159 {PCI_DEVICE_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", 160 CB_RF5C47X, PCCBB_PCIC_MEM_32}, 161 {PCI_DEVICE_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", 162 CB_RF5C47X, PCCBB_PCIC_MEM_32}, 163 {PCI_DEVICE_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", 164 CB_RF5C47X, PCCBB_PCIC_MEM_32}, 165 166 /* Toshiba products */ 167 {PCI_DEVICE_ID_TOSHIBA_TOPIC95, "ToPIC95 PCI-CardBus Bridge", 168 CB_TOPIC95, PCCBB_PCIC_MEM_32}, 169 {PCI_DEVICE_ID_TOSHIBA_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", 170 CB_TOPIC95B, PCCBB_PCIC_MEM_32}, 171 {PCI_DEVICE_ID_TOSHIBA_TOPIC97, "ToPIC97 PCI-CardBus Bridge", 172 CB_TOPIC97, PCCBB_PCIC_MEM_32}, 173 {PCI_DEVICE_ID_TOSHIBA_TOPIC100, "ToPIC100 PCI-CardBus Bridge", 174 CB_TOPIC97, PCCBB_PCIC_MEM_32}, 175 176 /* Cirrus Logic */ 177 {PCI_DEVICE_ID_PCIC_CLPD6832, "CLPD6832 PCI-CardBus Bridge", 178 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 179 {PCI_DEVICE_ID_PCIC_CLPD6833, "CLPD6833 PCI-CardBus Bridge", 180 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 181 182 /* 02Micro */ 183 {PCI_DEVICE_ID_PCIC_OZ6832, "O2Mirco OZ6832/6833 PCI-CardBus Bridge", 184 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 185 {PCI_DEVICE_ID_PCIC_OZ6860, "O2Mirco OZ6836/6860 PCI-CardBus Bridge", 186 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 187 {PCI_DEVICE_ID_PCIC_OZ6872, "O2Mirco OZ6812/6872 PCI-CardBus Bridge", 188 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 189 190 /* sentinel */ 191 {0 /* null id */, "unknown", 192 CB_UNKNOWN, 0}, 193 }; 194 195 static int cb_chipset(u_int32_t pci_id, const char **namep, int *flagp); 196 static int pccbb_probe(device_t brdev); 197 static void pccbb_chipinit(struct pccbb_softc *sc); 198 static int pccbb_attach(device_t brdev); 199 static int pccbb_detach(device_t brdev); 200 static int pccbb_shutdown(device_t brdev); 201 static void pccbb_driver_added(device_t brdev, driver_t *driver); 202 static void pccbb_child_detached(device_t brdev, device_t child); 203 static int pccbb_card_reprobe(device_t brdev, device_t busdev); 204 static void pccbb_event_thread(void *arg); 205 static void pccbb_create_event_thread(struct pccbb_softc *sc); 206 static void pccbb_start_threads(void *arg); 207 static void pccbb_insert(struct pccbb_softc *sc); 208 static void pccbb_removal(struct pccbb_softc *sc); 209 static void pccbb_intr(void *arg); 210 static int pccbb_detect_voltage(device_t brdev); 211 static int pccbb_power(device_t brdev, int volts); 212 static void pccbb_cardbus_reset(device_t brdev); 213 static int pccbb_cardbus_power_enable_socket(device_t brdev, 214 device_t child); 215 static void pccbb_cardbus_power_disable_socket(device_t brdev, 216 device_t child); 217 static int pccbb_cardbus_io_open(device_t brdev, int win, u_int32_t start, 218 u_int32_t end); 219 static int pccbb_cardbus_mem_open(device_t brdev, int win, 220 u_int32_t start, u_int32_t end); 221 static void pccbb_cardbus_auto_open(struct pccbb_softc *sc, int type); 222 static int pccbb_cardbus_activate_resource(device_t brdev, device_t child, 223 int type, int rid, struct resource *res); 224 static int pccbb_cardbus_deactivate_resource(device_t brdev, 225 device_t child, int type, int rid, struct resource *res); 226 static struct resource *pccbb_cardbus_alloc_resource(device_t brdev, 227 device_t child, int type, int *rid, u_long start, 228 u_long end, u_long count, u_int flags); 229 static int pccbb_cardbus_release_resource(device_t brdev, device_t child, 230 int type, int rid, struct resource *res); 231 static int pccbb_pcic_power_enable_socket(device_t brdev, device_t child); 232 static void pccbb_pcic_power_disable_socket(device_t brdev, device_t child); 233 static void pccbb_pcic_wait_ready(struct pccbb_softc *sc); 234 static void pccbb_pcic_do_mem_map(struct pccbb_softc *sc, int win); 235 static int pccbb_pcic_mem_map(struct pccbb_softc *sc, int kind, 236 struct resource *res); 237 static void pccbb_pcic_mem_unmap(struct pccbb_softc *sc, int window); 238 static int pccbb_pcic_mem_findmap(struct pccbb_softc *sc, 239 struct resource *res); 240 static void pccbb_pcic_do_io_map(struct pccbb_softc *sc, int win); 241 static int pccbb_pcic_io_map(struct pccbb_softc *sc, int width, 242 struct resource *r); 243 static void pccbb_pcic_io_unmap(struct pccbb_softc *sc, int window); 244 static int pccbb_pcic_io_findmap(struct pccbb_softc *sc, 245 struct resource *res); 246 static int pccbb_pcic_activate_resource(device_t brdev, device_t child, 247 int type, int rid, struct resource *res); 248 static int pccbb_pcic_deactivate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *res); 250 static struct resource *pccbb_pcic_alloc_resource(device_t brdev, 251 device_t child, int type, int *rid, u_long start, 252 u_long end, u_long count, u_int flags); 253 static int pccbb_pcic_release_resource(device_t brdev, device_t child, 254 int type, int rid, struct resource *res); 255 static int pccbb_pcic_set_res_flags(device_t brdev, device_t child, 256 int type, int rid, u_int32_t flags); 257 static int pccbb_pcic_set_memory_offset(device_t brdev, device_t child, 258 int rid, u_int32_t cardaddr, u_int32_t *deltap); 259 static int pccbb_power_enable_socket(device_t brdev, device_t child); 260 static void pccbb_power_disable_socket(device_t brdev, device_t child); 261 static int pccbb_activate_resource(device_t brdev, device_t child, 262 int type, int rid, struct resource *r); 263 static int pccbb_deactivate_resource(device_t brdev, device_t child, 264 int type, int rid, struct resource *r); 265 static struct resource *pccbb_alloc_resource(device_t brdev, device_t child, 266 int type, int *rid, u_long start, u_long end, u_long count, 267 u_int flags); 268 static int pccbb_release_resource(device_t brdev, device_t child, 269 int type, int rid, struct resource *r); 270 static int pccbb_read_ivar(device_t brdev, device_t child, int which, 271 uintptr_t *result); 272 static int pccbb_write_ivar(device_t brdev, device_t child, int which, 273 uintptr_t value); 274 static int pccbb_maxslots(device_t brdev); 275 static u_int32_t pccbb_read_config(device_t brdev, int b, int s, int f, 276 int reg, int width); 277 static void pccbb_write_config(device_t brdev, int b, int s, int f, 278 int reg, u_int32_t val, int width); 279 280 /************************************************************************/ 281 /* Probe/Attach */ 282 /************************************************************************/ 283 284 static int 285 cb_chipset(u_int32_t pci_id, const char **namep, int *flagp) 286 { 287 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 288 struct yenta_chipinfo *ycp, *ycend; 289 ycend = yc_chipsets + loopend; 290 291 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 292 if (ycp == ycend) { 293 /* not found */ 294 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 295 } 296 if (namep != NULL) { 297 *namep = ycp->yc_name; 298 } 299 if (flagp != NULL) { 300 *flagp = ycp->yc_flags; 301 } 302 return ycp->yc_chiptype; 303 } 304 305 static int 306 pccbb_probe(device_t brdev) 307 { 308 const char *name; 309 310 if (cb_chipset(pci_get_devid(brdev), &name, NULL) == CB_UNKNOWN) 311 return ENXIO; 312 device_set_desc(brdev, name); 313 return 0; 314 } 315 316 static void 317 pccbb_chipinit(struct pccbb_softc *sc) 318 { 319 /* Set CardBus latency timer */ 320 if (pci_read_config(sc->sc_dev, PCIR_SECLAT_1, 1) < 0x20) 321 pci_write_config(sc->sc_dev, PCIR_SECLAT_1, 0x20, 1); 322 323 /* Set PCI latency timer */ 324 if (pci_read_config(sc->sc_dev, PCIR_LATTIMER, 1) < 0x20) 325 pci_write_config(sc->sc_dev, PCIR_LATTIMER, 0x20, 1); 326 327 /* Enable memory access */ 328 PCI_MASK_CONFIG(sc->sc_dev, PCIR_COMMAND, 329 | PCIM_CMD_MEMEN 330 | PCIM_CMD_PORTEN 331 | PCIM_CMD_BUSMASTEREN, 2); 332 333 /* disable Legacy IO */ 334 switch (sc->sc_chipset) { 335 case CB_RF5C46X: 336 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL, 337 & ~(PCCBBM_BRIDGECTRL_RL_3E0_EN | 338 PCCBBM_BRIDGECTRL_RL_3E2_EN), 2); 339 break; 340 default: 341 pci_write_config(sc->sc_dev, PCCBBR_LEGACY, 0x0, 4); 342 break; 343 } 344 345 /* Use PCI interrupt for interrupt routing */ 346 PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL, 347 & ~(PCCBBM_BRIDGECTRL_MASTER_ABORT | 348 PCCBBM_BRIDGECTRL_INTR_IREQ_EN), 349 | PCCBBM_BRIDGECTRL_WRITE_POST_EN, 350 2); 351 352 /* XXX this should be a function table, ala OLDCARD. */ 353 switch (sc->sc_chipset) { 354 case CB_TI113X: 355 /* 356 * The TI 1030, TI 1130 and TI 1131 all require another bit 357 * be set to enable PCI routing of interrupts, and then 358 * a bit for each of the CSC and Function interrupts we 359 * want routed. 360 */ 361 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_CBCTRL, 362 | PCCBBM_CBCTRL_113X_PCI_INTR | 363 PCCBBM_CBCTRL_113X_PCI_CSC | PCCBBM_CBCTRL_113X_PCI_IRQ_EN, 364 1); 365 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_DEVCTRL, 366 & ~(PCCBBM_DEVCTRL_INT_SERIAL | 367 PCCBBM_DEVCTRL_INT_PCI), 1); 368 PCIC_WRITE(sc, PCIC_INTR, PCIC_INTR_ENABLE); 369 PCIC_WRITE(sc, PCIC_CSC_INTR, 0); 370 break; 371 case CB_TI12XX: 372 PCIC_WRITE(sc, PCIC_INTR, PCIC_INTR_ENABLE); 373 PCIC_WRITE(sc, PCIC_CSC_INTR, 0); 374 break; 375 case CB_TOPIC95B: 376 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_TOPIC_SOCKETCTRL, 377 | PCCBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 378 PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_TOPIC_SLOTCTRL, 379 | PCCBBM_TOPIC_SLOTCTRL_SLOTON | 380 PCCBBM_TOPIC_SLOTCTRL_SLOTEN | 381 PCCBBM_TOPIC_SLOTCTRL_ID_LOCK | 382 PCCBBM_TOPIC_SLOTCTRL_CARDBUS, 383 & ~PCCBBM_TOPIC_SLOTCTRL_SWDETECT, 4); 384 break; 385 } 386 387 /* close all memory and io windows */ 388 pci_write_config(sc->sc_dev, PCCBBR_MEMBASE0, 0xffffffff, 4); 389 pci_write_config(sc->sc_dev, PCCBBR_MEMLIMIT0, 0, 4); 390 pci_write_config(sc->sc_dev, PCCBBR_MEMBASE1, 0xffffffff, 4); 391 pci_write_config(sc->sc_dev, PCCBBR_MEMLIMIT1, 0, 4); 392 pci_write_config(sc->sc_dev, PCCBBR_IOBASE0, 0xffffffff, 4); 393 pci_write_config(sc->sc_dev, PCCBBR_IOLIMIT0, 0, 4); 394 pci_write_config(sc->sc_dev, PCCBBR_IOBASE1, 0xffffffff, 4); 395 pci_write_config(sc->sc_dev, PCCBBR_IOLIMIT1, 0, 4); 396 } 397 398 static int 399 pccbb_attach(device_t brdev) 400 { 401 struct pccbb_softc *sc = (struct pccbb_softc *)device_get_softc(brdev); 402 int rid; 403 u_int32_t tmp; 404 405 if (!softcs_init) { 406 softcs_init = 1; 407 STAILQ_INIT(&softcs); 408 } 409 mtx_init(&sc->sc_mtx, device_get_nameunit(brdev), MTX_DEF); 410 sc->sc_chipset = cb_chipset(pci_get_devid(brdev), NULL, &sc->sc_flags); 411 sc->sc_dev = brdev; 412 sc->sc_cbdev = NULL; 413 sc->sc_pccarddev = NULL; 414 sc->sc_secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 415 sc->sc_subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 416 sc->memalloc = 0; 417 sc->ioalloc = 0; 418 SLIST_INIT(&sc->rl); 419 420 /* Ths PCI bus should have given me memory... right? */ 421 rid=PCCBBR_SOCKBASE; 422 sc->sc_base_res=bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 423 0,~0,1, RF_ACTIVE); 424 if (!sc->sc_base_res) { 425 /* 426 * XXX EVILE HACK BAD THING! XXX 427 * The pci bus device should do this for us. 428 * Some BIOSes doesn't assign a memory space properly. 429 * So we try to manually put one in... 430 */ 431 u_int32_t sockbase; 432 433 sockbase = pci_read_config(brdev, rid, 4); 434 if (sockbase < 0x100000 || sockbase >= 0xfffffff0) { 435 pci_write_config(brdev, rid, 0xffffffff, 4); 436 sockbase = pci_read_config(brdev, rid, 4); 437 sockbase = (sockbase & 0xfffffff0) & 438 -(sockbase & 0xfffffff0); 439 sc->sc_base_res = bus_generic_alloc_resource( 440 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 441 &rid, 0x10000000, ~0, sockbase, 442 RF_ACTIVE|rman_make_alignment_flags(sockbase)); 443 if (!sc->sc_base_res){ 444 device_printf(brdev, 445 "Could not grab register memory\n"); 446 mtx_destroy(&sc->sc_mtx); 447 return ENOMEM; 448 } 449 pci_write_config(brdev, PCCBBR_SOCKBASE, 450 rman_get_start(sc->sc_base_res), 4); 451 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 452 rman_get_start(sc->sc_base_res))); 453 } else { 454 device_printf(brdev, "Could not map register memory\n"); 455 mtx_destroy(&sc->sc_mtx); 456 return ENOMEM; 457 } 458 } 459 460 sc->sc_socketreg = 461 (struct pccbb_socketreg *)rman_get_virtual(sc->sc_base_res); 462 pccbb_chipinit(sc); 463 464 /* CSC Interrupt: Card detect interrupt on */ 465 sc->sc_socketreg->socket_mask |= PCCBB_SOCKET_MASK_CD; 466 467 /* reset interrupt */ 468 tmp = sc->sc_socketreg->socket_event; 469 sc->sc_socketreg->socket_event = tmp; 470 471 /* Map and establish the interrupt. */ 472 rid=0; 473 sc->sc_irq_res=bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 474 RF_SHAREABLE | RF_ACTIVE); 475 if (sc->sc_irq_res == NULL) { 476 printf("pccbb: Unable to map IRQ...\n"); 477 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 478 sc->sc_base_res); 479 mtx_destroy(&sc->sc_mtx); 480 return ENOMEM; 481 } 482 483 if (bus_setup_intr(brdev, sc->sc_irq_res, INTR_TYPE_BIO, pccbb_intr, sc, 484 &(sc->sc_intrhand))) { 485 device_printf(brdev, "couldn't establish interrupt"); 486 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->sc_irq_res); 487 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 488 sc->sc_base_res); 489 mtx_destroy(&sc->sc_mtx); 490 return ENOMEM; 491 } 492 493 /* attach children */ 494 sc->sc_cbdev = device_add_child(brdev, "cardbus", -1); 495 if (sc->sc_cbdev == NULL) 496 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 497 else if (device_probe_and_attach(sc->sc_cbdev) != 0) { 498 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 499 sc->sc_cbdev = NULL; 500 } 501 502 sc->sc_pccarddev = device_add_child(brdev, "pccard", -1); 503 if (sc->sc_pccarddev == NULL) 504 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 505 else if (device_probe_and_attach(sc->sc_pccarddev) != 0) { 506 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 507 sc->sc_pccarddev = NULL; 508 } 509 510 #ifndef KLD_MODULE 511 if (sc->sc_cbdev == NULL && sc->sc_pccarddev == NULL) { 512 device_printf(brdev, 513 "ERROR: Failed to attach cardbus/pccard bus!\n"); 514 bus_teardown_intr(brdev, sc->sc_irq_res, sc->sc_intrhand); 515 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->sc_irq_res); 516 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 517 sc->sc_base_res); 518 mtx_destroy(&sc->sc_mtx); 519 return ENOMEM; 520 } 521 #endif 522 523 { 524 struct pccbb_sclist *sclist; 525 sclist = malloc(sizeof(struct pccbb_sclist), M_DEVBUF, 526 M_WAITOK); 527 sclist->sc = sc; 528 STAILQ_INSERT_TAIL(&softcs, sclist, entries); 529 } 530 return 0; 531 } 532 533 static int 534 pccbb_detach(device_t brdev) 535 { 536 struct pccbb_softc *sc = device_get_softc(brdev); 537 int numdevs; 538 device_t *devlist; 539 int tmp; 540 int error; 541 542 device_get_children(brdev, &devlist, &numdevs); 543 544 error = 0; 545 for (tmp = 0; tmp < numdevs; tmp++) { 546 if (device_detach(devlist[tmp]) == 0) 547 device_delete_child(brdev, devlist[tmp]); 548 else 549 error++; 550 } 551 free(devlist, M_TEMP); 552 if (error > 0) 553 return ENXIO; 554 555 mtx_lock(&sc->sc_mtx); 556 bus_teardown_intr(brdev, sc->sc_irq_res, sc->sc_intrhand); 557 558 sc->sc_flags |= PCCBB_KTHREAD_DONE; 559 if (sc->sc_flags & PCCBB_KTHREAD_RUNNING) { 560 wakeup(sc); 561 mtx_unlock(&sc->sc_mtx); 562 DEVPRINTF((brdev, "waiting for kthread exit...")); 563 error = tsleep(sc, PWAIT, "pccbb-detach-wait", 60 * hz); 564 if (error) 565 DPRINTF(("timeout\n")); 566 else 567 DPRINTF(("done\n")); 568 } else 569 mtx_unlock(&sc->sc_mtx); 570 571 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->sc_irq_res); 572 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 573 sc->sc_base_res); 574 mtx_destroy(&sc->sc_mtx); 575 return 0; 576 } 577 578 static int 579 pccbb_shutdown(device_t brdev) 580 { 581 struct pccbb_softc *sc = (struct pccbb_softc *)device_get_softc(brdev); 582 /* properly reset everything at shutdown */ 583 584 PCI_MASK_CONFIG(brdev, PCCBBR_BRIDGECTRL, |PCCBBM_BRIDGECTRL_RESET, 2); 585 PCIC_MASK(sc, PCIC_INTR, & ~PCIC_INTR_RESET); 586 587 sc->sc_socketreg->socket_mask = 0; 588 589 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 590 591 PCIC_WRITE(sc, PCIC_ADDRWIN_ENABLE, 0); 592 pci_write_config(brdev, PCCBBR_MEMBASE0, 0, 4); 593 pci_write_config(brdev, PCCBBR_MEMLIMIT0, 0, 4); 594 pci_write_config(brdev, PCCBBR_MEMBASE1, 0, 4); 595 pci_write_config(brdev, PCCBBR_MEMLIMIT1, 0, 4); 596 pci_write_config(brdev, PCCBBR_IOBASE0, 0, 4); 597 pci_write_config(brdev, PCCBBR_IOLIMIT0, 0, 4); 598 pci_write_config(brdev, PCCBBR_IOBASE1, 0, 4); 599 pci_write_config(brdev, PCCBBR_IOLIMIT1, 0, 4); 600 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 601 return 0; 602 } 603 604 static void 605 pccbb_driver_added(device_t brdev, driver_t *driver) 606 { 607 struct pccbb_softc *sc = device_get_softc(brdev); 608 device_t *devlist; 609 int tmp; 610 int numdevs; 611 int wake; 612 u_int32_t sockstate; 613 614 DEVICE_IDENTIFY(driver, brdev); 615 device_get_children(brdev, &devlist, &numdevs); 616 wake = 0; 617 sockstate = sc->sc_socketreg->socket_state; 618 for (tmp = 0; tmp < numdevs; tmp++) { 619 if (device_get_state(devlist[tmp]) == DS_NOTPRESENT && 620 device_probe_and_attach(devlist[tmp]) == 0) { 621 if (devlist[tmp] == NULL) 622 /* NOTHING */; 623 else if (strcmp(driver->name, "cardbus") == 0) { 624 sc->sc_cbdev = devlist[tmp]; 625 if (((sockstate & PCCBB_SOCKET_STAT_CD) == 0) && 626 (sockstate & PCCBB_SOCKET_STAT_CB)) 627 wake++; 628 } else if (strcmp(driver->name, "pccard") == 0) { 629 sc->sc_pccarddev = devlist[tmp]; 630 if (((sockstate & PCCBB_SOCKET_STAT_CD) == 0) && 631 (sockstate & PCCBB_SOCKET_STAT_16BIT)) 632 wake++; 633 } else 634 device_printf(brdev, 635 "Unsupported child bus: %s\n", 636 driver->name); 637 } 638 } 639 free(devlist, M_TEMP); 640 641 if (wake > 0) { 642 if ((sc->sc_socketreg->socket_state & PCCBB_SOCKET_STAT_CD) == 643 0) { 644 mtx_lock(&sc->sc_mtx); 645 wakeup(sc); 646 mtx_unlock(&sc->sc_mtx); 647 } 648 } 649 } 650 651 static void 652 pccbb_child_detached(device_t brdev, device_t child) 653 { 654 struct pccbb_softc *sc = device_get_softc(brdev); 655 if (child == sc->sc_cbdev) 656 sc->sc_cbdev = NULL; 657 else if (child == sc->sc_pccarddev) 658 sc->sc_pccarddev = NULL; 659 else 660 device_printf(brdev, "Unknown child detached: %s %p/%p\n", 661 device_get_nameunit(child), sc->sc_cbdev, sc->sc_pccarddev); 662 } 663 664 static int 665 pccbb_card_reprobe(device_t brdev, device_t busdev) { 666 struct pccbb_softc *sc = device_get_softc(brdev); 667 int wake = 0; 668 u_int32_t sockstate; 669 670 sockstate = sc->sc_socketreg->socket_state; 671 672 if ((sockstate & PCCBB_SOCKET_STAT_CD) == 0) { 673 if (busdev == sc->sc_cbdev && 674 (sockstate & PCCBB_SOCKET_STAT_CB)) 675 wake++; 676 else if (busdev == sc->sc_pccarddev && 677 (sockstate & PCCBB_SOCKET_STAT_16BIT)) 678 wake++; 679 680 if (wake > 0) { 681 mtx_lock(&sc->sc_mtx); 682 wakeup(sc); 683 mtx_unlock(&sc->sc_mtx); 684 return 0; 685 } 686 return EBUSY; 687 } 688 return ENOENT; 689 } 690 691 /************************************************************************/ 692 /* Kthreads */ 693 /************************************************************************/ 694 695 static void 696 pccbb_event_thread(void *arg) 697 { 698 struct pccbb_softc *sc = arg; 699 u_int32_t status; 700 701 mtx_lock(&Giant); 702 for(;;) { 703 if (!(sc->sc_flags & PCCBB_KTHREAD_RUNNING)) 704 sc->sc_flags |= PCCBB_KTHREAD_RUNNING; 705 else { 706 tsleep (sc, PWAIT, "pccbbev", 0); 707 /* 708 * Delay 1 second, make sure the user is done with 709 * whatever he is doing. We tsleep on sc->sc_flags, 710 * which should never be woken up. 711 * 712 * XXX Note: This can cause problems on card 713 * removal. See OLDCARD's ISR for how you may 714 * have to deal with the debouncing problem. The 715 * crux of the issue is interrupts delivered to 716 * the card after eject are unstable. 717 */ 718 tsleep (&sc->sc_flags, PWAIT, "pccbbev", 1*hz); 719 } 720 mtx_lock(&sc->sc_mtx); 721 if (sc->sc_flags & PCCBB_KTHREAD_DONE) 722 break; 723 724 status = sc->sc_socketreg->socket_state; 725 if ((status & PCCBB_SOCKET_STAT_CD) == 0) { 726 pccbb_insert(sc); 727 } else { 728 pccbb_removal(sc); 729 } 730 mtx_unlock(&sc->sc_mtx); 731 } 732 mtx_unlock(&sc->sc_mtx); 733 sc->sc_flags &= ~PCCBB_KTHREAD_RUNNING; 734 wakeup(sc); 735 kthread_exit(0); 736 } 737 738 static void 739 pccbb_create_event_thread(struct pccbb_softc *sc) 740 { 741 if (kthread_create(pccbb_event_thread, sc, &sc->event_thread, 742 0, "%s%d", device_get_name(sc->sc_dev), 743 device_get_unit(sc->sc_dev))) { 744 device_printf (sc->sc_dev, "unable to create event thread.\n"); 745 panic ("pccbb_create_event_thread"); 746 } 747 } 748 749 static void 750 pccbb_start_threads(void *arg) 751 { 752 struct pccbb_sclist *sclist; 753 754 STAILQ_FOREACH(sclist, &softcs, entries) { 755 pccbb_create_event_thread(sclist->sc); 756 } 757 } 758 759 /************************************************************************/ 760 /* Insert/removal */ 761 /************************************************************************/ 762 763 static void 764 pccbb_insert(struct pccbb_softc *sc) 765 { 766 u_int32_t sockevent, sockstate; 767 int timeout = 30; 768 769 do { 770 sockevent = sc->sc_socketreg->socket_event; 771 sockstate = sc->sc_socketreg->socket_state; 772 } while (sockstate & PCCBB_SOCKET_STAT_CD && --timeout > 0); 773 774 if (timeout < 0) { 775 device_printf (sc->sc_dev, "insert timeout"); 776 return; 777 } 778 779 DEVPRINTF((sc->sc_dev, "card inserted: event=0x%08x, state=%08x\n", 780 sockevent, sockstate)); 781 782 if (sockstate & PCCBB_SOCKET_STAT_16BIT && sc->sc_pccarddev != NULL) { 783 sc->sc_flags |= PCCBB_16BIT_CARD; 784 if (CARD_ATTACH_CARD(sc->sc_pccarddev) != 0) 785 device_printf(sc->sc_dev, "card activation failed\n"); 786 } else if (sockstate & PCCBB_SOCKET_STAT_CB && sc->sc_cbdev != NULL) { 787 sc->sc_flags &= ~PCCBB_16BIT_CARD; 788 if (CARD_ATTACH_CARD(sc->sc_cbdev) != 0) 789 device_printf(sc->sc_dev, "card activation failed\n"); 790 } else { 791 device_printf (sc->sc_dev, "Unsupported card type detected\n"); 792 } 793 } 794 795 static void 796 pccbb_removal(struct pccbb_softc *sc) 797 { 798 struct pccbb_reslist *rle; 799 800 if (sc->sc_flags & PCCBB_16BIT_CARD && sc->sc_pccarddev != NULL) 801 CARD_DETACH_CARD(sc->sc_pccarddev, DETACH_FORCE); 802 else if ((!(sc->sc_flags & PCCBB_16BIT_CARD)) && sc->sc_cbdev != NULL) 803 CARD_DETACH_CARD(sc->sc_cbdev, DETACH_FORCE); 804 805 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 806 device_printf(sc->sc_dev, "Danger Will Robinson: Resource " 807 "left allocated! This is a bug... " 808 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 809 rman_get_start(rle->res)); 810 SLIST_REMOVE_HEAD(&sc->rl, link); 811 free(rle, M_DEVBUF); 812 } 813 } 814 815 /************************************************************************/ 816 /* Interrupt Handler */ 817 /************************************************************************/ 818 819 static void 820 pccbb_intr(void *arg) 821 { 822 struct pccbb_softc *sc = arg; 823 u_int32_t sockevent; 824 825 if (!(sockevent = sc->sc_socketreg->socket_event)) { 826 /* not for me. */ 827 return; 828 } 829 830 /* reset bit */ 831 sc->sc_socketreg->socket_event = sockevent | 0x01; 832 833 if (sockevent & PCCBB_SOCKET_EVENT_CD) { 834 mtx_lock(&sc->sc_mtx); 835 wakeup(sc); 836 mtx_unlock(&sc->sc_mtx); 837 } else { 838 if (sockevent & PCCBB_SOCKET_EVENT_CSTS) { 839 DPRINTF((" cstsevent occures, 0x%08x\n", 840 sc->sc_socketreg->socket_state)); 841 } 842 if (sockevent & PCCBB_SOCKET_EVENT_POWER) { 843 DPRINTF((" pwrevent occures, 0x%08x\n", 844 sc->sc_socketreg->socket_state)); 845 } 846 } 847 848 return; 849 } 850 851 /************************************************************************/ 852 /* Generic Power functions */ 853 /************************************************************************/ 854 855 static int 856 pccbb_detect_voltage(device_t brdev) 857 { 858 struct pccbb_softc *sc = device_get_softc(brdev); 859 u_int32_t psr; 860 int vol = CARD_UKN_CARD; 861 862 psr = sc->sc_socketreg->socket_state; 863 864 if (psr & PCCBB_SOCKET_STAT_5VCARD) { 865 vol |= CARD_5V_CARD; 866 } 867 if (psr & PCCBB_SOCKET_STAT_3VCARD) { 868 vol |= CARD_3V_CARD; 869 } 870 if (psr & PCCBB_SOCKET_STAT_XVCARD) { 871 vol |= CARD_XV_CARD; 872 } 873 if (psr & PCCBB_SOCKET_STAT_YVCARD) { 874 vol |= CARD_YV_CARD; 875 } 876 877 return vol; 878 } 879 880 static int 881 pccbb_power(device_t brdev, int volts) 882 { 883 u_int32_t status, sock_ctrl; 884 struct pccbb_softc *sc = device_get_softc(brdev); 885 886 DEVPRINTF((sc->sc_dev, "pccbb_power: %s and %s [%x]\n", 887 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 888 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 889 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 890 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 891 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 892 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 893 "VCC-UNKNOWN", 894 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 895 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V" : 896 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC" : 897 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 898 "VPP-UNKNOWN", 899 volts)); 900 901 status = sc->sc_socketreg->socket_state; 902 sock_ctrl = sc->sc_socketreg->socket_control; 903 904 switch (volts & CARD_VCCMASK) { 905 case CARD_VCC_UC: 906 break; 907 case CARD_VCC_5V: 908 if (PCCBB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 909 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VCCMASK; 910 sock_ctrl |= PCCBB_SOCKET_CTRL_VCC_5V; 911 } else { 912 device_printf(sc->sc_dev, 913 "BAD voltage request: no 5 V card\n"); 914 } 915 break; 916 case CARD_VCC_3V: 917 if (PCCBB_SOCKET_STAT_3VCARD & status) { 918 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VCCMASK; 919 sock_ctrl |= PCCBB_SOCKET_CTRL_VCC_3V; 920 } else { 921 device_printf(sc->sc_dev, 922 "BAD voltage request: no 3.3 V card\n"); 923 } 924 break; 925 case CARD_VCC_0V: 926 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VCCMASK; 927 break; 928 default: 929 return 0; /* power NEVER changed */ 930 break; 931 } 932 933 switch (volts & CARD_VPPMASK) { 934 case CARD_VPP_UC: 935 break; 936 case CARD_VPP_0V: 937 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VPPMASK; 938 break; 939 case CARD_VPP_VCC: 940 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VPPMASK; 941 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 942 break; 943 case CARD_VPP_12V: 944 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VPPMASK; 945 sock_ctrl |= PCCBB_SOCKET_CTRL_VPP_12V; 946 break; 947 } 948 949 if (sc->sc_socketreg->socket_control == sock_ctrl) 950 return 1; /* no change necessary */ 951 952 sc->sc_socketreg->socket_control = sock_ctrl; 953 status = sc->sc_socketreg->socket_state; 954 955 /* 956 * XXX This busy wait is bogus. We should wait for a power 957 * interrupt and then whine if the status is bad. If we're 958 * worried about the card not coming up, then we should also 959 * schedule a timeout which we can cacel in the power interrupt. 960 */ 961 962 { 963 int timeout = 20; 964 u_int32_t sockevent; 965 do { 966 DELAY(20*1000); 967 sockevent = sc->sc_socketreg->socket_event; 968 } while (!(sockevent & PCCBB_SOCKET_EVENT_POWER) && 969 --timeout > 0); 970 /* reset event status */ 971 /* XXX should only reset EVENT_POWER */ 972 sc->sc_socketreg->socket_event = sockevent; 973 if (timeout < 0) { 974 printf ("VCC supply failed.\n"); 975 return 0; 976 } 977 } 978 /* XXX 979 * delay 400 ms: thgough the standard defines that the Vcc set-up time 980 * is 20 ms, some PC-Card bridge requires longer duration. 981 * XXX Note: We should check the stutus AFTER the delay to give time 982 * for things to stabilize. 983 */ 984 DELAY(400*1000); 985 986 if (status & PCCBB_SOCKET_STAT_BADVCC) { 987 device_printf(sc->sc_dev, 988 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 989 sock_ctrl ,status); 990 printf("pccbb_power: %s and %s [%x]\n", 991 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 992 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 993 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 994 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 995 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 996 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 997 "VCC-UNKNOWN", 998 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 999 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V": 1000 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC": 1001 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1002 "VPP-UNKNOWN", 1003 volts); 1004 return 0; 1005 } 1006 return 1; /* power changed correctly */ 1007 } 1008 1009 /************************************************************************/ 1010 /* Cardbus power functions */ 1011 /************************************************************************/ 1012 1013 static void 1014 pccbb_cardbus_reset(device_t brdev) 1015 { 1016 struct pccbb_softc *sc = device_get_softc(brdev); 1017 int delay_us; 1018 1019 delay_us = sc->sc_chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1020 1021 PCI_MASK_CONFIG(brdev, PCCBBR_BRIDGECTRL, |PCCBBM_BRIDGECTRL_RESET, 2); 1022 1023 DELAY(delay_us); 1024 1025 /* If a card exists, unreset it! */ 1026 if ((sc->sc_socketreg->socket_state & PCCBB_SOCKET_STAT_CD) == 0) { 1027 PCI_MASK_CONFIG(brdev, PCCBBR_BRIDGECTRL, 1028 &~PCCBBM_BRIDGECTRL_RESET, 2); 1029 DELAY(delay_us); 1030 } 1031 } 1032 1033 static int 1034 pccbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1035 { 1036 struct pccbb_softc *sc = device_get_softc(brdev); 1037 int voltage; 1038 1039 if ((sc->sc_socketreg->socket_state & PCCBB_SOCKET_STAT_CD) == 1040 PCCBB_SOCKET_STAT_CD) 1041 return ENODEV; 1042 1043 voltage = pccbb_detect_voltage(brdev); 1044 1045 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1046 if (voltage & CARD_5V_CARD) 1047 pccbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1048 else if (voltage & CARD_3V_CARD) 1049 pccbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1050 else { 1051 device_printf(brdev, "Unknown card voltage\n"); 1052 return ENXIO; 1053 } 1054 1055 pccbb_cardbus_reset(brdev); 1056 return 0; 1057 } 1058 1059 static void 1060 pccbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1061 { 1062 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1063 pccbb_cardbus_reset(brdev); 1064 } 1065 1066 /************************************************************************/ 1067 /* Cardbus Resource */ 1068 /************************************************************************/ 1069 1070 static int 1071 pccbb_cardbus_io_open(device_t brdev, int win, u_int32_t start, u_int32_t end) 1072 { 1073 int basereg; 1074 int limitreg; 1075 1076 if ((win < 0) || (win > 1)) { 1077 DEVPRINTF((brdev, 1078 "pccbb_cardbus_io_open: window out of range %d\n", win)); 1079 return EINVAL; 1080 } 1081 1082 basereg = win*8 + PCCBBR_IOBASE0; 1083 limitreg = win*8 + PCCBBR_IOLIMIT0; 1084 1085 pci_write_config(brdev, basereg, start, 4); 1086 pci_write_config(brdev, limitreg, end, 4); 1087 return 0; 1088 } 1089 1090 static int 1091 pccbb_cardbus_mem_open(device_t brdev, int win, u_int32_t start, u_int32_t end) 1092 { 1093 int basereg; 1094 int limitreg; 1095 1096 if ((win < 0) || (win > 1)) { 1097 DEVPRINTF((brdev, 1098 "pccbb_cardbus_mem_open: window out of range %d\n", win)); 1099 return EINVAL; 1100 } 1101 1102 basereg = win*8 + PCCBBR_MEMBASE0; 1103 limitreg = win*8 + PCCBBR_MEMLIMIT0; 1104 1105 pci_write_config(brdev, basereg, start, 4); 1106 pci_write_config(brdev, limitreg, end, 4); 1107 return 0; 1108 } 1109 1110 static void 1111 pccbb_cardbus_auto_open(struct pccbb_softc *sc, int type) 1112 { 1113 u_int32_t starts[2]; 1114 u_int32_t ends[2]; 1115 struct pccbb_reslist *rle; 1116 int align; 1117 int prefetchable[2]; 1118 1119 starts[0] = starts[1] = 0xffffffff; 1120 ends[0] = ends[1] = 0; 1121 1122 if (type == SYS_RES_MEMORY) 1123 align = PCCBB_MEMALIGN; 1124 else if (type == SYS_RES_IOPORT) 1125 align = PCCBB_IOALIGN; 1126 else 1127 align = 1; 1128 1129 SLIST_FOREACH(rle, &sc->rl, link) { 1130 if (rle->type != type) 1131 ; 1132 else if (rle->res == NULL) { 1133 device_printf(sc->sc_dev, "WARNING: Resource not reserved? " 1134 "(type=%d, addr=%lx)\n", 1135 rle->type, rman_get_start(rle->res)); 1136 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1137 } else if (starts[0] == 0xffffffff) { 1138 starts[0] = rman_get_start(rle->res); 1139 ends[0] = rman_get_end(rle->res); 1140 prefetchable[0] = 1141 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1142 } else if (rman_get_end(rle->res) > ends[0] && 1143 rman_get_start(rle->res) - ends[0] < 1144 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1145 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1146 ends[0] = rman_get_end(rle->res); 1147 } else if (rman_get_start(rle->res) < starts[0] && 1148 starts[0] - rman_get_end(rle->res) < 1149 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1150 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1151 starts[0] = rman_get_start(rle->res); 1152 } else if (starts[1] == 0xffffffff) { 1153 starts[1] = rman_get_start(rle->res); 1154 ends[1] = rman_get_end(rle->res); 1155 prefetchable[1] = 1156 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1157 } else if (rman_get_end(rle->res) > ends[1] && 1158 rman_get_start(rle->res) - ends[1] < 1159 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1160 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1161 ends[1] = rman_get_end(rle->res); 1162 } else if (rman_get_start(rle->res) < starts[1] && 1163 starts[1] - rman_get_end(rle->res) < 1164 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1165 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1166 starts[1] = rman_get_start(rle->res); 1167 } else { 1168 u_int32_t diffs[2]; 1169 int win; 1170 1171 diffs[0] = diffs[1] = 0xffffffff; 1172 if (rman_get_start(rle->res) > ends[0]) 1173 diffs[0] = rman_get_start(rle->res) - ends[0]; 1174 else if (rman_get_end(rle->res) < starts[0]) 1175 diffs[0] = starts[0] - rman_get_end(rle->res); 1176 if (rman_get_start(rle->res) > ends[1]) 1177 diffs[1] = rman_get_start(rle->res) - ends[1]; 1178 else if (rman_get_end(rle->res) < starts[1]) 1179 diffs[1] = starts[1] - rman_get_end(rle->res); 1180 1181 win = (diffs[0] <= diffs[1])?0:1; 1182 if (rman_get_start(rle->res) > ends[win]) 1183 ends[win] = rman_get_end(rle->res); 1184 else if (rman_get_end(rle->res) < starts[win]) 1185 starts[win] = rman_get_start(rle->res); 1186 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1187 prefetchable[win] = 0; 1188 } 1189 1190 if (starts[0] != 0xffffffff) 1191 starts[0] -= starts[0] % align; 1192 if (starts[1] != 0xffffffff) 1193 starts[1] -= starts[1] % align; 1194 if (ends[0] % align != 0) 1195 ends[0] += align - ends[0]%align - 1; 1196 if (ends[1] % align != 0) 1197 ends[1] += align - ends[1]%align - 1; 1198 } 1199 1200 if (type == SYS_RES_MEMORY) { 1201 u_int32_t reg; 1202 1203 pccbb_cardbus_mem_open(sc->sc_dev, 0, starts[0], ends[0]); 1204 pccbb_cardbus_mem_open(sc->sc_dev, 1, starts[1], ends[1]); 1205 reg = pci_read_config(sc->sc_dev, PCCBBR_BRIDGECTRL, 2); 1206 reg &= ~(PCCBBM_BRIDGECTRL_PREFETCH_0| 1207 PCCBBM_BRIDGECTRL_PREFETCH_1); 1208 reg |= (prefetchable[0]?PCCBBM_BRIDGECTRL_PREFETCH_0:0)| 1209 (prefetchable[1]?PCCBBM_BRIDGECTRL_PREFETCH_1:0); 1210 pci_write_config(sc->sc_dev, PCCBBR_BRIDGECTRL, reg, 2); 1211 } else if (type == SYS_RES_IOPORT) { 1212 pccbb_cardbus_io_open(sc->sc_dev, 0, starts[0], ends[0]); 1213 pccbb_cardbus_io_open(sc->sc_dev, 1, starts[1], ends[1]); 1214 } 1215 } 1216 1217 static int 1218 pccbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1219 int rid, struct resource *res) 1220 { 1221 int ret; 1222 1223 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1224 type, rid, res); 1225 if (ret != 0) return ret; 1226 pccbb_cardbus_auto_open(device_get_softc(brdev), type); 1227 return 0; 1228 } 1229 1230 static int 1231 pccbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1232 int rid, struct resource *res) 1233 { 1234 int ret; 1235 1236 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1237 type, rid, res); 1238 if (ret != 0) return ret; 1239 pccbb_cardbus_auto_open(device_get_softc(brdev), type); 1240 return 0; 1241 } 1242 1243 static struct resource * 1244 pccbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1245 u_long start, u_long end, u_long count, u_int flags) 1246 { 1247 struct pccbb_softc *sc = device_get_softc(brdev); 1248 struct pccbb_reslist *rle; 1249 int tmp; 1250 struct resource *res; 1251 1252 switch (type) { 1253 case SYS_RES_IRQ: 1254 tmp = rman_get_start(sc->sc_irq_res); 1255 if (start > tmp || end < tmp || count != 1) { 1256 device_printf(child, "requested interrupt %ld-%ld," 1257 "count = %ld not supported by pccbb\n", 1258 start, end, count); 1259 return NULL; 1260 } 1261 start = end = tmp; 1262 break; 1263 case SYS_RES_IOPORT: 1264 if (start <= 0x1000) 1265 start = 0x1000; 1266 if (end < start) 1267 end = start; 1268 break; 1269 case SYS_RES_MEMORY: 1270 if (start <= 0x44000000) 1271 start = 0x44000000; 1272 if (end < start) 1273 end = start; 1274 break; 1275 } 1276 1277 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1278 start, end, count, flags & ~RF_ACTIVE); 1279 if (res == NULL) { 1280 printf("pccbb alloc res fail\n"); 1281 return NULL; 1282 } 1283 1284 /* 1285 * Need to record allocated resource so we can iterate through 1286 * it later. 1287 */ 1288 rle = malloc(sizeof(struct pccbb_reslist), M_DEVBUF, M_NOWAIT); 1289 if (!res) 1290 panic("pccbb_cardbus_alloc_resource: can't record entry!"); 1291 rle->res = res; 1292 rle->type = type; 1293 rle->rid = *rid; 1294 rle->cardaddr = 0; 1295 SLIST_INSERT_HEAD(&sc->rl, rle, link); 1296 1297 if (flags & RF_ACTIVE) 1298 if (bus_activate_resource(child, type, *rid, res) != 0) { 1299 bus_release_resource(child, type, *rid, res); 1300 return NULL; 1301 } 1302 1303 return res; 1304 } 1305 1306 static int 1307 pccbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1308 int rid, struct resource *res) 1309 { 1310 struct pccbb_softc *sc = device_get_softc(brdev); 1311 struct pccbb_reslist *rle; 1312 1313 if (rman_get_flags(res) & RF_ACTIVE) { 1314 int error; 1315 error = bus_deactivate_resource(child, type, rid, res); 1316 if (error != 0) 1317 return error; 1318 } 1319 1320 SLIST_FOREACH(rle, &sc->rl, link) { 1321 if (rle->res == res) { 1322 SLIST_REMOVE(&sc->rl, rle, pccbb_reslist, link); 1323 free(rle, M_DEVBUF); 1324 break; 1325 } 1326 } 1327 1328 return BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1329 type, rid, res); 1330 } 1331 1332 /************************************************************************/ 1333 /* PC Card Power Functions */ 1334 /************************************************************************/ 1335 1336 static int 1337 pccbb_pcic_power_enable_socket(device_t brdev, device_t child) 1338 { 1339 struct pccbb_softc *sc = device_get_softc(brdev); 1340 1341 DPRINTF(("pccbb_pcic_socket_enable:\n")); 1342 1343 /* power down/up the socket to reset */ 1344 { 1345 int voltage = pccbb_detect_voltage(brdev); 1346 1347 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1348 if (voltage & CARD_5V_CARD) 1349 pccbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1350 else if (voltage & CARD_3V_CARD) 1351 pccbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1352 else { 1353 device_printf(brdev, "Unknown card voltage\n"); 1354 return ENXIO; 1355 } 1356 } 1357 1358 /* enable socket i/o */ 1359 PCIC_MASK(sc, PCIC_PWRCTL, | PCIC_PWRCTL_OE); 1360 1361 PCIC_WRITE(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1362 /* hold reset for 30ms */ 1363 DELAY(30*1000); 1364 /* clear the reset flag */ 1365 PCIC_MASK(sc, PCIC_INTR, | PCIC_INTR_RESET); 1366 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1367 DELAY(20*1000); 1368 1369 pccbb_pcic_wait_ready(sc); 1370 1371 /* disable all address windows */ 1372 PCIC_WRITE(sc, PCIC_ADDRWIN_ENABLE, 0); 1373 1374 { 1375 int cardtype; 1376 CARD_GET_TYPE(child, &cardtype); 1377 PCIC_MASK(sc, PCIC_INTR, | ((cardtype == PCCARD_IFTYPE_IO) ? 1378 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM)); 1379 DEVPRINTF((sc->sc_dev, "card type is %s\n", 1380 (cardtype == PCCARD_IFTYPE_IO) ? "io" : "mem")); 1381 } 1382 1383 /* reinstall all the memory and io mappings */ 1384 { 1385 int win; 1386 1387 for (win = 0; win < PCIC_MEM_WINS; ++win) { 1388 if (sc->memalloc & (1 << win)) { 1389 pccbb_pcic_do_mem_map(sc, win); 1390 } 1391 } 1392 for (win = 0; win < PCIC_IO_WINS; ++win) { 1393 if (sc->ioalloc & (1 << win)) { 1394 pccbb_pcic_do_io_map(sc, win); 1395 } 1396 } 1397 } 1398 return 0; 1399 } 1400 1401 static void 1402 pccbb_pcic_power_disable_socket(device_t brdev, device_t child) 1403 { 1404 struct pccbb_softc *sc = device_get_softc(brdev); 1405 1406 DPRINTF(("pccbb_pcic_socket_disable\n")); 1407 1408 /* reset signal asserting... */ 1409 PCIC_MASK(sc, PCIC_INTR, & ~PCIC_INTR_RESET); 1410 DELAY(2*1000); 1411 1412 /* power down the socket */ 1413 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1414 PCIC_MASK(sc, PCIC_PWRCTL, &~PCIC_PWRCTL_OE); 1415 1416 /* wait 300ms until power fails (Tpf). */ 1417 DELAY(300 * 1000); 1418 } 1419 1420 /************************************************************************/ 1421 /* PC Card Resource Functions */ 1422 /************************************************************************/ 1423 1424 static void 1425 pccbb_pcic_wait_ready(struct pccbb_softc *sc) 1426 { 1427 int i; 1428 DEVPRINTF((sc->sc_dev, "pccbb_pcic_wait_ready: status 0x%02x\n", 1429 PCIC_READ(sc, PCIC_IF_STATUS))); 1430 for (i = 0; i < 10000; i++) { 1431 if (PCIC_READ(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1432 return; 1433 } 1434 DELAY(500); 1435 } 1436 device_printf(sc->sc_dev, "ready never happened, status = %02x\n", 1437 PCIC_READ(sc, PCIC_IF_STATUS)); 1438 } 1439 1440 #define PCIC_MEMINFO(NUM) { \ 1441 PCIC_SYSMEM_ADDR ## NUM ## _START_LSB, \ 1442 PCIC_SYSMEM_ADDR ## NUM ## _START_MSB, \ 1443 PCIC_SYSMEM_ADDR ## NUM ## _STOP_LSB, \ 1444 PCIC_SYSMEM_ADDR ## NUM ## _STOP_MSB, \ 1445 PCIC_SYSMEM_ADDR ## NUM ## _WIN, \ 1446 PCIC_CARDMEM_ADDR ## NUM ## _LSB, \ 1447 PCIC_CARDMEM_ADDR ## NUM ## _MSB, \ 1448 PCIC_ADDRWIN_ENABLE_MEM ## NUM ##, \ 1449 } 1450 1451 static struct mem_map_index_st { 1452 int sysmem_start_lsb; 1453 int sysmem_start_msb; 1454 int sysmem_stop_lsb; 1455 int sysmem_stop_msb; 1456 int sysmem_win; 1457 int cardmem_lsb; 1458 int cardmem_msb; 1459 int memenable; 1460 } mem_map_index[] = { 1461 PCIC_MEMINFO(0), 1462 PCIC_MEMINFO(1), 1463 PCIC_MEMINFO(2), 1464 PCIC_MEMINFO(3), 1465 PCIC_MEMINFO(4), 1466 }; 1467 #undef PCIC_MEMINFO 1468 1469 static void 1470 pccbb_pcic_do_mem_map(struct pccbb_softc *sc, int win) 1471 { 1472 PCIC_WRITE(sc, mem_map_index[win].sysmem_start_lsb, 1473 (sc->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1474 PCIC_WRITE(sc, mem_map_index[win].sysmem_start_msb, 1475 ((sc->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1476 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 0x80); 1477 1478 PCIC_WRITE(sc, mem_map_index[win].sysmem_stop_lsb, 1479 ((sc->mem[win].addr + sc->mem[win].realsize - 1) >> 1480 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1481 PCIC_WRITE(sc, mem_map_index[win].sysmem_stop_msb, 1482 (((sc->mem[win].addr + sc->mem[win].realsize - 1) >> 1483 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1484 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 1485 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 1486 1487 PCIC_WRITE(sc, mem_map_index[win].sysmem_win, 1488 (sc->mem[win].addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff); 1489 1490 PCIC_WRITE(sc, mem_map_index[win].cardmem_lsb, 1491 (sc->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 1492 PCIC_WRITE(sc, mem_map_index[win].cardmem_msb, 1493 ((sc->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 1494 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 1495 ((sc->mem[win].kind == PCCARD_MEM_ATTR) ? 1496 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 1497 1498 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, | PCIC_ADDRWIN_ENABLE_MEMCS16 | 1499 mem_map_index[win].memenable); 1500 1501 DELAY(100); 1502 1503 #ifdef CBB_DEBUG 1504 { 1505 int r1, r2, r3, r4, r5, r6, r7; 1506 r1 = PCIC_READ(sc, mem_map_index[win].sysmem_start_msb); 1507 r2 = PCIC_READ(sc, mem_map_index[win].sysmem_start_lsb); 1508 r3 = PCIC_READ(sc, mem_map_index[win].sysmem_stop_msb); 1509 r4 = PCIC_READ(sc, mem_map_index[win].sysmem_stop_lsb); 1510 r5 = PCIC_READ(sc, mem_map_index[win].cardmem_msb); 1511 r6 = PCIC_READ(sc, mem_map_index[win].cardmem_lsb); 1512 r7 = PCIC_READ(sc, mem_map_index[win].sysmem_win); 1513 DPRINTF(("pccbb_pcic_do_mem_map window %d: %02x%02x %02x%02x " 1514 "%02x%02x %02x (%08x+%08x.%08x*%08lx)\n", 1515 win, r1, r2, r3, r4, r5, r6, r7, 1516 sc->mem[win].addr, sc->mem[win].size, sc->mem[win].realsize, 1517 sc->mem[win].offset)); 1518 } 1519 #endif 1520 } 1521 1522 static int 1523 pccbb_pcic_mem_map(struct pccbb_softc *sc, int kind, struct resource *res) 1524 { 1525 int win; 1526 struct pccbb_reslist *rle; 1527 bus_addr_t card_addr; 1528 1529 for (win = 0; win < PCIC_MEM_WINS; win++) { 1530 if ((sc->memalloc & (1 << win)) == 0) { 1531 sc->memalloc |= (1 << win); 1532 break; 1533 } 1534 } 1535 if (win >= PCIC_MEM_WINS) 1536 return (1); 1537 1538 SLIST_FOREACH(rle, &sc->rl, link) { 1539 if (rle->res == res) 1540 break; 1541 } 1542 if (!rle) { 1543 device_printf(sc->sc_dev, 1544 "pcic_map_mem: Memory resource not found\n"); 1545 return ENXIO; 1546 } 1547 card_addr = rle->cardaddr - rle->cardaddr % PCIC_MEM_PAGESIZE; 1548 sc->mem[win].memt = rman_get_bustag(res); 1549 sc->mem[win].memh = rman_get_bushandle(res); 1550 sc->mem[win].addr = rman_get_start(res); 1551 sc->mem[win].size = rman_get_end(res) - sc->mem[win].addr + 1; 1552 sc->mem[win].realsize = sc->mem[win].size + PCIC_MEM_PAGESIZE - 1; 1553 sc->mem[win].realsize = sc->mem[win].realsize - 1554 (sc->mem[win].realsize % PCIC_MEM_PAGESIZE); 1555 sc->mem[win].offset = ((long)card_addr) - 1556 ((long)(sc->mem[win].addr)); 1557 sc->mem[win].kind = kind; 1558 1559 DPRINTF(("pccbb_pcic_mem_map window %d bus %x+%x+%lx card addr %x\n", 1560 win, sc->mem[win].addr, sc->mem[win].size, 1561 sc->mem[win].offset, card_addr)); 1562 1563 pccbb_pcic_do_mem_map(sc, win); 1564 1565 return (0); 1566 } 1567 1568 static void 1569 pccbb_pcic_mem_unmap(struct pccbb_softc *sc, int window) 1570 { 1571 if (window >= PCIC_MEM_WINS) 1572 panic("pccbb_pcic_mem_unmap: window out of range"); 1573 1574 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, & ~mem_map_index[window].memenable); 1575 sc->memalloc &= ~(1 << window); 1576 } 1577 1578 static int 1579 pccbb_pcic_mem_findmap(struct pccbb_softc *sc, struct resource *res) 1580 { 1581 int win; 1582 1583 for (win = 0; win < PCIC_MEM_WINS; win++) { 1584 if (sc->mem[win].memt == rman_get_bustag(res) && 1585 sc->mem[win].addr == rman_get_start(res) && 1586 sc->mem[win].size == rman_get_size(res)) 1587 return win; 1588 } 1589 device_printf(sc->sc_dev, "Memory map not found!\n"); 1590 return -1; 1591 } 1592 1593 #define PCIC_IOINFO(NUM) { \ 1594 PCIC_IOADDR ## NUM ## _START_LSB, \ 1595 PCIC_IOADDR ## NUM ## _START_MSB, \ 1596 PCIC_IOADDR ## NUM ## _STOP_LSB, \ 1597 PCIC_IOADDR ## NUM ## _STOP_MSB, \ 1598 PCIC_ADDRWIN_ENABLE_IO ## NUM ##, \ 1599 PCIC_IOCTL_IO ## NUM ## _WAITSTATE \ 1600 | PCIC_IOCTL_IO ## NUM ## _ZEROWAIT \ 1601 | PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_MASK \ 1602 | PCIC_IOCTL_IO ## NUM ## _DATASIZE_MASK, \ 1603 { \ 1604 PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_CARD, \ 1605 PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_DATASIZE \ 1606 | PCIC_IOCTL_IO ## NUM ## _DATASIZE_8BIT, \ 1607 PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_DATASIZE \ 1608 | PCIC_IOCTL_IO ## NUM ## _DATASIZE_16BIT, \ 1609 } \ 1610 } 1611 1612 static struct io_map_index_st { 1613 int start_lsb; 1614 int start_msb; 1615 int stop_lsb; 1616 int stop_msb; 1617 int ioenable; 1618 int ioctlmask; 1619 int ioctlbits[3]; /* indexed by PCCARD_WIDTH_* */ 1620 } io_map_index[] = { 1621 PCIC_IOINFO(0), 1622 PCIC_IOINFO(1), 1623 }; 1624 #undef PCIC_IOINFO 1625 1626 static void 1627 pccbb_pcic_do_io_map(struct pccbb_softc *sc, int win) 1628 { 1629 PCIC_WRITE(sc, io_map_index[win].start_lsb, sc->io[win].addr & 0xff); 1630 PCIC_WRITE(sc, io_map_index[win].start_msb, 1631 (sc->io[win].addr >> 8) & 0xff); 1632 1633 PCIC_WRITE(sc, io_map_index[win].stop_lsb, 1634 (sc->io[win].addr + sc->io[win].size - 1) & 0xff); 1635 PCIC_WRITE(sc, io_map_index[win].stop_msb, 1636 ((sc->io[win].addr + sc->io[win].size - 1) >> 8) & 0xff); 1637 1638 PCIC_MASK2(sc, PCIC_IOCTL, 1639 & ~io_map_index[win].ioctlmask, 1640 | io_map_index[win].ioctlbits[sc->io[win].width]); 1641 1642 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, | io_map_index[win].ioenable); 1643 #ifdef CBB_DEBUG 1644 { 1645 int r1, r2, r3, r4; 1646 r1 = PCIC_READ(sc, io_map_index[win].start_msb); 1647 r2 = PCIC_READ(sc, io_map_index[win].start_lsb); 1648 r3 = PCIC_READ(sc, io_map_index[win].stop_msb); 1649 r4 = PCIC_READ(sc, io_map_index[win].stop_lsb); 1650 DPRINTF(("pccbb_pcic_do_io_map window %d: %02x%02x %02x%02x " 1651 "(%08x+%08x)\n", win, r1, r2, r3, r4, 1652 sc->io[win].addr, sc->io[win].size)); 1653 } 1654 #endif 1655 } 1656 1657 static int 1658 pccbb_pcic_io_map(struct pccbb_softc *sc, int width, struct resource *r) 1659 { 1660 int win; 1661 #ifdef CBB_DEBUG 1662 static char *width_names[] = { "auto", "io8", "io16"}; 1663 #endif 1664 1665 for (win=0; win < PCIC_IO_WINS; win++) { 1666 if ((sc->ioalloc & (1 << win)) == 0) { 1667 sc->ioalloc |= (1 << win); 1668 break; 1669 } 1670 } 1671 if (win >= PCIC_IO_WINS) 1672 return (1); 1673 1674 sc->io[win].iot = rman_get_bustag(r); 1675 sc->io[win].ioh = rman_get_bushandle(r); 1676 sc->io[win].addr = rman_get_start(r); 1677 sc->io[win].size = rman_get_end(r) - sc->io[win].addr + 1; 1678 sc->io[win].flags = 0; 1679 sc->io[win].width = width; 1680 1681 DPRINTF(("pccbb_pcic_io_map window %d %s port %x+%x\n", 1682 win, width_names[width], sc->io[win].addr, 1683 sc->io[win].size)); 1684 1685 pccbb_pcic_do_io_map(sc, win); 1686 1687 return (0); 1688 } 1689 1690 static void 1691 pccbb_pcic_io_unmap(struct pccbb_softc *sc, int window) 1692 { 1693 if (window >= PCIC_IO_WINS) 1694 panic("pccbb_pcic_io_unmap: window out of range"); 1695 1696 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, & ~io_map_index[window].ioenable); 1697 1698 sc->ioalloc &= ~(1 << window); 1699 1700 sc->io[window].iot = 0; 1701 sc->io[window].ioh = 0; 1702 sc->io[window].addr = 0; 1703 sc->io[window].size = 0; 1704 sc->io[window].flags = 0; 1705 sc->io[window].width = 0; 1706 } 1707 1708 static int 1709 pccbb_pcic_io_findmap(struct pccbb_softc *sc, struct resource *res) 1710 { 1711 int win; 1712 1713 for (win = 0; win < PCIC_IO_WINS; win++) { 1714 if (sc->io[win].iot == rman_get_bustag(res) && 1715 sc->io[win].addr == rman_get_start(res) && 1716 sc->io[win].size == rman_get_size(res)) 1717 return win; 1718 } 1719 device_printf(sc->sc_dev, "IO map not found!\n"); 1720 return -1; 1721 } 1722 1723 static int 1724 pccbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1725 struct resource *res) 1726 { 1727 int err; 1728 struct pccbb_softc *sc = device_get_softc(brdev); 1729 if (!(rman_get_flags(res) & RF_ACTIVE)) { /* not already activated */ 1730 switch (type) { 1731 case SYS_RES_IOPORT: 1732 err = pccbb_pcic_io_map(sc, 0, res); 1733 break; 1734 case SYS_RES_MEMORY: 1735 err = pccbb_pcic_mem_map(sc, 0, res); 1736 break; 1737 default: 1738 err = 0; 1739 break; 1740 } 1741 if (err) 1742 return err; 1743 1744 } 1745 return BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1746 type, rid, res); 1747 } 1748 1749 static int 1750 pccbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1751 int rid, struct resource *res) 1752 { 1753 struct pccbb_softc *sc = device_get_softc(brdev); 1754 int win; 1755 1756 if (rman_get_flags(res) & RF_ACTIVE) { /* if activated */ 1757 switch (type) { 1758 case SYS_RES_IOPORT: 1759 win = pccbb_pcic_io_findmap(sc, res); 1760 if (win >= 0) 1761 pccbb_pcic_io_unmap(sc, win); 1762 else 1763 return ENOENT; 1764 break; 1765 case SYS_RES_MEMORY: 1766 win = pccbb_pcic_mem_findmap(sc, res); 1767 if (win >= 0) 1768 pccbb_pcic_mem_unmap(sc, win); 1769 else 1770 return ENOENT; 1771 break; 1772 } 1773 } 1774 return BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1775 type, rid, res); 1776 } 1777 1778 static struct resource * 1779 pccbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1780 u_long start, u_long end, u_long count, u_int flags) 1781 { 1782 struct resource *res = NULL; 1783 struct pccbb_softc *sc = device_get_softc(brdev); 1784 struct pccbb_reslist *rle; 1785 int tmp; 1786 1787 if ((sc->sc_flags & PCCBB_PCIC_MEM_32) == 0) { 1788 /* XXX: how do we do this? */ 1789 panic("PCCBB bridge cannot handle non MEM_32 bridges\n"); 1790 } 1791 1792 switch (type) { 1793 case SYS_RES_MEMORY: 1794 if (start < 0x10000000) 1795 start = 0x10000000; /* XXX tweakable? */ 1796 if (end < start) 1797 end = start; 1798 flags = (flags & ~RF_ALIGNMENT_MASK) | 1799 rman_make_alignment_flags(PCCBB_MEMALIGN); 1800 break; 1801 case SYS_RES_IOPORT: 1802 if (start < 0x100) 1803 start = 0x100; /* XXX tweakable? */ 1804 if (end < start) 1805 end = start; 1806 break; 1807 case SYS_RES_IRQ: 1808 tmp = rman_get_start(sc->sc_irq_res); 1809 if (start > tmp || end < tmp || count != 1) { 1810 device_printf(child, "requested interrupt %ld-%ld," 1811 "count = %ld not supported by pccbb\n", 1812 start, end, count); 1813 return NULL; 1814 } 1815 flags |= RF_SHAREABLE; 1816 start = end = rman_get_start(sc->sc_irq_res); 1817 break; 1818 } 1819 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1820 start, end, count, flags & ~RF_ACTIVE); 1821 if (res == NULL) 1822 return NULL; 1823 1824 rle = malloc(sizeof(struct pccbb_reslist), M_DEVBUF, M_NOWAIT); 1825 if (!rle) 1826 panic("pccbb_pcic_alloc_resource: can't record entry!"); 1827 rle->res = res; 1828 rle->type = type; 1829 rle->rid = *rid; 1830 rle->cardaddr = 0; 1831 SLIST_INSERT_HEAD(&sc->rl, rle, link); 1832 1833 if (flags & RF_ACTIVE) { 1834 if (bus_activate_resource(child, type, *rid, res) != 0) { 1835 bus_release_resource(child, type, *rid, res); 1836 return NULL; 1837 } 1838 } 1839 1840 return res; 1841 } 1842 1843 static int 1844 pccbb_pcic_release_resource(device_t brdev, device_t child, int type, 1845 int rid, struct resource *res) 1846 { 1847 struct pccbb_softc *sc = device_get_softc(brdev); 1848 struct pccbb_reslist *rle; 1849 1850 if (rman_get_flags(res) & RF_ACTIVE) { 1851 int error; 1852 error = bus_deactivate_resource(child, type, rid, res); 1853 if (error != 0) 1854 return error; 1855 } 1856 1857 SLIST_FOREACH(rle, &sc->rl, link) { 1858 if (rle->res == res) { 1859 SLIST_REMOVE(&sc->rl, rle, pccbb_reslist, link); 1860 free(rle, M_DEVBUF); 1861 break; 1862 } 1863 } 1864 1865 return BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1866 type, rid, res); 1867 } 1868 1869 /************************************************************************/ 1870 /* PC Card methods */ 1871 /************************************************************************/ 1872 1873 static int 1874 pccbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1875 u_int32_t flags) 1876 { 1877 struct pccbb_softc *sc = device_get_softc(brdev); 1878 struct resource *res; 1879 struct pccbb_reslist *rle; 1880 int win; 1881 1882 res = NULL; 1883 if (type != SYS_RES_MEMORY) 1884 return (EINVAL); 1885 SLIST_FOREACH(rle, &sc->rl, link) { 1886 if (SYS_RES_MEMORY == rle->type && rid == rle->rid && 1887 child == rle->res->r_dev) { 1888 res = rle->res; 1889 break; 1890 } 1891 } 1892 1893 if (res == NULL) { 1894 device_printf(brdev, 1895 "set_res_flags: specified rid not found\n"); 1896 return ENOENT; 1897 } 1898 win = pccbb_pcic_mem_findmap(sc, res); 1899 if (win < 0) { 1900 device_printf(brdev, 1901 "set_res_flags: specified resource not active\n"); 1902 return ENOENT; 1903 } 1904 1905 sc->mem[win].kind = flags; 1906 pccbb_pcic_do_mem_map(sc, win); 1907 return 0; 1908 } 1909 1910 static int 1911 pccbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1912 u_int32_t cardaddr, u_int32_t *deltap) 1913 { 1914 struct pccbb_softc *sc = device_get_softc(brdev); 1915 int win; 1916 struct pccbb_reslist *rle; 1917 struct resource *res; 1918 u_int32_t delta; 1919 1920 win = -1; 1921 1922 res = NULL; 1923 SLIST_FOREACH(rle, &sc->rl, link) { 1924 if (SYS_RES_MEMORY == rle->type && rid == rle->rid && 1925 child == rle->res->r_dev) { 1926 res = rle->res; 1927 rle->cardaddr = cardaddr; 1928 break; 1929 } 1930 } 1931 1932 if (res == NULL) { 1933 device_printf(brdev, 1934 "set_memory_offset: specified rid not found\n"); 1935 return ENOENT; 1936 } 1937 win = pccbb_pcic_mem_findmap(sc, res); 1938 if (win < 0) { 1939 device_printf(brdev, 1940 "set_memory_offset: specified resource not active\n"); 1941 return ENOENT; 1942 } 1943 1944 delta = cardaddr % PCIC_MEM_PAGESIZE; 1945 if (deltap) 1946 *deltap = delta; 1947 cardaddr -= delta; 1948 sc->mem[win].realsize = sc->mem[win].size + delta + 1949 PCIC_MEM_PAGESIZE - 1; 1950 sc->mem[win].realsize = sc->mem[win].realsize - 1951 (sc->mem[win].realsize % PCIC_MEM_PAGESIZE); 1952 sc->mem[win].offset = cardaddr - sc->mem[win].addr; 1953 pccbb_pcic_do_mem_map(sc, win); 1954 1955 return 0; 1956 } 1957 1958 /************************************************************************/ 1959 /* POWER methods */ 1960 /************************************************************************/ 1961 1962 static int 1963 pccbb_power_enable_socket(device_t brdev, device_t child) 1964 { 1965 struct pccbb_softc *sc = device_get_softc(brdev); 1966 1967 if (sc->sc_flags & PCCBB_16BIT_CARD) 1968 return pccbb_pcic_power_enable_socket(brdev, child); 1969 else 1970 return pccbb_cardbus_power_enable_socket(brdev, child); 1971 } 1972 1973 static void 1974 pccbb_power_disable_socket(device_t brdev, device_t child) 1975 { 1976 struct pccbb_softc *sc = device_get_softc(brdev); 1977 if (sc->sc_flags & PCCBB_16BIT_CARD) 1978 pccbb_pcic_power_disable_socket(brdev, child); 1979 else 1980 pccbb_cardbus_power_disable_socket(brdev, child); 1981 } 1982 /************************************************************************/ 1983 /* BUS Methods */ 1984 /************************************************************************/ 1985 1986 1987 static int 1988 pccbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1989 struct resource *r) 1990 { 1991 struct pccbb_softc *sc = device_get_softc(brdev); 1992 1993 if (sc->sc_flags & PCCBB_16BIT_CARD) 1994 return pccbb_pcic_activate_resource(brdev, child, type, rid, r); 1995 else 1996 return pccbb_cardbus_activate_resource(brdev, child, type, rid, 1997 r); 1998 } 1999 2000 static int 2001 pccbb_deactivate_resource(device_t brdev, device_t child, int type, 2002 int rid, struct resource *r) 2003 { 2004 struct pccbb_softc *sc = device_get_softc(brdev); 2005 2006 if (sc->sc_flags & PCCBB_16BIT_CARD) 2007 return pccbb_pcic_deactivate_resource(brdev, child, type, 2008 rid, r); 2009 else 2010 return pccbb_cardbus_deactivate_resource(brdev, child, type, 2011 rid, r); 2012 } 2013 2014 static struct resource * 2015 pccbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 2016 u_long start, u_long end, u_long count, u_int flags) 2017 { 2018 struct pccbb_softc *sc = device_get_softc(brdev); 2019 2020 if (sc->sc_flags & PCCBB_16BIT_CARD) 2021 return pccbb_pcic_alloc_resource(brdev, child, type, rid, 2022 start, end, count, flags); 2023 else 2024 return pccbb_cardbus_alloc_resource(brdev, child, type, rid, 2025 start, end, count, flags); 2026 } 2027 2028 static int 2029 pccbb_release_resource(device_t brdev, device_t child, int type, int rid, 2030 struct resource *r) 2031 { 2032 struct pccbb_softc *sc = device_get_softc(brdev); 2033 2034 if (sc->sc_flags & PCCBB_16BIT_CARD) 2035 return pccbb_pcic_release_resource(brdev, child, type, 2036 rid, r); 2037 else 2038 return pccbb_cardbus_release_resource(brdev, child, type, 2039 rid, r); 2040 } 2041 2042 static int 2043 pccbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 2044 { 2045 struct pccbb_softc *sc = device_get_softc(brdev); 2046 2047 switch (which) { 2048 case PCIB_IVAR_BUS: 2049 *result = sc->sc_secbus; 2050 return(0); 2051 } 2052 return(ENOENT); 2053 } 2054 2055 static int 2056 pccbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 2057 { 2058 struct pccbb_softc *sc = device_get_softc(brdev); 2059 2060 switch (which) { 2061 case PCIB_IVAR_BUS: 2062 sc->sc_secbus = value; 2063 break; 2064 } 2065 return(ENOENT); 2066 } 2067 2068 /************************************************************************/ 2069 /* PCI compat methods */ 2070 /************************************************************************/ 2071 2072 static int 2073 pccbb_maxslots(device_t brdev) 2074 { 2075 return 0; 2076 } 2077 2078 static u_int32_t 2079 pccbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 2080 { 2081 /* 2082 * Pass through to the next ppb up the chain (i.e. our grandparent). 2083 */ 2084 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 2085 b, s, f, reg, width); 2086 } 2087 2088 static void 2089 pccbb_write_config(device_t brdev, int b, int s, int f, int reg, u_int32_t val, 2090 int width) 2091 { 2092 /* 2093 * Pass through to the next ppb up the chain (i.e. our grandparent). 2094 */ 2095 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 2096 b, s, f, reg, val, width); 2097 } 2098 2099 static device_method_t pccbb_methods[] = { 2100 /* Device interface */ 2101 DEVMETHOD(device_probe, pccbb_probe), 2102 DEVMETHOD(device_attach, pccbb_attach), 2103 DEVMETHOD(device_detach, pccbb_detach), 2104 DEVMETHOD(device_shutdown, pccbb_shutdown), 2105 DEVMETHOD(device_suspend, bus_generic_suspend), 2106 DEVMETHOD(device_resume, bus_generic_resume), 2107 2108 /* bus methods */ 2109 DEVMETHOD(bus_print_child, bus_generic_print_child), 2110 DEVMETHOD(bus_read_ivar, pccbb_read_ivar), 2111 DEVMETHOD(bus_write_ivar, pccbb_write_ivar), 2112 DEVMETHOD(bus_alloc_resource, pccbb_alloc_resource), 2113 DEVMETHOD(bus_release_resource, pccbb_release_resource), 2114 DEVMETHOD(bus_activate_resource, pccbb_activate_resource), 2115 DEVMETHOD(bus_deactivate_resource, pccbb_deactivate_resource), 2116 DEVMETHOD(bus_driver_added, pccbb_driver_added), 2117 DEVMETHOD(bus_child_detached, pccbb_child_detached), 2118 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2119 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2120 2121 /* 16-bit card interface */ 2122 DEVMETHOD(card_set_res_flags, pccbb_pcic_set_res_flags), 2123 DEVMETHOD(card_set_memory_offset, pccbb_pcic_set_memory_offset), 2124 DEVMETHOD(card_reprobe_card, pccbb_card_reprobe), 2125 2126 /* power interface */ 2127 DEVMETHOD(power_enable_socket, pccbb_power_enable_socket), 2128 DEVMETHOD(power_disable_socket, pccbb_power_disable_socket), 2129 2130 /* pcib compatibility interface */ 2131 DEVMETHOD(pcib_maxslots, pccbb_maxslots), 2132 DEVMETHOD(pcib_read_config, pccbb_read_config), 2133 DEVMETHOD(pcib_write_config, pccbb_write_config), 2134 {0,0} 2135 }; 2136 2137 static driver_t pccbb_driver = { 2138 "pccbb", 2139 pccbb_methods, 2140 sizeof(struct pccbb_softc) 2141 }; 2142 2143 static devclass_t pccbb_devclass; 2144 2145 DRIVER_MODULE(pccbb, pci, pccbb_driver, pccbb_devclass, 0, 0); 2146 2147 SYSINIT(pccbb, SI_SUB_KTHREAD_IDLE, SI_ORDER_ANY, pccbb_start_threads, 0); 2148