1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * and PCI to PCMCIA Bridge chips 62 * and ISA to PCMCIA host adapters 63 * and C Bus to PCMCIA host adapters 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include <sys/param.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/module.h> 86 #include <sys/kthread.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mutex.h> 90 #include <sys/proc.h> 91 #include <sys/rman.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 #include <machine/bus.h> 95 #include <machine/resource.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <machine/clock.h> 100 101 #include <dev/pccard/pccardreg.h> 102 #include <dev/pccard/pccardvar.h> 103 104 #include <dev/exca/excareg.h> 105 #include <dev/exca/excavar.h> 106 107 #include <dev/pccbb/pccbbreg.h> 108 #include <dev/pccbb/pccbbvar.h> 109 110 #include "power_if.h" 111 #include "card_if.h" 112 #include "pcib_if.h" 113 114 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 115 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 116 117 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 118 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 119 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 120 pci_write_config(DEV, REG, ( \ 121 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 122 123 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 124 125 #define CBB_START_MEM 0x88000000 126 #define CBB_START_32_IO 0x1000 127 #define CBB_START_16_IO 0x100 128 129 devclass_t cbb_devclass; 130 131 /* sysctl vars */ 132 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 133 134 /* There's no way to say TUNEABLE_LONG to get the right types */ 135 u_long cbb_start_mem = CBB_START_MEM; 136 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 137 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 138 &cbb_start_mem, CBB_START_MEM, 139 "Starting address for memory allocations"); 140 141 u_long cbb_start_16_io = CBB_START_16_IO; 142 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 143 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 144 &cbb_start_16_io, CBB_START_16_IO, 145 "Starting ioport for 16-bit cards"); 146 147 u_long cbb_start_32_io = CBB_START_32_IO; 148 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 149 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 150 &cbb_start_32_io, CBB_START_32_IO, 151 "Starting ioport for 32-bit cards"); 152 153 int cbb_debug = 0; 154 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 155 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 156 "Verbose cardbus bridge debugging"); 157 158 static void cbb_insert(struct cbb_softc *sc); 159 static void cbb_removal(struct cbb_softc *sc); 160 static uint32_t cbb_detect_voltage(device_t brdev); 161 static void cbb_cardbus_reset(device_t brdev); 162 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 163 uint32_t end); 164 static int cbb_cardbus_mem_open(device_t brdev, int win, 165 uint32_t start, uint32_t end); 166 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 167 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 168 int type, int rid, struct resource *res); 169 static int cbb_cardbus_deactivate_resource(device_t brdev, 170 device_t child, int type, int rid, struct resource *res); 171 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 172 device_t child, int type, int *rid, u_long start, 173 u_long end, u_long count, u_int flags); 174 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 175 int type, int rid, struct resource *res); 176 static int cbb_cardbus_power_enable_socket(device_t brdev, 177 device_t child); 178 static void cbb_cardbus_power_disable_socket(device_t brdev, 179 device_t child); 180 static void cbb_func_intr(void *arg); 181 182 static void 183 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 184 { 185 struct cbb_reslist *rle; 186 187 SLIST_FOREACH(rle, &sc->rl, link) { 188 if (rle->res == res) { 189 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 190 free(rle, M_DEVBUF); 191 return; 192 } 193 } 194 } 195 196 static struct resource * 197 cbb_find_res(struct cbb_softc *sc, int type, int rid) 198 { 199 struct cbb_reslist *rle; 200 201 SLIST_FOREACH(rle, &sc->rl, link) 202 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 203 return (rle->res); 204 return (NULL); 205 } 206 207 static void 208 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 209 int rid) 210 { 211 struct cbb_reslist *rle; 212 213 /* 214 * Need to record allocated resource so we can iterate through 215 * it later. 216 */ 217 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 218 if (rle == NULL) 219 panic("cbb_cardbus_alloc_resource: can't record entry!"); 220 rle->res = res; 221 rle->type = type; 222 rle->rid = rid; 223 SLIST_INSERT_HEAD(&sc->rl, rle, link); 224 } 225 226 static void 227 cbb_destroy_res(struct cbb_softc *sc) 228 { 229 struct cbb_reslist *rle; 230 231 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 232 device_printf(sc->dev, "Danger Will Robinson: Resource " 233 "left allocated! This is a bug... " 234 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 235 rman_get_start(rle->res)); 236 SLIST_REMOVE_HEAD(&sc->rl, link); 237 free(rle, M_DEVBUF); 238 } 239 } 240 241 /* 242 * Disable function interrupts by telling the bridge to generate IRQ1 243 * interrupts. These interrupts aren't really generated by the chip, since 244 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 245 * initialization, so this helps to work around the problem. 246 * 247 * XXX We can't do this workaround for all chipsets, because this 248 * XXX causes interference with the keyboard because somechipsets will 249 * XXX actually signal IRQ1 over their serial interrupt connections to 250 * XXX the south bridge. Disable it it for now. 251 */ 252 void 253 cbb_disable_func_intr(struct cbb_softc *sc) 254 { 255 #if 0 256 uint8_t reg; 257 258 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 259 EXCA_INTR_IRQ_RESERVED1; 260 exca_putb(&sc->exca[0], EXCA_INTR, reg); 261 #endif 262 } 263 264 /* 265 * Enable function interrupts. We turn on function interrupts when the card 266 * requests an interrupt. The PCMCIA standard says that we should set 267 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 268 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 269 * cards. 270 */ 271 static void 272 cbb_enable_func_intr(struct cbb_softc *sc) 273 { 274 uint8_t reg; 275 276 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 277 EXCA_INTR_IRQ_NONE; 278 exca_putb(&sc->exca[0], EXCA_INTR, reg); 279 } 280 281 int 282 cbb_detach(device_t brdev) 283 { 284 struct cbb_softc *sc = device_get_softc(brdev); 285 int numdevs; 286 device_t *devlist; 287 int tmp; 288 int error; 289 290 device_get_children(brdev, &devlist, &numdevs); 291 292 error = 0; 293 for (tmp = 0; tmp < numdevs; tmp++) { 294 if (device_detach(devlist[tmp]) == 0) 295 device_delete_child(brdev, devlist[tmp]); 296 else 297 error++; 298 } 299 free(devlist, M_TEMP); 300 if (error > 0) 301 return (ENXIO); 302 303 mtx_lock(&sc->mtx); 304 /* 305 * XXX do we teardown all the ones still registered to guard against 306 * XXX buggy client drivers? 307 */ 308 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 309 /* 310 * Wait for the thread to die. kthread_exit will do a wakeup 311 * on the event thread's struct thread * so that we know it is 312 * save to proceed. IF the thread is running, set the please 313 * die flag and wait for it to comply. Since the wakeup on 314 * the event thread happens only in kthread_exit, we don't 315 * need to loop here. 316 */ 317 sc->flags |= CBB_KTHREAD_DONE; 318 if (sc->flags & CBB_KTHREAD_RUNNING) { 319 cv_broadcast(&sc->cv); 320 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 321 } 322 mtx_unlock(&sc->mtx); 323 324 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 325 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 326 sc->base_res); 327 mtx_destroy(&sc->mtx); 328 cv_destroy(&sc->cv); 329 cv_destroy(&sc->powercv); 330 return (0); 331 } 332 333 int 334 cbb_shutdown(device_t brdev) 335 { 336 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 337 /* properly reset everything at shutdown */ 338 339 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 340 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 341 342 cbb_set(sc, CBB_SOCKET_MASK, 0); 343 344 cbb_power(brdev, CARD_OFF); 345 346 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 347 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 348 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 349 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 350 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 351 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 352 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 353 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 354 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 355 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 356 return (0); 357 } 358 359 int 360 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 361 int flags, driver_intr_t *intr, void *arg, void **cookiep) 362 { 363 struct cbb_intrhand *ih; 364 struct cbb_softc *sc = device_get_softc(dev); 365 int err; 366 367 /* 368 * Well, this is no longer strictly true. You can have multiple 369 * FAST ISRs, but can't mix fast and slow, so we have to assume 370 * least common denominator until the base system supports mixing 371 * and matching better. 372 */ 373 if ((flags & INTR_FAST) != 0) 374 return (EINVAL); 375 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 376 if (ih == NULL) 377 return (ENOMEM); 378 *cookiep = ih; 379 ih->intr = intr; 380 ih->arg = arg; 381 ih->sc = sc; 382 /* 383 * XXX need to turn on ISA interrupts, if we ever support them, but 384 * XXX for now that's all we need to do. 385 */ 386 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 387 cbb_func_intr, ih, &ih->cookie); 388 if (err != 0) { 389 free(ih, M_DEVBUF); 390 return (err); 391 } 392 cbb_enable_func_intr(sc); 393 sc->flags |= CBB_CARD_OK; 394 return 0; 395 } 396 397 int 398 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 399 void *cookie) 400 { 401 struct cbb_intrhand *ih; 402 int err; 403 404 /* XXX Need to do different things for ISA interrupts. */ 405 ih = (struct cbb_intrhand *) cookie; 406 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 407 ih->cookie); 408 if (err != 0) 409 return (err); 410 free(ih, M_DEVBUF); 411 return (0); 412 } 413 414 415 void 416 cbb_driver_added(device_t brdev, driver_t *driver) 417 { 418 struct cbb_softc *sc = device_get_softc(brdev); 419 device_t *devlist; 420 device_t dev; 421 int tmp; 422 int numdevs; 423 int wake = 0; 424 425 DEVICE_IDENTIFY(driver, brdev); 426 device_get_children(brdev, &devlist, &numdevs); 427 for (tmp = 0; tmp < numdevs; tmp++) { 428 dev = devlist[tmp]; 429 if (device_get_state(dev) == DS_NOTPRESENT && 430 device_probe_and_attach(dev) == 0) 431 wake++; 432 } 433 free(devlist, M_TEMP); 434 435 if (wake > 0) { 436 mtx_lock(&sc->mtx); 437 cv_signal(&sc->cv); 438 mtx_unlock(&sc->mtx); 439 } 440 } 441 442 void 443 cbb_child_detached(device_t brdev, device_t child) 444 { 445 struct cbb_softc *sc = device_get_softc(brdev); 446 447 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 448 device_printf(brdev, "Unknown child detached: %s\n", 449 device_get_nameunit(child)); 450 } 451 452 /************************************************************************/ 453 /* Kthreads */ 454 /************************************************************************/ 455 456 void 457 cbb_event_thread(void *arg) 458 { 459 struct cbb_softc *sc = arg; 460 uint32_t status; 461 int err; 462 int not_a_card = 0; 463 464 sc->flags |= CBB_KTHREAD_RUNNING; 465 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 466 /* 467 * We take out Giant here because we need it deep, 468 * down in the bowels of the vm system for mapping the 469 * memory we need to read the CIS. In addition, since 470 * we are adding/deleting devices from the dev tree, 471 * and that code isn't MP safe, we have to hold Giant. 472 */ 473 mtx_lock(&Giant); 474 status = cbb_get(sc, CBB_SOCKET_STATE); 475 DPRINTF(("Status is 0x%x\n", status)); 476 if (!CBB_CARD_PRESENT(status)) { 477 not_a_card = 0; /* We know card type */ 478 cbb_removal(sc); 479 } else if (status & CBB_STATE_NOT_A_CARD) { 480 /* 481 * Up to 20 times, try to rescan the card when we 482 * see NOT_A_CARD. 483 */ 484 if (not_a_card++ < 20) { 485 DEVPRINTF((sc->dev, 486 "Not a card bit set, rescanning\n")); 487 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 488 } else { 489 device_printf(sc->dev, 490 "Can't determine card type\n"); 491 } 492 } else { 493 not_a_card = 0; /* We know card type */ 494 cbb_insert(sc); 495 } 496 mtx_unlock(&Giant); 497 498 /* 499 * Wait until it has been 1s since the last time we 500 * get an interrupt. We handle the rest of the interrupt 501 * at the top of the loop. Although we clear the bit in the 502 * ISR, we signal sc->cv from the detach path after we've 503 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 504 * 1s sleep here. 505 * 506 * In our ISR, we turn off the card changed interrupt. Turn 507 * them back on here before we wait for them to happen. We 508 * turn them on/off so that we can tolerate a large latency 509 * between the time we signal cbb_event_thread and it gets 510 * a chance to run. 511 */ 512 mtx_lock(&sc->mtx); 513 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 514 cv_wait(&sc->cv, &sc->mtx); 515 err = 0; 516 while (err != EWOULDBLOCK && 517 (sc->flags & CBB_KTHREAD_DONE) == 0) 518 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 519 mtx_unlock(&sc->mtx); 520 } 521 sc->flags &= ~CBB_KTHREAD_RUNNING; 522 kthread_exit(0); 523 } 524 525 /************************************************************************/ 526 /* Insert/removal */ 527 /************************************************************************/ 528 529 static void 530 cbb_insert(struct cbb_softc *sc) 531 { 532 uint32_t sockevent, sockstate; 533 534 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 535 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 536 537 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 538 sockevent, sockstate)); 539 540 if (sockstate & CBB_STATE_R2_CARD) { 541 if (sc->exca[0].pccarddev) { 542 sc->flags |= CBB_16BIT_CARD; 543 exca_insert(&sc->exca[0]); 544 } else { 545 device_printf(sc->dev, 546 "16-bit card inserted, but no pccard bus.\n"); 547 } 548 } else if (sockstate & CBB_STATE_CB_CARD) { 549 if (sc->cbdev != NULL) { 550 sc->flags &= ~CBB_16BIT_CARD; 551 CARD_ATTACH_CARD(sc->cbdev); 552 } else { 553 device_printf(sc->dev, 554 "CardBus card inserted, but no cardbus bus.\n"); 555 } 556 } else { 557 /* 558 * We should power the card down, and try again a couple of 559 * times if this happens. XXX 560 */ 561 device_printf(sc->dev, "Unsupported card type detected\n"); 562 } 563 } 564 565 static void 566 cbb_removal(struct cbb_softc *sc) 567 { 568 sc->flags &= ~CBB_CARD_OK; 569 if (sc->flags & CBB_16BIT_CARD) { 570 exca_removal(&sc->exca[0]); 571 } else { 572 if (sc->cbdev != NULL) 573 CARD_DETACH_CARD(sc->cbdev); 574 } 575 cbb_destroy_res(sc); 576 } 577 578 /************************************************************************/ 579 /* Interrupt Handler */ 580 /************************************************************************/ 581 582 /* 583 * Since we touch hardware in the worst case, we don't need to use atomic 584 * ops on the CARD_OK tests. They would save us a trip to the hardware 585 * if CARD_OK was recently cleared and the caches haven't updated yet. 586 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 587 * machine, this is about 33-66ns, whereas a trip the the hardware 588 * is about that. On slower machines, the cost is even higher, so the 589 * trip to the hardware is cheaper and achieves the same ends that 590 * a fully locked operation would give us. 591 * 592 * This is a separate routine because we'd have to use locking and/or 593 * other synchronization in cbb_intr to do this there. That would be 594 * even more expensive. 595 * 596 * I need to investigate what this means for a SMP machine with multiple 597 * CPUs servicing the ISR when an eject happens. In the case of a dirty 598 * eject, CD glitches and we might read 'card present' from the hardware 599 * due to this jitter. If we assumed that cbb_intr() ran before 600 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 601 * CD changes were clear there, then we'd know the card was gone. 602 */ 603 static void 604 cbb_func_intr(void *arg) 605 { 606 struct cbb_intrhand *ih = (struct cbb_intrhand *)arg; 607 struct cbb_softc *sc = ih->sc; 608 609 /* 610 * Make sure that the card is really there. 611 */ 612 if ((sc->flags & CBB_CARD_OK) == 0) 613 return; 614 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 615 sc->flags &= ~CBB_CARD_OK; 616 return; 617 } 618 619 /* 620 * nb: don't have to check for giant or not, since that's done 621 * in the ISR dispatch 622 */ 623 (*ih->intr)(ih->arg); 624 } 625 626 void 627 cbb_intr(void *arg) 628 { 629 struct cbb_softc *sc = arg; 630 uint32_t sockevent; 631 632 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 633 if (sockevent != 0) { 634 /* ack the interrupt */ 635 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 636 637 /* 638 * If anything has happened to the socket, we assume that 639 * the card is no longer OK, and we shouldn't call its 640 * ISR. We set CARD_OK as soon as we've attached the 641 * card. This helps in a noisy eject, which happens 642 * all too often when users are ejecting their PC Cards. 643 * 644 * We use this method in preference to checking to see if 645 * the card is still there because the check suffers from 646 * a race condition in the bouncing case. Prior versions 647 * of the pccard software used a similar trick and achieved 648 * excellent results. 649 */ 650 if (sockevent & CBB_SOCKET_EVENT_CD) { 651 mtx_lock(&sc->mtx); 652 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 653 sc->flags &= ~CBB_CARD_OK; 654 cbb_disable_func_intr(sc); 655 cv_signal(&sc->cv); 656 mtx_unlock(&sc->mtx); 657 } 658 /* 659 * If we get a power interrupt, wakeup anybody that might 660 * be waiting for one. 661 */ 662 if (sockevent & CBB_SOCKET_EVENT_POWER) { 663 mtx_lock(&sc->mtx); 664 sc->powerintr++; 665 cv_signal(&sc->powercv); 666 mtx_unlock(&sc->mtx); 667 } 668 } 669 /* 670 * Some chips also require us to read the old ExCA registe for 671 * card status change when we route CSC vis PCI. This isn't supposed 672 * to be required, but it clears the interrupt state on some chipsets. 673 * Maybe there's a setting that would obviate its need. Maybe we 674 * should test the status bits and deal with them, but so far we've 675 * not found any machines that don't also give us the socket status 676 * indication above. 677 * 678 * We have to call this unconditionally because some bridges deliver 679 * the even independent of the CBB_SOCKET_EVENT_CD above. 680 */ 681 exca_getb(&sc->exca[0], EXCA_CSC); 682 } 683 684 /************************************************************************/ 685 /* Generic Power functions */ 686 /************************************************************************/ 687 688 static uint32_t 689 cbb_detect_voltage(device_t brdev) 690 { 691 struct cbb_softc *sc = device_get_softc(brdev); 692 uint32_t psr; 693 uint32_t vol = CARD_UKN_CARD; 694 695 psr = cbb_get(sc, CBB_SOCKET_STATE); 696 697 if (psr & CBB_STATE_5VCARD) 698 vol |= CARD_5V_CARD; 699 if (psr & CBB_STATE_3VCARD) 700 vol |= CARD_3V_CARD; 701 if (psr & CBB_STATE_XVCARD) 702 vol |= CARD_XV_CARD; 703 if (psr & CBB_STATE_YVCARD) 704 vol |= CARD_YV_CARD; 705 706 return (vol); 707 } 708 709 static uint8_t 710 cbb_o2micro_power_hack(struct cbb_softc *sc) 711 { 712 uint8_t reg; 713 714 /* 715 * Issue #2: INT# not qualified with IRQ Routing Bit. An 716 * unexpected PCI INT# may be generated during PC Card 717 * initialization even with the IRQ Routing Bit Set with some 718 * PC Cards. 719 * 720 * This is a two part issue. The first part is that some of 721 * our older controllers have an issue in which the slot's PCI 722 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 723 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 724 * is selected (ExCA register 03h bits 3:0, of the slot, are 725 * cleared) we will generate INT# if IREQ# is asserted. The 726 * second part is because some PC Cards prematurally assert 727 * IREQ# before the ExCA registers are fully programmed. This 728 * in turn asserts INT# because ExCA register 03h bits 3:0 729 * (ISA IRQ Select) are not yet programmed. 730 * 731 * The fix for this issue, which will work for any controller 732 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 733 * (select IRQ1), of the slot, before turning on slot power. 734 * Selecting IRQ1 will result in INT# NOT being asserted 735 * (because IRQ1 is selected), and IRQ1 won't be asserted 736 * because our controllers don't generate IRQ1. 737 * 738 * Other, non O2Micro controllers will generate irq 1 in some 739 * situations, so we can't do this hack for everybody. Reports of 740 * keyboard controller's interrupts being suppressed occurred when 741 * we did this. 742 */ 743 reg = exca_getb(&sc->exca[0], EXCA_INTR); 744 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 745 return (reg); 746 } 747 748 /* 749 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 750 * we don't have an interrupt storm on power on. This has the efect of 751 * disabling card status change interrupts for the duration of poweron. 752 */ 753 static void 754 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 755 { 756 exca_putb(&sc->exca[0], EXCA_INTR, reg); 757 } 758 759 int 760 cbb_power(device_t brdev, int volts) 761 { 762 uint32_t status, sock_ctrl, mask; 763 struct cbb_softc *sc = device_get_softc(brdev); 764 int cnt, sane; 765 int retval = 0; 766 int on = 0; 767 uint8_t reg = 0; 768 769 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 770 771 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 772 switch (volts & CARD_VCCMASK) { 773 case 5: 774 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 775 on++; 776 break; 777 case 3: 778 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 779 on++; 780 break; 781 case XV: 782 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 783 on++; 784 break; 785 case YV: 786 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 787 on++; 788 break; 789 case 0: 790 break; 791 default: 792 return (0); /* power NEVER changed */ 793 } 794 795 /* VPP == VCC */ 796 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 797 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 798 799 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 800 return (1); /* no change necessary */ 801 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 802 if (volts != 0 && sc->chipset == CB_O2MICRO) 803 reg = cbb_o2micro_power_hack(sc); 804 805 /* 806 * We have to mask the card change detect interrupt while we're 807 * messing with the power. It is allowed to bounce while we're 808 * messing with power as things settle down. In addition, we mask off 809 * the card's function interrupt by routing it via the ISA bus. This 810 * bit generally only affects 16bit cards. Some bridges allow one to 811 * set another bit to have it also affect 32bit cards. Since 32bit 812 * cards are required to be better behaved, we don't bother to get 813 * into those bridge specific features. 814 */ 815 mask = cbb_get(sc, CBB_SOCKET_MASK); 816 mask |= CBB_SOCKET_MASK_POWER; 817 mask &= ~CBB_SOCKET_MASK_CD; 818 cbb_set(sc, CBB_SOCKET_MASK, mask); 819 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 820 |CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 821 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 822 if (on) { 823 mtx_lock(&sc->mtx); 824 cnt = sc->powerintr; 825 sane = 200; 826 while (!(cbb_get(sc, CBB_SOCKET_STATE) & CBB_STATE_POWER_CYCLE) && 827 cnt == sc->powerintr && sane-- > 0) 828 cv_timedwait(&sc->powercv, &sc->mtx, hz / 10); 829 mtx_unlock(&sc->mtx); 830 if (sane <= 0) 831 device_printf(sc->dev, "power timeout, doom?\n"); 832 } 833 834 /* 835 * After the power is good, we can turn off the power interrupt. 836 * However, the PC Card standard says that we must delay turning the 837 * CD bit back on for a bit to allow for bouncyness on power down 838 * (recall that we don't wait above for a power down, since we don't 839 * get an interrupt for that). We're called either from the suspend 840 * code in which case we don't want to turn card change on again, or 841 * we're called from the card insertion code, in which case the cbb 842 * thread will turn it on for us before it waits to be woken by a 843 * change event. 844 */ 845 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_POWER); 846 status = cbb_get(sc, CBB_SOCKET_STATE); 847 if (on) { 848 if ((status & CBB_STATE_POWER_CYCLE) == 0) 849 device_printf(sc->dev, "Power not on?\n"); 850 } 851 if (status & CBB_STATE_BAD_VCC_REQ) { 852 device_printf(sc->dev, "Bad Vcc requested\n"); 853 /* XXX Do we want to do something to mitigate things here? */ 854 goto done; 855 } 856 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 857 & ~CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 858 retval = 1; 859 done:; 860 if (volts != 0 && sc->chipset == CB_O2MICRO) 861 cbb_o2micro_power_hack2(sc, reg); 862 return (retval); 863 } 864 865 static int 866 cbb_current_voltage(device_t brdev) 867 { 868 struct cbb_softc *sc = device_get_softc(brdev); 869 uint32_t ctrl; 870 871 ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 872 switch (ctrl & CBB_SOCKET_CTRL_VCCMASK) { 873 case CBB_SOCKET_CTRL_VCC_5V: 874 return CARD_5V_CARD; 875 case CBB_SOCKET_CTRL_VCC_3V: 876 return CARD_3V_CARD; 877 case CBB_SOCKET_CTRL_VCC_XV: 878 return CARD_XV_CARD; 879 case CBB_SOCKET_CTRL_VCC_YV: 880 return CARD_YV_CARD; 881 } 882 return 0; 883 } 884 885 /* 886 * detect the voltage for the card, and set it. Since the power 887 * used is the square of the voltage, lower voltages is a big win 888 * and what Windows does (and what Microsoft prefers). The MS paper 889 * also talks about preferring the CIS entry as well, but that has 890 * to be done elsewhere. We also optimize power sequencing here 891 * and don't change things if we're already powered up at a supported 892 * voltage. 893 * 894 * In addition, we power up with OE disabled. We'll set it later 895 * in the power up sequence. 896 */ 897 static int 898 cbb_do_power(device_t brdev) 899 { 900 struct cbb_softc *sc = device_get_softc(brdev); 901 uint32_t voltage, curpwr; 902 uint32_t status; 903 904 /* Don't enable OE (output enable) until power stable */ 905 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 906 907 voltage = cbb_detect_voltage(brdev); 908 curpwr = cbb_current_voltage(brdev); 909 status = cbb_get(sc, CBB_SOCKET_STATE); 910 if ((status & CBB_STATE_POWER_CYCLE) && (voltage & curpwr)) 911 return 0; 912 /* Prefer lowest voltage supported */ 913 cbb_power(brdev, CARD_OFF); 914 if (voltage & CARD_YV_CARD) 915 cbb_power(brdev, CARD_VCC(YV)); 916 else if (voltage & CARD_XV_CARD) 917 cbb_power(brdev, CARD_VCC(XV)); 918 else if (voltage & CARD_3V_CARD) 919 cbb_power(brdev, CARD_VCC(3)); 920 else if (voltage & CARD_5V_CARD) 921 cbb_power(brdev, CARD_VCC(5)); 922 else { 923 device_printf(brdev, "Unknown card voltage\n"); 924 return (ENXIO); 925 } 926 return (0); 927 } 928 929 /************************************************************************/ 930 /* CardBus power functions */ 931 /************************************************************************/ 932 933 static void 934 cbb_cardbus_reset(device_t brdev) 935 { 936 struct cbb_softc *sc = device_get_softc(brdev); 937 int delay; 938 939 /* 940 * 20ms is necessary for most bridges. For some reason, the Ricoh 941 * RF5C47x bridges need 400ms. 942 */ 943 delay = sc->chipset == CB_RF5C47X ? 400 : 20; 944 945 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 946 947 tsleep(sc, PZERO, "cbbP3", hz * delay / 1000); 948 949 /* If a card exists, unreset it! */ 950 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 951 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 952 &~CBBM_BRIDGECTRL_RESET, 2); 953 tsleep(sc, PZERO, "cbbP3", hz * delay / 1000); 954 } 955 } 956 957 static int 958 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 959 { 960 struct cbb_softc *sc = device_get_softc(brdev); 961 int err; 962 963 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 964 return (ENODEV); 965 966 err = cbb_do_power(brdev); 967 if (err) 968 return (err); 969 cbb_cardbus_reset(brdev); 970 return (0); 971 } 972 973 static void 974 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 975 { 976 cbb_power(brdev, CARD_OFF); 977 cbb_cardbus_reset(brdev); 978 } 979 980 /************************************************************************/ 981 /* CardBus Resource */ 982 /************************************************************************/ 983 984 static int 985 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 986 { 987 int basereg; 988 int limitreg; 989 990 if ((win < 0) || (win > 1)) { 991 DEVPRINTF((brdev, 992 "cbb_cardbus_io_open: window out of range %d\n", win)); 993 return (EINVAL); 994 } 995 996 basereg = win * 8 + CBBR_IOBASE0; 997 limitreg = win * 8 + CBBR_IOLIMIT0; 998 999 pci_write_config(brdev, basereg, start, 4); 1000 pci_write_config(brdev, limitreg, end, 4); 1001 return (0); 1002 } 1003 1004 static int 1005 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1006 { 1007 int basereg; 1008 int limitreg; 1009 1010 if ((win < 0) || (win > 1)) { 1011 DEVPRINTF((brdev, 1012 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1013 return (EINVAL); 1014 } 1015 1016 basereg = win*8 + CBBR_MEMBASE0; 1017 limitreg = win*8 + CBBR_MEMLIMIT0; 1018 1019 pci_write_config(brdev, basereg, start, 4); 1020 pci_write_config(brdev, limitreg, end, 4); 1021 return (0); 1022 } 1023 1024 /* 1025 * XXX The following function belongs in the pci bus layer. 1026 */ 1027 static void 1028 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1029 { 1030 uint32_t starts[2]; 1031 uint32_t ends[2]; 1032 struct cbb_reslist *rle; 1033 int align; 1034 int prefetchable[2]; 1035 uint32_t reg; 1036 1037 starts[0] = starts[1] = 0xffffffff; 1038 ends[0] = ends[1] = 0; 1039 1040 if (type == SYS_RES_MEMORY) 1041 align = CBB_MEMALIGN; 1042 else if (type == SYS_RES_IOPORT) 1043 align = CBB_IOALIGN; 1044 else 1045 align = 1; 1046 1047 /* 1048 * This looks somewhat bogus, and doesn't seem to really respect 1049 * alignment. The alignment stuff is happening too late (it 1050 * should happen at allocation time, not activation time) and 1051 * this code looks generally to be too complex for the purpose 1052 * it surves. 1053 */ 1054 SLIST_FOREACH(rle, &sc->rl, link) { 1055 if (rle->type != type) 1056 ; 1057 else if (rle->res == NULL) { 1058 device_printf(sc->dev, "WARNING: Resource not reserved? " 1059 "(type=%d, addr=%lx)\n", 1060 rle->type, rman_get_start(rle->res)); 1061 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1062 /* XXX */ 1063 } else if (starts[0] == 0xffffffff) { 1064 starts[0] = rman_get_start(rle->res); 1065 ends[0] = rman_get_end(rle->res); 1066 prefetchable[0] = 1067 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1068 } else if (rman_get_end(rle->res) > ends[0] && 1069 rman_get_start(rle->res) - ends[0] < 1070 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1071 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1072 ends[0] = rman_get_end(rle->res); 1073 } else if (rman_get_start(rle->res) < starts[0] && 1074 starts[0] - rman_get_end(rle->res) < 1075 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1076 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1077 starts[0] = rman_get_start(rle->res); 1078 } else if (starts[1] == 0xffffffff) { 1079 starts[1] = rman_get_start(rle->res); 1080 ends[1] = rman_get_end(rle->res); 1081 prefetchable[1] = 1082 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1083 } else if (rman_get_end(rle->res) > ends[1] && 1084 rman_get_start(rle->res) - ends[1] < 1085 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1086 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1087 ends[1] = rman_get_end(rle->res); 1088 } else if (rman_get_start(rle->res) < starts[1] && 1089 starts[1] - rman_get_end(rle->res) < 1090 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1091 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1092 starts[1] = rman_get_start(rle->res); 1093 } else { 1094 uint32_t diffs[2]; 1095 int win; 1096 1097 diffs[0] = diffs[1] = 0xffffffff; 1098 if (rman_get_start(rle->res) > ends[0]) 1099 diffs[0] = rman_get_start(rle->res) - ends[0]; 1100 else if (rman_get_end(rle->res) < starts[0]) 1101 diffs[0] = starts[0] - rman_get_end(rle->res); 1102 if (rman_get_start(rle->res) > ends[1]) 1103 diffs[1] = rman_get_start(rle->res) - ends[1]; 1104 else if (rman_get_end(rle->res) < starts[1]) 1105 diffs[1] = starts[1] - rman_get_end(rle->res); 1106 1107 win = (diffs[0] <= diffs[1])?0:1; 1108 if (rman_get_start(rle->res) > ends[win]) 1109 ends[win] = rman_get_end(rle->res); 1110 else if (rman_get_end(rle->res) < starts[win]) 1111 starts[win] = rman_get_start(rle->res); 1112 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1113 prefetchable[win] = 0; 1114 } 1115 1116 if (starts[0] != 0xffffffff) 1117 starts[0] -= starts[0] % align; 1118 if (starts[1] != 0xffffffff) 1119 starts[1] -= starts[1] % align; 1120 if (ends[0] % align != 0) 1121 ends[0] += align - ends[0] % align - 1; 1122 if (ends[1] % align != 0) 1123 ends[1] += align - ends[1] % align - 1; 1124 } 1125 1126 if (type == SYS_RES_MEMORY) { 1127 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1128 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1129 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1130 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1131 CBBM_BRIDGECTRL_PREFETCH_1); 1132 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1133 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1134 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1135 } else if (type == SYS_RES_IOPORT) { 1136 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1137 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1138 } 1139 } 1140 1141 static int 1142 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1143 int rid, struct resource *res) 1144 { 1145 int ret; 1146 1147 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1148 type, rid, res); 1149 if (ret != 0) 1150 return (ret); 1151 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1152 return (0); 1153 } 1154 1155 static int 1156 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1157 int rid, struct resource *res) 1158 { 1159 int ret; 1160 1161 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1162 type, rid, res); 1163 if (ret != 0) 1164 return (ret); 1165 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1166 return (0); 1167 } 1168 1169 static struct resource * 1170 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1171 int *rid, u_long start, u_long end, u_long count, u_int flags) 1172 { 1173 struct cbb_softc *sc = device_get_softc(brdev); 1174 int tmp; 1175 struct resource *res; 1176 u_long align; 1177 1178 switch (type) { 1179 case SYS_RES_IRQ: 1180 tmp = rman_get_start(sc->irq_res); 1181 if (start > tmp || end < tmp || count != 1) { 1182 device_printf(child, "requested interrupt %ld-%ld," 1183 "count = %ld not supported by cbb\n", 1184 start, end, count); 1185 return (NULL); 1186 } 1187 start = end = tmp; 1188 flags |= RF_SHAREABLE; 1189 break; 1190 case SYS_RES_IOPORT: 1191 if (start <= cbb_start_32_io) 1192 start = cbb_start_32_io; 1193 if (end < start) 1194 end = start; 1195 break; 1196 case SYS_RES_MEMORY: 1197 if (start <= cbb_start_mem) 1198 start = cbb_start_mem; 1199 if (end < start) 1200 end = start; 1201 if (count < CBB_MEMALIGN) 1202 align = CBB_MEMALIGN; 1203 else 1204 align = count; 1205 if (align > (1 << RF_ALIGNMENT(flags))) 1206 flags = (flags & ~RF_ALIGNMENT_MASK) | 1207 rman_make_alignment_flags(align); 1208 break; 1209 } 1210 1211 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1212 start, end, count, flags & ~RF_ACTIVE); 1213 if (res == NULL) { 1214 printf("cbb alloc res fail\n"); 1215 return (NULL); 1216 } 1217 cbb_insert_res(sc, res, type, *rid); 1218 if (flags & RF_ACTIVE) 1219 if (bus_activate_resource(child, type, *rid, res) != 0) { 1220 bus_release_resource(child, type, *rid, res); 1221 return (NULL); 1222 } 1223 1224 return (res); 1225 } 1226 1227 static int 1228 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1229 int rid, struct resource *res) 1230 { 1231 struct cbb_softc *sc = device_get_softc(brdev); 1232 int error; 1233 1234 if (rman_get_flags(res) & RF_ACTIVE) { 1235 error = bus_deactivate_resource(child, type, rid, res); 1236 if (error != 0) 1237 return (error); 1238 } 1239 cbb_remove_res(sc, res); 1240 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1241 type, rid, res)); 1242 } 1243 1244 /************************************************************************/ 1245 /* PC Card Power Functions */ 1246 /************************************************************************/ 1247 1248 static int 1249 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1250 { 1251 struct cbb_softc *sc = device_get_softc(brdev); 1252 int err; 1253 1254 DPRINTF(("cbb_pcic_socket_enable:\n")); 1255 1256 /* power down/up the socket to reset */ 1257 err = cbb_do_power(brdev); 1258 if (err) 1259 return (err); 1260 exca_reset(&sc->exca[0], child); 1261 1262 return (0); 1263 } 1264 1265 static void 1266 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1267 { 1268 struct cbb_softc *sc = device_get_softc(brdev); 1269 1270 DPRINTF(("cbb_pcic_socket_disable\n")); 1271 1272 /* Turn off the card's interrupt and leave it in reset */ 1273 exca_putb(&sc->exca[0], EXCA_INTR, 0); 1274 tsleep(sc, PZERO, "cbbP1", hz / 100); 1275 1276 /* power down the socket */ 1277 cbb_power(brdev, CARD_OFF); 1278 exca_putb(&sc->exca[0], EXCA_PWRCTL, 0); 1279 1280 /* wait 300ms until power fails (Tpf). */ 1281 tsleep(sc, PZERO, "cbbP1", hz * 300 / 1000); 1282 } 1283 1284 /************************************************************************/ 1285 /* POWER methods */ 1286 /************************************************************************/ 1287 1288 int 1289 cbb_power_enable_socket(device_t brdev, device_t child) 1290 { 1291 struct cbb_softc *sc = device_get_softc(brdev); 1292 1293 if (sc->flags & CBB_16BIT_CARD) 1294 return (cbb_pcic_power_enable_socket(brdev, child)); 1295 else 1296 return (cbb_cardbus_power_enable_socket(brdev, child)); 1297 } 1298 1299 void 1300 cbb_power_disable_socket(device_t brdev, device_t child) 1301 { 1302 struct cbb_softc *sc = device_get_softc(brdev); 1303 if (sc->flags & CBB_16BIT_CARD) 1304 cbb_pcic_power_disable_socket(brdev, child); 1305 else 1306 cbb_cardbus_power_disable_socket(brdev, child); 1307 } 1308 1309 static int 1310 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1311 struct resource *res) 1312 { 1313 struct cbb_softc *sc = device_get_softc(brdev); 1314 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1315 } 1316 1317 static int 1318 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1319 int rid, struct resource *res) 1320 { 1321 struct cbb_softc *sc = device_get_softc(brdev); 1322 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1323 } 1324 1325 static struct resource * 1326 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1327 u_long start, u_long end, u_long count, u_int flags) 1328 { 1329 struct resource *res = NULL; 1330 struct cbb_softc *sc = device_get_softc(brdev); 1331 int align; 1332 int tmp; 1333 1334 switch (type) { 1335 case SYS_RES_MEMORY: 1336 if (start < cbb_start_mem) 1337 start = cbb_start_mem; 1338 if (end < start) 1339 end = start; 1340 if (count < CBB_MEMALIGN) 1341 align = CBB_MEMALIGN; 1342 else 1343 align = count; 1344 if (align > (1 << RF_ALIGNMENT(flags))) 1345 flags = (flags & ~RF_ALIGNMENT_MASK) | 1346 rman_make_alignment_flags(align); 1347 break; 1348 case SYS_RES_IOPORT: 1349 if (start < cbb_start_16_io) 1350 start = cbb_start_16_io; 1351 if (end < start) 1352 end = start; 1353 break; 1354 case SYS_RES_IRQ: 1355 tmp = rman_get_start(sc->irq_res); 1356 if (start > tmp || end < tmp || count != 1) { 1357 device_printf(child, "requested interrupt %ld-%ld," 1358 "count = %ld not supported by cbb\n", 1359 start, end, count); 1360 return (NULL); 1361 } 1362 flags |= RF_SHAREABLE; 1363 start = end = rman_get_start(sc->irq_res); 1364 break; 1365 } 1366 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1367 start, end, count, flags & ~RF_ACTIVE); 1368 if (res == NULL) 1369 return (NULL); 1370 cbb_insert_res(sc, res, type, *rid); 1371 if (flags & RF_ACTIVE) { 1372 if (bus_activate_resource(child, type, *rid, res) != 0) { 1373 bus_release_resource(child, type, *rid, res); 1374 return (NULL); 1375 } 1376 } 1377 1378 return (res); 1379 } 1380 1381 static int 1382 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1383 int rid, struct resource *res) 1384 { 1385 struct cbb_softc *sc = device_get_softc(brdev); 1386 int error; 1387 1388 if (rman_get_flags(res) & RF_ACTIVE) { 1389 error = bus_deactivate_resource(child, type, rid, res); 1390 if (error != 0) 1391 return (error); 1392 } 1393 cbb_remove_res(sc, res); 1394 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1395 type, rid, res)); 1396 } 1397 1398 /************************************************************************/ 1399 /* PC Card methods */ 1400 /************************************************************************/ 1401 1402 int 1403 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1404 uint32_t flags) 1405 { 1406 struct cbb_softc *sc = device_get_softc(brdev); 1407 struct resource *res; 1408 1409 if (type != SYS_RES_MEMORY) 1410 return (EINVAL); 1411 res = cbb_find_res(sc, type, rid); 1412 if (res == NULL) { 1413 device_printf(brdev, 1414 "set_res_flags: specified rid not found\n"); 1415 return (ENOENT); 1416 } 1417 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1418 } 1419 1420 int 1421 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1422 uint32_t cardaddr, uint32_t *deltap) 1423 { 1424 struct cbb_softc *sc = device_get_softc(brdev); 1425 struct resource *res; 1426 1427 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1428 if (res == NULL) { 1429 device_printf(brdev, 1430 "set_memory_offset: specified rid not found\n"); 1431 return (ENOENT); 1432 } 1433 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1434 } 1435 1436 /************************************************************************/ 1437 /* BUS Methods */ 1438 /************************************************************************/ 1439 1440 1441 int 1442 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1443 struct resource *r) 1444 { 1445 struct cbb_softc *sc = device_get_softc(brdev); 1446 1447 if (sc->flags & CBB_16BIT_CARD) 1448 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1449 else 1450 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1451 r)); 1452 } 1453 1454 int 1455 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1456 int rid, struct resource *r) 1457 { 1458 struct cbb_softc *sc = device_get_softc(brdev); 1459 1460 if (sc->flags & CBB_16BIT_CARD) 1461 return (cbb_pcic_deactivate_resource(brdev, child, type, 1462 rid, r)); 1463 else 1464 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1465 rid, r)); 1466 } 1467 1468 struct resource * 1469 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1470 u_long start, u_long end, u_long count, u_int flags) 1471 { 1472 struct cbb_softc *sc = device_get_softc(brdev); 1473 1474 if (sc->flags & CBB_16BIT_CARD) 1475 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1476 start, end, count, flags)); 1477 else 1478 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1479 start, end, count, flags)); 1480 } 1481 1482 int 1483 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1484 struct resource *r) 1485 { 1486 struct cbb_softc *sc = device_get_softc(brdev); 1487 1488 if (sc->flags & CBB_16BIT_CARD) 1489 return (cbb_pcic_release_resource(brdev, child, type, 1490 rid, r)); 1491 else 1492 return (cbb_cardbus_release_resource(brdev, child, type, 1493 rid, r)); 1494 } 1495 1496 int 1497 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1498 { 1499 struct cbb_softc *sc = device_get_softc(brdev); 1500 1501 switch (which) { 1502 case PCIB_IVAR_BUS: 1503 *result = sc->secbus; 1504 return (0); 1505 } 1506 return (ENOENT); 1507 } 1508 1509 int 1510 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1511 { 1512 struct cbb_softc *sc = device_get_softc(brdev); 1513 1514 switch (which) { 1515 case PCIB_IVAR_BUS: 1516 sc->secbus = value; 1517 break; 1518 } 1519 return (ENOENT); 1520 } 1521 1522 /************************************************************************/ 1523 /* PCI compat methods */ 1524 /************************************************************************/ 1525 1526 int 1527 cbb_maxslots(device_t brdev) 1528 { 1529 return (0); 1530 } 1531 1532 uint32_t 1533 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1534 { 1535 uint32_t rv; 1536 1537 /* 1538 * Pass through to the next ppb up the chain (i.e. our grandparent). 1539 */ 1540 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1541 b, s, f, reg, width); 1542 return (rv); 1543 } 1544 1545 void 1546 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1547 int width) 1548 { 1549 /* 1550 * Pass through to the next ppb up the chain (i.e. our grandparent). 1551 */ 1552 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1553 b, s, f, reg, val, width); 1554 } 1555 1556 int 1557 cbb_suspend(device_t self) 1558 { 1559 int error = 0; 1560 struct cbb_softc *sc = device_get_softc(self); 1561 1562 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1563 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1564 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1565 error = bus_generic_suspend(self); 1566 return (error); 1567 } 1568 1569 int 1570 cbb_resume(device_t self) 1571 { 1572 int error = 0; 1573 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1574 uint32_t tmp; 1575 1576 /* 1577 * Some BIOSes will not save the BARs for the pci chips, so we 1578 * must do it ourselves. If the BAR is reset to 0 for an I/O 1579 * device, it will read back as 0x1, so no explicit test for 1580 * memory devices are needed. 1581 * 1582 * Note: The PCI bus code should do this automatically for us on 1583 * suspend/resume, but until it does, we have to cope. 1584 */ 1585 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1586 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1587 rman_get_start(sc->base_res))); 1588 1589 sc->chipinit(sc); 1590 1591 /* reset interrupt -- Do we really need to do this? */ 1592 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1593 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1594 1595 /* re-establish the interrupt. */ 1596 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 1597 cbb_intr, sc, &sc->intrhand)) { 1598 device_printf(self, "couldn't re-establish interrupt"); 1599 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1600 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1601 sc->base_res); 1602 sc->irq_res = NULL; 1603 sc->base_res = NULL; 1604 return (ENOMEM); 1605 } 1606 1607 /* CSC Interrupt: Card detect interrupt on */ 1608 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1609 1610 /* Signal the thread to wakeup. */ 1611 mtx_lock(&sc->mtx); 1612 cv_signal(&sc->cv); 1613 mtx_unlock(&sc->mtx); 1614 1615 error = bus_generic_resume(self); 1616 1617 return (error); 1618 } 1619 1620 int 1621 cbb_child_present(device_t self) 1622 { 1623 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1624 uint32_t sockstate; 1625 1626 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1627 return (CBB_CARD_PRESENT(sockstate) && 1628 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1629 } 1630