1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * and PCI to PCMCIA Bridge chips 62 * and ISA to PCMCIA host adapters 63 * and C Bus to PCMCIA host adapters 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include <sys/param.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/module.h> 86 #include <sys/kthread.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mutex.h> 90 #include <sys/proc.h> 91 #include <sys/rman.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 #include <machine/bus.h> 95 #include <machine/resource.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <machine/clock.h> 100 101 #include <dev/pccard/pccardreg.h> 102 #include <dev/pccard/pccardvar.h> 103 104 #include <dev/exca/excareg.h> 105 #include <dev/exca/excavar.h> 106 107 #include <dev/pccbb/pccbbreg.h> 108 #include <dev/pccbb/pccbbvar.h> 109 110 #include "power_if.h" 111 #include "card_if.h" 112 #include "pcib_if.h" 113 114 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 115 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 116 117 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 118 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 119 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 120 pci_write_config(DEV, REG, ( \ 121 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 122 123 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 124 125 #define CBB_START_MEM 0x88000000 126 #define CBB_START_32_IO 0x1000 127 #define CBB_START_16_IO 0x100 128 129 devclass_t cbb_devclass; 130 131 /* sysctl vars */ 132 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 133 134 /* There's no way to say TUNEABLE_LONG to get the right types */ 135 u_long cbb_start_mem = CBB_START_MEM; 136 TUNABLE_ULONG("hw.cbb.start_memory", &cbb_start_mem); 137 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 138 &cbb_start_mem, CBB_START_MEM, 139 "Starting address for memory allocations"); 140 141 u_long cbb_start_16_io = CBB_START_16_IO; 142 TUNABLE_ULONG("hw.cbb.start_16_io", &cbb_start_16_io); 143 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 144 &cbb_start_16_io, CBB_START_16_IO, 145 "Starting ioport for 16-bit cards"); 146 147 u_long cbb_start_32_io = CBB_START_32_IO; 148 TUNABLE_ULONG("hw.cbb.start_32_io", &cbb_start_32_io); 149 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 150 &cbb_start_32_io, CBB_START_32_IO, 151 "Starting ioport for 32-bit cards"); 152 153 int cbb_debug = 0; 154 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 155 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 156 "Verbose cardbus bridge debugging"); 157 158 static void cbb_insert(struct cbb_softc *sc); 159 static void cbb_removal(struct cbb_softc *sc); 160 static uint32_t cbb_detect_voltage(device_t brdev); 161 static void cbb_cardbus_reset(device_t brdev); 162 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 163 uint32_t end); 164 static int cbb_cardbus_mem_open(device_t brdev, int win, 165 uint32_t start, uint32_t end); 166 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 167 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 168 int type, int rid, struct resource *res); 169 static int cbb_cardbus_deactivate_resource(device_t brdev, 170 device_t child, int type, int rid, struct resource *res); 171 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 172 device_t child, int type, int *rid, u_long start, 173 u_long end, u_long count, u_int flags); 174 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 175 int type, int rid, struct resource *res); 176 static int cbb_cardbus_power_enable_socket(device_t brdev, 177 device_t child); 178 static void cbb_cardbus_power_disable_socket(device_t brdev, 179 device_t child); 180 static void cbb_func_intr(void *arg); 181 182 static void 183 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 184 { 185 struct cbb_reslist *rle; 186 187 SLIST_FOREACH(rle, &sc->rl, link) { 188 if (rle->res == res) { 189 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 190 free(rle, M_DEVBUF); 191 return; 192 } 193 } 194 } 195 196 static struct resource * 197 cbb_find_res(struct cbb_softc *sc, int type, int rid) 198 { 199 struct cbb_reslist *rle; 200 201 SLIST_FOREACH(rle, &sc->rl, link) 202 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 203 return (rle->res); 204 return (NULL); 205 } 206 207 static void 208 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 209 int rid) 210 { 211 struct cbb_reslist *rle; 212 213 /* 214 * Need to record allocated resource so we can iterate through 215 * it later. 216 */ 217 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 218 if (rle == NULL) 219 panic("cbb_cardbus_alloc_resource: can't record entry!"); 220 rle->res = res; 221 rle->type = type; 222 rle->rid = rid; 223 SLIST_INSERT_HEAD(&sc->rl, rle, link); 224 } 225 226 static void 227 cbb_destroy_res(struct cbb_softc *sc) 228 { 229 struct cbb_reslist *rle; 230 231 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 232 device_printf(sc->dev, "Danger Will Robinson: Resource " 233 "left allocated! This is a bug... " 234 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 235 rman_get_start(rle->res)); 236 SLIST_REMOVE_HEAD(&sc->rl, link); 237 free(rle, M_DEVBUF); 238 } 239 } 240 241 /* 242 * Disable function interrupts by telling the bridge to generate IRQ1 243 * interrupts. These interrupts aren't really generated by the chip, since 244 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 245 * initialization, so this helps to work around the problem. 246 * 247 * XXX We can't do this workaround for all chipsets, because this 248 * XXX causes interference with the keyboard because somechipsets will 249 * XXX actually signal IRQ1 over their serial interrupt connections to 250 * XXX the south bridge. Disable it it for now. 251 */ 252 void 253 cbb_disable_func_intr(struct cbb_softc *sc) 254 { 255 #if 0 256 uint8_t reg; 257 258 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 259 EXCA_INTR_IRQ_RESERVED1; 260 exca_putb(&sc->exca[0], EXCA_INTR, reg); 261 #endif 262 } 263 264 /* 265 * Enable function interrupts. We turn on function interrupts when the card 266 * requests an interrupt. The PCMCIA standard says that we should set 267 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 268 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 269 * cards. 270 */ 271 static void 272 cbb_enable_func_intr(struct cbb_softc *sc) 273 { 274 uint8_t reg; 275 276 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 277 EXCA_INTR_IRQ_NONE; 278 exca_putb(&sc->exca[0], EXCA_INTR, reg); 279 } 280 281 int 282 cbb_detach(device_t brdev) 283 { 284 struct cbb_softc *sc = device_get_softc(brdev); 285 int numdevs; 286 device_t *devlist; 287 int tmp; 288 int error; 289 290 /* 291 * Before we delete the children (which we have to do because 292 * attach doesn't check for children busses correctly), we have 293 * to detach the children. Even if we didn't need to delete the 294 * children, we have to detach them. 295 */ 296 error = bus_generic_detach(brdev); 297 if (error != 0) 298 return (error); 299 300 /* 301 * Since the attach routine doesn't search for children before it 302 * attaches them to this device, we must delete them here in order 303 * for the kldload/unload case to work. If we failed to do that, then 304 * we'd get duplicate devices when cbb.ko was reloaded. 305 */ 306 device_get_children(brdev, &devlist, &numdevs); 307 for (tmp = 0; tmp < numdevs; tmp++) 308 device_delete_child(brdev, devlist[tmp]); 309 free(devlist, M_TEMP); 310 311 /* Turn off the interrupts */ 312 cbb_set(sc, CBB_SOCKET_MASK, 0); 313 314 /* reset 16-bit pcmcia bus */ 315 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 316 317 /* turn off power */ 318 cbb_power(brdev, CARD_OFF); 319 320 /* Ack the interrupt */ 321 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 322 323 /* 324 * Wait for the thread to die. kthread_exit will do a wakeup 325 * on the event thread's struct thread * so that we know it is 326 * save to proceed. IF the thread is running, set the please 327 * die flag and wait for it to comply. Since the wakeup on 328 * the event thread happens only in kthread_exit, we don't 329 * need to loop here. 330 */ 331 mtx_lock(&sc->mtx); 332 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 333 sc->flags |= CBB_KTHREAD_DONE; 334 if (sc->flags & CBB_KTHREAD_RUNNING) { 335 cv_broadcast(&sc->cv); 336 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 337 } 338 mtx_unlock(&sc->mtx); 339 340 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 341 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 342 sc->base_res); 343 mtx_destroy(&sc->mtx); 344 cv_destroy(&sc->cv); 345 cv_destroy(&sc->powercv); 346 return (0); 347 } 348 349 int 350 cbb_shutdown(device_t brdev) 351 { 352 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 353 354 /* 355 * Place the cards in reset, turn off the interrupts and power 356 * down the socket. 357 */ 358 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 359 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 360 cbb_set(sc, CBB_SOCKET_MASK, 0); 361 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 362 cbb_power(brdev, CARD_OFF); 363 364 /* 365 * For paranoia, turn off all address decoding. Really not needed, 366 * it seems, but it can't hurt 367 */ 368 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 369 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 370 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 371 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 372 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 373 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 374 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 375 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 376 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 377 return (0); 378 } 379 380 int 381 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 382 int flags, driver_intr_t *intr, void *arg, void **cookiep) 383 { 384 struct cbb_intrhand *ih; 385 struct cbb_softc *sc = device_get_softc(dev); 386 int err; 387 388 /* 389 * Well, this is no longer strictly true. You can have multiple 390 * FAST ISRs, but can't mix fast and slow, so we have to assume 391 * least common denominator until the base system supports mixing 392 * and matching better. 393 */ 394 if ((flags & INTR_FAST) != 0) 395 return (EINVAL); 396 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 397 if (ih == NULL) 398 return (ENOMEM); 399 *cookiep = ih; 400 ih->intr = intr; 401 ih->arg = arg; 402 ih->sc = sc; 403 /* 404 * XXX need to turn on ISA interrupts, if we ever support them, but 405 * XXX for now that's all we need to do. 406 */ 407 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 408 cbb_func_intr, ih, &ih->cookie); 409 if (err != 0) { 410 free(ih, M_DEVBUF); 411 return (err); 412 } 413 cbb_enable_func_intr(sc); 414 sc->flags |= CBB_CARD_OK; 415 return 0; 416 } 417 418 int 419 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 420 void *cookie) 421 { 422 struct cbb_intrhand *ih; 423 int err; 424 425 /* XXX Need to do different things for ISA interrupts. */ 426 ih = (struct cbb_intrhand *) cookie; 427 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 428 ih->cookie); 429 if (err != 0) 430 return (err); 431 free(ih, M_DEVBUF); 432 return (0); 433 } 434 435 436 void 437 cbb_driver_added(device_t brdev, driver_t *driver) 438 { 439 struct cbb_softc *sc = device_get_softc(brdev); 440 device_t *devlist; 441 device_t dev; 442 int tmp; 443 int numdevs; 444 int wake = 0; 445 446 DEVICE_IDENTIFY(driver, brdev); 447 device_get_children(brdev, &devlist, &numdevs); 448 for (tmp = 0; tmp < numdevs; tmp++) { 449 dev = devlist[tmp]; 450 if (device_get_state(dev) == DS_NOTPRESENT && 451 device_probe_and_attach(dev) == 0) 452 wake++; 453 } 454 free(devlist, M_TEMP); 455 456 if (wake > 0) { 457 mtx_lock(&sc->mtx); 458 cv_signal(&sc->cv); 459 mtx_unlock(&sc->mtx); 460 } 461 } 462 463 void 464 cbb_child_detached(device_t brdev, device_t child) 465 { 466 struct cbb_softc *sc = device_get_softc(brdev); 467 468 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 469 device_printf(brdev, "Unknown child detached: %s\n", 470 device_get_nameunit(child)); 471 } 472 473 /************************************************************************/ 474 /* Kthreads */ 475 /************************************************************************/ 476 477 void 478 cbb_event_thread(void *arg) 479 { 480 struct cbb_softc *sc = arg; 481 uint32_t status; 482 int err; 483 int not_a_card = 0; 484 485 sc->flags |= CBB_KTHREAD_RUNNING; 486 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 487 /* 488 * We take out Giant here because we need it deep, 489 * down in the bowels of the vm system for mapping the 490 * memory we need to read the CIS. In addition, since 491 * we are adding/deleting devices from the dev tree, 492 * and that code isn't MP safe, we have to hold Giant. 493 */ 494 mtx_lock(&Giant); 495 status = cbb_get(sc, CBB_SOCKET_STATE); 496 DPRINTF(("Status is 0x%x\n", status)); 497 if (!CBB_CARD_PRESENT(status)) { 498 not_a_card = 0; /* We know card type */ 499 cbb_removal(sc); 500 } else if (status & CBB_STATE_NOT_A_CARD) { 501 /* 502 * Up to 20 times, try to rescan the card when we 503 * see NOT_A_CARD. 504 */ 505 if (not_a_card++ < 20) { 506 DEVPRINTF((sc->dev, 507 "Not a card bit set, rescanning\n")); 508 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 509 } else { 510 device_printf(sc->dev, 511 "Can't determine card type\n"); 512 } 513 } else { 514 not_a_card = 0; /* We know card type */ 515 cbb_insert(sc); 516 } 517 mtx_unlock(&Giant); 518 519 /* 520 * Wait until it has been 1s since the last time we 521 * get an interrupt. We handle the rest of the interrupt 522 * at the top of the loop. Although we clear the bit in the 523 * ISR, we signal sc->cv from the detach path after we've 524 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 525 * 1s sleep here. 526 * 527 * In our ISR, we turn off the card changed interrupt. Turn 528 * them back on here before we wait for them to happen. We 529 * turn them on/off so that we can tolerate a large latency 530 * between the time we signal cbb_event_thread and it gets 531 * a chance to run. 532 */ 533 mtx_lock(&sc->mtx); 534 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 535 cv_wait(&sc->cv, &sc->mtx); 536 err = 0; 537 while (err != EWOULDBLOCK && 538 (sc->flags & CBB_KTHREAD_DONE) == 0) 539 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 540 mtx_unlock(&sc->mtx); 541 } 542 sc->flags &= ~CBB_KTHREAD_RUNNING; 543 kthread_exit(0); 544 } 545 546 /************************************************************************/ 547 /* Insert/removal */ 548 /************************************************************************/ 549 550 static void 551 cbb_insert(struct cbb_softc *sc) 552 { 553 uint32_t sockevent, sockstate; 554 555 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 556 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 557 558 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 559 sockevent, sockstate)); 560 561 if (sockstate & CBB_STATE_R2_CARD) { 562 if (sc->exca[0].pccarddev) { 563 sc->flags |= CBB_16BIT_CARD; 564 exca_insert(&sc->exca[0]); 565 } else { 566 device_printf(sc->dev, 567 "16-bit card inserted, but no pccard bus.\n"); 568 } 569 } else if (sockstate & CBB_STATE_CB_CARD) { 570 if (sc->cbdev != NULL) { 571 sc->flags &= ~CBB_16BIT_CARD; 572 CARD_ATTACH_CARD(sc->cbdev); 573 } else { 574 device_printf(sc->dev, 575 "CardBus card inserted, but no cardbus bus.\n"); 576 } 577 } else { 578 /* 579 * We should power the card down, and try again a couple of 580 * times if this happens. XXX 581 */ 582 device_printf(sc->dev, "Unsupported card type detected\n"); 583 } 584 } 585 586 static void 587 cbb_removal(struct cbb_softc *sc) 588 { 589 sc->flags &= ~CBB_CARD_OK; 590 if (sc->flags & CBB_16BIT_CARD) { 591 exca_removal(&sc->exca[0]); 592 } else { 593 if (sc->cbdev != NULL) 594 CARD_DETACH_CARD(sc->cbdev); 595 } 596 cbb_destroy_res(sc); 597 } 598 599 /************************************************************************/ 600 /* Interrupt Handler */ 601 /************************************************************************/ 602 603 /* 604 * Since we touch hardware in the worst case, we don't need to use atomic 605 * ops on the CARD_OK tests. They would save us a trip to the hardware 606 * if CARD_OK was recently cleared and the caches haven't updated yet. 607 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 608 * machine, this is about 33-66ns, whereas a trip the the hardware 609 * is about that. On slower machines, the cost is even higher, so the 610 * trip to the hardware is cheaper and achieves the same ends that 611 * a fully locked operation would give us. 612 * 613 * This is a separate routine because we'd have to use locking and/or 614 * other synchronization in cbb_intr to do this there. That would be 615 * even more expensive. 616 * 617 * I need to investigate what this means for a SMP machine with multiple 618 * CPUs servicing the ISR when an eject happens. In the case of a dirty 619 * eject, CD glitches and we might read 'card present' from the hardware 620 * due to this jitter. If we assumed that cbb_intr() ran before 621 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 622 * CD changes were clear there, then we'd know the card was gone. 623 */ 624 static void 625 cbb_func_intr(void *arg) 626 { 627 struct cbb_intrhand *ih = (struct cbb_intrhand *)arg; 628 struct cbb_softc *sc = ih->sc; 629 630 /* 631 * Make sure that the card is really there. 632 */ 633 if ((sc->flags & CBB_CARD_OK) == 0) 634 return; 635 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 636 sc->flags &= ~CBB_CARD_OK; 637 return; 638 } 639 640 /* 641 * nb: don't have to check for giant or not, since that's done 642 * in the ISR dispatch 643 */ 644 (*ih->intr)(ih->arg); 645 } 646 647 void 648 cbb_intr(void *arg) 649 { 650 struct cbb_softc *sc = arg; 651 uint32_t sockevent; 652 653 /* 654 * Read the socket event. Sometimes, the theory goes, the PCI 655 * bus is so loaded that it cannot satisfy the read request, so 656 * we get garbage back from the following read. We have to filter 657 * out the garbage so that we don't spontaneously reset the card 658 * under high load. PCI isn't supposed to act like this. No doubt 659 * this is a bug in the PCI bridge chipset (or cbb brige) that's being 660 * used in certain amd64 laptops today. Work around the issue by 661 * assuming that any bits we don't know about being set means that 662 * we got garbage. 663 */ 664 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 665 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 666 /* ack the interrupt */ 667 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 668 669 /* 670 * If anything has happened to the socket, we assume that 671 * the card is no longer OK, and we shouldn't call its 672 * ISR. We set CARD_OK as soon as we've attached the 673 * card. This helps in a noisy eject, which happens 674 * all too often when users are ejecting their PC Cards. 675 * 676 * We use this method in preference to checking to see if 677 * the card is still there because the check suffers from 678 * a race condition in the bouncing case. Prior versions 679 * of the pccard software used a similar trick and achieved 680 * excellent results. 681 */ 682 if (sockevent & CBB_SOCKET_EVENT_CD) { 683 mtx_lock(&sc->mtx); 684 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 685 sc->flags &= ~CBB_CARD_OK; 686 cbb_disable_func_intr(sc); 687 cv_signal(&sc->cv); 688 mtx_unlock(&sc->mtx); 689 } 690 /* 691 * If we get a power interrupt, wakeup anybody that might 692 * be waiting for one. 693 */ 694 if (sockevent & CBB_SOCKET_EVENT_POWER) { 695 mtx_lock(&sc->mtx); 696 sc->powerintr++; 697 cv_signal(&sc->powercv); 698 mtx_unlock(&sc->mtx); 699 } 700 } 701 /* 702 * Some chips also require us to read the old ExCA registe for 703 * card status change when we route CSC vis PCI. This isn't supposed 704 * to be required, but it clears the interrupt state on some chipsets. 705 * Maybe there's a setting that would obviate its need. Maybe we 706 * should test the status bits and deal with them, but so far we've 707 * not found any machines that don't also give us the socket status 708 * indication above. 709 * 710 * We have to call this unconditionally because some bridges deliver 711 * the event independent of the CBB_SOCKET_EVENT_CD above. 712 */ 713 exca_getb(&sc->exca[0], EXCA_CSC); 714 } 715 716 /************************************************************************/ 717 /* Generic Power functions */ 718 /************************************************************************/ 719 720 static uint32_t 721 cbb_detect_voltage(device_t brdev) 722 { 723 struct cbb_softc *sc = device_get_softc(brdev); 724 uint32_t psr; 725 uint32_t vol = CARD_UKN_CARD; 726 727 psr = cbb_get(sc, CBB_SOCKET_STATE); 728 729 if (psr & CBB_STATE_5VCARD && psr & CBB_STATE_5VSOCK) 730 vol |= CARD_5V_CARD; 731 if (psr & CBB_STATE_3VCARD && psr & CBB_STATE_3VSOCK) 732 vol |= CARD_3V_CARD; 733 if (psr & CBB_STATE_XVCARD && psr & CBB_STATE_XVSOCK) 734 vol |= CARD_XV_CARD; 735 if (psr & CBB_STATE_YVCARD && psr & CBB_STATE_YVSOCK) 736 vol |= CARD_YV_CARD; 737 738 return (vol); 739 } 740 741 static uint8_t 742 cbb_o2micro_power_hack(struct cbb_softc *sc) 743 { 744 uint8_t reg; 745 746 /* 747 * Issue #2: INT# not qualified with IRQ Routing Bit. An 748 * unexpected PCI INT# may be generated during PC Card 749 * initialization even with the IRQ Routing Bit Set with some 750 * PC Cards. 751 * 752 * This is a two part issue. The first part is that some of 753 * our older controllers have an issue in which the slot's PCI 754 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 755 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 756 * is selected (ExCA register 03h bits 3:0, of the slot, are 757 * cleared) we will generate INT# if IREQ# is asserted. The 758 * second part is because some PC Cards prematurally assert 759 * IREQ# before the ExCA registers are fully programmed. This 760 * in turn asserts INT# because ExCA register 03h bits 3:0 761 * (ISA IRQ Select) are not yet programmed. 762 * 763 * The fix for this issue, which will work for any controller 764 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 765 * (select IRQ1), of the slot, before turning on slot power. 766 * Selecting IRQ1 will result in INT# NOT being asserted 767 * (because IRQ1 is selected), and IRQ1 won't be asserted 768 * because our controllers don't generate IRQ1. 769 * 770 * Other, non O2Micro controllers will generate irq 1 in some 771 * situations, so we can't do this hack for everybody. Reports of 772 * keyboard controller's interrupts being suppressed occurred when 773 * we did this. 774 */ 775 reg = exca_getb(&sc->exca[0], EXCA_INTR); 776 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 777 return (reg); 778 } 779 780 /* 781 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 782 * we don't have an interrupt storm on power on. This has the efect of 783 * disabling card status change interrupts for the duration of poweron. 784 */ 785 static void 786 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 787 { 788 exca_putb(&sc->exca[0], EXCA_INTR, reg); 789 } 790 791 int 792 cbb_power(device_t brdev, int volts) 793 { 794 uint32_t status, sock_ctrl, mask; 795 struct cbb_softc *sc = device_get_softc(brdev); 796 int cnt, sane; 797 int retval = 0; 798 int on = 0; 799 uint8_t reg = 0; 800 801 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 802 803 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 804 switch (volts & CARD_VCCMASK) { 805 case 5: 806 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 807 on++; 808 break; 809 case 3: 810 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 811 on++; 812 break; 813 case XV: 814 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 815 on++; 816 break; 817 case YV: 818 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 819 on++; 820 break; 821 case 0: 822 break; 823 default: 824 return (0); /* power NEVER changed */ 825 } 826 827 /* VPP == VCC */ 828 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 829 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 830 831 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 832 return (1); /* no change necessary */ 833 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 834 if (volts != 0 && sc->chipset == CB_O2MICRO) 835 reg = cbb_o2micro_power_hack(sc); 836 837 /* 838 * We have to mask the card change detect interrupt while we're 839 * messing with the power. It is allowed to bounce while we're 840 * messing with power as things settle down. In addition, we mask off 841 * the card's function interrupt by routing it via the ISA bus. This 842 * bit generally only affects 16bit cards. Some bridges allow one to 843 * set another bit to have it also affect 32bit cards. Since 32bit 844 * cards are required to be better behaved, we don't bother to get 845 * into those bridge specific features. 846 */ 847 mask = cbb_get(sc, CBB_SOCKET_MASK); 848 mask |= CBB_SOCKET_MASK_POWER; 849 mask &= ~CBB_SOCKET_MASK_CD; 850 cbb_set(sc, CBB_SOCKET_MASK, mask); 851 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 852 |CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 853 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 854 if (on) { 855 mtx_lock(&sc->mtx); 856 cnt = sc->powerintr; 857 sane = 200; 858 while (!(cbb_get(sc, CBB_SOCKET_STATE) & CBB_STATE_POWER_CYCLE) && 859 cnt == sc->powerintr && sane-- > 0) 860 cv_timedwait(&sc->powercv, &sc->mtx, hz / 10); 861 mtx_unlock(&sc->mtx); 862 if (sane <= 0) 863 device_printf(sc->dev, "power timeout, doom?\n"); 864 } 865 866 /* 867 * After the power is good, we can turn off the power interrupt. 868 * However, the PC Card standard says that we must delay turning the 869 * CD bit back on for a bit to allow for bouncyness on power down 870 * (recall that we don't wait above for a power down, since we don't 871 * get an interrupt for that). We're called either from the suspend 872 * code in which case we don't want to turn card change on again, or 873 * we're called from the card insertion code, in which case the cbb 874 * thread will turn it on for us before it waits to be woken by a 875 * change event. 876 */ 877 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_POWER); 878 status = cbb_get(sc, CBB_SOCKET_STATE); 879 if (on) { 880 if ((status & CBB_STATE_POWER_CYCLE) == 0) 881 device_printf(sc->dev, "Power not on?\n"); 882 } 883 if (status & CBB_STATE_BAD_VCC_REQ) { 884 device_printf(sc->dev, "Bad Vcc requested\n"); 885 /* XXX Do we want to do something to mitigate things here? */ 886 goto done; 887 } 888 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 889 & ~CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 890 retval = 1; 891 done:; 892 if (volts != 0 && sc->chipset == CB_O2MICRO) 893 cbb_o2micro_power_hack2(sc, reg); 894 return (retval); 895 } 896 897 static int 898 cbb_current_voltage(device_t brdev) 899 { 900 struct cbb_softc *sc = device_get_softc(brdev); 901 uint32_t ctrl; 902 903 ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 904 switch (ctrl & CBB_SOCKET_CTRL_VCCMASK) { 905 case CBB_SOCKET_CTRL_VCC_5V: 906 return CARD_5V_CARD; 907 case CBB_SOCKET_CTRL_VCC_3V: 908 return CARD_3V_CARD; 909 case CBB_SOCKET_CTRL_VCC_XV: 910 return CARD_XV_CARD; 911 case CBB_SOCKET_CTRL_VCC_YV: 912 return CARD_YV_CARD; 913 } 914 return 0; 915 } 916 917 /* 918 * detect the voltage for the card, and set it. Since the power 919 * used is the square of the voltage, lower voltages is a big win 920 * and what Windows does (and what Microsoft prefers). The MS paper 921 * also talks about preferring the CIS entry as well, but that has 922 * to be done elsewhere. We also optimize power sequencing here 923 * and don't change things if we're already powered up at a supported 924 * voltage. 925 * 926 * In addition, we power up with OE disabled. We'll set it later 927 * in the power up sequence. 928 */ 929 static int 930 cbb_do_power(device_t brdev) 931 { 932 struct cbb_softc *sc = device_get_softc(brdev); 933 uint32_t voltage, curpwr; 934 uint32_t status; 935 936 /* Don't enable OE (output enable) until power stable */ 937 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 938 939 voltage = cbb_detect_voltage(brdev); 940 curpwr = cbb_current_voltage(brdev); 941 status = cbb_get(sc, CBB_SOCKET_STATE); 942 if ((status & CBB_STATE_POWER_CYCLE) && (voltage & curpwr)) 943 return 0; 944 /* Prefer lowest voltage supported */ 945 cbb_power(brdev, CARD_OFF); 946 if (voltage & CARD_YV_CARD) 947 cbb_power(brdev, CARD_VCC(YV)); 948 else if (voltage & CARD_XV_CARD) 949 cbb_power(brdev, CARD_VCC(XV)); 950 else if (voltage & CARD_3V_CARD) 951 cbb_power(brdev, CARD_VCC(3)); 952 else if (voltage & CARD_5V_CARD) 953 cbb_power(brdev, CARD_VCC(5)); 954 else { 955 device_printf(brdev, "Unknown card voltage\n"); 956 return (ENXIO); 957 } 958 return (0); 959 } 960 961 /************************************************************************/ 962 /* CardBus power functions */ 963 /************************************************************************/ 964 965 static void 966 cbb_cardbus_reset(device_t brdev) 967 { 968 struct cbb_softc *sc = device_get_softc(brdev); 969 int delay; 970 971 /* 972 * 20ms is necessary for most bridges. For some reason, the Ricoh 973 * RF5C47x bridges need 400ms. 974 */ 975 delay = sc->chipset == CB_RF5C47X ? 400 : 20; 976 977 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 978 979 tsleep(sc, PZERO, "cbbP3", hz * delay / 1000); 980 981 /* If a card exists, unreset it! */ 982 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 983 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 984 &~CBBM_BRIDGECTRL_RESET, 2); 985 tsleep(sc, PZERO, "cbbP3", hz * delay / 1000); 986 } 987 } 988 989 static int 990 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 991 { 992 struct cbb_softc *sc = device_get_softc(brdev); 993 int err; 994 995 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 996 return (ENODEV); 997 998 err = cbb_do_power(brdev); 999 if (err) 1000 return (err); 1001 cbb_cardbus_reset(brdev); 1002 return (0); 1003 } 1004 1005 static void 1006 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1007 { 1008 cbb_power(brdev, CARD_OFF); 1009 cbb_cardbus_reset(brdev); 1010 } 1011 1012 /************************************************************************/ 1013 /* CardBus Resource */ 1014 /************************************************************************/ 1015 1016 static int 1017 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1018 { 1019 int basereg; 1020 int limitreg; 1021 1022 if ((win < 0) || (win > 1)) { 1023 DEVPRINTF((brdev, 1024 "cbb_cardbus_io_open: window out of range %d\n", win)); 1025 return (EINVAL); 1026 } 1027 1028 basereg = win * 8 + CBBR_IOBASE0; 1029 limitreg = win * 8 + CBBR_IOLIMIT0; 1030 1031 pci_write_config(brdev, basereg, start, 4); 1032 pci_write_config(brdev, limitreg, end, 4); 1033 return (0); 1034 } 1035 1036 static int 1037 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1038 { 1039 int basereg; 1040 int limitreg; 1041 1042 if ((win < 0) || (win > 1)) { 1043 DEVPRINTF((brdev, 1044 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1045 return (EINVAL); 1046 } 1047 1048 basereg = win*8 + CBBR_MEMBASE0; 1049 limitreg = win*8 + CBBR_MEMLIMIT0; 1050 1051 pci_write_config(brdev, basereg, start, 4); 1052 pci_write_config(brdev, limitreg, end, 4); 1053 return (0); 1054 } 1055 1056 #define START_NONE 0xffffffff 1057 #define END_NONE 0 1058 1059 static void 1060 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1061 { 1062 uint32_t starts[2]; 1063 uint32_t ends[2]; 1064 struct cbb_reslist *rle; 1065 int align, i; 1066 uint32_t reg; 1067 1068 starts[0] = starts[1] = START_NONE; 1069 ends[0] = ends[1] = END_NONE; 1070 1071 if (type == SYS_RES_MEMORY) 1072 align = CBB_MEMALIGN; 1073 else if (type == SYS_RES_IOPORT) 1074 align = CBB_IOALIGN; 1075 else 1076 align = 1; 1077 1078 SLIST_FOREACH(rle, &sc->rl, link) { 1079 if (rle->type != type) 1080 continue; 1081 if (rle->res == NULL) 1082 continue; 1083 if (!(rman_get_flags(rle->res) & RF_ACTIVE)) 1084 continue; 1085 if (rman_get_flags(rle->res) & RF_PREFETCHABLE) 1086 i = 1; 1087 else 1088 i = 0; 1089 if (rman_get_start(rle->res) < starts[i]) 1090 starts[i] = rman_get_start(rle->res); 1091 if (rman_get_end(rle->res) > ends[i]) 1092 ends[i] = rman_get_end(rle->res); 1093 } 1094 for (i = 0; i < 2; i++) { 1095 if (starts[i] == START_NONE) 1096 continue; 1097 starts[i] &= ~(align - 1); 1098 ends[i] = ((ends[i] + align - 1) & ~(align - 1)) - 1; 1099 } 1100 if (starts[0] != START_NONE && starts[1] != START_NONE) { 1101 if (starts[0] < starts[1]) { 1102 if (ends[0] > starts[1]) { 1103 device_printf(sc->dev, "Overlapping ranges" 1104 " for prefetch and non-prefetch memory\n"); 1105 return; 1106 } 1107 } else { 1108 if (ends[1] > starts[0]) { 1109 device_printf(sc->dev, "Overlapping ranges" 1110 " for prefetch and non-prefetch memory\n"); 1111 return; 1112 } 1113 } 1114 } 1115 1116 if (type == SYS_RES_MEMORY) { 1117 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1118 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1119 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1120 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0 | 1121 CBBM_BRIDGECTRL_PREFETCH_1); 1122 if (starts[1] != START_NONE) 1123 reg |= CBBM_BRIDGECTRL_PREFETCH_1; 1124 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1125 if (bootverbose) { 1126 device_printf(sc->dev, "Opening memory:\n"); 1127 if (starts[0] != START_NONE) 1128 device_printf(sc->dev, "Normal: %#x-%#x\n", 1129 starts[0], ends[0]); 1130 if (starts[1] != START_NONE) 1131 device_printf(sc->dev, "Prefetch: %#x-%#x\n", 1132 starts[1], ends[1]); 1133 } 1134 } else if (type == SYS_RES_IOPORT) { 1135 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1136 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1137 if (bootverbose && starts[0] != START_NONE) 1138 device_printf(sc->dev, "Opening I/O: %#x-%#x\n", 1139 starts[0], ends[0]); 1140 } 1141 } 1142 1143 static int 1144 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1145 int rid, struct resource *res) 1146 { 1147 int ret; 1148 1149 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1150 type, rid, res); 1151 if (ret != 0) 1152 return (ret); 1153 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1154 return (0); 1155 } 1156 1157 static int 1158 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1159 int rid, struct resource *res) 1160 { 1161 int ret; 1162 1163 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1164 type, rid, res); 1165 if (ret != 0) 1166 return (ret); 1167 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1168 return (0); 1169 } 1170 1171 static struct resource * 1172 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1173 int *rid, u_long start, u_long end, u_long count, u_int flags) 1174 { 1175 struct cbb_softc *sc = device_get_softc(brdev); 1176 int tmp; 1177 struct resource *res; 1178 u_long align; 1179 1180 switch (type) { 1181 case SYS_RES_IRQ: 1182 tmp = rman_get_start(sc->irq_res); 1183 if (start > tmp || end < tmp || count != 1) { 1184 device_printf(child, "requested interrupt %ld-%ld," 1185 "count = %ld not supported by cbb\n", 1186 start, end, count); 1187 return (NULL); 1188 } 1189 start = end = tmp; 1190 flags |= RF_SHAREABLE; 1191 break; 1192 case SYS_RES_IOPORT: 1193 if (start <= cbb_start_32_io) 1194 start = cbb_start_32_io; 1195 if (end < start) 1196 end = start; 1197 if (count > (1 << RF_ALIGNMENT(flags))) 1198 flags = (flags & ~RF_ALIGNMENT_MASK) | 1199 rman_make_alignment_flags(count); 1200 break; 1201 case SYS_RES_MEMORY: 1202 if (start <= cbb_start_mem) 1203 start = cbb_start_mem; 1204 if (end < start) 1205 end = start; 1206 if (count < CBB_MEMALIGN) 1207 align = CBB_MEMALIGN; 1208 else 1209 align = count; 1210 if (align > (1 << RF_ALIGNMENT(flags))) 1211 flags = (flags & ~RF_ALIGNMENT_MASK) | 1212 rman_make_alignment_flags(align); 1213 break; 1214 } 1215 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1216 start, end, count, flags & ~RF_ACTIVE); 1217 if (res == NULL) { 1218 printf("cbb alloc res fail\n"); 1219 return (NULL); 1220 } 1221 cbb_insert_res(sc, res, type, *rid); 1222 if (flags & RF_ACTIVE) 1223 if (bus_activate_resource(child, type, *rid, res) != 0) { 1224 bus_release_resource(child, type, *rid, res); 1225 return (NULL); 1226 } 1227 1228 return (res); 1229 } 1230 1231 static int 1232 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1233 int rid, struct resource *res) 1234 { 1235 struct cbb_softc *sc = device_get_softc(brdev); 1236 int error; 1237 1238 if (rman_get_flags(res) & RF_ACTIVE) { 1239 error = bus_deactivate_resource(child, type, rid, res); 1240 if (error != 0) 1241 return (error); 1242 } 1243 cbb_remove_res(sc, res); 1244 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1245 type, rid, res)); 1246 } 1247 1248 /************************************************************************/ 1249 /* PC Card Power Functions */ 1250 /************************************************************************/ 1251 1252 static int 1253 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1254 { 1255 struct cbb_softc *sc = device_get_softc(brdev); 1256 int err; 1257 1258 DPRINTF(("cbb_pcic_socket_enable:\n")); 1259 1260 /* power down/up the socket to reset */ 1261 err = cbb_do_power(brdev); 1262 if (err) 1263 return (err); 1264 exca_reset(&sc->exca[0], child); 1265 1266 return (0); 1267 } 1268 1269 static void 1270 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1271 { 1272 struct cbb_softc *sc = device_get_softc(brdev); 1273 1274 DPRINTF(("cbb_pcic_socket_disable\n")); 1275 1276 /* Turn off the card's interrupt and leave it in reset */ 1277 exca_putb(&sc->exca[0], EXCA_INTR, 0); 1278 tsleep(sc, PZERO, "cbbP1", hz / 100); 1279 1280 /* power down the socket */ 1281 cbb_power(brdev, CARD_OFF); 1282 exca_putb(&sc->exca[0], EXCA_PWRCTL, 0); 1283 1284 /* wait 300ms until power fails (Tpf). */ 1285 tsleep(sc, PZERO, "cbbP1", hz * 300 / 1000); 1286 } 1287 1288 /************************************************************************/ 1289 /* POWER methods */ 1290 /************************************************************************/ 1291 1292 int 1293 cbb_power_enable_socket(device_t brdev, device_t child) 1294 { 1295 struct cbb_softc *sc = device_get_softc(brdev); 1296 1297 if (sc->flags & CBB_16BIT_CARD) 1298 return (cbb_pcic_power_enable_socket(brdev, child)); 1299 else 1300 return (cbb_cardbus_power_enable_socket(brdev, child)); 1301 } 1302 1303 void 1304 cbb_power_disable_socket(device_t brdev, device_t child) 1305 { 1306 struct cbb_softc *sc = device_get_softc(brdev); 1307 if (sc->flags & CBB_16BIT_CARD) 1308 cbb_pcic_power_disable_socket(brdev, child); 1309 else 1310 cbb_cardbus_power_disable_socket(brdev, child); 1311 } 1312 1313 static int 1314 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1315 struct resource *res) 1316 { 1317 struct cbb_softc *sc = device_get_softc(brdev); 1318 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1319 } 1320 1321 static int 1322 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1323 int rid, struct resource *res) 1324 { 1325 struct cbb_softc *sc = device_get_softc(brdev); 1326 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1327 } 1328 1329 static struct resource * 1330 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1331 u_long start, u_long end, u_long count, u_int flags) 1332 { 1333 struct resource *res = NULL; 1334 struct cbb_softc *sc = device_get_softc(brdev); 1335 int align; 1336 int tmp; 1337 1338 switch (type) { 1339 case SYS_RES_MEMORY: 1340 if (start < cbb_start_mem) 1341 start = cbb_start_mem; 1342 if (end < start) 1343 end = start; 1344 if (count < CBB_MEMALIGN) 1345 align = CBB_MEMALIGN; 1346 else 1347 align = count; 1348 if (align > (1 << RF_ALIGNMENT(flags))) 1349 flags = (flags & ~RF_ALIGNMENT_MASK) | 1350 rman_make_alignment_flags(align); 1351 break; 1352 case SYS_RES_IOPORT: 1353 if (start < cbb_start_16_io) 1354 start = cbb_start_16_io; 1355 if (end < start) 1356 end = start; 1357 break; 1358 case SYS_RES_IRQ: 1359 tmp = rman_get_start(sc->irq_res); 1360 if (start > tmp || end < tmp || count != 1) { 1361 device_printf(child, "requested interrupt %ld-%ld," 1362 "count = %ld not supported by cbb\n", 1363 start, end, count); 1364 return (NULL); 1365 } 1366 flags |= RF_SHAREABLE; 1367 start = end = rman_get_start(sc->irq_res); 1368 break; 1369 } 1370 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1371 start, end, count, flags & ~RF_ACTIVE); 1372 if (res == NULL) 1373 return (NULL); 1374 cbb_insert_res(sc, res, type, *rid); 1375 if (flags & RF_ACTIVE) { 1376 if (bus_activate_resource(child, type, *rid, res) != 0) { 1377 bus_release_resource(child, type, *rid, res); 1378 return (NULL); 1379 } 1380 } 1381 1382 return (res); 1383 } 1384 1385 static int 1386 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1387 int rid, struct resource *res) 1388 { 1389 struct cbb_softc *sc = device_get_softc(brdev); 1390 int error; 1391 1392 if (rman_get_flags(res) & RF_ACTIVE) { 1393 error = bus_deactivate_resource(child, type, rid, res); 1394 if (error != 0) 1395 return (error); 1396 } 1397 cbb_remove_res(sc, res); 1398 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1399 type, rid, res)); 1400 } 1401 1402 /************************************************************************/ 1403 /* PC Card methods */ 1404 /************************************************************************/ 1405 1406 int 1407 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1408 uint32_t flags) 1409 { 1410 struct cbb_softc *sc = device_get_softc(brdev); 1411 struct resource *res; 1412 1413 if (type != SYS_RES_MEMORY) 1414 return (EINVAL); 1415 res = cbb_find_res(sc, type, rid); 1416 if (res == NULL) { 1417 device_printf(brdev, 1418 "set_res_flags: specified rid not found\n"); 1419 return (ENOENT); 1420 } 1421 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1422 } 1423 1424 int 1425 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1426 uint32_t cardaddr, uint32_t *deltap) 1427 { 1428 struct cbb_softc *sc = device_get_softc(brdev); 1429 struct resource *res; 1430 1431 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1432 if (res == NULL) { 1433 device_printf(brdev, 1434 "set_memory_offset: specified rid not found\n"); 1435 return (ENOENT); 1436 } 1437 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1438 } 1439 1440 /************************************************************************/ 1441 /* BUS Methods */ 1442 /************************************************************************/ 1443 1444 1445 int 1446 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1447 struct resource *r) 1448 { 1449 struct cbb_softc *sc = device_get_softc(brdev); 1450 1451 if (sc->flags & CBB_16BIT_CARD) 1452 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1453 else 1454 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1455 r)); 1456 } 1457 1458 int 1459 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1460 int rid, struct resource *r) 1461 { 1462 struct cbb_softc *sc = device_get_softc(brdev); 1463 1464 if (sc->flags & CBB_16BIT_CARD) 1465 return (cbb_pcic_deactivate_resource(brdev, child, type, 1466 rid, r)); 1467 else 1468 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1469 rid, r)); 1470 } 1471 1472 struct resource * 1473 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1474 u_long start, u_long end, u_long count, u_int flags) 1475 { 1476 struct cbb_softc *sc = device_get_softc(brdev); 1477 1478 if (sc->flags & CBB_16BIT_CARD) 1479 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1480 start, end, count, flags)); 1481 else 1482 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1483 start, end, count, flags)); 1484 } 1485 1486 int 1487 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1488 struct resource *r) 1489 { 1490 struct cbb_softc *sc = device_get_softc(brdev); 1491 1492 if (sc->flags & CBB_16BIT_CARD) 1493 return (cbb_pcic_release_resource(brdev, child, type, 1494 rid, r)); 1495 else 1496 return (cbb_cardbus_release_resource(brdev, child, type, 1497 rid, r)); 1498 } 1499 1500 int 1501 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1502 { 1503 struct cbb_softc *sc = device_get_softc(brdev); 1504 1505 switch (which) { 1506 case PCIB_IVAR_BUS: 1507 *result = sc->secbus; 1508 return (0); 1509 } 1510 return (ENOENT); 1511 } 1512 1513 int 1514 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1515 { 1516 struct cbb_softc *sc = device_get_softc(brdev); 1517 1518 switch (which) { 1519 case PCIB_IVAR_BUS: 1520 sc->secbus = value; 1521 break; 1522 } 1523 return (ENOENT); 1524 } 1525 1526 /************************************************************************/ 1527 /* PCI compat methods */ 1528 /************************************************************************/ 1529 1530 int 1531 cbb_maxslots(device_t brdev) 1532 { 1533 return (0); 1534 } 1535 1536 uint32_t 1537 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1538 { 1539 uint32_t rv; 1540 1541 /* 1542 * Pass through to the next ppb up the chain (i.e. our grandparent). 1543 */ 1544 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1545 b, s, f, reg, width); 1546 return (rv); 1547 } 1548 1549 void 1550 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1551 int width) 1552 { 1553 /* 1554 * Pass through to the next ppb up the chain (i.e. our grandparent). 1555 */ 1556 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1557 b, s, f, reg, val, width); 1558 } 1559 1560 int 1561 cbb_suspend(device_t self) 1562 { 1563 int error = 0; 1564 struct cbb_softc *sc = device_get_softc(self); 1565 1566 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1567 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1568 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1569 error = bus_generic_suspend(self); 1570 return (error); 1571 } 1572 1573 int 1574 cbb_resume(device_t self) 1575 { 1576 int error = 0; 1577 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1578 uint32_t tmp; 1579 1580 /* 1581 * Some BIOSes will not save the BARs for the pci chips, so we 1582 * must do it ourselves. If the BAR is reset to 0 for an I/O 1583 * device, it will read back as 0x1, so no explicit test for 1584 * memory devices are needed. 1585 * 1586 * Note: The PCI bus code should do this automatically for us on 1587 * suspend/resume, but until it does, we have to cope. 1588 */ 1589 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1590 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1591 rman_get_start(sc->base_res))); 1592 1593 sc->chipinit(sc); 1594 1595 /* reset interrupt -- Do we really need to do this? */ 1596 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1597 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1598 1599 /* re-establish the interrupt. */ 1600 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 1601 cbb_intr, sc, &sc->intrhand)) { 1602 device_printf(self, "couldn't re-establish interrupt"); 1603 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1604 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1605 sc->base_res); 1606 sc->irq_res = NULL; 1607 sc->base_res = NULL; 1608 return (ENOMEM); 1609 } 1610 1611 /* CSC Interrupt: Card detect interrupt on */ 1612 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1613 1614 /* Signal the thread to wakeup. */ 1615 mtx_lock(&sc->mtx); 1616 cv_signal(&sc->cv); 1617 mtx_unlock(&sc->mtx); 1618 1619 error = bus_generic_resume(self); 1620 1621 return (error); 1622 } 1623 1624 int 1625 cbb_child_present(device_t self) 1626 { 1627 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1628 uint32_t sockstate; 1629 1630 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1631 return (CBB_CARD_PRESENT(sockstate) && 1632 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1633 } 1634