1 /* 2 * Copyright (c) 2002-2003 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for PCI to CardBus Bridge chips 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <machine/clock.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 120 121 #define CBB_START_MEM 0x88000000 122 #define CBB_START_32_IO 0x1000 123 #define CBB_START_16_IO 0x100 124 125 struct yenta_chipinfo { 126 uint32_t yc_id; 127 const char *yc_name; 128 int yc_chiptype; 129 } yc_chipsets[] = { 130 /* Texas Instruments chips */ 131 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 132 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 133 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 134 135 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 141 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 142 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 143 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 145 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 149 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 156 157 /* ENE */ 158 {PCIC_ID_ENE_CB710, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 164 165 /* Ricoh chips */ 166 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 167 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 168 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 169 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 170 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 171 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 172 173 /* Toshiba products */ 174 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 175 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 176 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 177 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 178 179 /* Cirrus Logic */ 180 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 181 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 182 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 183 184 /* 02Micro */ 185 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 186 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 187 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 188 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 189 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 190 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 191 /* 711E1 */ 192 193 /* sentinel */ 194 {0 /* null id */, "unknown", CB_UNKNOWN}, 195 }; 196 197 /* sysctl vars */ 198 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 199 200 /* There's no way to say TUNEABLE_LONG to get the right types */ 201 u_long cbb_start_mem = CBB_START_MEM; 202 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 203 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 204 &cbb_start_mem, CBB_START_MEM, 205 "Starting address for memory allocations"); 206 207 u_long cbb_start_16_io = CBB_START_16_IO; 208 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 209 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 210 &cbb_start_16_io, CBB_START_16_IO, 211 "Starting ioport for 16-bit cards"); 212 213 u_long cbb_start_32_io = CBB_START_32_IO; 214 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 215 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 216 &cbb_start_32_io, CBB_START_32_IO, 217 "Starting ioport for 32-bit cards"); 218 219 int cbb_debug = 0; 220 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 221 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 222 "Verbose cardbus bridge debugging"); 223 224 static int cbb_chipset(uint32_t pci_id, const char **namep); 225 static int cbb_probe(device_t brdev); 226 static void cbb_chipinit(struct cbb_softc *sc); 227 static int cbb_attach(device_t brdev); 228 static int cbb_detach(device_t brdev); 229 static int cbb_shutdown(device_t brdev); 230 static void cbb_driver_added(device_t brdev, driver_t *driver); 231 static void cbb_child_detached(device_t brdev, device_t child); 232 static void cbb_event_thread(void *arg); 233 static void cbb_insert(struct cbb_softc *sc); 234 static void cbb_removal(struct cbb_softc *sc); 235 static void cbb_intr(void *arg); 236 static int cbb_detect_voltage(device_t brdev); 237 static int cbb_power(device_t brdev, int volts); 238 static void cbb_cardbus_reset(device_t brdev); 239 static int cbb_cardbus_power_enable_socket(device_t brdev, 240 device_t child); 241 static void cbb_cardbus_power_disable_socket(device_t brdev, 242 device_t child); 243 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 244 uint32_t end); 245 static int cbb_cardbus_mem_open(device_t brdev, int win, 246 uint32_t start, uint32_t end); 247 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 248 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *res); 250 static int cbb_cardbus_deactivate_resource(device_t brdev, 251 device_t child, int type, int rid, struct resource *res); 252 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 253 device_t child, int type, int *rid, u_long start, 254 u_long end, u_long count, u_int flags); 255 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 256 int type, int rid, struct resource *res); 257 static int cbb_power_enable_socket(device_t brdev, device_t child); 258 static void cbb_power_disable_socket(device_t brdev, device_t child); 259 static int cbb_activate_resource(device_t brdev, device_t child, 260 int type, int rid, struct resource *r); 261 static int cbb_deactivate_resource(device_t brdev, device_t child, 262 int type, int rid, struct resource *r); 263 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 264 int type, int *rid, u_long start, u_long end, u_long count, 265 u_int flags); 266 static int cbb_release_resource(device_t brdev, device_t child, 267 int type, int rid, struct resource *r); 268 static int cbb_read_ivar(device_t brdev, device_t child, int which, 269 uintptr_t *result); 270 static int cbb_write_ivar(device_t brdev, device_t child, int which, 271 uintptr_t value); 272 static int cbb_maxslots(device_t brdev); 273 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 274 int reg, int width); 275 static void cbb_write_config(device_t brdev, int b, int s, int f, 276 int reg, uint32_t val, int width); 277 278 /* 279 */ 280 static __inline void 281 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 282 { 283 bus_space_write_4(sc->bst, sc->bsh, reg, val); 284 } 285 286 static __inline uint32_t 287 cbb_get(struct cbb_softc *sc, uint32_t reg) 288 { 289 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 290 } 291 292 static __inline void 293 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 294 { 295 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 296 } 297 298 static __inline void 299 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 300 { 301 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 302 } 303 304 static void 305 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 306 { 307 struct cbb_reslist *rle; 308 309 SLIST_FOREACH(rle, &sc->rl, link) { 310 if (rle->res == res) { 311 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 312 free(rle, M_DEVBUF); 313 return; 314 } 315 } 316 } 317 318 static struct resource * 319 cbb_find_res(struct cbb_softc *sc, int type, int rid) 320 { 321 struct cbb_reslist *rle; 322 323 SLIST_FOREACH(rle, &sc->rl, link) 324 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 325 return (rle->res); 326 return (NULL); 327 } 328 329 static void 330 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 331 int rid) 332 { 333 struct cbb_reslist *rle; 334 335 /* 336 * Need to record allocated resource so we can iterate through 337 * it later. 338 */ 339 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 340 if (!res) 341 panic("cbb_cardbus_alloc_resource: can't record entry!"); 342 rle->res = res; 343 rle->type = type; 344 rle->rid = rid; 345 SLIST_INSERT_HEAD(&sc->rl, rle, link); 346 } 347 348 static void 349 cbb_destroy_res(struct cbb_softc *sc) 350 { 351 struct cbb_reslist *rle; 352 353 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 354 device_printf(sc->dev, "Danger Will Robinson: Resource " 355 "left allocated! This is a bug... " 356 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 357 rman_get_start(rle->res)); 358 SLIST_REMOVE_HEAD(&sc->rl, link); 359 free(rle, M_DEVBUF); 360 } 361 } 362 363 /************************************************************************/ 364 /* Probe/Attach */ 365 /************************************************************************/ 366 367 static int 368 cbb_chipset(uint32_t pci_id, const char **namep) 369 { 370 struct yenta_chipinfo *ycp; 371 372 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 373 continue; 374 if (namep != NULL) 375 *namep = ycp->yc_name; 376 return (ycp->yc_chiptype); 377 } 378 379 static int 380 cbb_probe(device_t brdev) 381 { 382 const char *name; 383 uint32_t progif; 384 uint32_t subclass; 385 386 /* 387 * Do we know that we support the chipset? If so, then we 388 * accept the device. 389 */ 390 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 391 device_set_desc(brdev, name); 392 return (0); 393 } 394 395 /* 396 * We do support generic CardBus bridges. All that we've seen 397 * to date have progif 0 (the Yenta spec, and successors mandate 398 * this). We do not support PCI PCMCIA bridges (with one exception) 399 * with this driver since they generally are I/O mapped. Those 400 * are supported by the pcic driver. This should help us be more 401 * future proof. 402 */ 403 subclass = pci_get_subclass(brdev); 404 progif = pci_get_progif(brdev); 405 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 406 device_set_desc(brdev, "PCI-CardBus Bridge"); 407 return (0); 408 } 409 return (ENXIO); 410 } 411 412 413 /* 414 * Disable function interrupts by telling the bridge to generate IRQ1 415 * interrupts. These interrupts aren't really generated by the chip, since 416 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 417 * initialization, so this helps to work around the problem. 418 */ 419 static void 420 cbb_disable_func_intr(struct cbb_softc *sc) 421 { 422 uint8_t reg; 423 424 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 425 EXCA_INTR_IRQ_RESERVED1; 426 exca_putb(&sc->exca, EXCA_INTR, reg); 427 } 428 429 /* 430 * Enable function interrupts. We turn on function interrupts when the card 431 * requests an interrupt. The PCMCIA standard says that we should set 432 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 433 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 434 * cards. 435 */ 436 static void 437 cbb_enable_func_intr(struct cbb_softc *sc) 438 { 439 uint8_t reg; 440 441 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 442 EXCA_INTR_IRQ_NONE; 443 exca_putb(&sc->exca, EXCA_INTR, reg); 444 } 445 446 static void 447 cbb_chipinit(struct cbb_softc *sc) 448 { 449 uint32_t mux, sysctrl, reg; 450 451 /* Set CardBus latency timer */ 452 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 453 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 454 455 /* Set PCI latency timer */ 456 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 457 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 458 459 /* Enable memory access */ 460 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 461 | PCIM_CMD_MEMEN 462 | PCIM_CMD_PORTEN 463 | PCIM_CMD_BUSMASTEREN, 2); 464 465 /* disable Legacy IO */ 466 switch (sc->chipset) { 467 case CB_RF5C46X: 468 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 469 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 470 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 471 break; 472 default: 473 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 474 break; 475 } 476 477 /* Use PCI interrupt for interrupt routing */ 478 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 479 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 480 CBBM_BRIDGECTRL_INTR_IREQ_EN), 481 | CBBM_BRIDGECTRL_WRITE_POST_EN, 482 2); 483 484 /* 485 * XXX this should be a function table, ala OLDCARD. This means 486 * that we could more easily support ISA interrupts for pccard 487 * cards if we had to. 488 */ 489 switch (sc->chipset) { 490 case CB_TI113X: 491 /* 492 * The TI 1031, TI 1130 and TI 1131 all require another bit 493 * be set to enable PCI routing of interrupts, and then 494 * a bit for each of the CSC and Function interrupts we 495 * want routed. 496 */ 497 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 498 | CBBM_CBCTRL_113X_PCI_INTR | 499 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 500 1); 501 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 502 & ~(CBBM_DEVCTRL_INT_SERIAL | 503 CBBM_DEVCTRL_INT_PCI), 1); 504 break; 505 case CB_TI12XX: 506 /* 507 * Some TI 12xx (and [14][45]xx) based pci cards 508 * sometimes have issues with the MFUNC register not 509 * being initialized due to a bad EEPROM on board. 510 * Laptops that this matters on have this register 511 * properly initialized. 512 * 513 * The TI125X parts have a different register. 514 */ 515 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 516 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 517 if (mux == 0) { 518 mux = (mux & ~CBBM_MFUNC_PIN0) | 519 CBBM_MFUNC_PIN0_INTA; 520 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 521 mux = (mux & ~CBBM_MFUNC_PIN1) | 522 CBBM_MFUNC_PIN1_INTB; 523 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 524 } 525 /*FALLTHROUGH*/ 526 case CB_TI125X: 527 /* 528 * Disable zoom video. Some machines initialize this 529 * improperly and exerpience has shown that this helps 530 * prevent strange behavior. 531 */ 532 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 533 break; 534 case CB_O2MICRO: 535 /* 536 * Issue #1: INT# generated at the same time as 537 * selected ISA IRQ. When IREQ# or STSCHG# is active, 538 * in addition to the ISA IRQ being generated, INT# 539 * will also be generated at the same time. 540 * 541 * Some of the older controllers have an issue in 542 * which the slot's PCI INT# will be asserted whenever 543 * IREQ# or STSCGH# is asserted even if ExCA registers 544 * 03h or 05h have an ISA IRQ selected. 545 * 546 * The fix for this issue, which will work for any 547 * controller (old or new), is to set ExCA registers 548 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 549 * These bits are undocumented. By setting this 550 * register (of each slot) to '1010xxxxb' a routing of 551 * IREQ# to INTC# and STSCHG# to INTC# is selected. 552 * Since INTC# isn't connected there will be no 553 * unexpected PCI INT when IREQ# or STSCHG# is active. 554 * However, INTA# (slot 0) or INTB# (slot 1) will 555 * still be correctly generated if NO ISA IRQ is 556 * selected (ExCA regs 03h or 05h are cleared). 557 */ 558 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 559 reg = (reg & 0x0f) | 560 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 561 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 562 563 break; 564 case CB_TOPIC97: 565 /* 566 * Disable Zoom Video, ToPIC 97, 100. 567 */ 568 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 569 /* 570 * ToPIC 97, 100 571 * At offset 0xa1: INTERRUPT CONTROL register 572 * 0x1: Turn on INT interrupts. 573 */ 574 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 575 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 576 goto topic_common; 577 case CB_TOPIC95: 578 /* 579 * SOCKETCTRL appears to be TOPIC 95/B specific 580 */ 581 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 582 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 583 584 topic_common:; 585 /* 586 * At offset 0xa0: SLOT CONTROL 587 * 0x80 Enable CardBus Functionality 588 * 0x40 Enable CardBus and PC Card registers 589 * 0x20 Lock ID in exca regs 590 * 0x10 Write protect ID in config regs 591 * Clear the rest of the bits, which defaults the slot 592 * in legacy mode to 0x3e0 and offset 0. (legacy 593 * mode is determined elsewhere) 594 */ 595 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 596 CBBM_TOPIC_SLOTCTRL_SLOTON | 597 CBBM_TOPIC_SLOTCTRL_SLOTEN | 598 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 599 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 600 601 /* 602 * At offset 0xa3 Card Detect Control Register 603 * 0x80 CARDBUS enbale 604 * 0x01 Cleared for hardware change detect 605 */ 606 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 607 | CBBM_TOPIC_CDC_CARDBUS, 608 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 609 break; 610 } 611 612 /* 613 * Need to tell ExCA registers to CSC interrupts route via PCI 614 * interrupts. There are two ways to do this. Once is to set 615 * INTR_ENABLE and the other is to set CSC to 0. Since both 616 * methods are mutually compatible, we do both. 617 */ 618 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 619 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 620 621 cbb_disable_func_intr(sc); 622 623 /* close all memory and io windows */ 624 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 625 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 626 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 627 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 628 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 629 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 630 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 631 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 632 } 633 634 #ifndef BURN_BRIDGES 635 static void 636 cbb_powerstate_d0(device_t dev) 637 { 638 u_int32_t membase, irq; 639 640 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 641 /* Save important PCI config data. */ 642 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 643 irq = pci_read_config(dev, PCIR_INTLINE, 4); 644 645 /* Reset the power state. */ 646 device_printf(dev, "chip is in D%d power mode " 647 "-- setting to D0\n", pci_get_powerstate(dev)); 648 649 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 650 651 /* Restore PCI config data. */ 652 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 653 pci_write_config(dev, PCIR_INTLINE, irq, 4); 654 } 655 } 656 #endif 657 658 /* 659 * Print out the config space 660 */ 661 static void 662 cbb_print_config(device_t dev) 663 { 664 int i; 665 666 device_printf(dev, "PCI Configuration space:"); 667 for (i = 0; i < 256; i += 4) { 668 if (i % 16 == 0) 669 printf("\n 0x%02x: ", i); 670 printf("0x%08x ", pci_read_config(dev, i, 4)); 671 } 672 printf("\n"); 673 } 674 675 static int 676 cbb_attach(device_t brdev) 677 { 678 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 679 int rid; 680 681 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 682 cv_init(&sc->cv, "cbb cv"); 683 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 684 sc->dev = brdev; 685 sc->cbdev = NULL; 686 sc->exca.pccarddev = NULL; 687 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 688 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 689 SLIST_INIT(&sc->rl); 690 STAILQ_INIT(&sc->intr_handlers); 691 #ifndef BURN_BRIDGES 692 cbb_powerstate_d0(brdev); 693 694 /* 695 * The PCI bus code should assign us memory in the absense 696 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 697 * up something here until the PCI/acpi code properly assigns the 698 * resource. 699 */ 700 #endif 701 rid = CBBR_SOCKBASE; 702 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 703 0, ~0, 1, RF_ACTIVE); 704 if (!sc->base_res) { 705 #ifdef BURN_BRIDGES 706 device_printf(brdev, "Could not map register memory\n"); 707 mtx_destroy(&sc->mtx); 708 cv_destroy(&sc->cv); 709 return (ENOMEM); 710 #else 711 uint32_t sockbase; 712 /* 713 * Generally, the BIOS will assign this memory for us. 714 * However, newer BIOSes do not because the MS design 715 * documents have mandated that this is for the OS 716 * to assign rather than the BIOS. This driver shouldn't 717 * be doing this, but until the pci bus code (or acpi) 718 * does this, we allow CardBus bridges to work on more 719 * machines. 720 */ 721 pci_write_config(brdev, rid, 0xfffffffful, 4); 722 sockbase = pci_read_config(brdev, rid, 4); 723 sockbase = (sockbase & 0xfffffff0ul) & 724 -(sockbase & 0xfffffff0ul); 725 sc->base_res = bus_generic_alloc_resource( 726 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 727 &rid, cbb_start_mem, ~0, sockbase, 728 RF_ACTIVE | rman_make_alignment_flags(sockbase)); 729 if (!sc->base_res) { 730 device_printf(brdev, 731 "Could not grab register memory\n"); 732 mtx_destroy(&sc->mtx); 733 cv_destroy(&sc->cv); 734 return (ENOMEM); 735 } 736 sc->flags |= CBB_KLUDGE_ALLOC; 737 pci_write_config(brdev, CBBR_SOCKBASE, 738 rman_get_start(sc->base_res), 4); 739 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 740 rman_get_start(sc->base_res))); 741 #endif 742 } else { 743 DEVPRINTF((brdev, "Found memory at %08lx\n", 744 rman_get_start(sc->base_res))); 745 } 746 747 sc->bst = rman_get_bustag(sc->base_res); 748 sc->bsh = rman_get_bushandle(sc->base_res); 749 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 750 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 751 sc->exca.chipset = EXCA_CARDBUS; 752 cbb_chipinit(sc); 753 754 /* attach children */ 755 sc->cbdev = device_add_child(brdev, "cardbus", -1); 756 if (sc->cbdev == NULL) 757 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 758 else if (device_probe_and_attach(sc->cbdev) != 0) { 759 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 760 sc->cbdev = NULL; 761 } 762 763 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 764 if (sc->exca.pccarddev == NULL) 765 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 766 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) { 767 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 768 sc->exca.pccarddev = NULL; 769 } 770 771 /* Map and establish the interrupt. */ 772 rid = 0; 773 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 774 RF_SHAREABLE | RF_ACTIVE); 775 if (sc->irq_res == NULL) { 776 printf("cbb: Unable to map IRQ...\n"); 777 goto err; 778 } 779 780 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 781 cbb_intr, sc, &sc->intrhand)) { 782 device_printf(brdev, "couldn't establish interrupt"); 783 goto err; 784 } 785 786 /* reset 16-bit pcmcia bus */ 787 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 788 789 /* turn off power */ 790 cbb_power(brdev, CARD_OFF); 791 792 /* CSC Interrupt: Card detect interrupt on */ 793 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 794 795 /* reset interrupt */ 796 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 797 798 if (bootverbose) 799 cbb_print_config(brdev); 800 801 /* Start the thread */ 802 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 803 "%s", device_get_nameunit(brdev))) { 804 device_printf(brdev, "unable to create event thread.\n"); 805 panic("cbb_create_event_thread"); 806 } 807 808 return (0); 809 err: 810 if (sc->irq_res) 811 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 812 if (sc->base_res) { 813 if (sc->flags & CBB_KLUDGE_ALLOC) 814 bus_generic_release_resource(device_get_parent(brdev), 815 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 816 sc->base_res); 817 else 818 bus_release_resource(brdev, SYS_RES_MEMORY, 819 CBBR_SOCKBASE, sc->base_res); 820 } 821 mtx_destroy(&sc->mtx); 822 cv_destroy(&sc->cv); 823 return (ENOMEM); 824 } 825 826 static int 827 cbb_detach(device_t brdev) 828 { 829 struct cbb_softc *sc = device_get_softc(brdev); 830 int numdevs; 831 device_t *devlist; 832 int tmp; 833 int error; 834 835 device_get_children(brdev, &devlist, &numdevs); 836 837 error = 0; 838 for (tmp = 0; tmp < numdevs; tmp++) { 839 if (device_detach(devlist[tmp]) == 0) 840 device_delete_child(brdev, devlist[tmp]); 841 else 842 error++; 843 } 844 free(devlist, M_TEMP); 845 if (error > 0) 846 return (ENXIO); 847 848 mtx_lock(&sc->mtx); 849 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 850 sc->flags |= CBB_KTHREAD_DONE; 851 if (sc->flags & CBB_KTHREAD_RUNNING) { 852 cv_broadcast(&sc->cv); 853 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 854 } 855 mtx_unlock(&sc->mtx); 856 857 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 858 if (sc->flags & CBB_KLUDGE_ALLOC) 859 bus_generic_release_resource(device_get_parent(brdev), 860 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, sc->base_res); 861 else 862 bus_release_resource(brdev, SYS_RES_MEMORY, 863 CBBR_SOCKBASE, sc->base_res); 864 mtx_destroy(&sc->mtx); 865 cv_destroy(&sc->cv); 866 return (0); 867 } 868 869 static int 870 cbb_shutdown(device_t brdev) 871 { 872 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 873 /* properly reset everything at shutdown */ 874 875 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 876 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 877 878 cbb_set(sc, CBB_SOCKET_MASK, 0); 879 880 cbb_power(brdev, CARD_OFF); 881 882 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 883 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 884 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 885 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 886 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 887 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 888 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 889 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 890 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 891 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 892 return (0); 893 } 894 895 static int 896 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 897 int flags, driver_intr_t *intr, void *arg, void **cookiep) 898 { 899 struct cbb_intrhand *ih; 900 struct cbb_softc *sc = device_get_softc(dev); 901 902 /* 903 * You aren't allowed to have fast interrupts for pccard/cardbus 904 * things since those interrupts are PCI and shared. Since we use 905 * the PCI interrupt for the status change interrupts, it can't be 906 * free for use by the driver. Fast interrupts must not be shared. 907 */ 908 if ((flags & INTR_FAST) != 0) 909 return (EINVAL); 910 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 911 if (ih == NULL) 912 return (ENOMEM); 913 *cookiep = ih; 914 ih->intr = intr; 915 ih->arg = arg; 916 ih->flags = flags & INTR_MPSAFE; 917 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 918 cbb_enable_func_intr(sc); 919 /* 920 * XXX need to turn on ISA interrupts, if we ever support them, but 921 * XXX for now that's all we need to do. 922 */ 923 return (0); 924 } 925 926 static int 927 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 928 void *cookie) 929 { 930 struct cbb_intrhand *ih; 931 struct cbb_softc *sc = device_get_softc(dev); 932 933 /* XXX Need to do different things for ISA interrupts. */ 934 ih = (struct cbb_intrhand *) cookie; 935 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 936 free(ih, M_DEVBUF); 937 return (0); 938 } 939 940 941 static void 942 cbb_driver_added(device_t brdev, driver_t *driver) 943 { 944 struct cbb_softc *sc = device_get_softc(brdev); 945 device_t *devlist; 946 device_t dev; 947 int tmp; 948 int numdevs; 949 int wake = 0; 950 951 DEVICE_IDENTIFY(driver, brdev); 952 device_get_children(brdev, &devlist, &numdevs); 953 for (tmp = 0; tmp < numdevs; tmp++) { 954 dev = devlist[tmp]; 955 if (device_get_state(dev) == DS_NOTPRESENT && 956 device_probe_and_attach(dev) == 0) 957 wake++; 958 } 959 free(devlist, M_TEMP); 960 961 if (wake > 0) { 962 mtx_lock(&sc->mtx); 963 cv_signal(&sc->cv); 964 mtx_unlock(&sc->mtx); 965 } 966 } 967 968 static void 969 cbb_child_detached(device_t brdev, device_t child) 970 { 971 struct cbb_softc *sc = device_get_softc(brdev); 972 973 if (child != sc->cbdev && child != sc->exca.pccarddev) 974 device_printf(brdev, "Unknown child detached: %s\n", 975 device_get_nameunit(child)); 976 } 977 978 /************************************************************************/ 979 /* Kthreads */ 980 /************************************************************************/ 981 982 static void 983 cbb_event_thread(void *arg) 984 { 985 struct cbb_softc *sc = arg; 986 uint32_t status; 987 int err; 988 int not_a_card = 0; 989 990 sc->flags |= CBB_KTHREAD_RUNNING; 991 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 992 /* 993 * We take out Giant here because we need it deep, 994 * down in the bowels of the vm system for mapping the 995 * memory we need to read the CIS. In addition, since 996 * we are adding/deleting devices from the dev tree, 997 * and that code isn't MP safe, we have to hold Giant. 998 */ 999 mtx_lock(&Giant); 1000 status = cbb_get(sc, CBB_SOCKET_STATE); 1001 DPRINTF(("Status is 0x%x\n", status)); 1002 if (!CBB_CARD_PRESENT(status)) { 1003 not_a_card = 0; /* We know card type */ 1004 cbb_removal(sc); 1005 } else if (status & CBB_STATE_NOT_A_CARD) { 1006 /* 1007 * Up to 20 times, try to rescan the card when we 1008 * see NOT_A_CARD. 1009 */ 1010 if (not_a_card++ < 20) { 1011 DEVPRINTF((sc->dev, 1012 "Not a card bit set, rescanning\n")); 1013 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 1014 } else { 1015 device_printf(sc->dev, 1016 "Can't determine card type\n"); 1017 } 1018 } else { 1019 not_a_card = 0; /* We know card type */ 1020 cbb_insert(sc); 1021 } 1022 mtx_unlock(&Giant); 1023 1024 /* 1025 * Wait until it has been 1s since the last time we 1026 * get an interrupt. We handle the rest of the interrupt 1027 * at the top of the loop. Although we clear the bit in the 1028 * ISR, we signal sc->cv from the detach path after we've 1029 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 1030 * 1s sleep here. 1031 * 1032 * In our ISR, we turn off the card changed interrupt. Turn 1033 * them back on here before we wait for them to happen. We 1034 * turn them on/off so that we can tolerate a large latency 1035 * between the time we signal cbb_event_thread and it gets 1036 * a chance to run. 1037 */ 1038 mtx_lock(&sc->mtx); 1039 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1040 cv_wait(&sc->cv, &sc->mtx); 1041 err = 0; 1042 while (err != EWOULDBLOCK && 1043 (sc->flags & CBB_KTHREAD_DONE) == 0) 1044 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 1045 mtx_unlock(&sc->mtx); 1046 } 1047 sc->flags &= ~CBB_KTHREAD_RUNNING; 1048 mtx_lock(&Giant); /* kthread_exit drops */ 1049 kthread_exit(0); 1050 } 1051 1052 /************************************************************************/ 1053 /* Insert/removal */ 1054 /************************************************************************/ 1055 1056 static void 1057 cbb_insert(struct cbb_softc *sc) 1058 { 1059 uint32_t sockevent, sockstate; 1060 1061 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1062 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1063 1064 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1065 sockevent, sockstate)); 1066 1067 if (sockstate & CBB_STATE_R2_CARD) { 1068 if (sc->exca.pccarddev) 1069 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1070 exca_insert(&sc->exca); 1071 } else if (sockstate & CBB_STATE_CB_CARD) { 1072 if (sc->cbdev != NULL) { 1073 sc->flags &= ~CBB_16BIT_CARD; 1074 sc->flags |= CBB_CARD_OK; 1075 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1076 device_printf(sc->dev, 1077 "CardBus card activation failed\n"); 1078 } else { 1079 device_printf(sc->dev, 1080 "CardBus card inserted, but no cardbus bus.\n"); 1081 } 1082 } else { 1083 /* 1084 * We should power the card down, and try again a couple of 1085 * times if this happens. XXX 1086 */ 1087 device_printf(sc->dev, "Unsupported card type detected\n"); 1088 } 1089 } 1090 1091 static void 1092 cbb_removal(struct cbb_softc *sc) 1093 { 1094 if (sc->flags & CBB_16BIT_CARD) { 1095 exca_removal(&sc->exca); 1096 } else { 1097 if (sc->cbdev != NULL) 1098 CARD_DETACH_CARD(sc->cbdev); 1099 } 1100 cbb_destroy_res(sc); 1101 } 1102 1103 /************************************************************************/ 1104 /* Interrupt Handler */ 1105 /************************************************************************/ 1106 1107 static void 1108 cbb_intr(void *arg) 1109 { 1110 struct cbb_softc *sc = arg; 1111 uint32_t sockevent; 1112 struct cbb_intrhand *ih; 1113 1114 /* 1115 * This ISR needs work XXX 1116 */ 1117 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1118 if (sockevent != 0) { 1119 DPRINTF(("CBB EVENT 0x%x\n", sockevent)); 1120 /* ack the interrupt */ 1121 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1122 1123 /* 1124 * If anything has happened to the socket, we assume that 1125 * the card is no longer OK, and we shouldn't call its 1126 * ISR. We set CARD_OK as soon as we've attached the 1127 * card. This helps in a noisy eject, which happens 1128 * all too often when users are ejecting their PC Cards. 1129 * 1130 * We use this method in preference to checking to see if 1131 * the card is still there because the check suffers from 1132 * a race condition in the bouncing case. Prior versions 1133 * of the pccard software used a similar trick and achieved 1134 * excellent results. 1135 */ 1136 if (sockevent & CBB_SOCKET_EVENT_CD) { 1137 mtx_lock(&sc->mtx); 1138 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1139 sc->flags &= ~CBB_CARD_OK; 1140 cbb_disable_func_intr(sc); 1141 DPRINTF(("Waking up thread\n")); 1142 cv_signal(&sc->cv); 1143 mtx_unlock(&sc->mtx); 1144 } 1145 } 1146 /* 1147 * Some chips also require us to read the old ExCA registe for 1148 * card status change when we route CSC vis PCI. This isn't supposed 1149 * to be required, but it clears the interrupt state on some chipsets. 1150 * Maybe there's a setting that would obviate its need. Maybe we 1151 * should test the status bits and deal with them, but so far we've 1152 * not found any machines that don't also give us the socket status 1153 * indication above. 1154 * 1155 * We have to call this unconditionally because some bridges deliver 1156 * the even independent of the CBB_SOCKET_EVENT_CD above. 1157 */ 1158 exca_getb(&sc->exca, EXCA_CSC); 1159 1160 /* 1161 * If the card is OK, call all the interrupt handlers. 1162 */ 1163 if (sc->flags & CBB_CARD_OK) { 1164 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1165 if ((ih->flags & INTR_MPSAFE) != 0) 1166 mtx_lock(&Giant); 1167 (*ih->intr)(ih->arg); 1168 if ((ih->flags & INTR_MPSAFE) != 0) 1169 mtx_unlock(&Giant); 1170 } 1171 } 1172 } 1173 1174 /************************************************************************/ 1175 /* Generic Power functions */ 1176 /************************************************************************/ 1177 1178 static int 1179 cbb_detect_voltage(device_t brdev) 1180 { 1181 struct cbb_softc *sc = device_get_softc(brdev); 1182 uint32_t psr; 1183 int vol = CARD_UKN_CARD; 1184 1185 psr = cbb_get(sc, CBB_SOCKET_STATE); 1186 1187 if (psr & CBB_STATE_5VCARD) 1188 vol |= CARD_5V_CARD; 1189 if (psr & CBB_STATE_3VCARD) 1190 vol |= CARD_3V_CARD; 1191 if (psr & CBB_STATE_XVCARD) 1192 vol |= CARD_XV_CARD; 1193 if (psr & CBB_STATE_YVCARD) 1194 vol |= CARD_YV_CARD; 1195 1196 return (vol); 1197 } 1198 1199 static uint8_t 1200 cbb_o2micro_power_hack(struct cbb_softc *sc) 1201 { 1202 uint8_t reg; 1203 1204 /* 1205 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1206 * unexpected PCI INT# may be generated during PC-Card 1207 * initialization even with the IRQ Routing Bit Set with some 1208 * PC-Cards. 1209 * 1210 * This is a two part issue. The first part is that some of 1211 * our older controllers have an issue in which the slot's PCI 1212 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1213 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1214 * is selected (ExCA register 03h bits 3:0, of the slot, are 1215 * cleared) we will generate INT# if IREQ# is asserted. The 1216 * second part is because some PC-Cards prematurally assert 1217 * IREQ# before the ExCA registers are fully programmed. This 1218 * in turn asserts INT# because ExCA register 03h bits 3:0 1219 * (ISA IRQ Select) are not yet programmed. 1220 * 1221 * The fix for this issue, which will work for any controller 1222 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1223 * (select IRQ1), of the slot, before turning on slot power. 1224 * Selecting IRQ1 will result in INT# NOT being asserted 1225 * (because IRQ1 is selected), and IRQ1 won't be asserted 1226 * because our controllers don't generate IRQ1. 1227 */ 1228 reg = exca_getb(&sc->exca, EXCA_INTR); 1229 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1230 return (reg); 1231 } 1232 1233 /* 1234 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1235 * we don't have an interrupt storm on power on. This has the efect of 1236 * disabling card status change interrupts for the duration of poweron. 1237 */ 1238 static void 1239 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1240 { 1241 exca_putb(&sc->exca, EXCA_INTR, reg); 1242 } 1243 1244 static int 1245 cbb_power(device_t brdev, int volts) 1246 { 1247 uint32_t status, sock_ctrl; 1248 struct cbb_softc *sc = device_get_softc(brdev); 1249 int timeout; 1250 int retval = 0; 1251 uint32_t sockevent; 1252 uint8_t reg = 0; 1253 1254 status = cbb_get(sc, CBB_SOCKET_STATE); 1255 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1256 1257 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1258 switch (volts & CARD_VCCMASK) { 1259 case 5: 1260 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1261 break; 1262 case 3: 1263 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1264 break; 1265 case XV: 1266 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1267 break; 1268 case YV: 1269 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1270 break; 1271 case 0: 1272 break; 1273 default: 1274 return (0); /* power NEVER changed */ 1275 } 1276 1277 /* VPP == VCC */ 1278 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1279 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1280 1281 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1282 return (1); /* no change necessary */ 1283 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1284 if (volts != 0 && sc->chipset == CB_O2MICRO) 1285 reg = cbb_o2micro_power_hack(sc); 1286 1287 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1288 status = cbb_get(sc, CBB_SOCKET_STATE); 1289 1290 /* 1291 * XXX This busy wait is bogus. We should wait for a power 1292 * interrupt and then whine if the status is bad. If we're 1293 * worried about the card not coming up, then we should also 1294 * schedule a timeout which we can cancel in the power interrupt. 1295 */ 1296 timeout = 20; 1297 do { 1298 DELAY(20*1000); 1299 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1300 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1301 /* reset event status */ 1302 /* XXX should only reset EVENT_POWER */ 1303 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1304 if (timeout < 0) { 1305 printf ("VCC supply failed.\n"); 1306 goto done; 1307 } 1308 1309 /* XXX 1310 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1311 * is 20 ms, some PC-Card bridge requires longer duration. 1312 * XXX Note: We should check the stutus AFTER the delay to give time 1313 * for things to stabilize. 1314 */ 1315 DELAY(400*1000); 1316 1317 if (status & CBB_STATE_BAD_VCC_REQ) { 1318 device_printf(sc->dev, 1319 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1320 sock_ctrl ,status); 1321 printf("cbb_power: %dV\n", volts); 1322 goto done; 1323 } 1324 retval = 1; 1325 done:; 1326 if (volts != 0 && sc->chipset == CB_O2MICRO) 1327 cbb_o2micro_power_hack2(sc, reg); 1328 return (retval); 1329 } 1330 1331 /* 1332 * detect the voltage for the card, and set it. Since the power 1333 * used is the square of the voltage, lower voltages is a big win 1334 * and what Windows does (and what Microsoft prefers). The MS paper 1335 * also talks about preferring the CIS entry as well. 1336 */ 1337 static int 1338 cbb_do_power(device_t brdev) 1339 { 1340 int voltage; 1341 1342 /* Prefer lowest voltage supported */ 1343 voltage = cbb_detect_voltage(brdev); 1344 cbb_power(brdev, CARD_OFF); 1345 if (voltage & CARD_YV_CARD) 1346 cbb_power(brdev, CARD_VCC(YV)); 1347 else if (voltage & CARD_XV_CARD) 1348 cbb_power(brdev, CARD_VCC(XV)); 1349 else if (voltage & CARD_3V_CARD) 1350 cbb_power(brdev, CARD_VCC(3)); 1351 else if (voltage & CARD_5V_CARD) 1352 cbb_power(brdev, CARD_VCC(5)); 1353 else { 1354 device_printf(brdev, "Unknown card voltage\n"); 1355 return (ENXIO); 1356 } 1357 return (0); 1358 } 1359 1360 /************************************************************************/ 1361 /* CardBus power functions */ 1362 /************************************************************************/ 1363 1364 static void 1365 cbb_cardbus_reset(device_t brdev) 1366 { 1367 struct cbb_softc *sc = device_get_softc(brdev); 1368 int delay_us; 1369 1370 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1371 1372 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1373 1374 DELAY(delay_us); 1375 1376 /* If a card exists, unreset it! */ 1377 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 1378 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1379 &~CBBM_BRIDGECTRL_RESET, 2); 1380 DELAY(delay_us); 1381 } 1382 } 1383 1384 static int 1385 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1386 { 1387 struct cbb_softc *sc = device_get_softc(brdev); 1388 int err; 1389 1390 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 1391 return (ENODEV); 1392 1393 err = cbb_do_power(brdev); 1394 if (err) 1395 return (err); 1396 cbb_cardbus_reset(brdev); 1397 return (0); 1398 } 1399 1400 static void 1401 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1402 { 1403 cbb_power(brdev, CARD_OFF); 1404 cbb_cardbus_reset(brdev); 1405 } 1406 1407 /************************************************************************/ 1408 /* CardBus Resource */ 1409 /************************************************************************/ 1410 1411 static int 1412 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1413 { 1414 int basereg; 1415 int limitreg; 1416 1417 if ((win < 0) || (win > 1)) { 1418 DEVPRINTF((brdev, 1419 "cbb_cardbus_io_open: window out of range %d\n", win)); 1420 return (EINVAL); 1421 } 1422 1423 basereg = win * 8 + CBBR_IOBASE0; 1424 limitreg = win * 8 + CBBR_IOLIMIT0; 1425 1426 pci_write_config(brdev, basereg, start, 4); 1427 pci_write_config(brdev, limitreg, end, 4); 1428 return (0); 1429 } 1430 1431 static int 1432 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1433 { 1434 int basereg; 1435 int limitreg; 1436 1437 if ((win < 0) || (win > 1)) { 1438 DEVPRINTF((brdev, 1439 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1440 return (EINVAL); 1441 } 1442 1443 basereg = win*8 + CBBR_MEMBASE0; 1444 limitreg = win*8 + CBBR_MEMLIMIT0; 1445 1446 pci_write_config(brdev, basereg, start, 4); 1447 pci_write_config(brdev, limitreg, end, 4); 1448 return (0); 1449 } 1450 1451 /* 1452 * XXX The following function belongs in the pci bus layer. 1453 */ 1454 static void 1455 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1456 { 1457 uint32_t starts[2]; 1458 uint32_t ends[2]; 1459 struct cbb_reslist *rle; 1460 int align; 1461 int prefetchable[2]; 1462 uint32_t reg; 1463 1464 starts[0] = starts[1] = 0xffffffff; 1465 ends[0] = ends[1] = 0; 1466 1467 if (type == SYS_RES_MEMORY) 1468 align = CBB_MEMALIGN; 1469 else if (type == SYS_RES_IOPORT) 1470 align = CBB_IOALIGN; 1471 else 1472 align = 1; 1473 1474 /* 1475 * This looks somewhat bogus, and doesn't seem to really respect 1476 * alignment. The alignment stuff is happening too late (it 1477 * should happen at allocation time, not activation time) and 1478 * this code looks generally to be too complex for the purpose 1479 * it surves. 1480 */ 1481 SLIST_FOREACH(rle, &sc->rl, link) { 1482 if (rle->type != type) 1483 ; 1484 else if (rle->res == NULL) { 1485 device_printf(sc->dev, "WARNING: Resource not reserved? " 1486 "(type=%d, addr=%lx)\n", 1487 rle->type, rman_get_start(rle->res)); 1488 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1489 /* XXX */ 1490 } else if (starts[0] == 0xffffffff) { 1491 starts[0] = rman_get_start(rle->res); 1492 ends[0] = rman_get_end(rle->res); 1493 prefetchable[0] = 1494 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1495 } else if (rman_get_end(rle->res) > ends[0] && 1496 rman_get_start(rle->res) - ends[0] < 1497 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1498 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1499 ends[0] = rman_get_end(rle->res); 1500 } else if (rman_get_start(rle->res) < starts[0] && 1501 starts[0] - rman_get_end(rle->res) < 1502 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1503 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1504 starts[0] = rman_get_start(rle->res); 1505 } else if (starts[1] == 0xffffffff) { 1506 starts[1] = rman_get_start(rle->res); 1507 ends[1] = rman_get_end(rle->res); 1508 prefetchable[1] = 1509 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1510 } else if (rman_get_end(rle->res) > ends[1] && 1511 rman_get_start(rle->res) - ends[1] < 1512 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1513 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1514 ends[1] = rman_get_end(rle->res); 1515 } else if (rman_get_start(rle->res) < starts[1] && 1516 starts[1] - rman_get_end(rle->res) < 1517 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1518 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1519 starts[1] = rman_get_start(rle->res); 1520 } else { 1521 uint32_t diffs[2]; 1522 int win; 1523 1524 diffs[0] = diffs[1] = 0xffffffff; 1525 if (rman_get_start(rle->res) > ends[0]) 1526 diffs[0] = rman_get_start(rle->res) - ends[0]; 1527 else if (rman_get_end(rle->res) < starts[0]) 1528 diffs[0] = starts[0] - rman_get_end(rle->res); 1529 if (rman_get_start(rle->res) > ends[1]) 1530 diffs[1] = rman_get_start(rle->res) - ends[1]; 1531 else if (rman_get_end(rle->res) < starts[1]) 1532 diffs[1] = starts[1] - rman_get_end(rle->res); 1533 1534 win = (diffs[0] <= diffs[1])?0:1; 1535 if (rman_get_start(rle->res) > ends[win]) 1536 ends[win] = rman_get_end(rle->res); 1537 else if (rman_get_end(rle->res) < starts[win]) 1538 starts[win] = rman_get_start(rle->res); 1539 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1540 prefetchable[win] = 0; 1541 } 1542 1543 if (starts[0] != 0xffffffff) 1544 starts[0] -= starts[0] % align; 1545 if (starts[1] != 0xffffffff) 1546 starts[1] -= starts[1] % align; 1547 if (ends[0] % align != 0) 1548 ends[0] += align - ends[0] % align - 1; 1549 if (ends[1] % align != 0) 1550 ends[1] += align - ends[1] % align - 1; 1551 } 1552 1553 if (type == SYS_RES_MEMORY) { 1554 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1555 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1556 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1557 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1558 CBBM_BRIDGECTRL_PREFETCH_1); 1559 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1560 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1561 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1562 } else if (type == SYS_RES_IOPORT) { 1563 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1564 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1565 } 1566 } 1567 1568 static int 1569 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1570 int rid, struct resource *res) 1571 { 1572 int ret; 1573 1574 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1575 type, rid, res); 1576 if (ret != 0) 1577 return (ret); 1578 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1579 return (0); 1580 } 1581 1582 static int 1583 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1584 int rid, struct resource *res) 1585 { 1586 int ret; 1587 1588 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1589 type, rid, res); 1590 if (ret != 0) 1591 return (ret); 1592 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1593 return (0); 1594 } 1595 1596 static struct resource * 1597 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1598 int *rid, u_long start, u_long end, u_long count, u_int flags) 1599 { 1600 struct cbb_softc *sc = device_get_softc(brdev); 1601 int tmp; 1602 struct resource *res; 1603 1604 switch (type) { 1605 case SYS_RES_IRQ: 1606 tmp = rman_get_start(sc->irq_res); 1607 if (start > tmp || end < tmp || count != 1) { 1608 device_printf(child, "requested interrupt %ld-%ld," 1609 "count = %ld not supported by cbb\n", 1610 start, end, count); 1611 return (NULL); 1612 } 1613 start = end = tmp; 1614 flags |= RF_SHAREABLE; 1615 break; 1616 case SYS_RES_IOPORT: 1617 if (start <= cbb_start_32_io) 1618 start = cbb_start_32_io; 1619 if (end < start) 1620 end = start; 1621 break; 1622 case SYS_RES_MEMORY: 1623 if (start <= cbb_start_mem) 1624 start = cbb_start_mem; 1625 if (end < start) 1626 end = start; 1627 if (RF_ALIGNMENT(flags) < CBB_MEMALIGN_BITS) 1628 flags = (flags & ~RF_ALIGNMENT_MASK) | 1629 rman_make_alignment_flags(CBB_MEMALIGN); 1630 break; 1631 } 1632 1633 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1634 start, end, count, flags & ~RF_ACTIVE); 1635 if (res == NULL) { 1636 printf("cbb alloc res fail\n"); 1637 return (NULL); 1638 } 1639 cbb_insert_res(sc, res, type, *rid); 1640 if (flags & RF_ACTIVE) 1641 if (bus_activate_resource(child, type, *rid, res) != 0) { 1642 bus_release_resource(child, type, *rid, res); 1643 return (NULL); 1644 } 1645 1646 return (res); 1647 } 1648 1649 static int 1650 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1651 int rid, struct resource *res) 1652 { 1653 struct cbb_softc *sc = device_get_softc(brdev); 1654 int error; 1655 1656 if (rman_get_flags(res) & RF_ACTIVE) { 1657 error = bus_deactivate_resource(child, type, rid, res); 1658 if (error != 0) 1659 return (error); 1660 } 1661 cbb_remove_res(sc, res); 1662 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1663 type, rid, res)); 1664 } 1665 1666 /************************************************************************/ 1667 /* PC Card Power Functions */ 1668 /************************************************************************/ 1669 1670 static int 1671 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1672 { 1673 struct cbb_softc *sc = device_get_softc(brdev); 1674 int err; 1675 1676 DPRINTF(("cbb_pcic_socket_enable:\n")); 1677 1678 /* power down/up the socket to reset */ 1679 err = cbb_do_power(brdev); 1680 if (err) 1681 return (err); 1682 exca_reset(&sc->exca, child); 1683 1684 return (0); 1685 } 1686 1687 static void 1688 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1689 { 1690 struct cbb_softc *sc = device_get_softc(brdev); 1691 1692 DPRINTF(("cbb_pcic_socket_disable\n")); 1693 1694 /* reset signal asserting... */ 1695 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1696 DELAY(2*1000); 1697 1698 /* power down the socket */ 1699 cbb_power(brdev, CARD_OFF); 1700 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1701 1702 /* wait 300ms until power fails (Tpf). */ 1703 DELAY(300 * 1000); 1704 } 1705 1706 /************************************************************************/ 1707 /* POWER methods */ 1708 /************************************************************************/ 1709 1710 static int 1711 cbb_power_enable_socket(device_t brdev, device_t child) 1712 { 1713 struct cbb_softc *sc = device_get_softc(brdev); 1714 1715 if (sc->flags & CBB_16BIT_CARD) 1716 return (cbb_pcic_power_enable_socket(brdev, child)); 1717 else 1718 return (cbb_cardbus_power_enable_socket(brdev, child)); 1719 } 1720 1721 static void 1722 cbb_power_disable_socket(device_t brdev, device_t child) 1723 { 1724 struct cbb_softc *sc = device_get_softc(brdev); 1725 if (sc->flags & CBB_16BIT_CARD) 1726 cbb_pcic_power_disable_socket(brdev, child); 1727 else 1728 cbb_cardbus_power_disable_socket(brdev, child); 1729 } 1730 1731 static int 1732 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1733 struct resource *res) 1734 { 1735 struct cbb_softc *sc = device_get_softc(brdev); 1736 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1737 } 1738 1739 static int 1740 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1741 int rid, struct resource *res) 1742 { 1743 struct cbb_softc *sc = device_get_softc(brdev); 1744 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1745 } 1746 1747 static struct resource * 1748 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1749 u_long start, u_long end, u_long count, u_int flags) 1750 { 1751 struct resource *res = NULL; 1752 struct cbb_softc *sc = device_get_softc(brdev); 1753 int tmp; 1754 1755 switch (type) { 1756 case SYS_RES_MEMORY: 1757 if (start < cbb_start_mem) 1758 start = cbb_start_mem; 1759 if (end < start) 1760 end = start; 1761 flags = (flags & ~RF_ALIGNMENT_MASK) | 1762 rman_make_alignment_flags(CBB_MEMALIGN); 1763 break; 1764 case SYS_RES_IOPORT: 1765 if (start < cbb_start_16_io) 1766 start = cbb_start_16_io; 1767 if (end < start) 1768 end = start; 1769 break; 1770 case SYS_RES_IRQ: 1771 tmp = rman_get_start(sc->irq_res); 1772 if (start > tmp || end < tmp || count != 1) { 1773 device_printf(child, "requested interrupt %ld-%ld," 1774 "count = %ld not supported by cbb\n", 1775 start, end, count); 1776 return (NULL); 1777 } 1778 flags |= RF_SHAREABLE; 1779 start = end = rman_get_start(sc->irq_res); 1780 break; 1781 } 1782 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1783 start, end, count, flags & ~RF_ACTIVE); 1784 if (res == NULL) 1785 return (NULL); 1786 cbb_insert_res(sc, res, type, *rid); 1787 if (flags & RF_ACTIVE) { 1788 if (bus_activate_resource(child, type, *rid, res) != 0) { 1789 bus_release_resource(child, type, *rid, res); 1790 return (NULL); 1791 } 1792 } 1793 1794 return (res); 1795 } 1796 1797 static int 1798 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1799 int rid, struct resource *res) 1800 { 1801 struct cbb_softc *sc = device_get_softc(brdev); 1802 int error; 1803 1804 if (rman_get_flags(res) & RF_ACTIVE) { 1805 error = bus_deactivate_resource(child, type, rid, res); 1806 if (error != 0) 1807 return (error); 1808 } 1809 cbb_remove_res(sc, res); 1810 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1811 type, rid, res)); 1812 } 1813 1814 /************************************************************************/ 1815 /* PC Card methods */ 1816 /************************************************************************/ 1817 1818 static int 1819 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1820 uint32_t flags) 1821 { 1822 struct cbb_softc *sc = device_get_softc(brdev); 1823 struct resource *res; 1824 1825 if (type != SYS_RES_MEMORY) 1826 return (EINVAL); 1827 res = cbb_find_res(sc, type, rid); 1828 if (res == NULL) { 1829 device_printf(brdev, 1830 "set_res_flags: specified rid not found\n"); 1831 return (ENOENT); 1832 } 1833 return (exca_mem_set_flags(&sc->exca, res, flags)); 1834 } 1835 1836 static int 1837 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1838 uint32_t cardaddr, uint32_t *deltap) 1839 { 1840 struct cbb_softc *sc = device_get_softc(brdev); 1841 struct resource *res; 1842 1843 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1844 if (res == NULL) { 1845 device_printf(brdev, 1846 "set_memory_offset: specified rid not found\n"); 1847 return (ENOENT); 1848 } 1849 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1850 } 1851 1852 /************************************************************************/ 1853 /* BUS Methods */ 1854 /************************************************************************/ 1855 1856 1857 static int 1858 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1859 struct resource *r) 1860 { 1861 struct cbb_softc *sc = device_get_softc(brdev); 1862 1863 if (sc->flags & CBB_16BIT_CARD) 1864 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1865 else 1866 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1867 r)); 1868 } 1869 1870 static int 1871 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1872 int rid, struct resource *r) 1873 { 1874 struct cbb_softc *sc = device_get_softc(brdev); 1875 1876 if (sc->flags & CBB_16BIT_CARD) 1877 return (cbb_pcic_deactivate_resource(brdev, child, type, 1878 rid, r)); 1879 else 1880 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1881 rid, r)); 1882 } 1883 1884 static struct resource * 1885 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1886 u_long start, u_long end, u_long count, u_int flags) 1887 { 1888 struct cbb_softc *sc = device_get_softc(brdev); 1889 1890 if (sc->flags & CBB_16BIT_CARD) 1891 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1892 start, end, count, flags)); 1893 else 1894 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1895 start, end, count, flags)); 1896 } 1897 1898 static int 1899 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1900 struct resource *r) 1901 { 1902 struct cbb_softc *sc = device_get_softc(brdev); 1903 1904 if (sc->flags & CBB_16BIT_CARD) 1905 return (cbb_pcic_release_resource(brdev, child, type, 1906 rid, r)); 1907 else 1908 return (cbb_cardbus_release_resource(brdev, child, type, 1909 rid, r)); 1910 } 1911 1912 static int 1913 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1914 { 1915 struct cbb_softc *sc = device_get_softc(brdev); 1916 1917 switch (which) { 1918 case PCIB_IVAR_BUS: 1919 *result = sc->secbus; 1920 return (0); 1921 } 1922 return (ENOENT); 1923 } 1924 1925 static int 1926 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1927 { 1928 struct cbb_softc *sc = device_get_softc(brdev); 1929 1930 switch (which) { 1931 case PCIB_IVAR_BUS: 1932 sc->secbus = value; 1933 break; 1934 } 1935 return (ENOENT); 1936 } 1937 1938 /************************************************************************/ 1939 /* PCI compat methods */ 1940 /************************************************************************/ 1941 1942 static int 1943 cbb_maxslots(device_t brdev) 1944 { 1945 return (0); 1946 } 1947 1948 static uint32_t 1949 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1950 { 1951 /* 1952 * Pass through to the next ppb up the chain (i.e. our grandparent). 1953 */ 1954 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1955 b, s, f, reg, width)); 1956 } 1957 1958 static void 1959 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1960 int width) 1961 { 1962 /* 1963 * Pass through to the next ppb up the chain (i.e. our grandparent). 1964 */ 1965 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1966 b, s, f, reg, val, width); 1967 } 1968 1969 static int 1970 cbb_suspend(device_t self) 1971 { 1972 int error = 0; 1973 struct cbb_softc *sc = device_get_softc(self); 1974 1975 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1976 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1977 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1978 error = bus_generic_suspend(self); 1979 return (error); 1980 } 1981 1982 static int 1983 cbb_resume(device_t self) 1984 { 1985 int error = 0; 1986 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1987 uint32_t tmp; 1988 1989 /* 1990 * Some BIOSes will not save the BARs for the pci chips, so we 1991 * must do it ourselves. If the BAR is reset to 0 for an I/O 1992 * device, it will read back as 0x1, so no explicit test for 1993 * memory devices are needed. 1994 * 1995 * Note: The PCI bus code should do this automatically for us on 1996 * suspend/resume, but until it does, we have to cope. 1997 */ 1998 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1999 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 2000 rman_get_start(sc->base_res))); 2001 2002 cbb_chipinit(sc); 2003 2004 /* reset interrupt -- Do we really need to do this? */ 2005 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 2006 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 2007 2008 /* re-establish the interrupt. */ 2009 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 2010 &sc->intrhand)) { 2011 device_printf(self, "couldn't re-establish interrupt"); 2012 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 2013 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 2014 sc->base_res); 2015 sc->irq_res = NULL; 2016 sc->base_res = NULL; 2017 return (ENOMEM); 2018 } 2019 2020 /* CSC Interrupt: Card detect interrupt on */ 2021 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 2022 2023 /* Signal the thread to wakeup. */ 2024 mtx_lock(&sc->mtx); 2025 cv_signal(&sc->cv); 2026 mtx_unlock(&sc->mtx); 2027 2028 error = bus_generic_resume(self); 2029 2030 return (error); 2031 } 2032 2033 static int 2034 cbb_child_present(device_t self) 2035 { 2036 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 2037 uint32_t sockstate; 2038 2039 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 2040 return (CBB_CARD_PRESENT(sockstate) && 2041 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 2042 } 2043 2044 static device_method_t cbb_methods[] = { 2045 /* Device interface */ 2046 DEVMETHOD(device_probe, cbb_probe), 2047 DEVMETHOD(device_attach, cbb_attach), 2048 DEVMETHOD(device_detach, cbb_detach), 2049 DEVMETHOD(device_shutdown, cbb_shutdown), 2050 DEVMETHOD(device_suspend, cbb_suspend), 2051 DEVMETHOD(device_resume, cbb_resume), 2052 2053 /* bus methods */ 2054 DEVMETHOD(bus_print_child, bus_generic_print_child), 2055 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 2056 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 2057 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 2058 DEVMETHOD(bus_release_resource, cbb_release_resource), 2059 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 2060 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 2061 DEVMETHOD(bus_driver_added, cbb_driver_added), 2062 DEVMETHOD(bus_child_detached, cbb_child_detached), 2063 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 2064 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 2065 DEVMETHOD(bus_child_present, cbb_child_present), 2066 2067 /* 16-bit card interface */ 2068 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 2069 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 2070 2071 /* power interface */ 2072 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 2073 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 2074 2075 /* pcib compatibility interface */ 2076 DEVMETHOD(pcib_maxslots, cbb_maxslots), 2077 DEVMETHOD(pcib_read_config, cbb_read_config), 2078 DEVMETHOD(pcib_write_config, cbb_write_config), 2079 {0,0} 2080 }; 2081 2082 static driver_t cbb_driver = { 2083 "cbb", 2084 cbb_methods, 2085 sizeof(struct cbb_softc) 2086 }; 2087 2088 static devclass_t cbb_devclass; 2089 2090 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2091 MODULE_VERSION(cbb, 1); 2092 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2093