1 /* 2 * Copyright (c) 2002-2003 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/cdefs.h> 76 __FBSDID("$FreeBSD$"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/condvar.h> 82 #include <sys/errno.h> 83 #include <sys/kernel.h> 84 #include <sys/lock.h> 85 #include <sys/malloc.h> 86 #include <sys/mutex.h> 87 #include <sys/sysctl.h> 88 #include <sys/kthread.h> 89 #include <sys/bus.h> 90 #include <machine/bus.h> 91 #include <sys/rman.h> 92 #include <machine/resource.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <machine/clock.h> 97 98 #include <dev/pccard/pccardreg.h> 99 #include <dev/pccard/pccardvar.h> 100 101 #include <dev/exca/excareg.h> 102 #include <dev/exca/excavar.h> 103 104 #include <dev/pccbb/pccbbreg.h> 105 #include <dev/pccbb/pccbbvar.h> 106 107 #include "power_if.h" 108 #include "card_if.h" 109 #include "pcib_if.h" 110 111 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 112 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 113 114 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 116 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 117 pci_write_config(DEV, REG, ( \ 118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 119 120 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 121 122 #define CBB_START_MEM 0x88000000 123 #define CBB_START_32_IO 0x1000 124 #define CBB_START_16_IO 0x100 125 126 struct yenta_chipinfo { 127 uint32_t yc_id; 128 const char *yc_name; 129 int yc_chiptype; 130 } yc_chipsets[] = { 131 /* Texas Instruments chips */ 132 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 133 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 134 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 135 136 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 142 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 143 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 144 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 146 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 150 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 157 158 /* ENE */ 159 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 165 166 /* Ricoh chips */ 167 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 168 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 169 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 170 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 171 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 172 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 173 174 /* Toshiba products */ 175 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 176 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 177 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 178 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 179 180 /* Cirrus Logic */ 181 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 182 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 183 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 184 185 /* 02Micro */ 186 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 187 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 188 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 189 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 190 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 191 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 192 /* 711E1 */ 193 194 /* sentinel */ 195 {0 /* null id */, "unknown", CB_UNKNOWN}, 196 }; 197 198 /* sysctl vars */ 199 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 200 201 /* There's no way to say TUNEABLE_LONG to get the right types */ 202 u_long cbb_start_mem = CBB_START_MEM; 203 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 205 &cbb_start_mem, CBB_START_MEM, 206 "Starting address for memory allocations"); 207 208 u_long cbb_start_16_io = CBB_START_16_IO; 209 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 211 &cbb_start_16_io, CBB_START_16_IO, 212 "Starting ioport for 16-bit cards"); 213 214 u_long cbb_start_32_io = CBB_START_32_IO; 215 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 216 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 217 &cbb_start_32_io, CBB_START_32_IO, 218 "Starting ioport for 32-bit cards"); 219 220 int cbb_debug = 0; 221 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 222 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 223 "Verbose cardbus bridge debugging"); 224 225 static int cbb_chipset(uint32_t pci_id, const char **namep); 226 static int cbb_probe(device_t brdev); 227 static void cbb_chipinit(struct cbb_softc *sc); 228 static int cbb_attach(device_t brdev); 229 static int cbb_detach(device_t brdev); 230 static int cbb_shutdown(device_t brdev); 231 static void cbb_driver_added(device_t brdev, driver_t *driver); 232 static void cbb_child_detached(device_t brdev, device_t child); 233 static void cbb_event_thread(void *arg); 234 static void cbb_insert(struct cbb_softc *sc); 235 static void cbb_removal(struct cbb_softc *sc); 236 static void cbb_intr(void *arg); 237 static int cbb_detect_voltage(device_t brdev); 238 static int cbb_power(device_t brdev, int volts); 239 static void cbb_cardbus_reset(device_t brdev); 240 static int cbb_cardbus_power_enable_socket(device_t brdev, 241 device_t child); 242 static void cbb_cardbus_power_disable_socket(device_t brdev, 243 device_t child); 244 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 245 uint32_t end); 246 static int cbb_cardbus_mem_open(device_t brdev, int win, 247 uint32_t start, uint32_t end); 248 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 249 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 250 int type, int rid, struct resource *res); 251 static int cbb_cardbus_deactivate_resource(device_t brdev, 252 device_t child, int type, int rid, struct resource *res); 253 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 254 device_t child, int type, int *rid, u_long start, 255 u_long end, u_long count, u_int flags); 256 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 257 int type, int rid, struct resource *res); 258 static int cbb_power_enable_socket(device_t brdev, device_t child); 259 static void cbb_power_disable_socket(device_t brdev, device_t child); 260 static int cbb_activate_resource(device_t brdev, device_t child, 261 int type, int rid, struct resource *r); 262 static int cbb_deactivate_resource(device_t brdev, device_t child, 263 int type, int rid, struct resource *r); 264 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 265 int type, int *rid, u_long start, u_long end, u_long count, 266 u_int flags); 267 static int cbb_release_resource(device_t brdev, device_t child, 268 int type, int rid, struct resource *r); 269 static int cbb_read_ivar(device_t brdev, device_t child, int which, 270 uintptr_t *result); 271 static int cbb_write_ivar(device_t brdev, device_t child, int which, 272 uintptr_t value); 273 static int cbb_maxslots(device_t brdev); 274 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 275 int reg, int width); 276 static void cbb_write_config(device_t brdev, int b, int s, int f, 277 int reg, uint32_t val, int width); 278 279 /* 280 */ 281 static __inline void 282 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 283 { 284 bus_space_write_4(sc->bst, sc->bsh, reg, val); 285 } 286 287 static __inline uint32_t 288 cbb_get(struct cbb_softc *sc, uint32_t reg) 289 { 290 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 291 } 292 293 static __inline void 294 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 295 { 296 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 297 } 298 299 static __inline void 300 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 301 { 302 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 303 } 304 305 static void 306 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 307 { 308 struct cbb_reslist *rle; 309 310 SLIST_FOREACH(rle, &sc->rl, link) { 311 if (rle->res == res) { 312 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 313 free(rle, M_DEVBUF); 314 return; 315 } 316 } 317 } 318 319 static struct resource * 320 cbb_find_res(struct cbb_softc *sc, int type, int rid) 321 { 322 struct cbb_reslist *rle; 323 324 SLIST_FOREACH(rle, &sc->rl, link) 325 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 326 return (rle->res); 327 return (NULL); 328 } 329 330 static void 331 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 332 int rid) 333 { 334 struct cbb_reslist *rle; 335 336 /* 337 * Need to record allocated resource so we can iterate through 338 * it later. 339 */ 340 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 341 if (rle == NULL) 342 panic("cbb_cardbus_alloc_resource: can't record entry!"); 343 rle->res = res; 344 rle->type = type; 345 rle->rid = rid; 346 SLIST_INSERT_HEAD(&sc->rl, rle, link); 347 } 348 349 static void 350 cbb_destroy_res(struct cbb_softc *sc) 351 { 352 struct cbb_reslist *rle; 353 354 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 355 device_printf(sc->dev, "Danger Will Robinson: Resource " 356 "left allocated! This is a bug... " 357 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 358 rman_get_start(rle->res)); 359 SLIST_REMOVE_HEAD(&sc->rl, link); 360 free(rle, M_DEVBUF); 361 } 362 } 363 364 /************************************************************************/ 365 /* Probe/Attach */ 366 /************************************************************************/ 367 368 static int 369 cbb_chipset(uint32_t pci_id, const char **namep) 370 { 371 struct yenta_chipinfo *ycp; 372 373 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 374 continue; 375 if (namep != NULL) 376 *namep = ycp->yc_name; 377 return (ycp->yc_chiptype); 378 } 379 380 static int 381 cbb_probe(device_t brdev) 382 { 383 const char *name; 384 uint32_t progif; 385 uint32_t subclass; 386 387 /* 388 * Do we know that we support the chipset? If so, then we 389 * accept the device. 390 */ 391 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 392 device_set_desc(brdev, name); 393 return (0); 394 } 395 396 /* 397 * We do support generic CardBus bridges. All that we've seen 398 * to date have progif 0 (the Yenta spec, and successors mandate 399 * this). We do not support PCI PCMCIA bridges (with one exception) 400 * with this driver since they generally are I/O mapped. Those 401 * are supported by the pcic driver. This should help us be more 402 * future proof. 403 */ 404 subclass = pci_get_subclass(brdev); 405 progif = pci_get_progif(brdev); 406 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 407 device_set_desc(brdev, "PCI-CardBus Bridge"); 408 return (0); 409 } 410 return (ENXIO); 411 } 412 413 414 /* 415 * Disable function interrupts by telling the bridge to generate IRQ1 416 * interrupts. These interrupts aren't really generated by the chip, since 417 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 418 * initialization, so this helps to work around the problem. 419 * 420 * XXX We can't do this workaround for all chipsets, because this 421 * XXX causes interference with the keyboard because somechipsets will 422 * XXX actually signal IRQ1 over their serial interrupt connections to 423 * XXX the south bridge. Disable it it for now. 424 */ 425 static void 426 cbb_disable_func_intr(struct cbb_softc *sc) 427 { 428 #if 0 429 uint8_t reg; 430 431 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 432 EXCA_INTR_IRQ_RESERVED1; 433 exca_putb(&sc->exca, EXCA_INTR, reg); 434 #endif 435 } 436 437 /* 438 * Enable function interrupts. We turn on function interrupts when the card 439 * requests an interrupt. The PCMCIA standard says that we should set 440 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 441 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 442 * cards. 443 */ 444 static void 445 cbb_enable_func_intr(struct cbb_softc *sc) 446 { 447 uint8_t reg; 448 449 reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 450 EXCA_INTR_IRQ_NONE; 451 exca_putb(&sc->exca, EXCA_INTR, reg); 452 } 453 454 static void 455 cbb_chipinit(struct cbb_softc *sc) 456 { 457 uint32_t mux, sysctrl, reg; 458 459 /* Set CardBus latency timer */ 460 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 461 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 462 463 /* Set PCI latency timer */ 464 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 465 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 466 467 /* Enable memory access */ 468 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 469 | PCIM_CMD_MEMEN 470 | PCIM_CMD_PORTEN 471 | PCIM_CMD_BUSMASTEREN, 2); 472 473 /* disable Legacy IO */ 474 switch (sc->chipset) { 475 case CB_RF5C46X: 476 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 477 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 478 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 479 break; 480 default: 481 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 482 break; 483 } 484 485 /* Use PCI interrupt for interrupt routing */ 486 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 487 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 488 CBBM_BRIDGECTRL_INTR_IREQ_EN), 489 | CBBM_BRIDGECTRL_WRITE_POST_EN, 490 2); 491 492 /* 493 * XXX this should be a function table, ala OLDCARD. This means 494 * that we could more easily support ISA interrupts for pccard 495 * cards if we had to. 496 */ 497 switch (sc->chipset) { 498 case CB_TI113X: 499 /* 500 * The TI 1031, TI 1130 and TI 1131 all require another bit 501 * be set to enable PCI routing of interrupts, and then 502 * a bit for each of the CSC and Function interrupts we 503 * want routed. 504 */ 505 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 506 | CBBM_CBCTRL_113X_PCI_INTR | 507 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 508 1); 509 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 510 & ~(CBBM_DEVCTRL_INT_SERIAL | 511 CBBM_DEVCTRL_INT_PCI), 1); 512 break; 513 case CB_TI12XX: 514 /* 515 * Some TI 12xx (and [14][45]xx) based pci cards 516 * sometimes have issues with the MFUNC register not 517 * being initialized due to a bad EEPROM on board. 518 * Laptops that this matters on have this register 519 * properly initialized. 520 * 521 * The TI125X parts have a different register. 522 */ 523 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 524 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 525 if (mux == 0) { 526 mux = (mux & ~CBBM_MFUNC_PIN0) | 527 CBBM_MFUNC_PIN0_INTA; 528 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 529 mux = (mux & ~CBBM_MFUNC_PIN1) | 530 CBBM_MFUNC_PIN1_INTB; 531 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 532 } 533 /*FALLTHROUGH*/ 534 case CB_TI125X: 535 /* 536 * Disable zoom video. Some machines initialize this 537 * improperly and exerpience has shown that this helps 538 * prevent strange behavior. 539 */ 540 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 541 break; 542 case CB_O2MICRO: 543 /* 544 * Issue #1: INT# generated at the same time as 545 * selected ISA IRQ. When IREQ# or STSCHG# is active, 546 * in addition to the ISA IRQ being generated, INT# 547 * will also be generated at the same time. 548 * 549 * Some of the older controllers have an issue in 550 * which the slot's PCI INT# will be asserted whenever 551 * IREQ# or STSCGH# is asserted even if ExCA registers 552 * 03h or 05h have an ISA IRQ selected. 553 * 554 * The fix for this issue, which will work for any 555 * controller (old or new), is to set ExCA registers 556 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 557 * These bits are undocumented. By setting this 558 * register (of each slot) to '1010xxxxb' a routing of 559 * IREQ# to INTC# and STSCHG# to INTC# is selected. 560 * Since INTC# isn't connected there will be no 561 * unexpected PCI INT when IREQ# or STSCHG# is active. 562 * However, INTA# (slot 0) or INTB# (slot 1) will 563 * still be correctly generated if NO ISA IRQ is 564 * selected (ExCA regs 03h or 05h are cleared). 565 */ 566 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 567 reg = (reg & 0x0f) | 568 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 569 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 570 571 break; 572 case CB_TOPIC97: 573 /* 574 * Disable Zoom Video, ToPIC 97, 100. 575 */ 576 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 577 /* 578 * ToPIC 97, 100 579 * At offset 0xa1: INTERRUPT CONTROL register 580 * 0x1: Turn on INT interrupts. 581 */ 582 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 583 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 584 goto topic_common; 585 case CB_TOPIC95: 586 /* 587 * SOCKETCTRL appears to be TOPIC 95/B specific 588 */ 589 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 590 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 591 592 topic_common:; 593 /* 594 * At offset 0xa0: SLOT CONTROL 595 * 0x80 Enable CardBus Functionality 596 * 0x40 Enable CardBus and PC Card registers 597 * 0x20 Lock ID in exca regs 598 * 0x10 Write protect ID in config regs 599 * Clear the rest of the bits, which defaults the slot 600 * in legacy mode to 0x3e0 and offset 0. (legacy 601 * mode is determined elsewhere) 602 */ 603 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 604 CBBM_TOPIC_SLOTCTRL_SLOTON | 605 CBBM_TOPIC_SLOTCTRL_SLOTEN | 606 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 607 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 608 609 /* 610 * At offset 0xa3 Card Detect Control Register 611 * 0x80 CARDBUS enbale 612 * 0x01 Cleared for hardware change detect 613 */ 614 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 615 | CBBM_TOPIC_CDC_CARDBUS, 616 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 617 break; 618 } 619 620 /* 621 * Need to tell ExCA registers to CSC interrupts route via PCI 622 * interrupts. There are two ways to do this. Once is to set 623 * INTR_ENABLE and the other is to set CSC to 0. Since both 624 * methods are mutually compatible, we do both. 625 */ 626 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 627 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 628 629 cbb_disable_func_intr(sc); 630 631 /* close all memory and io windows */ 632 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 633 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 634 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 635 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 636 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 637 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 638 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 639 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 640 } 641 642 #ifndef BURN_BRIDGES 643 static void 644 cbb_powerstate_d0(device_t dev) 645 { 646 u_int32_t membase, irq; 647 648 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 649 /* Save important PCI config data. */ 650 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 651 irq = pci_read_config(dev, PCIR_INTLINE, 4); 652 653 /* Reset the power state. */ 654 device_printf(dev, "chip is in D%d power mode " 655 "-- setting to D0\n", pci_get_powerstate(dev)); 656 657 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 658 659 /* Restore PCI config data. */ 660 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 661 pci_write_config(dev, PCIR_INTLINE, irq, 4); 662 } 663 } 664 #endif 665 666 /* 667 * Print out the config space 668 */ 669 static void 670 cbb_print_config(device_t dev) 671 { 672 int i; 673 674 device_printf(dev, "PCI Configuration space:"); 675 for (i = 0; i < 256; i += 4) { 676 if (i % 16 == 0) 677 printf("\n 0x%02x: ", i); 678 printf("0x%08x ", pci_read_config(dev, i, 4)); 679 } 680 printf("\n"); 681 } 682 683 static int 684 cbb_attach(device_t brdev) 685 { 686 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 687 int rid; 688 689 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 690 cv_init(&sc->cv, "cbb cv"); 691 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 692 sc->dev = brdev; 693 sc->cbdev = NULL; 694 sc->exca.pccarddev = NULL; 695 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 696 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 697 SLIST_INIT(&sc->rl); 698 STAILQ_INIT(&sc->intr_handlers); 699 #ifndef BURN_BRIDGES 700 cbb_powerstate_d0(brdev); 701 702 /* 703 * The PCI bus code should assign us memory in the absense 704 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 705 * up something here until the PCI/acpi code properly assigns the 706 * resource. 707 */ 708 #endif 709 rid = CBBR_SOCKBASE; 710 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 711 0, ~0, 1, RF_ACTIVE); 712 if (!sc->base_res) { 713 #ifdef BURN_BRIDGES 714 device_printf(brdev, "Could not map register memory\n"); 715 mtx_destroy(&sc->mtx); 716 cv_destroy(&sc->cv); 717 return (ENOMEM); 718 #else 719 uint32_t sockbase; 720 /* 721 * Generally, the BIOS will assign this memory for us. 722 * However, newer BIOSes do not because the MS design 723 * documents have mandated that this is for the OS 724 * to assign rather than the BIOS. This driver shouldn't 725 * be doing this, but until the pci bus code (or acpi) 726 * does this, we allow CardBus bridges to work on more 727 * machines. 728 */ 729 pci_write_config(brdev, rid, 0xfffffffful, 4); 730 sockbase = pci_read_config(brdev, rid, 4); 731 sockbase = (sockbase & 0xfffffff0ul) & 732 -(sockbase & 0xfffffff0ul); 733 sc->base_res = bus_generic_alloc_resource( 734 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 735 &rid, cbb_start_mem, ~0, sockbase, 736 RF_ACTIVE | rman_make_alignment_flags(sockbase)); 737 if (!sc->base_res) { 738 device_printf(brdev, 739 "Could not grab register memory\n"); 740 mtx_destroy(&sc->mtx); 741 cv_destroy(&sc->cv); 742 return (ENOMEM); 743 } 744 sc->flags |= CBB_KLUDGE_ALLOC; 745 pci_write_config(brdev, CBBR_SOCKBASE, 746 rman_get_start(sc->base_res), 4); 747 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 748 rman_get_start(sc->base_res))); 749 #endif 750 } else { 751 DEVPRINTF((brdev, "Found memory at %08lx\n", 752 rman_get_start(sc->base_res))); 753 } 754 755 sc->bst = rman_get_bustag(sc->base_res); 756 sc->bsh = rman_get_bushandle(sc->base_res); 757 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 758 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 759 sc->exca.chipset = EXCA_CARDBUS; 760 cbb_chipinit(sc); 761 762 /* attach children */ 763 sc->cbdev = device_add_child(brdev, "cardbus", -1); 764 if (sc->cbdev == NULL) 765 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 766 else if (device_probe_and_attach(sc->cbdev) != 0) { 767 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 768 sc->cbdev = NULL; 769 } 770 771 sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); 772 if (sc->exca.pccarddev == NULL) 773 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 774 else if (device_probe_and_attach(sc->exca.pccarddev) != 0) { 775 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 776 sc->exca.pccarddev = NULL; 777 } 778 779 /* Map and establish the interrupt. */ 780 rid = 0; 781 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 782 RF_SHAREABLE | RF_ACTIVE); 783 if (sc->irq_res == NULL) { 784 printf("cbb: Unable to map IRQ...\n"); 785 goto err; 786 } 787 788 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 789 cbb_intr, sc, &sc->intrhand)) { 790 device_printf(brdev, "couldn't establish interrupt"); 791 goto err; 792 } 793 794 /* reset 16-bit pcmcia bus */ 795 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 796 797 /* turn off power */ 798 cbb_power(brdev, CARD_OFF); 799 800 /* CSC Interrupt: Card detect interrupt on */ 801 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 802 803 /* reset interrupt */ 804 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 805 806 if (bootverbose) 807 cbb_print_config(brdev); 808 809 /* Start the thread */ 810 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 811 "%s", device_get_nameunit(brdev))) { 812 device_printf(brdev, "unable to create event thread.\n"); 813 panic("cbb_create_event_thread"); 814 } 815 816 return (0); 817 err: 818 if (sc->irq_res) 819 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 820 if (sc->base_res) { 821 if (sc->flags & CBB_KLUDGE_ALLOC) 822 bus_generic_release_resource(device_get_parent(brdev), 823 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 824 sc->base_res); 825 else 826 bus_release_resource(brdev, SYS_RES_MEMORY, 827 CBBR_SOCKBASE, sc->base_res); 828 } 829 mtx_destroy(&sc->mtx); 830 cv_destroy(&sc->cv); 831 return (ENOMEM); 832 } 833 834 static int 835 cbb_detach(device_t brdev) 836 { 837 struct cbb_softc *sc = device_get_softc(brdev); 838 int numdevs; 839 device_t *devlist; 840 int tmp; 841 int error; 842 843 device_get_children(brdev, &devlist, &numdevs); 844 845 error = 0; 846 for (tmp = 0; tmp < numdevs; tmp++) { 847 if (device_detach(devlist[tmp]) == 0) 848 device_delete_child(brdev, devlist[tmp]); 849 else 850 error++; 851 } 852 free(devlist, M_TEMP); 853 if (error > 0) 854 return (ENXIO); 855 856 mtx_lock(&sc->mtx); 857 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 858 sc->flags |= CBB_KTHREAD_DONE; 859 if (sc->flags & CBB_KTHREAD_RUNNING) { 860 cv_broadcast(&sc->cv); 861 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 862 } 863 mtx_unlock(&sc->mtx); 864 865 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 866 if (sc->flags & CBB_KLUDGE_ALLOC) 867 bus_generic_release_resource(device_get_parent(brdev), 868 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, sc->base_res); 869 else 870 bus_release_resource(brdev, SYS_RES_MEMORY, 871 CBBR_SOCKBASE, sc->base_res); 872 mtx_destroy(&sc->mtx); 873 cv_destroy(&sc->cv); 874 return (0); 875 } 876 877 static int 878 cbb_shutdown(device_t brdev) 879 { 880 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 881 /* properly reset everything at shutdown */ 882 883 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 884 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 885 886 cbb_set(sc, CBB_SOCKET_MASK, 0); 887 888 cbb_power(brdev, CARD_OFF); 889 890 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 891 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 892 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 893 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 894 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 895 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 896 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 897 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 898 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 899 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 900 return (0); 901 } 902 903 static int 904 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 905 int flags, driver_intr_t *intr, void *arg, void **cookiep) 906 { 907 struct cbb_intrhand *ih; 908 struct cbb_softc *sc = device_get_softc(dev); 909 910 /* 911 * You aren't allowed to have fast interrupts for pccard/cardbus 912 * things since those interrupts are PCI and shared. Since we use 913 * the PCI interrupt for the status change interrupts, it can't be 914 * free for use by the driver. Fast interrupts must not be shared. 915 */ 916 if ((flags & INTR_FAST) != 0) 917 return (EINVAL); 918 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 919 if (ih == NULL) 920 return (ENOMEM); 921 *cookiep = ih; 922 ih->intr = intr; 923 ih->arg = arg; 924 ih->flags = flags & INTR_MPSAFE; 925 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 926 cbb_enable_func_intr(sc); 927 /* 928 * XXX need to turn on ISA interrupts, if we ever support them, but 929 * XXX for now that's all we need to do. 930 */ 931 return (0); 932 } 933 934 static int 935 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 936 void *cookie) 937 { 938 struct cbb_intrhand *ih; 939 struct cbb_softc *sc = device_get_softc(dev); 940 941 /* XXX Need to do different things for ISA interrupts. */ 942 ih = (struct cbb_intrhand *) cookie; 943 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 944 free(ih, M_DEVBUF); 945 return (0); 946 } 947 948 949 static void 950 cbb_driver_added(device_t brdev, driver_t *driver) 951 { 952 struct cbb_softc *sc = device_get_softc(brdev); 953 device_t *devlist; 954 device_t dev; 955 int tmp; 956 int numdevs; 957 int wake = 0; 958 959 DEVICE_IDENTIFY(driver, brdev); 960 device_get_children(brdev, &devlist, &numdevs); 961 for (tmp = 0; tmp < numdevs; tmp++) { 962 dev = devlist[tmp]; 963 if (device_get_state(dev) == DS_NOTPRESENT && 964 device_probe_and_attach(dev) == 0) 965 wake++; 966 } 967 free(devlist, M_TEMP); 968 969 if (wake > 0) { 970 mtx_lock(&sc->mtx); 971 cv_signal(&sc->cv); 972 mtx_unlock(&sc->mtx); 973 } 974 } 975 976 static void 977 cbb_child_detached(device_t brdev, device_t child) 978 { 979 struct cbb_softc *sc = device_get_softc(brdev); 980 981 if (child != sc->cbdev && child != sc->exca.pccarddev) 982 device_printf(brdev, "Unknown child detached: %s\n", 983 device_get_nameunit(child)); 984 } 985 986 /************************************************************************/ 987 /* Kthreads */ 988 /************************************************************************/ 989 990 static void 991 cbb_event_thread(void *arg) 992 { 993 struct cbb_softc *sc = arg; 994 uint32_t status; 995 int err; 996 int not_a_card = 0; 997 998 sc->flags |= CBB_KTHREAD_RUNNING; 999 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 1000 /* 1001 * We take out Giant here because we need it deep, 1002 * down in the bowels of the vm system for mapping the 1003 * memory we need to read the CIS. In addition, since 1004 * we are adding/deleting devices from the dev tree, 1005 * and that code isn't MP safe, we have to hold Giant. 1006 */ 1007 mtx_lock(&Giant); 1008 status = cbb_get(sc, CBB_SOCKET_STATE); 1009 DPRINTF(("Status is 0x%x\n", status)); 1010 if (!CBB_CARD_PRESENT(status)) { 1011 not_a_card = 0; /* We know card type */ 1012 cbb_removal(sc); 1013 } else if (status & CBB_STATE_NOT_A_CARD) { 1014 /* 1015 * Up to 20 times, try to rescan the card when we 1016 * see NOT_A_CARD. 1017 */ 1018 if (not_a_card++ < 20) { 1019 DEVPRINTF((sc->dev, 1020 "Not a card bit set, rescanning\n")); 1021 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 1022 } else { 1023 device_printf(sc->dev, 1024 "Can't determine card type\n"); 1025 } 1026 } else { 1027 not_a_card = 0; /* We know card type */ 1028 cbb_insert(sc); 1029 } 1030 mtx_unlock(&Giant); 1031 1032 /* 1033 * Wait until it has been 1s since the last time we 1034 * get an interrupt. We handle the rest of the interrupt 1035 * at the top of the loop. Although we clear the bit in the 1036 * ISR, we signal sc->cv from the detach path after we've 1037 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 1038 * 1s sleep here. 1039 * 1040 * In our ISR, we turn off the card changed interrupt. Turn 1041 * them back on here before we wait for them to happen. We 1042 * turn them on/off so that we can tolerate a large latency 1043 * between the time we signal cbb_event_thread and it gets 1044 * a chance to run. 1045 */ 1046 mtx_lock(&sc->mtx); 1047 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1048 cv_wait(&sc->cv, &sc->mtx); 1049 err = 0; 1050 while (err != EWOULDBLOCK && 1051 (sc->flags & CBB_KTHREAD_DONE) == 0) 1052 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 1053 mtx_unlock(&sc->mtx); 1054 } 1055 sc->flags &= ~CBB_KTHREAD_RUNNING; 1056 mtx_lock(&Giant); /* kthread_exit drops */ 1057 kthread_exit(0); 1058 } 1059 1060 /************************************************************************/ 1061 /* Insert/removal */ 1062 /************************************************************************/ 1063 1064 static void 1065 cbb_insert(struct cbb_softc *sc) 1066 { 1067 uint32_t sockevent, sockstate; 1068 1069 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1070 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1071 1072 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 1073 sockevent, sockstate)); 1074 1075 if (sockstate & CBB_STATE_R2_CARD) { 1076 if (sc->exca.pccarddev) 1077 sc->flags |= CBB_16BIT_CARD | CBB_CARD_OK; 1078 exca_insert(&sc->exca); 1079 } else if (sockstate & CBB_STATE_CB_CARD) { 1080 if (sc->cbdev != NULL) { 1081 sc->flags &= ~CBB_16BIT_CARD; 1082 sc->flags |= CBB_CARD_OK; 1083 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 1084 device_printf(sc->dev, 1085 "CardBus card activation failed\n"); 1086 } else { 1087 device_printf(sc->dev, 1088 "CardBus card inserted, but no cardbus bus.\n"); 1089 } 1090 } else { 1091 /* 1092 * We should power the card down, and try again a couple of 1093 * times if this happens. XXX 1094 */ 1095 device_printf(sc->dev, "Unsupported card type detected\n"); 1096 } 1097 } 1098 1099 static void 1100 cbb_removal(struct cbb_softc *sc) 1101 { 1102 if (sc->flags & CBB_16BIT_CARD) { 1103 exca_removal(&sc->exca); 1104 } else { 1105 if (sc->cbdev != NULL) 1106 CARD_DETACH_CARD(sc->cbdev); 1107 } 1108 cbb_destroy_res(sc); 1109 } 1110 1111 /************************************************************************/ 1112 /* Interrupt Handler */ 1113 /************************************************************************/ 1114 1115 static void 1116 cbb_intr(void *arg) 1117 { 1118 struct cbb_softc *sc = arg; 1119 uint32_t sockevent; 1120 struct cbb_intrhand *ih; 1121 1122 /* 1123 * This ISR needs work XXX 1124 */ 1125 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1126 if (sockevent != 0) { 1127 DPRINTF(("CBB EVENT 0x%x\n", sockevent)); 1128 /* ack the interrupt */ 1129 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 1130 1131 /* 1132 * If anything has happened to the socket, we assume that 1133 * the card is no longer OK, and we shouldn't call its 1134 * ISR. We set CARD_OK as soon as we've attached the 1135 * card. This helps in a noisy eject, which happens 1136 * all too often when users are ejecting their PC Cards. 1137 * 1138 * We use this method in preference to checking to see if 1139 * the card is still there because the check suffers from 1140 * a race condition in the bouncing case. Prior versions 1141 * of the pccard software used a similar trick and achieved 1142 * excellent results. 1143 */ 1144 if (sockevent & CBB_SOCKET_EVENT_CD) { 1145 mtx_lock(&sc->mtx); 1146 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1147 sc->flags &= ~CBB_CARD_OK; 1148 cbb_disable_func_intr(sc); 1149 DPRINTF(("Waking up thread\n")); 1150 cv_signal(&sc->cv); 1151 mtx_unlock(&sc->mtx); 1152 } 1153 } 1154 /* 1155 * Some chips also require us to read the old ExCA registe for 1156 * card status change when we route CSC vis PCI. This isn't supposed 1157 * to be required, but it clears the interrupt state on some chipsets. 1158 * Maybe there's a setting that would obviate its need. Maybe we 1159 * should test the status bits and deal with them, but so far we've 1160 * not found any machines that don't also give us the socket status 1161 * indication above. 1162 * 1163 * We have to call this unconditionally because some bridges deliver 1164 * the even independent of the CBB_SOCKET_EVENT_CD above. 1165 */ 1166 exca_getb(&sc->exca, EXCA_CSC); 1167 1168 /* 1169 * If the card is OK, call all the interrupt handlers. 1170 */ 1171 if (sc->flags & CBB_CARD_OK) { 1172 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1173 if ((ih->flags & INTR_MPSAFE) == 0) 1174 mtx_lock(&Giant); 1175 (*ih->intr)(ih->arg); 1176 if ((ih->flags & INTR_MPSAFE) == 0) 1177 mtx_unlock(&Giant); 1178 } 1179 } 1180 } 1181 1182 /************************************************************************/ 1183 /* Generic Power functions */ 1184 /************************************************************************/ 1185 1186 static int 1187 cbb_detect_voltage(device_t brdev) 1188 { 1189 struct cbb_softc *sc = device_get_softc(brdev); 1190 uint32_t psr; 1191 int vol = CARD_UKN_CARD; 1192 1193 psr = cbb_get(sc, CBB_SOCKET_STATE); 1194 1195 if (psr & CBB_STATE_5VCARD) 1196 vol |= CARD_5V_CARD; 1197 if (psr & CBB_STATE_3VCARD) 1198 vol |= CARD_3V_CARD; 1199 if (psr & CBB_STATE_XVCARD) 1200 vol |= CARD_XV_CARD; 1201 if (psr & CBB_STATE_YVCARD) 1202 vol |= CARD_YV_CARD; 1203 1204 return (vol); 1205 } 1206 1207 static uint8_t 1208 cbb_o2micro_power_hack(struct cbb_softc *sc) 1209 { 1210 uint8_t reg; 1211 1212 /* 1213 * Issue #2: INT# not qualified with IRQ Routing Bit. An 1214 * unexpected PCI INT# may be generated during PC-Card 1215 * initialization even with the IRQ Routing Bit Set with some 1216 * PC-Cards. 1217 * 1218 * This is a two part issue. The first part is that some of 1219 * our older controllers have an issue in which the slot's PCI 1220 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 1221 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 1222 * is selected (ExCA register 03h bits 3:0, of the slot, are 1223 * cleared) we will generate INT# if IREQ# is asserted. The 1224 * second part is because some PC-Cards prematurally assert 1225 * IREQ# before the ExCA registers are fully programmed. This 1226 * in turn asserts INT# because ExCA register 03h bits 3:0 1227 * (ISA IRQ Select) are not yet programmed. 1228 * 1229 * The fix for this issue, which will work for any controller 1230 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 1231 * (select IRQ1), of the slot, before turning on slot power. 1232 * Selecting IRQ1 will result in INT# NOT being asserted 1233 * (because IRQ1 is selected), and IRQ1 won't be asserted 1234 * because our controllers don't generate IRQ1. 1235 */ 1236 reg = exca_getb(&sc->exca, EXCA_INTR); 1237 exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1); 1238 return (reg); 1239 } 1240 1241 /* 1242 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 1243 * we don't have an interrupt storm on power on. This has the efect of 1244 * disabling card status change interrupts for the duration of poweron. 1245 */ 1246 static void 1247 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 1248 { 1249 exca_putb(&sc->exca, EXCA_INTR, reg); 1250 } 1251 1252 static int 1253 cbb_power(device_t brdev, int volts) 1254 { 1255 uint32_t status, sock_ctrl; 1256 struct cbb_softc *sc = device_get_softc(brdev); 1257 int timeout; 1258 int retval = 0; 1259 uint32_t sockevent; 1260 uint8_t reg = 0; 1261 1262 status = cbb_get(sc, CBB_SOCKET_STATE); 1263 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1264 1265 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1266 switch (volts & CARD_VCCMASK) { 1267 case 5: 1268 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1269 break; 1270 case 3: 1271 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1272 break; 1273 case XV: 1274 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 1275 break; 1276 case YV: 1277 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 1278 break; 1279 case 0: 1280 break; 1281 default: 1282 return (0); /* power NEVER changed */ 1283 } 1284 1285 /* VPP == VCC */ 1286 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1287 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1288 1289 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1290 return (1); /* no change necessary */ 1291 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 1292 if (volts != 0 && sc->chipset == CB_O2MICRO) 1293 reg = cbb_o2micro_power_hack(sc); 1294 1295 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1296 status = cbb_get(sc, CBB_SOCKET_STATE); 1297 1298 /* 1299 * XXX This busy wait is bogus. We should wait for a power 1300 * interrupt and then whine if the status is bad. If we're 1301 * worried about the card not coming up, then we should also 1302 * schedule a timeout which we can cancel in the power interrupt. 1303 */ 1304 timeout = 20; 1305 do { 1306 DELAY(20*1000); 1307 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1308 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1309 /* reset event status */ 1310 /* XXX should only reset EVENT_POWER */ 1311 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1312 if (timeout < 0) { 1313 printf ("VCC supply failed.\n"); 1314 goto done; 1315 } 1316 1317 /* XXX 1318 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1319 * is 20 ms, some PC-Card bridge requires longer duration. 1320 * XXX Note: We should check the stutus AFTER the delay to give time 1321 * for things to stabilize. 1322 */ 1323 DELAY(400*1000); 1324 1325 if (status & CBB_STATE_BAD_VCC_REQ) { 1326 device_printf(sc->dev, 1327 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1328 sock_ctrl ,status); 1329 printf("cbb_power: %dV\n", volts); 1330 goto done; 1331 } 1332 retval = 1; 1333 done:; 1334 if (volts != 0 && sc->chipset == CB_O2MICRO) 1335 cbb_o2micro_power_hack2(sc, reg); 1336 return (retval); 1337 } 1338 1339 /* 1340 * detect the voltage for the card, and set it. Since the power 1341 * used is the square of the voltage, lower voltages is a big win 1342 * and what Windows does (and what Microsoft prefers). The MS paper 1343 * also talks about preferring the CIS entry as well. 1344 */ 1345 static int 1346 cbb_do_power(device_t brdev) 1347 { 1348 int voltage; 1349 1350 /* Prefer lowest voltage supported */ 1351 voltage = cbb_detect_voltage(brdev); 1352 cbb_power(brdev, CARD_OFF); 1353 if (voltage & CARD_YV_CARD) 1354 cbb_power(brdev, CARD_VCC(YV)); 1355 else if (voltage & CARD_XV_CARD) 1356 cbb_power(brdev, CARD_VCC(XV)); 1357 else if (voltage & CARD_3V_CARD) 1358 cbb_power(brdev, CARD_VCC(3)); 1359 else if (voltage & CARD_5V_CARD) 1360 cbb_power(brdev, CARD_VCC(5)); 1361 else { 1362 device_printf(brdev, "Unknown card voltage\n"); 1363 return (ENXIO); 1364 } 1365 return (0); 1366 } 1367 1368 /************************************************************************/ 1369 /* CardBus power functions */ 1370 /************************************************************************/ 1371 1372 static void 1373 cbb_cardbus_reset(device_t brdev) 1374 { 1375 struct cbb_softc *sc = device_get_softc(brdev); 1376 int delay_us; 1377 1378 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1379 1380 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1381 1382 DELAY(delay_us); 1383 1384 /* If a card exists, unreset it! */ 1385 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 1386 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1387 &~CBBM_BRIDGECTRL_RESET, 2); 1388 DELAY(delay_us); 1389 } 1390 } 1391 1392 static int 1393 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1394 { 1395 struct cbb_softc *sc = device_get_softc(brdev); 1396 int err; 1397 1398 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 1399 return (ENODEV); 1400 1401 err = cbb_do_power(brdev); 1402 if (err) 1403 return (err); 1404 cbb_cardbus_reset(brdev); 1405 return (0); 1406 } 1407 1408 static void 1409 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1410 { 1411 cbb_power(brdev, CARD_OFF); 1412 cbb_cardbus_reset(brdev); 1413 } 1414 1415 /************************************************************************/ 1416 /* CardBus Resource */ 1417 /************************************************************************/ 1418 1419 static int 1420 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1421 { 1422 int basereg; 1423 int limitreg; 1424 1425 if ((win < 0) || (win > 1)) { 1426 DEVPRINTF((brdev, 1427 "cbb_cardbus_io_open: window out of range %d\n", win)); 1428 return (EINVAL); 1429 } 1430 1431 basereg = win * 8 + CBBR_IOBASE0; 1432 limitreg = win * 8 + CBBR_IOLIMIT0; 1433 1434 pci_write_config(brdev, basereg, start, 4); 1435 pci_write_config(brdev, limitreg, end, 4); 1436 return (0); 1437 } 1438 1439 static int 1440 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1441 { 1442 int basereg; 1443 int limitreg; 1444 1445 if ((win < 0) || (win > 1)) { 1446 DEVPRINTF((brdev, 1447 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1448 return (EINVAL); 1449 } 1450 1451 basereg = win*8 + CBBR_MEMBASE0; 1452 limitreg = win*8 + CBBR_MEMLIMIT0; 1453 1454 pci_write_config(brdev, basereg, start, 4); 1455 pci_write_config(brdev, limitreg, end, 4); 1456 return (0); 1457 } 1458 1459 /* 1460 * XXX The following function belongs in the pci bus layer. 1461 */ 1462 static void 1463 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1464 { 1465 uint32_t starts[2]; 1466 uint32_t ends[2]; 1467 struct cbb_reslist *rle; 1468 int align; 1469 int prefetchable[2]; 1470 uint32_t reg; 1471 1472 starts[0] = starts[1] = 0xffffffff; 1473 ends[0] = ends[1] = 0; 1474 1475 if (type == SYS_RES_MEMORY) 1476 align = CBB_MEMALIGN; 1477 else if (type == SYS_RES_IOPORT) 1478 align = CBB_IOALIGN; 1479 else 1480 align = 1; 1481 1482 /* 1483 * This looks somewhat bogus, and doesn't seem to really respect 1484 * alignment. The alignment stuff is happening too late (it 1485 * should happen at allocation time, not activation time) and 1486 * this code looks generally to be too complex for the purpose 1487 * it surves. 1488 */ 1489 SLIST_FOREACH(rle, &sc->rl, link) { 1490 if (rle->type != type) 1491 ; 1492 else if (rle->res == NULL) { 1493 device_printf(sc->dev, "WARNING: Resource not reserved? " 1494 "(type=%d, addr=%lx)\n", 1495 rle->type, rman_get_start(rle->res)); 1496 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1497 /* XXX */ 1498 } else if (starts[0] == 0xffffffff) { 1499 starts[0] = rman_get_start(rle->res); 1500 ends[0] = rman_get_end(rle->res); 1501 prefetchable[0] = 1502 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1503 } else if (rman_get_end(rle->res) > ends[0] && 1504 rman_get_start(rle->res) - ends[0] < 1505 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1506 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1507 ends[0] = rman_get_end(rle->res); 1508 } else if (rman_get_start(rle->res) < starts[0] && 1509 starts[0] - rman_get_end(rle->res) < 1510 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1511 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1512 starts[0] = rman_get_start(rle->res); 1513 } else if (starts[1] == 0xffffffff) { 1514 starts[1] = rman_get_start(rle->res); 1515 ends[1] = rman_get_end(rle->res); 1516 prefetchable[1] = 1517 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1518 } else if (rman_get_end(rle->res) > ends[1] && 1519 rman_get_start(rle->res) - ends[1] < 1520 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1521 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1522 ends[1] = rman_get_end(rle->res); 1523 } else if (rman_get_start(rle->res) < starts[1] && 1524 starts[1] - rman_get_end(rle->res) < 1525 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1526 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1527 starts[1] = rman_get_start(rle->res); 1528 } else { 1529 uint32_t diffs[2]; 1530 int win; 1531 1532 diffs[0] = diffs[1] = 0xffffffff; 1533 if (rman_get_start(rle->res) > ends[0]) 1534 diffs[0] = rman_get_start(rle->res) - ends[0]; 1535 else if (rman_get_end(rle->res) < starts[0]) 1536 diffs[0] = starts[0] - rman_get_end(rle->res); 1537 if (rman_get_start(rle->res) > ends[1]) 1538 diffs[1] = rman_get_start(rle->res) - ends[1]; 1539 else if (rman_get_end(rle->res) < starts[1]) 1540 diffs[1] = starts[1] - rman_get_end(rle->res); 1541 1542 win = (diffs[0] <= diffs[1])?0:1; 1543 if (rman_get_start(rle->res) > ends[win]) 1544 ends[win] = rman_get_end(rle->res); 1545 else if (rman_get_end(rle->res) < starts[win]) 1546 starts[win] = rman_get_start(rle->res); 1547 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1548 prefetchable[win] = 0; 1549 } 1550 1551 if (starts[0] != 0xffffffff) 1552 starts[0] -= starts[0] % align; 1553 if (starts[1] != 0xffffffff) 1554 starts[1] -= starts[1] % align; 1555 if (ends[0] % align != 0) 1556 ends[0] += align - ends[0] % align - 1; 1557 if (ends[1] % align != 0) 1558 ends[1] += align - ends[1] % align - 1; 1559 } 1560 1561 if (type == SYS_RES_MEMORY) { 1562 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1563 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1564 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1565 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1566 CBBM_BRIDGECTRL_PREFETCH_1); 1567 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1568 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1569 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1570 } else if (type == SYS_RES_IOPORT) { 1571 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1572 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1573 } 1574 } 1575 1576 static int 1577 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1578 int rid, struct resource *res) 1579 { 1580 int ret; 1581 1582 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1583 type, rid, res); 1584 if (ret != 0) 1585 return (ret); 1586 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1587 return (0); 1588 } 1589 1590 static int 1591 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1592 int rid, struct resource *res) 1593 { 1594 int ret; 1595 1596 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1597 type, rid, res); 1598 if (ret != 0) 1599 return (ret); 1600 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1601 return (0); 1602 } 1603 1604 static struct resource * 1605 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1606 int *rid, u_long start, u_long end, u_long count, u_int flags) 1607 { 1608 struct cbb_softc *sc = device_get_softc(brdev); 1609 int tmp; 1610 struct resource *res; 1611 1612 switch (type) { 1613 case SYS_RES_IRQ: 1614 tmp = rman_get_start(sc->irq_res); 1615 if (start > tmp || end < tmp || count != 1) { 1616 device_printf(child, "requested interrupt %ld-%ld," 1617 "count = %ld not supported by cbb\n", 1618 start, end, count); 1619 return (NULL); 1620 } 1621 start = end = tmp; 1622 flags |= RF_SHAREABLE; 1623 break; 1624 case SYS_RES_IOPORT: 1625 if (start <= cbb_start_32_io) 1626 start = cbb_start_32_io; 1627 if (end < start) 1628 end = start; 1629 break; 1630 case SYS_RES_MEMORY: 1631 if (start <= cbb_start_mem) 1632 start = cbb_start_mem; 1633 if (end < start) 1634 end = start; 1635 if (RF_ALIGNMENT(flags) < CBB_MEMALIGN_BITS) 1636 flags = (flags & ~RF_ALIGNMENT_MASK) | 1637 rman_make_alignment_flags(CBB_MEMALIGN); 1638 break; 1639 } 1640 1641 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1642 start, end, count, flags & ~RF_ACTIVE); 1643 if (res == NULL) { 1644 printf("cbb alloc res fail\n"); 1645 return (NULL); 1646 } 1647 cbb_insert_res(sc, res, type, *rid); 1648 if (flags & RF_ACTIVE) 1649 if (bus_activate_resource(child, type, *rid, res) != 0) { 1650 bus_release_resource(child, type, *rid, res); 1651 return (NULL); 1652 } 1653 1654 return (res); 1655 } 1656 1657 static int 1658 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1659 int rid, struct resource *res) 1660 { 1661 struct cbb_softc *sc = device_get_softc(brdev); 1662 int error; 1663 1664 if (rman_get_flags(res) & RF_ACTIVE) { 1665 error = bus_deactivate_resource(child, type, rid, res); 1666 if (error != 0) 1667 return (error); 1668 } 1669 cbb_remove_res(sc, res); 1670 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1671 type, rid, res)); 1672 } 1673 1674 /************************************************************************/ 1675 /* PC Card Power Functions */ 1676 /************************************************************************/ 1677 1678 static int 1679 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1680 { 1681 struct cbb_softc *sc = device_get_softc(brdev); 1682 int err; 1683 1684 DPRINTF(("cbb_pcic_socket_enable:\n")); 1685 1686 /* power down/up the socket to reset */ 1687 err = cbb_do_power(brdev); 1688 if (err) 1689 return (err); 1690 exca_reset(&sc->exca, child); 1691 1692 return (0); 1693 } 1694 1695 static void 1696 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1697 { 1698 struct cbb_softc *sc = device_get_softc(brdev); 1699 1700 DPRINTF(("cbb_pcic_socket_disable\n")); 1701 1702 /* reset signal asserting... */ 1703 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1704 DELAY(2*1000); 1705 1706 /* power down the socket */ 1707 cbb_power(brdev, CARD_OFF); 1708 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1709 1710 /* wait 300ms until power fails (Tpf). */ 1711 DELAY(300 * 1000); 1712 } 1713 1714 /************************************************************************/ 1715 /* POWER methods */ 1716 /************************************************************************/ 1717 1718 static int 1719 cbb_power_enable_socket(device_t brdev, device_t child) 1720 { 1721 struct cbb_softc *sc = device_get_softc(brdev); 1722 1723 if (sc->flags & CBB_16BIT_CARD) 1724 return (cbb_pcic_power_enable_socket(brdev, child)); 1725 else 1726 return (cbb_cardbus_power_enable_socket(brdev, child)); 1727 } 1728 1729 static void 1730 cbb_power_disable_socket(device_t brdev, device_t child) 1731 { 1732 struct cbb_softc *sc = device_get_softc(brdev); 1733 if (sc->flags & CBB_16BIT_CARD) 1734 cbb_pcic_power_disable_socket(brdev, child); 1735 else 1736 cbb_cardbus_power_disable_socket(brdev, child); 1737 } 1738 1739 static int 1740 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1741 struct resource *res) 1742 { 1743 struct cbb_softc *sc = device_get_softc(brdev); 1744 return (exca_activate_resource(&sc->exca, child, type, rid, res)); 1745 } 1746 1747 static int 1748 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1749 int rid, struct resource *res) 1750 { 1751 struct cbb_softc *sc = device_get_softc(brdev); 1752 return (exca_deactivate_resource(&sc->exca, child, type, rid, res)); 1753 } 1754 1755 static struct resource * 1756 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1757 u_long start, u_long end, u_long count, u_int flags) 1758 { 1759 struct resource *res = NULL; 1760 struct cbb_softc *sc = device_get_softc(brdev); 1761 int tmp; 1762 1763 switch (type) { 1764 case SYS_RES_MEMORY: 1765 if (start < cbb_start_mem) 1766 start = cbb_start_mem; 1767 if (end < start) 1768 end = start; 1769 flags = (flags & ~RF_ALIGNMENT_MASK) | 1770 rman_make_alignment_flags(CBB_MEMALIGN); 1771 break; 1772 case SYS_RES_IOPORT: 1773 if (start < cbb_start_16_io) 1774 start = cbb_start_16_io; 1775 if (end < start) 1776 end = start; 1777 break; 1778 case SYS_RES_IRQ: 1779 tmp = rman_get_start(sc->irq_res); 1780 if (start > tmp || end < tmp || count != 1) { 1781 device_printf(child, "requested interrupt %ld-%ld," 1782 "count = %ld not supported by cbb\n", 1783 start, end, count); 1784 return (NULL); 1785 } 1786 flags |= RF_SHAREABLE; 1787 start = end = rman_get_start(sc->irq_res); 1788 break; 1789 } 1790 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1791 start, end, count, flags & ~RF_ACTIVE); 1792 if (res == NULL) 1793 return (NULL); 1794 cbb_insert_res(sc, res, type, *rid); 1795 if (flags & RF_ACTIVE) { 1796 if (bus_activate_resource(child, type, *rid, res) != 0) { 1797 bus_release_resource(child, type, *rid, res); 1798 return (NULL); 1799 } 1800 } 1801 1802 return (res); 1803 } 1804 1805 static int 1806 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1807 int rid, struct resource *res) 1808 { 1809 struct cbb_softc *sc = device_get_softc(brdev); 1810 int error; 1811 1812 if (rman_get_flags(res) & RF_ACTIVE) { 1813 error = bus_deactivate_resource(child, type, rid, res); 1814 if (error != 0) 1815 return (error); 1816 } 1817 cbb_remove_res(sc, res); 1818 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1819 type, rid, res)); 1820 } 1821 1822 /************************************************************************/ 1823 /* PC Card methods */ 1824 /************************************************************************/ 1825 1826 static int 1827 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1828 uint32_t flags) 1829 { 1830 struct cbb_softc *sc = device_get_softc(brdev); 1831 struct resource *res; 1832 1833 if (type != SYS_RES_MEMORY) 1834 return (EINVAL); 1835 res = cbb_find_res(sc, type, rid); 1836 if (res == NULL) { 1837 device_printf(brdev, 1838 "set_res_flags: specified rid not found\n"); 1839 return (ENOENT); 1840 } 1841 return (exca_mem_set_flags(&sc->exca, res, flags)); 1842 } 1843 1844 static int 1845 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1846 uint32_t cardaddr, uint32_t *deltap) 1847 { 1848 struct cbb_softc *sc = device_get_softc(brdev); 1849 struct resource *res; 1850 1851 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1852 if (res == NULL) { 1853 device_printf(brdev, 1854 "set_memory_offset: specified rid not found\n"); 1855 return (ENOENT); 1856 } 1857 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1858 } 1859 1860 /************************************************************************/ 1861 /* BUS Methods */ 1862 /************************************************************************/ 1863 1864 1865 static int 1866 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1867 struct resource *r) 1868 { 1869 struct cbb_softc *sc = device_get_softc(brdev); 1870 1871 if (sc->flags & CBB_16BIT_CARD) 1872 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1873 else 1874 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1875 r)); 1876 } 1877 1878 static int 1879 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1880 int rid, struct resource *r) 1881 { 1882 struct cbb_softc *sc = device_get_softc(brdev); 1883 1884 if (sc->flags & CBB_16BIT_CARD) 1885 return (cbb_pcic_deactivate_resource(brdev, child, type, 1886 rid, r)); 1887 else 1888 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1889 rid, r)); 1890 } 1891 1892 static struct resource * 1893 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1894 u_long start, u_long end, u_long count, u_int flags) 1895 { 1896 struct cbb_softc *sc = device_get_softc(brdev); 1897 1898 if (sc->flags & CBB_16BIT_CARD) 1899 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1900 start, end, count, flags)); 1901 else 1902 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1903 start, end, count, flags)); 1904 } 1905 1906 static int 1907 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1908 struct resource *r) 1909 { 1910 struct cbb_softc *sc = device_get_softc(brdev); 1911 1912 if (sc->flags & CBB_16BIT_CARD) 1913 return (cbb_pcic_release_resource(brdev, child, type, 1914 rid, r)); 1915 else 1916 return (cbb_cardbus_release_resource(brdev, child, type, 1917 rid, r)); 1918 } 1919 1920 static int 1921 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1922 { 1923 struct cbb_softc *sc = device_get_softc(brdev); 1924 1925 switch (which) { 1926 case PCIB_IVAR_BUS: 1927 *result = sc->secbus; 1928 return (0); 1929 } 1930 return (ENOENT); 1931 } 1932 1933 static int 1934 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1935 { 1936 struct cbb_softc *sc = device_get_softc(brdev); 1937 1938 switch (which) { 1939 case PCIB_IVAR_BUS: 1940 sc->secbus = value; 1941 break; 1942 } 1943 return (ENOENT); 1944 } 1945 1946 /************************************************************************/ 1947 /* PCI compat methods */ 1948 /************************************************************************/ 1949 1950 static int 1951 cbb_maxslots(device_t brdev) 1952 { 1953 return (0); 1954 } 1955 1956 static uint32_t 1957 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1958 { 1959 /* 1960 * Pass through to the next ppb up the chain (i.e. our grandparent). 1961 */ 1962 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1963 b, s, f, reg, width)); 1964 } 1965 1966 static void 1967 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1968 int width) 1969 { 1970 /* 1971 * Pass through to the next ppb up the chain (i.e. our grandparent). 1972 */ 1973 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1974 b, s, f, reg, val, width); 1975 } 1976 1977 static int 1978 cbb_suspend(device_t self) 1979 { 1980 int error = 0; 1981 struct cbb_softc *sc = device_get_softc(self); 1982 1983 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1984 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1985 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1986 error = bus_generic_suspend(self); 1987 return (error); 1988 } 1989 1990 static int 1991 cbb_resume(device_t self) 1992 { 1993 int error = 0; 1994 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1995 uint32_t tmp; 1996 1997 /* 1998 * Some BIOSes will not save the BARs for the pci chips, so we 1999 * must do it ourselves. If the BAR is reset to 0 for an I/O 2000 * device, it will read back as 0x1, so no explicit test for 2001 * memory devices are needed. 2002 * 2003 * Note: The PCI bus code should do this automatically for us on 2004 * suspend/resume, but until it does, we have to cope. 2005 */ 2006 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 2007 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 2008 rman_get_start(sc->base_res))); 2009 2010 cbb_chipinit(sc); 2011 2012 /* reset interrupt -- Do we really need to do this? */ 2013 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 2014 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 2015 2016 /* re-establish the interrupt. */ 2017 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 2018 &sc->intrhand)) { 2019 device_printf(self, "couldn't re-establish interrupt"); 2020 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 2021 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 2022 sc->base_res); 2023 sc->irq_res = NULL; 2024 sc->base_res = NULL; 2025 return (ENOMEM); 2026 } 2027 2028 /* CSC Interrupt: Card detect interrupt on */ 2029 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 2030 2031 /* Signal the thread to wakeup. */ 2032 mtx_lock(&sc->mtx); 2033 cv_signal(&sc->cv); 2034 mtx_unlock(&sc->mtx); 2035 2036 error = bus_generic_resume(self); 2037 2038 return (error); 2039 } 2040 2041 static int 2042 cbb_child_present(device_t self) 2043 { 2044 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 2045 uint32_t sockstate; 2046 2047 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 2048 return (CBB_CARD_PRESENT(sockstate) && 2049 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 2050 } 2051 2052 static device_method_t cbb_methods[] = { 2053 /* Device interface */ 2054 DEVMETHOD(device_probe, cbb_probe), 2055 DEVMETHOD(device_attach, cbb_attach), 2056 DEVMETHOD(device_detach, cbb_detach), 2057 DEVMETHOD(device_shutdown, cbb_shutdown), 2058 DEVMETHOD(device_suspend, cbb_suspend), 2059 DEVMETHOD(device_resume, cbb_resume), 2060 2061 /* bus methods */ 2062 DEVMETHOD(bus_print_child, bus_generic_print_child), 2063 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 2064 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 2065 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 2066 DEVMETHOD(bus_release_resource, cbb_release_resource), 2067 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 2068 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 2069 DEVMETHOD(bus_driver_added, cbb_driver_added), 2070 DEVMETHOD(bus_child_detached, cbb_child_detached), 2071 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 2072 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 2073 DEVMETHOD(bus_child_present, cbb_child_present), 2074 2075 /* 16-bit card interface */ 2076 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 2077 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 2078 2079 /* power interface */ 2080 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 2081 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 2082 2083 /* pcib compatibility interface */ 2084 DEVMETHOD(pcib_maxslots, cbb_maxslots), 2085 DEVMETHOD(pcib_read_config, cbb_read_config), 2086 DEVMETHOD(pcib_write_config, cbb_write_config), 2087 {0,0} 2088 }; 2089 2090 static driver_t cbb_driver = { 2091 "cbb", 2092 cbb_methods, 2093 sizeof(struct cbb_softc) 2094 }; 2095 2096 static devclass_t cbb_devclass; 2097 2098 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 2099 MODULE_VERSION(cbb, 1); 2100 MODULE_DEPEND(cbb, exca, 1, 1, 1); 2101