1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * and PCI to PCMCIA Bridge chips 62 * and ISA to PCMCIA host adapters 63 * and C Bus to PCMCIA host adapters 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include <sys/param.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/module.h> 86 #include <sys/kthread.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mutex.h> 90 #include <sys/proc.h> 91 #include <sys/rman.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 #include <machine/bus.h> 95 #include <machine/resource.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <machine/clock.h> 100 101 #include <dev/pccard/pccardreg.h> 102 #include <dev/pccard/pccardvar.h> 103 104 #include <dev/exca/excareg.h> 105 #include <dev/exca/excavar.h> 106 107 #include <dev/pccbb/pccbbreg.h> 108 #include <dev/pccbb/pccbbvar.h> 109 110 #include "power_if.h" 111 #include "card_if.h" 112 #include "pcib_if.h" 113 114 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 115 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 116 117 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 118 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 119 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 120 pci_write_config(DEV, REG, ( \ 121 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 122 123 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 124 125 #define CBB_START_MEM 0x88000000 126 #define CBB_START_32_IO 0x1000 127 #define CBB_START_16_IO 0x100 128 129 devclass_t cbb_devclass; 130 131 /* sysctl vars */ 132 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 133 134 /* There's no way to say TUNEABLE_LONG to get the right types */ 135 u_long cbb_start_mem = CBB_START_MEM; 136 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 137 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 138 &cbb_start_mem, CBB_START_MEM, 139 "Starting address for memory allocations"); 140 141 u_long cbb_start_16_io = CBB_START_16_IO; 142 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 143 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 144 &cbb_start_16_io, CBB_START_16_IO, 145 "Starting ioport for 16-bit cards"); 146 147 u_long cbb_start_32_io = CBB_START_32_IO; 148 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 149 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 150 &cbb_start_32_io, CBB_START_32_IO, 151 "Starting ioport for 32-bit cards"); 152 153 int cbb_debug = 0; 154 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 155 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 156 "Verbose cardbus bridge debugging"); 157 158 static void cbb_insert(struct cbb_softc *sc); 159 static void cbb_removal(struct cbb_softc *sc); 160 static int cbb_detect_voltage(device_t brdev); 161 static void cbb_cardbus_reset(device_t brdev); 162 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 163 uint32_t end); 164 static int cbb_cardbus_mem_open(device_t brdev, int win, 165 uint32_t start, uint32_t end); 166 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 167 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 168 int type, int rid, struct resource *res); 169 static int cbb_cardbus_deactivate_resource(device_t brdev, 170 device_t child, int type, int rid, struct resource *res); 171 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 172 device_t child, int type, int *rid, u_long start, 173 u_long end, u_long count, u_int flags); 174 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 175 int type, int rid, struct resource *res); 176 static int cbb_cardbus_power_enable_socket(device_t brdev, 177 device_t child); 178 static void cbb_cardbus_power_disable_socket(device_t brdev, 179 device_t child); 180 static void cbb_func_intr(void *arg); 181 182 static void 183 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 184 { 185 struct cbb_reslist *rle; 186 187 SLIST_FOREACH(rle, &sc->rl, link) { 188 if (rle->res == res) { 189 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 190 free(rle, M_DEVBUF); 191 return; 192 } 193 } 194 } 195 196 static struct resource * 197 cbb_find_res(struct cbb_softc *sc, int type, int rid) 198 { 199 struct cbb_reslist *rle; 200 201 SLIST_FOREACH(rle, &sc->rl, link) 202 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 203 return (rle->res); 204 return (NULL); 205 } 206 207 static void 208 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 209 int rid) 210 { 211 struct cbb_reslist *rle; 212 213 /* 214 * Need to record allocated resource so we can iterate through 215 * it later. 216 */ 217 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 218 if (rle == NULL) 219 panic("cbb_cardbus_alloc_resource: can't record entry!"); 220 rle->res = res; 221 rle->type = type; 222 rle->rid = rid; 223 SLIST_INSERT_HEAD(&sc->rl, rle, link); 224 } 225 226 static void 227 cbb_destroy_res(struct cbb_softc *sc) 228 { 229 struct cbb_reslist *rle; 230 231 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 232 device_printf(sc->dev, "Danger Will Robinson: Resource " 233 "left allocated! This is a bug... " 234 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 235 rman_get_start(rle->res)); 236 SLIST_REMOVE_HEAD(&sc->rl, link); 237 free(rle, M_DEVBUF); 238 } 239 } 240 241 /* 242 * Disable function interrupts by telling the bridge to generate IRQ1 243 * interrupts. These interrupts aren't really generated by the chip, since 244 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 245 * initialization, so this helps to work around the problem. 246 * 247 * XXX We can't do this workaround for all chipsets, because this 248 * XXX causes interference with the keyboard because somechipsets will 249 * XXX actually signal IRQ1 over their serial interrupt connections to 250 * XXX the south bridge. Disable it it for now. 251 */ 252 void 253 cbb_disable_func_intr(struct cbb_softc *sc) 254 { 255 #if 0 256 uint8_t reg; 257 258 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 259 EXCA_INTR_IRQ_RESERVED1; 260 exca_putb(&sc->exca[0], EXCA_INTR, reg); 261 #endif 262 } 263 264 /* 265 * Enable function interrupts. We turn on function interrupts when the card 266 * requests an interrupt. The PCMCIA standard says that we should set 267 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 268 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 269 * cards. 270 */ 271 static void 272 cbb_enable_func_intr(struct cbb_softc *sc) 273 { 274 uint8_t reg; 275 276 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 277 EXCA_INTR_IRQ_NONE; 278 exca_putb(&sc->exca[0], EXCA_INTR, reg); 279 } 280 281 int 282 cbb_detach(device_t brdev) 283 { 284 struct cbb_softc *sc = device_get_softc(brdev); 285 int numdevs; 286 device_t *devlist; 287 int tmp; 288 int error; 289 290 device_get_children(brdev, &devlist, &numdevs); 291 292 error = 0; 293 for (tmp = 0; tmp < numdevs; tmp++) { 294 if (device_detach(devlist[tmp]) == 0) 295 device_delete_child(brdev, devlist[tmp]); 296 else 297 error++; 298 } 299 free(devlist, M_TEMP); 300 if (error > 0) 301 return (ENXIO); 302 303 mtx_lock(&sc->mtx); 304 /* 305 * XXX do we teardown all the ones still registered to guard against 306 * XXX buggy client drivers? 307 */ 308 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 309 sc->flags |= CBB_KTHREAD_DONE; 310 if (sc->flags & CBB_KTHREAD_RUNNING) { 311 cv_broadcast(&sc->cv); 312 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 313 } 314 mtx_unlock(&sc->mtx); 315 316 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 317 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 318 sc->base_res); 319 mtx_destroy(&sc->mtx); 320 cv_destroy(&sc->cv); 321 return (0); 322 } 323 324 int 325 cbb_shutdown(device_t brdev) 326 { 327 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 328 /* properly reset everything at shutdown */ 329 330 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 331 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 332 333 cbb_set(sc, CBB_SOCKET_MASK, 0); 334 335 cbb_power(brdev, CARD_OFF); 336 337 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 338 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 339 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 340 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 341 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 342 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 343 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 344 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 345 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 346 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 347 return (0); 348 } 349 350 int 351 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 352 int flags, driver_intr_t *intr, void *arg, void **cookiep) 353 { 354 struct cbb_intrhand *ih; 355 struct cbb_softc *sc = device_get_softc(dev); 356 int err; 357 358 /* 359 * Well, this is no longer strictly true. You can have multiple 360 * FAST ISRs, but can't mix fast and slow, so we have to assume 361 * least common denominator until the base system supports mixing 362 * and matching better. 363 */ 364 if ((flags & INTR_FAST) != 0) 365 return (EINVAL); 366 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 367 if (ih == NULL) 368 return (ENOMEM); 369 *cookiep = ih; 370 ih->intr = intr; 371 ih->arg = arg; 372 ih->sc = sc; 373 /* 374 * XXX need to turn on ISA interrupts, if we ever support them, but 375 * XXX for now that's all we need to do. 376 */ 377 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 378 cbb_func_intr, ih, &ih->cookie); 379 if (err != 0) { 380 free(ih, M_DEVBUF); 381 return (err); 382 } 383 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 384 cbb_enable_func_intr(sc); 385 sc->flags |= CBB_CARD_OK; 386 return 0; 387 } 388 389 int 390 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 391 void *cookie) 392 { 393 struct cbb_intrhand *ih; 394 struct cbb_softc *sc = device_get_softc(dev); 395 int err; 396 397 /* XXX Need to do different things for ISA interrupts. */ 398 ih = (struct cbb_intrhand *) cookie; 399 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 400 ih->cookie); 401 if (err != 0) 402 return (err); 403 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 404 free(ih, M_DEVBUF); 405 return (0); 406 } 407 408 409 void 410 cbb_driver_added(device_t brdev, driver_t *driver) 411 { 412 struct cbb_softc *sc = device_get_softc(brdev); 413 device_t *devlist; 414 device_t dev; 415 int tmp; 416 int numdevs; 417 int wake = 0; 418 419 DEVICE_IDENTIFY(driver, brdev); 420 device_get_children(brdev, &devlist, &numdevs); 421 for (tmp = 0; tmp < numdevs; tmp++) { 422 dev = devlist[tmp]; 423 if (device_get_state(dev) == DS_NOTPRESENT && 424 device_probe_and_attach(dev) == 0) 425 wake++; 426 } 427 free(devlist, M_TEMP); 428 429 if (wake > 0) { 430 mtx_lock(&sc->mtx); 431 cv_signal(&sc->cv); 432 mtx_unlock(&sc->mtx); 433 } 434 } 435 436 void 437 cbb_child_detached(device_t brdev, device_t child) 438 { 439 struct cbb_softc *sc = device_get_softc(brdev); 440 441 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 442 device_printf(brdev, "Unknown child detached: %s\n", 443 device_get_nameunit(child)); 444 } 445 446 /************************************************************************/ 447 /* Kthreads */ 448 /************************************************************************/ 449 450 void 451 cbb_event_thread(void *arg) 452 { 453 struct cbb_softc *sc = arg; 454 uint32_t status; 455 int err; 456 int not_a_card = 0; 457 458 sc->flags |= CBB_KTHREAD_RUNNING; 459 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 460 /* 461 * We take out Giant here because we need it deep, 462 * down in the bowels of the vm system for mapping the 463 * memory we need to read the CIS. In addition, since 464 * we are adding/deleting devices from the dev tree, 465 * and that code isn't MP safe, we have to hold Giant. 466 */ 467 mtx_lock(&Giant); 468 status = cbb_get(sc, CBB_SOCKET_STATE); 469 DPRINTF(("Status is 0x%x\n", status)); 470 if (!CBB_CARD_PRESENT(status)) { 471 not_a_card = 0; /* We know card type */ 472 cbb_removal(sc); 473 } else if (status & CBB_STATE_NOT_A_CARD) { 474 /* 475 * Up to 20 times, try to rescan the card when we 476 * see NOT_A_CARD. 477 */ 478 if (not_a_card++ < 20) { 479 DEVPRINTF((sc->dev, 480 "Not a card bit set, rescanning\n")); 481 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 482 } else { 483 device_printf(sc->dev, 484 "Can't determine card type\n"); 485 } 486 } else { 487 not_a_card = 0; /* We know card type */ 488 cbb_insert(sc); 489 } 490 mtx_unlock(&Giant); 491 492 /* 493 * Wait until it has been 1s since the last time we 494 * get an interrupt. We handle the rest of the interrupt 495 * at the top of the loop. Although we clear the bit in the 496 * ISR, we signal sc->cv from the detach path after we've 497 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 498 * 1s sleep here. 499 * 500 * In our ISR, we turn off the card changed interrupt. Turn 501 * them back on here before we wait for them to happen. We 502 * turn them on/off so that we can tolerate a large latency 503 * between the time we signal cbb_event_thread and it gets 504 * a chance to run. 505 */ 506 mtx_lock(&sc->mtx); 507 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 508 cv_wait(&sc->cv, &sc->mtx); 509 err = 0; 510 while (err != EWOULDBLOCK && 511 (sc->flags & CBB_KTHREAD_DONE) == 0) 512 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 513 mtx_unlock(&sc->mtx); 514 } 515 sc->flags &= ~CBB_KTHREAD_RUNNING; 516 kthread_exit(0); 517 } 518 519 /************************************************************************/ 520 /* Insert/removal */ 521 /************************************************************************/ 522 523 static void 524 cbb_insert(struct cbb_softc *sc) 525 { 526 uint32_t sockevent, sockstate; 527 528 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 529 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 530 531 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 532 sockevent, sockstate)); 533 534 if (sockstate & CBB_STATE_R2_CARD) { 535 if (sc->exca[0].pccarddev) { 536 sc->flags |= CBB_16BIT_CARD; 537 exca_insert(&sc->exca[0]); 538 } 539 } else if (sockstate & CBB_STATE_CB_CARD) { 540 if (sc->cbdev != NULL) { 541 sc->flags &= ~CBB_16BIT_CARD; 542 CARD_ATTACH_CARD(sc->cbdev); 543 } else { 544 device_printf(sc->dev, 545 "CardBus card inserted, but no cardbus bus.\n"); 546 } 547 } else { 548 /* 549 * We should power the card down, and try again a couple of 550 * times if this happens. XXX 551 */ 552 device_printf(sc->dev, "Unsupported card type detected\n"); 553 } 554 } 555 556 static void 557 cbb_removal(struct cbb_softc *sc) 558 { 559 sc->flags &= ~CBB_CARD_OK; 560 if (sc->flags & CBB_16BIT_CARD) { 561 exca_removal(&sc->exca[0]); 562 } else { 563 if (sc->cbdev != NULL) 564 CARD_DETACH_CARD(sc->cbdev); 565 } 566 cbb_destroy_res(sc); 567 } 568 569 /************************************************************************/ 570 /* Interrupt Handler */ 571 /************************************************************************/ 572 573 /* 574 * Since we touch hardware in the worst case, we don't need to use atomic 575 * ops on the CARD_OK tests. They would save us a trip to the hardware 576 * if CARD_OK was recently cleared and the caches haven't updated yet. 577 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 578 * machine, this is about 33-66ns, whereas a trip the the hardware 579 * is about that. On slower machines, the cost is even higher, so the 580 * trip to the hardware is cheaper and achieves the same ends that 581 * a fully locked operation would give us. 582 * 583 * This is a separate routine because we'd have to use locking and/or 584 * other synchronization in cbb_intr to do this there. That would be 585 * even more expensive. 586 * 587 * I need to investigate what this means for a SMP machine with multiple 588 * CPUs servicing the ISR when an eject happens. In the case of a dirty 589 * eject, CD glitches and we might read 'card present' from the hardware 590 * due to this jitter. If we assumed that cbb_intr() ran before 591 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 592 * CD changes were clear there, then we'd know the card was gone. 593 */ 594 static void 595 cbb_func_intr(void *arg) 596 { 597 struct cbb_intrhand *ih = (struct cbb_intrhand *)arg; 598 struct cbb_softc *sc = ih->sc; 599 600 /* 601 * Make sure that the card is really there. 602 */ 603 if ((sc->flags & CBB_CARD_OK) == 0) 604 return; 605 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 606 sc->flags &= ~CBB_CARD_OK; 607 return; 608 } 609 610 /* 611 * nb: don't have to check for giant or not, since that's done 612 * in the ISR dispatch 613 */ 614 (*ih->intr)(ih->arg); 615 } 616 617 void 618 cbb_intr(void *arg) 619 { 620 struct cbb_softc *sc = arg; 621 uint32_t sockevent; 622 623 /* 624 * This ISR needs work XXX 625 */ 626 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 627 if (sockevent != 0) { 628 /* ack the interrupt */ 629 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 630 631 /* 632 * If anything has happened to the socket, we assume that 633 * the card is no longer OK, and we shouldn't call its 634 * ISR. We set CARD_OK as soon as we've attached the 635 * card. This helps in a noisy eject, which happens 636 * all too often when users are ejecting their PC Cards. 637 * 638 * We use this method in preference to checking to see if 639 * the card is still there because the check suffers from 640 * a race condition in the bouncing case. Prior versions 641 * of the pccard software used a similar trick and achieved 642 * excellent results. 643 */ 644 if (sockevent & CBB_SOCKET_EVENT_CD) { 645 mtx_lock(&sc->mtx); 646 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 647 sc->flags &= ~CBB_CARD_OK; 648 cbb_disable_func_intr(sc); 649 cv_signal(&sc->cv); 650 mtx_unlock(&sc->mtx); 651 } 652 } 653 /* 654 * Some chips also require us to read the old ExCA registe for 655 * card status change when we route CSC vis PCI. This isn't supposed 656 * to be required, but it clears the interrupt state on some chipsets. 657 * Maybe there's a setting that would obviate its need. Maybe we 658 * should test the status bits and deal with them, but so far we've 659 * not found any machines that don't also give us the socket status 660 * indication above. 661 * 662 * We have to call this unconditionally because some bridges deliver 663 * the even independent of the CBB_SOCKET_EVENT_CD above. 664 */ 665 exca_getb(&sc->exca[0], EXCA_CSC); 666 } 667 668 /************************************************************************/ 669 /* Generic Power functions */ 670 /************************************************************************/ 671 672 static int 673 cbb_detect_voltage(device_t brdev) 674 { 675 struct cbb_softc *sc = device_get_softc(brdev); 676 uint32_t psr; 677 int vol = CARD_UKN_CARD; 678 679 psr = cbb_get(sc, CBB_SOCKET_STATE); 680 681 if (psr & CBB_STATE_5VCARD) 682 vol |= CARD_5V_CARD; 683 if (psr & CBB_STATE_3VCARD) 684 vol |= CARD_3V_CARD; 685 if (psr & CBB_STATE_XVCARD) 686 vol |= CARD_XV_CARD; 687 if (psr & CBB_STATE_YVCARD) 688 vol |= CARD_YV_CARD; 689 690 return (vol); 691 } 692 693 static uint8_t 694 cbb_o2micro_power_hack(struct cbb_softc *sc) 695 { 696 uint8_t reg; 697 698 /* 699 * Issue #2: INT# not qualified with IRQ Routing Bit. An 700 * unexpected PCI INT# may be generated during PC-Card 701 * initialization even with the IRQ Routing Bit Set with some 702 * PC-Cards. 703 * 704 * This is a two part issue. The first part is that some of 705 * our older controllers have an issue in which the slot's PCI 706 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 707 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 708 * is selected (ExCA register 03h bits 3:0, of the slot, are 709 * cleared) we will generate INT# if IREQ# is asserted. The 710 * second part is because some PC-Cards prematurally assert 711 * IREQ# before the ExCA registers are fully programmed. This 712 * in turn asserts INT# because ExCA register 03h bits 3:0 713 * (ISA IRQ Select) are not yet programmed. 714 * 715 * The fix for this issue, which will work for any controller 716 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 717 * (select IRQ1), of the slot, before turning on slot power. 718 * Selecting IRQ1 will result in INT# NOT being asserted 719 * (because IRQ1 is selected), and IRQ1 won't be asserted 720 * because our controllers don't generate IRQ1. 721 */ 722 reg = exca_getb(&sc->exca[0], EXCA_INTR); 723 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 724 return (reg); 725 } 726 727 /* 728 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 729 * we don't have an interrupt storm on power on. This has the efect of 730 * disabling card status change interrupts for the duration of poweron. 731 */ 732 static void 733 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 734 { 735 exca_putb(&sc->exca[0], EXCA_INTR, reg); 736 } 737 738 int 739 cbb_power(device_t brdev, int volts) 740 { 741 uint32_t status, sock_ctrl; 742 struct cbb_softc *sc = device_get_softc(brdev); 743 int timeout; 744 int retval = 0; 745 uint32_t sockevent; 746 uint8_t reg = 0; 747 748 status = cbb_get(sc, CBB_SOCKET_STATE); 749 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 750 751 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 752 switch (volts & CARD_VCCMASK) { 753 case 5: 754 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 755 break; 756 case 3: 757 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 758 break; 759 case XV: 760 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 761 break; 762 case YV: 763 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 764 break; 765 case 0: 766 break; 767 default: 768 return (0); /* power NEVER changed */ 769 } 770 771 /* VPP == VCC */ 772 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 773 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 774 775 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 776 return (1); /* no change necessary */ 777 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 778 if (volts != 0 && sc->chipset == CB_O2MICRO) 779 reg = cbb_o2micro_power_hack(sc); 780 781 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 782 status = cbb_get(sc, CBB_SOCKET_STATE); 783 784 /* 785 * XXX This busy wait is bogus. We should wait for a power 786 * interrupt and then whine if the status is bad. If we're 787 * worried about the card not coming up, then we should also 788 * schedule a timeout which we can cancel in the power interrupt. 789 */ 790 timeout = 20; 791 do { 792 DELAY(20*1000); 793 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 794 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 795 /* reset event status */ 796 /* XXX should only reset EVENT_POWER */ 797 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 798 if (timeout < 0) { 799 printf ("VCC supply failed.\n"); 800 goto done; 801 } 802 803 /* XXX 804 * delay 400 ms: thgough the standard defines that the Vcc set-up time 805 * is 20 ms, some PC-Card bridge requires longer duration. 806 * XXX Note: We should check the stutus AFTER the delay to give time 807 * for things to stabilize. 808 */ 809 DELAY(400*1000); 810 811 if (status & CBB_STATE_BAD_VCC_REQ) { 812 device_printf(sc->dev, 813 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 814 sock_ctrl ,status); 815 printf("cbb_power: %dV\n", volts); 816 goto done; 817 } 818 retval = 1; 819 done:; 820 if (volts != 0 && sc->chipset == CB_O2MICRO) 821 cbb_o2micro_power_hack2(sc, reg); 822 return (retval); 823 } 824 825 /* 826 * detect the voltage for the card, and set it. Since the power 827 * used is the square of the voltage, lower voltages is a big win 828 * and what Windows does (and what Microsoft prefers). The MS paper 829 * also talks about preferring the CIS entry as well. In addition, 830 * we power up with OE disabled. We'll set it later in the power 831 * up sequence. 832 */ 833 static int 834 cbb_do_power(device_t brdev) 835 { 836 struct cbb_softc *sc = device_get_softc(brdev); 837 int voltage; 838 839 /* Don't enable OE */ 840 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 841 842 /* Prefer lowest voltage supported */ 843 voltage = cbb_detect_voltage(brdev); 844 cbb_power(brdev, CARD_OFF); 845 if (voltage & CARD_YV_CARD) 846 cbb_power(brdev, CARD_VCC(YV)); 847 else if (voltage & CARD_XV_CARD) 848 cbb_power(brdev, CARD_VCC(XV)); 849 else if (voltage & CARD_3V_CARD) 850 cbb_power(brdev, CARD_VCC(3)); 851 else if (voltage & CARD_5V_CARD) 852 cbb_power(brdev, CARD_VCC(5)); 853 else { 854 device_printf(brdev, "Unknown card voltage\n"); 855 return (ENXIO); 856 } 857 return (0); 858 } 859 860 /************************************************************************/ 861 /* CardBus power functions */ 862 /************************************************************************/ 863 864 static void 865 cbb_cardbus_reset(device_t brdev) 866 { 867 struct cbb_softc *sc = device_get_softc(brdev); 868 int delay_us; 869 870 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 871 872 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 873 874 DELAY(delay_us); 875 876 /* If a card exists, unreset it! */ 877 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 878 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 879 &~CBBM_BRIDGECTRL_RESET, 2); 880 DELAY(delay_us); 881 } 882 } 883 884 static int 885 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 886 { 887 struct cbb_softc *sc = device_get_softc(brdev); 888 int err; 889 890 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 891 return (ENODEV); 892 893 err = cbb_do_power(brdev); 894 if (err) 895 return (err); 896 cbb_cardbus_reset(brdev); 897 return (0); 898 } 899 900 static void 901 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 902 { 903 cbb_power(brdev, CARD_OFF); 904 cbb_cardbus_reset(brdev); 905 } 906 907 /************************************************************************/ 908 /* CardBus Resource */ 909 /************************************************************************/ 910 911 static int 912 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 913 { 914 int basereg; 915 int limitreg; 916 917 if ((win < 0) || (win > 1)) { 918 DEVPRINTF((brdev, 919 "cbb_cardbus_io_open: window out of range %d\n", win)); 920 return (EINVAL); 921 } 922 923 basereg = win * 8 + CBBR_IOBASE0; 924 limitreg = win * 8 + CBBR_IOLIMIT0; 925 926 pci_write_config(brdev, basereg, start, 4); 927 pci_write_config(brdev, limitreg, end, 4); 928 return (0); 929 } 930 931 static int 932 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 933 { 934 int basereg; 935 int limitreg; 936 937 if ((win < 0) || (win > 1)) { 938 DEVPRINTF((brdev, 939 "cbb_cardbus_mem_open: window out of range %d\n", win)); 940 return (EINVAL); 941 } 942 943 basereg = win*8 + CBBR_MEMBASE0; 944 limitreg = win*8 + CBBR_MEMLIMIT0; 945 946 pci_write_config(brdev, basereg, start, 4); 947 pci_write_config(brdev, limitreg, end, 4); 948 return (0); 949 } 950 951 /* 952 * XXX The following function belongs in the pci bus layer. 953 */ 954 static void 955 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 956 { 957 uint32_t starts[2]; 958 uint32_t ends[2]; 959 struct cbb_reslist *rle; 960 int align; 961 int prefetchable[2]; 962 uint32_t reg; 963 964 starts[0] = starts[1] = 0xffffffff; 965 ends[0] = ends[1] = 0; 966 967 if (type == SYS_RES_MEMORY) 968 align = CBB_MEMALIGN; 969 else if (type == SYS_RES_IOPORT) 970 align = CBB_IOALIGN; 971 else 972 align = 1; 973 974 /* 975 * This looks somewhat bogus, and doesn't seem to really respect 976 * alignment. The alignment stuff is happening too late (it 977 * should happen at allocation time, not activation time) and 978 * this code looks generally to be too complex for the purpose 979 * it surves. 980 */ 981 SLIST_FOREACH(rle, &sc->rl, link) { 982 if (rle->type != type) 983 ; 984 else if (rle->res == NULL) { 985 device_printf(sc->dev, "WARNING: Resource not reserved? " 986 "(type=%d, addr=%lx)\n", 987 rle->type, rman_get_start(rle->res)); 988 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 989 /* XXX */ 990 } else if (starts[0] == 0xffffffff) { 991 starts[0] = rman_get_start(rle->res); 992 ends[0] = rman_get_end(rle->res); 993 prefetchable[0] = 994 rman_get_flags(rle->res) & RF_PREFETCHABLE; 995 } else if (rman_get_end(rle->res) > ends[0] && 996 rman_get_start(rle->res) - ends[0] < 997 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 998 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 999 ends[0] = rman_get_end(rle->res); 1000 } else if (rman_get_start(rle->res) < starts[0] && 1001 starts[0] - rman_get_end(rle->res) < 1002 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1003 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1004 starts[0] = rman_get_start(rle->res); 1005 } else if (starts[1] == 0xffffffff) { 1006 starts[1] = rman_get_start(rle->res); 1007 ends[1] = rman_get_end(rle->res); 1008 prefetchable[1] = 1009 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1010 } else if (rman_get_end(rle->res) > ends[1] && 1011 rman_get_start(rle->res) - ends[1] < 1012 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1013 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1014 ends[1] = rman_get_end(rle->res); 1015 } else if (rman_get_start(rle->res) < starts[1] && 1016 starts[1] - rman_get_end(rle->res) < 1017 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1018 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1019 starts[1] = rman_get_start(rle->res); 1020 } else { 1021 uint32_t diffs[2]; 1022 int win; 1023 1024 diffs[0] = diffs[1] = 0xffffffff; 1025 if (rman_get_start(rle->res) > ends[0]) 1026 diffs[0] = rman_get_start(rle->res) - ends[0]; 1027 else if (rman_get_end(rle->res) < starts[0]) 1028 diffs[0] = starts[0] - rman_get_end(rle->res); 1029 if (rman_get_start(rle->res) > ends[1]) 1030 diffs[1] = rman_get_start(rle->res) - ends[1]; 1031 else if (rman_get_end(rle->res) < starts[1]) 1032 diffs[1] = starts[1] - rman_get_end(rle->res); 1033 1034 win = (diffs[0] <= diffs[1])?0:1; 1035 if (rman_get_start(rle->res) > ends[win]) 1036 ends[win] = rman_get_end(rle->res); 1037 else if (rman_get_end(rle->res) < starts[win]) 1038 starts[win] = rman_get_start(rle->res); 1039 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1040 prefetchable[win] = 0; 1041 } 1042 1043 if (starts[0] != 0xffffffff) 1044 starts[0] -= starts[0] % align; 1045 if (starts[1] != 0xffffffff) 1046 starts[1] -= starts[1] % align; 1047 if (ends[0] % align != 0) 1048 ends[0] += align - ends[0] % align - 1; 1049 if (ends[1] % align != 0) 1050 ends[1] += align - ends[1] % align - 1; 1051 } 1052 1053 if (type == SYS_RES_MEMORY) { 1054 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1055 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1056 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1057 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1058 CBBM_BRIDGECTRL_PREFETCH_1); 1059 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1060 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1061 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1062 } else if (type == SYS_RES_IOPORT) { 1063 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1064 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1065 } 1066 } 1067 1068 static int 1069 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1070 int rid, struct resource *res) 1071 { 1072 int ret; 1073 1074 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1075 type, rid, res); 1076 if (ret != 0) 1077 return (ret); 1078 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1079 return (0); 1080 } 1081 1082 static int 1083 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1084 int rid, struct resource *res) 1085 { 1086 int ret; 1087 1088 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1089 type, rid, res); 1090 if (ret != 0) 1091 return (ret); 1092 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1093 return (0); 1094 } 1095 1096 static struct resource * 1097 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1098 int *rid, u_long start, u_long end, u_long count, u_int flags) 1099 { 1100 struct cbb_softc *sc = device_get_softc(brdev); 1101 int tmp; 1102 struct resource *res; 1103 u_long align; 1104 1105 switch (type) { 1106 case SYS_RES_IRQ: 1107 tmp = rman_get_start(sc->irq_res); 1108 if (start > tmp || end < tmp || count != 1) { 1109 device_printf(child, "requested interrupt %ld-%ld," 1110 "count = %ld not supported by cbb\n", 1111 start, end, count); 1112 return (NULL); 1113 } 1114 start = end = tmp; 1115 flags |= RF_SHAREABLE; 1116 break; 1117 case SYS_RES_IOPORT: 1118 if (start <= cbb_start_32_io) 1119 start = cbb_start_32_io; 1120 if (end < start) 1121 end = start; 1122 break; 1123 case SYS_RES_MEMORY: 1124 if (start <= cbb_start_mem) 1125 start = cbb_start_mem; 1126 if (end < start) 1127 end = start; 1128 if (count < CBB_MEMALIGN) 1129 align = CBB_MEMALIGN; 1130 else 1131 align = count; 1132 if (align > (1 << RF_ALIGNMENT(flags))) 1133 flags = (flags & ~RF_ALIGNMENT_MASK) | 1134 rman_make_alignment_flags(align); 1135 break; 1136 } 1137 1138 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1139 start, end, count, flags & ~RF_ACTIVE); 1140 if (res == NULL) { 1141 printf("cbb alloc res fail\n"); 1142 return (NULL); 1143 } 1144 cbb_insert_res(sc, res, type, *rid); 1145 if (flags & RF_ACTIVE) 1146 if (bus_activate_resource(child, type, *rid, res) != 0) { 1147 bus_release_resource(child, type, *rid, res); 1148 return (NULL); 1149 } 1150 1151 return (res); 1152 } 1153 1154 static int 1155 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1156 int rid, struct resource *res) 1157 { 1158 struct cbb_softc *sc = device_get_softc(brdev); 1159 int error; 1160 1161 if (rman_get_flags(res) & RF_ACTIVE) { 1162 error = bus_deactivate_resource(child, type, rid, res); 1163 if (error != 0) 1164 return (error); 1165 } 1166 cbb_remove_res(sc, res); 1167 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1168 type, rid, res)); 1169 } 1170 1171 /************************************************************************/ 1172 /* PC Card Power Functions */ 1173 /************************************************************************/ 1174 1175 static int 1176 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1177 { 1178 struct cbb_softc *sc = device_get_softc(brdev); 1179 int err; 1180 1181 DPRINTF(("cbb_pcic_socket_enable:\n")); 1182 1183 /* power down/up the socket to reset */ 1184 err = cbb_do_power(brdev); 1185 if (err) 1186 return (err); 1187 exca_reset(&sc->exca[0], child); 1188 1189 return (0); 1190 } 1191 1192 static void 1193 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1194 { 1195 struct cbb_softc *sc = device_get_softc(brdev); 1196 1197 DPRINTF(("cbb_pcic_socket_disable\n")); 1198 1199 /* reset signal asserting... */ 1200 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 1201 DELAY(2*1000); 1202 1203 /* power down the socket */ 1204 cbb_power(brdev, CARD_OFF); 1205 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 1206 1207 /* wait 300ms until power fails (Tpf). */ 1208 DELAY(300 * 1000); 1209 } 1210 1211 /************************************************************************/ 1212 /* POWER methods */ 1213 /************************************************************************/ 1214 1215 int 1216 cbb_power_enable_socket(device_t brdev, device_t child) 1217 { 1218 struct cbb_softc *sc = device_get_softc(brdev); 1219 1220 if (sc->flags & CBB_16BIT_CARD) 1221 return (cbb_pcic_power_enable_socket(brdev, child)); 1222 else 1223 return (cbb_cardbus_power_enable_socket(brdev, child)); 1224 } 1225 1226 void 1227 cbb_power_disable_socket(device_t brdev, device_t child) 1228 { 1229 struct cbb_softc *sc = device_get_softc(brdev); 1230 if (sc->flags & CBB_16BIT_CARD) 1231 cbb_pcic_power_disable_socket(brdev, child); 1232 else 1233 cbb_cardbus_power_disable_socket(brdev, child); 1234 } 1235 1236 static int 1237 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1238 struct resource *res) 1239 { 1240 struct cbb_softc *sc = device_get_softc(brdev); 1241 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1242 } 1243 1244 static int 1245 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1246 int rid, struct resource *res) 1247 { 1248 struct cbb_softc *sc = device_get_softc(brdev); 1249 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1250 } 1251 1252 static struct resource * 1253 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1254 u_long start, u_long end, u_long count, u_int flags) 1255 { 1256 struct resource *res = NULL; 1257 struct cbb_softc *sc = device_get_softc(brdev); 1258 int align; 1259 int tmp; 1260 1261 switch (type) { 1262 case SYS_RES_MEMORY: 1263 if (start < cbb_start_mem) 1264 start = cbb_start_mem; 1265 if (end < start) 1266 end = start; 1267 if (count < CBB_MEMALIGN) 1268 align = CBB_MEMALIGN; 1269 else 1270 align = count; 1271 if (align > (1 << RF_ALIGNMENT(flags))) 1272 flags = (flags & ~RF_ALIGNMENT_MASK) | 1273 rman_make_alignment_flags(align); 1274 break; 1275 case SYS_RES_IOPORT: 1276 if (start < cbb_start_16_io) 1277 start = cbb_start_16_io; 1278 if (end < start) 1279 end = start; 1280 break; 1281 case SYS_RES_IRQ: 1282 tmp = rman_get_start(sc->irq_res); 1283 if (start > tmp || end < tmp || count != 1) { 1284 device_printf(child, "requested interrupt %ld-%ld," 1285 "count = %ld not supported by cbb\n", 1286 start, end, count); 1287 return (NULL); 1288 } 1289 flags |= RF_SHAREABLE; 1290 start = end = rman_get_start(sc->irq_res); 1291 break; 1292 } 1293 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1294 start, end, count, flags & ~RF_ACTIVE); 1295 if (res == NULL) 1296 return (NULL); 1297 cbb_insert_res(sc, res, type, *rid); 1298 if (flags & RF_ACTIVE) { 1299 if (bus_activate_resource(child, type, *rid, res) != 0) { 1300 bus_release_resource(child, type, *rid, res); 1301 return (NULL); 1302 } 1303 } 1304 1305 return (res); 1306 } 1307 1308 static int 1309 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1310 int rid, struct resource *res) 1311 { 1312 struct cbb_softc *sc = device_get_softc(brdev); 1313 int error; 1314 1315 if (rman_get_flags(res) & RF_ACTIVE) { 1316 error = bus_deactivate_resource(child, type, rid, res); 1317 if (error != 0) 1318 return (error); 1319 } 1320 cbb_remove_res(sc, res); 1321 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1322 type, rid, res)); 1323 } 1324 1325 /************************************************************************/ 1326 /* PC Card methods */ 1327 /************************************************************************/ 1328 1329 int 1330 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1331 uint32_t flags) 1332 { 1333 struct cbb_softc *sc = device_get_softc(brdev); 1334 struct resource *res; 1335 1336 if (type != SYS_RES_MEMORY) 1337 return (EINVAL); 1338 res = cbb_find_res(sc, type, rid); 1339 if (res == NULL) { 1340 device_printf(brdev, 1341 "set_res_flags: specified rid not found\n"); 1342 return (ENOENT); 1343 } 1344 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1345 } 1346 1347 int 1348 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1349 uint32_t cardaddr, uint32_t *deltap) 1350 { 1351 struct cbb_softc *sc = device_get_softc(brdev); 1352 struct resource *res; 1353 1354 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1355 if (res == NULL) { 1356 device_printf(brdev, 1357 "set_memory_offset: specified rid not found\n"); 1358 return (ENOENT); 1359 } 1360 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1361 } 1362 1363 /************************************************************************/ 1364 /* BUS Methods */ 1365 /************************************************************************/ 1366 1367 1368 int 1369 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1370 struct resource *r) 1371 { 1372 struct cbb_softc *sc = device_get_softc(brdev); 1373 1374 if (sc->flags & CBB_16BIT_CARD) 1375 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1376 else 1377 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1378 r)); 1379 } 1380 1381 int 1382 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1383 int rid, struct resource *r) 1384 { 1385 struct cbb_softc *sc = device_get_softc(brdev); 1386 1387 if (sc->flags & CBB_16BIT_CARD) 1388 return (cbb_pcic_deactivate_resource(brdev, child, type, 1389 rid, r)); 1390 else 1391 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1392 rid, r)); 1393 } 1394 1395 struct resource * 1396 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1397 u_long start, u_long end, u_long count, u_int flags) 1398 { 1399 struct cbb_softc *sc = device_get_softc(brdev); 1400 1401 if (sc->flags & CBB_16BIT_CARD) 1402 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1403 start, end, count, flags)); 1404 else 1405 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1406 start, end, count, flags)); 1407 } 1408 1409 int 1410 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1411 struct resource *r) 1412 { 1413 struct cbb_softc *sc = device_get_softc(brdev); 1414 1415 if (sc->flags & CBB_16BIT_CARD) 1416 return (cbb_pcic_release_resource(brdev, child, type, 1417 rid, r)); 1418 else 1419 return (cbb_cardbus_release_resource(brdev, child, type, 1420 rid, r)); 1421 } 1422 1423 int 1424 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1425 { 1426 struct cbb_softc *sc = device_get_softc(brdev); 1427 1428 switch (which) { 1429 case PCIB_IVAR_BUS: 1430 *result = sc->secbus; 1431 return (0); 1432 } 1433 return (ENOENT); 1434 } 1435 1436 int 1437 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1438 { 1439 struct cbb_softc *sc = device_get_softc(brdev); 1440 1441 switch (which) { 1442 case PCIB_IVAR_BUS: 1443 sc->secbus = value; 1444 break; 1445 } 1446 return (ENOENT); 1447 } 1448 1449 /************************************************************************/ 1450 /* PCI compat methods */ 1451 /************************************************************************/ 1452 1453 int 1454 cbb_maxslots(device_t brdev) 1455 { 1456 return (0); 1457 } 1458 1459 uint32_t 1460 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1461 { 1462 uint32_t rv; 1463 1464 /* 1465 * Pass through to the next ppb up the chain (i.e. our grandparent). 1466 */ 1467 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1468 b, s, f, reg, width); 1469 return (rv); 1470 } 1471 1472 void 1473 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1474 int width) 1475 { 1476 /* 1477 * Pass through to the next ppb up the chain (i.e. our grandparent). 1478 */ 1479 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1480 b, s, f, reg, val, width); 1481 } 1482 1483 int 1484 cbb_suspend(device_t self) 1485 { 1486 int error = 0; 1487 struct cbb_softc *sc = device_get_softc(self); 1488 1489 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1490 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1491 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1492 error = bus_generic_suspend(self); 1493 return (error); 1494 } 1495 1496 int 1497 cbb_resume(device_t self) 1498 { 1499 int error = 0; 1500 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1501 uint32_t tmp; 1502 1503 /* 1504 * Some BIOSes will not save the BARs for the pci chips, so we 1505 * must do it ourselves. If the BAR is reset to 0 for an I/O 1506 * device, it will read back as 0x1, so no explicit test for 1507 * memory devices are needed. 1508 * 1509 * Note: The PCI bus code should do this automatically for us on 1510 * suspend/resume, but until it does, we have to cope. 1511 */ 1512 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1513 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1514 rman_get_start(sc->base_res))); 1515 1516 sc->chipinit(sc); 1517 1518 /* reset interrupt -- Do we really need to do this? */ 1519 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1520 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1521 1522 /* re-establish the interrupt. */ 1523 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 1524 cbb_intr, sc, &sc->intrhand)) { 1525 device_printf(self, "couldn't re-establish interrupt"); 1526 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1527 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1528 sc->base_res); 1529 sc->irq_res = NULL; 1530 sc->base_res = NULL; 1531 return (ENOMEM); 1532 } 1533 1534 /* CSC Interrupt: Card detect interrupt on */ 1535 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1536 1537 /* Signal the thread to wakeup. */ 1538 mtx_lock(&sc->mtx); 1539 cv_signal(&sc->cv); 1540 mtx_unlock(&sc->mtx); 1541 1542 error = bus_generic_resume(self); 1543 1544 return (error); 1545 } 1546 1547 int 1548 cbb_child_present(device_t self) 1549 { 1550 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1551 uint32_t sockstate; 1552 1553 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1554 return (CBB_CARD_PRESENT(sockstate) && 1555 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1556 } 1557