1 /* 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * and PCI to PCMCIA Bridge chips 63 * and ISA to PCMCIA host adapters 64 * and C Bus to PCMCIA host adapters 65 * 66 * References: 67 * TI Datasheets: 68 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 69 * 70 * Written by Jonathan Chen <jon@freebsd.org> 71 * The author would like to acknowledge: 72 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 73 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 74 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 75 * * David Cross: Author of the initial ugly hack for a specific cardbus card 76 */ 77 78 #include <sys/cdefs.h> 79 __FBSDID("$FreeBSD$"); 80 81 #include <sys/param.h> 82 #include <sys/bus.h> 83 #include <sys/condvar.h> 84 #include <sys/errno.h> 85 #include <sys/kernel.h> 86 #include <sys/module.h> 87 #include <sys/kthread.h> 88 #include <sys/lock.h> 89 #include <sys/malloc.h> 90 #include <sys/mutex.h> 91 #include <sys/proc.h> 92 #include <sys/rman.h> 93 #include <sys/sysctl.h> 94 #include <sys/systm.h> 95 #include <machine/bus.h> 96 #include <machine/resource.h> 97 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcivar.h> 100 #include <machine/clock.h> 101 102 #include <dev/pccard/pccardreg.h> 103 #include <dev/pccard/pccardvar.h> 104 105 #include <dev/exca/excareg.h> 106 #include <dev/exca/excavar.h> 107 108 #include <dev/pccbb/pccbbreg.h> 109 #include <dev/pccbb/pccbbvar.h> 110 111 #include "power_if.h" 112 #include "card_if.h" 113 #include "pcib_if.h" 114 115 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 116 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 117 118 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 119 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 120 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 121 pci_write_config(DEV, REG, ( \ 122 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 123 124 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 125 126 #define CBB_START_MEM 0x88000000 127 #define CBB_START_32_IO 0x1000 128 #define CBB_START_16_IO 0x100 129 130 devclass_t cbb_devclass; 131 132 /* sysctl vars */ 133 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 134 135 /* There's no way to say TUNEABLE_LONG to get the right types */ 136 u_long cbb_start_mem = CBB_START_MEM; 137 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 138 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 139 &cbb_start_mem, CBB_START_MEM, 140 "Starting address for memory allocations"); 141 142 u_long cbb_start_16_io = CBB_START_16_IO; 143 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 144 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 145 &cbb_start_16_io, CBB_START_16_IO, 146 "Starting ioport for 16-bit cards"); 147 148 u_long cbb_start_32_io = CBB_START_32_IO; 149 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 150 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 151 &cbb_start_32_io, CBB_START_32_IO, 152 "Starting ioport for 32-bit cards"); 153 154 int cbb_debug = 0; 155 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 156 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 157 "Verbose cardbus bridge debugging"); 158 159 static void cbb_insert(struct cbb_softc *sc); 160 static void cbb_removal(struct cbb_softc *sc); 161 static int cbb_detect_voltage(device_t brdev); 162 static void cbb_cardbus_reset(device_t brdev); 163 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 164 uint32_t end); 165 static int cbb_cardbus_mem_open(device_t brdev, int win, 166 uint32_t start, uint32_t end); 167 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 168 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 169 int type, int rid, struct resource *res); 170 static int cbb_cardbus_deactivate_resource(device_t brdev, 171 device_t child, int type, int rid, struct resource *res); 172 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 173 device_t child, int type, int *rid, u_long start, 174 u_long end, u_long count, u_int flags); 175 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 176 int type, int rid, struct resource *res); 177 static int cbb_cardbus_power_enable_socket(device_t brdev, 178 device_t child); 179 static void cbb_cardbus_power_disable_socket(device_t brdev, 180 device_t child); 181 static void cbb_func_intr(void *arg); 182 183 static void 184 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 185 { 186 struct cbb_reslist *rle; 187 188 SLIST_FOREACH(rle, &sc->rl, link) { 189 if (rle->res == res) { 190 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 191 free(rle, M_DEVBUF); 192 return; 193 } 194 } 195 } 196 197 static struct resource * 198 cbb_find_res(struct cbb_softc *sc, int type, int rid) 199 { 200 struct cbb_reslist *rle; 201 202 SLIST_FOREACH(rle, &sc->rl, link) 203 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 204 return (rle->res); 205 return (NULL); 206 } 207 208 static void 209 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 210 int rid) 211 { 212 struct cbb_reslist *rle; 213 214 /* 215 * Need to record allocated resource so we can iterate through 216 * it later. 217 */ 218 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 219 if (rle == NULL) 220 panic("cbb_cardbus_alloc_resource: can't record entry!"); 221 rle->res = res; 222 rle->type = type; 223 rle->rid = rid; 224 SLIST_INSERT_HEAD(&sc->rl, rle, link); 225 } 226 227 static void 228 cbb_destroy_res(struct cbb_softc *sc) 229 { 230 struct cbb_reslist *rle; 231 232 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 233 device_printf(sc->dev, "Danger Will Robinson: Resource " 234 "left allocated! This is a bug... " 235 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 236 rman_get_start(rle->res)); 237 SLIST_REMOVE_HEAD(&sc->rl, link); 238 free(rle, M_DEVBUF); 239 } 240 } 241 242 /* 243 * Disable function interrupts by telling the bridge to generate IRQ1 244 * interrupts. These interrupts aren't really generated by the chip, since 245 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 246 * initialization, so this helps to work around the problem. 247 * 248 * XXX We can't do this workaround for all chipsets, because this 249 * XXX causes interference with the keyboard because somechipsets will 250 * XXX actually signal IRQ1 over their serial interrupt connections to 251 * XXX the south bridge. Disable it it for now. 252 */ 253 void 254 cbb_disable_func_intr(struct cbb_softc *sc) 255 { 256 #if 0 257 uint8_t reg; 258 259 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 260 EXCA_INTR_IRQ_RESERVED1; 261 exca_putb(&sc->exca[0], EXCA_INTR, reg); 262 #endif 263 } 264 265 /* 266 * Enable function interrupts. We turn on function interrupts when the card 267 * requests an interrupt. The PCMCIA standard says that we should set 268 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 269 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 270 * cards. 271 */ 272 static void 273 cbb_enable_func_intr(struct cbb_softc *sc) 274 { 275 uint8_t reg; 276 277 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 278 EXCA_INTR_IRQ_NONE; 279 exca_putb(&sc->exca[0], EXCA_INTR, reg); 280 } 281 282 int 283 cbb_detach(device_t brdev) 284 { 285 struct cbb_softc *sc = device_get_softc(brdev); 286 int numdevs; 287 device_t *devlist; 288 int tmp; 289 int error; 290 291 device_get_children(brdev, &devlist, &numdevs); 292 293 error = 0; 294 for (tmp = 0; tmp < numdevs; tmp++) { 295 if (device_detach(devlist[tmp]) == 0) 296 device_delete_child(brdev, devlist[tmp]); 297 else 298 error++; 299 } 300 free(devlist, M_TEMP); 301 if (error > 0) 302 return (ENXIO); 303 304 mtx_lock(&sc->mtx); 305 /* 306 * XXX do we teardown all the ones still registered to guard against 307 * XXX buggy client drivers? 308 */ 309 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 310 sc->flags |= CBB_KTHREAD_DONE; 311 if (sc->flags & CBB_KTHREAD_RUNNING) { 312 cv_broadcast(&sc->cv); 313 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 314 } 315 mtx_unlock(&sc->mtx); 316 317 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 318 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 319 sc->base_res); 320 mtx_destroy(&sc->mtx); 321 cv_destroy(&sc->cv); 322 return (0); 323 } 324 325 int 326 cbb_shutdown(device_t brdev) 327 { 328 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 329 /* properly reset everything at shutdown */ 330 331 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 332 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 333 334 cbb_set(sc, CBB_SOCKET_MASK, 0); 335 336 cbb_power(brdev, CARD_OFF); 337 338 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 339 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 340 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 341 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 342 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 343 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 344 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 345 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 346 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 347 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 348 return (0); 349 } 350 351 int 352 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 353 int flags, driver_intr_t *intr, void *arg, void **cookiep) 354 { 355 struct cbb_intrhand *ih; 356 struct cbb_softc *sc = device_get_softc(dev); 357 int err; 358 359 /* 360 * Well, this is no longer strictly true. You can have multiple 361 * FAST ISRs, but can't mix fast and slow, so we have to assume 362 * least common denominator until the base system supports mixing 363 * and matching better. 364 */ 365 if ((flags & INTR_FAST) != 0) 366 return (EINVAL); 367 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 368 if (ih == NULL) 369 return (ENOMEM); 370 *cookiep = ih; 371 ih->intr = intr; 372 ih->arg = arg; 373 ih->sc = sc; 374 /* 375 * XXX need to turn on ISA interrupts, if we ever support them, but 376 * XXX for now that's all we need to do. 377 */ 378 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 379 cbb_func_intr, ih, &ih->cookie); 380 if (err != 0) { 381 free(ih, M_DEVBUF); 382 return (err); 383 } 384 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 385 cbb_enable_func_intr(sc); 386 sc->flags |= CBB_CARD_OK; 387 return 0; 388 } 389 390 int 391 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 392 void *cookie) 393 { 394 struct cbb_intrhand *ih; 395 struct cbb_softc *sc = device_get_softc(dev); 396 int err; 397 398 /* XXX Need to do different things for ISA interrupts. */ 399 ih = (struct cbb_intrhand *) cookie; 400 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 401 ih->cookie); 402 if (err != 0) 403 return (err); 404 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 405 free(ih, M_DEVBUF); 406 return (0); 407 } 408 409 410 void 411 cbb_driver_added(device_t brdev, driver_t *driver) 412 { 413 struct cbb_softc *sc = device_get_softc(brdev); 414 device_t *devlist; 415 device_t dev; 416 int tmp; 417 int numdevs; 418 int wake = 0; 419 420 DEVICE_IDENTIFY(driver, brdev); 421 device_get_children(brdev, &devlist, &numdevs); 422 for (tmp = 0; tmp < numdevs; tmp++) { 423 dev = devlist[tmp]; 424 if (device_get_state(dev) == DS_NOTPRESENT && 425 device_probe_and_attach(dev) == 0) 426 wake++; 427 } 428 free(devlist, M_TEMP); 429 430 if (wake > 0) { 431 mtx_lock(&sc->mtx); 432 cv_signal(&sc->cv); 433 mtx_unlock(&sc->mtx); 434 } 435 } 436 437 void 438 cbb_child_detached(device_t brdev, device_t child) 439 { 440 struct cbb_softc *sc = device_get_softc(brdev); 441 442 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 443 device_printf(brdev, "Unknown child detached: %s\n", 444 device_get_nameunit(child)); 445 } 446 447 /************************************************************************/ 448 /* Kthreads */ 449 /************************************************************************/ 450 451 void 452 cbb_event_thread(void *arg) 453 { 454 struct cbb_softc *sc = arg; 455 uint32_t status; 456 int err; 457 int not_a_card = 0; 458 459 sc->flags |= CBB_KTHREAD_RUNNING; 460 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 461 /* 462 * We take out Giant here because we need it deep, 463 * down in the bowels of the vm system for mapping the 464 * memory we need to read the CIS. In addition, since 465 * we are adding/deleting devices from the dev tree, 466 * and that code isn't MP safe, we have to hold Giant. 467 */ 468 mtx_lock(&Giant); 469 status = cbb_get(sc, CBB_SOCKET_STATE); 470 DPRINTF(("Status is 0x%x\n", status)); 471 if (!CBB_CARD_PRESENT(status)) { 472 not_a_card = 0; /* We know card type */ 473 cbb_removal(sc); 474 } else if (status & CBB_STATE_NOT_A_CARD) { 475 /* 476 * Up to 20 times, try to rescan the card when we 477 * see NOT_A_CARD. 478 */ 479 if (not_a_card++ < 20) { 480 DEVPRINTF((sc->dev, 481 "Not a card bit set, rescanning\n")); 482 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 483 } else { 484 device_printf(sc->dev, 485 "Can't determine card type\n"); 486 } 487 } else { 488 not_a_card = 0; /* We know card type */ 489 cbb_insert(sc); 490 } 491 mtx_unlock(&Giant); 492 493 /* 494 * Wait until it has been 1s since the last time we 495 * get an interrupt. We handle the rest of the interrupt 496 * at the top of the loop. Although we clear the bit in the 497 * ISR, we signal sc->cv from the detach path after we've 498 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 499 * 1s sleep here. 500 * 501 * In our ISR, we turn off the card changed interrupt. Turn 502 * them back on here before we wait for them to happen. We 503 * turn them on/off so that we can tolerate a large latency 504 * between the time we signal cbb_event_thread and it gets 505 * a chance to run. 506 */ 507 mtx_lock(&sc->mtx); 508 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 509 cv_wait(&sc->cv, &sc->mtx); 510 err = 0; 511 while (err != EWOULDBLOCK && 512 (sc->flags & CBB_KTHREAD_DONE) == 0) 513 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 514 mtx_unlock(&sc->mtx); 515 } 516 sc->flags &= ~CBB_KTHREAD_RUNNING; 517 kthread_exit(0); 518 } 519 520 /************************************************************************/ 521 /* Insert/removal */ 522 /************************************************************************/ 523 524 static void 525 cbb_insert(struct cbb_softc *sc) 526 { 527 uint32_t sockevent, sockstate; 528 529 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 530 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 531 532 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 533 sockevent, sockstate)); 534 535 if (sockstate & CBB_STATE_R2_CARD) { 536 if (sc->exca[0].pccarddev) { 537 sc->flags |= CBB_16BIT_CARD; 538 exca_insert(&sc->exca[0]); 539 } 540 } else if (sockstate & CBB_STATE_CB_CARD) { 541 if (sc->cbdev != NULL) { 542 sc->flags &= ~CBB_16BIT_CARD; 543 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 544 device_printf(sc->dev, 545 "CardBus card activation failed\n"); 546 } else { 547 device_printf(sc->dev, 548 "CardBus card inserted, but no cardbus bus.\n"); 549 } 550 } else { 551 /* 552 * We should power the card down, and try again a couple of 553 * times if this happens. XXX 554 */ 555 device_printf(sc->dev, "Unsupported card type detected\n"); 556 } 557 } 558 559 static void 560 cbb_removal(struct cbb_softc *sc) 561 { 562 sc->flags &= ~CBB_CARD_OK; 563 if (sc->flags & CBB_16BIT_CARD) { 564 exca_removal(&sc->exca[0]); 565 } else { 566 if (sc->cbdev != NULL) 567 CARD_DETACH_CARD(sc->cbdev); 568 } 569 cbb_destroy_res(sc); 570 } 571 572 /************************************************************************/ 573 /* Interrupt Handler */ 574 /************************************************************************/ 575 576 /* 577 * Since we touch hardware in the worst case, we don't need to use atomic 578 * ops on the CARD_OK tests. They would save us a trip to the hardware 579 * if CARD_OK was recently cleared and the caches haven't updated yet. 580 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 581 * machine, this is about 33-66ns, whereas a trip the the hardware 582 * is about that. On slower machines, the cost is even higher, so the 583 * trip to the hardware is cheaper and achieves the same ends that 584 * a fully locked operation would give us. 585 * 586 * This is a separate routine because we'd have to use locking and/or 587 * other synchronization in cbb_intr to do this there. That would be 588 * even more expensive. 589 * 590 * I need to investigate what this means for a SMP machine with multiple 591 * CPUs servicing the ISR when an eject happens. In the case of a dirty 592 * eject, CD glitches and we might read 'card present' from the hardware 593 * due to this jitter. If we assumed that cbb_intr() ran before 594 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 595 * CD changes were clear there, then we'd know the card was gone. 596 */ 597 static void 598 cbb_func_intr(void *arg) 599 { 600 struct cbb_intrhand *ih = (struct cbb_intrhand *)arg; 601 struct cbb_softc *sc = ih->sc; 602 603 /* 604 * Make sure that the card is really there. 605 */ 606 if ((sc->flags & CBB_CARD_OK) == 0) 607 return; 608 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 609 sc->flags &= ~CBB_CARD_OK; 610 return; 611 } 612 613 /* 614 * nb: don't have to check for giant or not, since that's done 615 * in the ISR dispatch 616 */ 617 (*ih->intr)(ih->arg); 618 } 619 620 void 621 cbb_intr(void *arg) 622 { 623 struct cbb_softc *sc = arg; 624 uint32_t sockevent; 625 626 /* 627 * This ISR needs work XXX 628 */ 629 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 630 if (sockevent != 0) { 631 /* ack the interrupt */ 632 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 633 634 /* 635 * If anything has happened to the socket, we assume that 636 * the card is no longer OK, and we shouldn't call its 637 * ISR. We set CARD_OK as soon as we've attached the 638 * card. This helps in a noisy eject, which happens 639 * all too often when users are ejecting their PC Cards. 640 * 641 * We use this method in preference to checking to see if 642 * the card is still there because the check suffers from 643 * a race condition in the bouncing case. Prior versions 644 * of the pccard software used a similar trick and achieved 645 * excellent results. 646 */ 647 if (sockevent & CBB_SOCKET_EVENT_CD) { 648 mtx_lock(&sc->mtx); 649 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 650 sc->flags &= ~CBB_CARD_OK; 651 cbb_disable_func_intr(sc); 652 cv_signal(&sc->cv); 653 mtx_unlock(&sc->mtx); 654 } 655 } 656 /* 657 * Some chips also require us to read the old ExCA registe for 658 * card status change when we route CSC vis PCI. This isn't supposed 659 * to be required, but it clears the interrupt state on some chipsets. 660 * Maybe there's a setting that would obviate its need. Maybe we 661 * should test the status bits and deal with them, but so far we've 662 * not found any machines that don't also give us the socket status 663 * indication above. 664 * 665 * We have to call this unconditionally because some bridges deliver 666 * the even independent of the CBB_SOCKET_EVENT_CD above. 667 */ 668 exca_getb(&sc->exca[0], EXCA_CSC); 669 } 670 671 /************************************************************************/ 672 /* Generic Power functions */ 673 /************************************************************************/ 674 675 static int 676 cbb_detect_voltage(device_t brdev) 677 { 678 struct cbb_softc *sc = device_get_softc(brdev); 679 uint32_t psr; 680 int vol = CARD_UKN_CARD; 681 682 psr = cbb_get(sc, CBB_SOCKET_STATE); 683 684 if (psr & CBB_STATE_5VCARD) 685 vol |= CARD_5V_CARD; 686 if (psr & CBB_STATE_3VCARD) 687 vol |= CARD_3V_CARD; 688 if (psr & CBB_STATE_XVCARD) 689 vol |= CARD_XV_CARD; 690 if (psr & CBB_STATE_YVCARD) 691 vol |= CARD_YV_CARD; 692 693 return (vol); 694 } 695 696 static uint8_t 697 cbb_o2micro_power_hack(struct cbb_softc *sc) 698 { 699 uint8_t reg; 700 701 /* 702 * Issue #2: INT# not qualified with IRQ Routing Bit. An 703 * unexpected PCI INT# may be generated during PC-Card 704 * initialization even with the IRQ Routing Bit Set with some 705 * PC-Cards. 706 * 707 * This is a two part issue. The first part is that some of 708 * our older controllers have an issue in which the slot's PCI 709 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 710 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 711 * is selected (ExCA register 03h bits 3:0, of the slot, are 712 * cleared) we will generate INT# if IREQ# is asserted. The 713 * second part is because some PC-Cards prematurally assert 714 * IREQ# before the ExCA registers are fully programmed. This 715 * in turn asserts INT# because ExCA register 03h bits 3:0 716 * (ISA IRQ Select) are not yet programmed. 717 * 718 * The fix for this issue, which will work for any controller 719 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 720 * (select IRQ1), of the slot, before turning on slot power. 721 * Selecting IRQ1 will result in INT# NOT being asserted 722 * (because IRQ1 is selected), and IRQ1 won't be asserted 723 * because our controllers don't generate IRQ1. 724 */ 725 reg = exca_getb(&sc->exca[0], EXCA_INTR); 726 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 727 return (reg); 728 } 729 730 /* 731 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 732 * we don't have an interrupt storm on power on. This has the efect of 733 * disabling card status change interrupts for the duration of poweron. 734 */ 735 static void 736 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 737 { 738 exca_putb(&sc->exca[0], EXCA_INTR, reg); 739 } 740 741 int 742 cbb_power(device_t brdev, int volts) 743 { 744 uint32_t status, sock_ctrl; 745 struct cbb_softc *sc = device_get_softc(brdev); 746 int timeout; 747 int retval = 0; 748 uint32_t sockevent; 749 uint8_t reg = 0; 750 751 status = cbb_get(sc, CBB_SOCKET_STATE); 752 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 753 754 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 755 switch (volts & CARD_VCCMASK) { 756 case 5: 757 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 758 break; 759 case 3: 760 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 761 break; 762 case XV: 763 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 764 break; 765 case YV: 766 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 767 break; 768 case 0: 769 break; 770 default: 771 return (0); /* power NEVER changed */ 772 } 773 774 /* VPP == VCC */ 775 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 776 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 777 778 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 779 return (1); /* no change necessary */ 780 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 781 if (volts != 0 && sc->chipset == CB_O2MICRO) 782 reg = cbb_o2micro_power_hack(sc); 783 784 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 785 status = cbb_get(sc, CBB_SOCKET_STATE); 786 787 /* 788 * XXX This busy wait is bogus. We should wait for a power 789 * interrupt and then whine if the status is bad. If we're 790 * worried about the card not coming up, then we should also 791 * schedule a timeout which we can cancel in the power interrupt. 792 */ 793 timeout = 20; 794 do { 795 DELAY(20*1000); 796 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 797 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 798 /* reset event status */ 799 /* XXX should only reset EVENT_POWER */ 800 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 801 if (timeout < 0) { 802 printf ("VCC supply failed.\n"); 803 goto done; 804 } 805 806 /* XXX 807 * delay 400 ms: thgough the standard defines that the Vcc set-up time 808 * is 20 ms, some PC-Card bridge requires longer duration. 809 * XXX Note: We should check the stutus AFTER the delay to give time 810 * for things to stabilize. 811 */ 812 DELAY(400*1000); 813 814 if (status & CBB_STATE_BAD_VCC_REQ) { 815 device_printf(sc->dev, 816 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 817 sock_ctrl ,status); 818 printf("cbb_power: %dV\n", volts); 819 goto done; 820 } 821 retval = 1; 822 done:; 823 if (volts != 0 && sc->chipset == CB_O2MICRO) 824 cbb_o2micro_power_hack2(sc, reg); 825 return (retval); 826 } 827 828 /* 829 * detect the voltage for the card, and set it. Since the power 830 * used is the square of the voltage, lower voltages is a big win 831 * and what Windows does (and what Microsoft prefers). The MS paper 832 * also talks about preferring the CIS entry as well. In addition, 833 * we power up with OE disabled. We'll set it later in the power 834 * up sequence. 835 */ 836 static int 837 cbb_do_power(device_t brdev) 838 { 839 struct cbb_softc *sc = device_get_softc(brdev); 840 int voltage; 841 842 /* Don't enable OE */ 843 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 844 845 /* Prefer lowest voltage supported */ 846 voltage = cbb_detect_voltage(brdev); 847 cbb_power(brdev, CARD_OFF); 848 if (voltage & CARD_YV_CARD) 849 cbb_power(brdev, CARD_VCC(YV)); 850 else if (voltage & CARD_XV_CARD) 851 cbb_power(brdev, CARD_VCC(XV)); 852 else if (voltage & CARD_3V_CARD) 853 cbb_power(brdev, CARD_VCC(3)); 854 else if (voltage & CARD_5V_CARD) 855 cbb_power(brdev, CARD_VCC(5)); 856 else { 857 device_printf(brdev, "Unknown card voltage\n"); 858 return (ENXIO); 859 } 860 return (0); 861 } 862 863 /************************************************************************/ 864 /* CardBus power functions */ 865 /************************************************************************/ 866 867 static void 868 cbb_cardbus_reset(device_t brdev) 869 { 870 struct cbb_softc *sc = device_get_softc(brdev); 871 int delay_us; 872 873 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 874 875 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 876 877 DELAY(delay_us); 878 879 /* If a card exists, unreset it! */ 880 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 881 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 882 &~CBBM_BRIDGECTRL_RESET, 2); 883 DELAY(delay_us); 884 } 885 } 886 887 static int 888 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 889 { 890 struct cbb_softc *sc = device_get_softc(brdev); 891 int err; 892 893 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 894 return (ENODEV); 895 896 err = cbb_do_power(brdev); 897 if (err) 898 return (err); 899 cbb_cardbus_reset(brdev); 900 return (0); 901 } 902 903 static void 904 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 905 { 906 cbb_power(brdev, CARD_OFF); 907 cbb_cardbus_reset(brdev); 908 } 909 910 /************************************************************************/ 911 /* CardBus Resource */ 912 /************************************************************************/ 913 914 static int 915 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 916 { 917 int basereg; 918 int limitreg; 919 920 if ((win < 0) || (win > 1)) { 921 DEVPRINTF((brdev, 922 "cbb_cardbus_io_open: window out of range %d\n", win)); 923 return (EINVAL); 924 } 925 926 basereg = win * 8 + CBBR_IOBASE0; 927 limitreg = win * 8 + CBBR_IOLIMIT0; 928 929 pci_write_config(brdev, basereg, start, 4); 930 pci_write_config(brdev, limitreg, end, 4); 931 return (0); 932 } 933 934 static int 935 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 936 { 937 int basereg; 938 int limitreg; 939 940 if ((win < 0) || (win > 1)) { 941 DEVPRINTF((brdev, 942 "cbb_cardbus_mem_open: window out of range %d\n", win)); 943 return (EINVAL); 944 } 945 946 basereg = win*8 + CBBR_MEMBASE0; 947 limitreg = win*8 + CBBR_MEMLIMIT0; 948 949 pci_write_config(brdev, basereg, start, 4); 950 pci_write_config(brdev, limitreg, end, 4); 951 return (0); 952 } 953 954 /* 955 * XXX The following function belongs in the pci bus layer. 956 */ 957 static void 958 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 959 { 960 uint32_t starts[2]; 961 uint32_t ends[2]; 962 struct cbb_reslist *rle; 963 int align; 964 int prefetchable[2]; 965 uint32_t reg; 966 967 starts[0] = starts[1] = 0xffffffff; 968 ends[0] = ends[1] = 0; 969 970 if (type == SYS_RES_MEMORY) 971 align = CBB_MEMALIGN; 972 else if (type == SYS_RES_IOPORT) 973 align = CBB_IOALIGN; 974 else 975 align = 1; 976 977 /* 978 * This looks somewhat bogus, and doesn't seem to really respect 979 * alignment. The alignment stuff is happening too late (it 980 * should happen at allocation time, not activation time) and 981 * this code looks generally to be too complex for the purpose 982 * it surves. 983 */ 984 SLIST_FOREACH(rle, &sc->rl, link) { 985 if (rle->type != type) 986 ; 987 else if (rle->res == NULL) { 988 device_printf(sc->dev, "WARNING: Resource not reserved? " 989 "(type=%d, addr=%lx)\n", 990 rle->type, rman_get_start(rle->res)); 991 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 992 /* XXX */ 993 } else if (starts[0] == 0xffffffff) { 994 starts[0] = rman_get_start(rle->res); 995 ends[0] = rman_get_end(rle->res); 996 prefetchable[0] = 997 rman_get_flags(rle->res) & RF_PREFETCHABLE; 998 } else if (rman_get_end(rle->res) > ends[0] && 999 rman_get_start(rle->res) - ends[0] < 1000 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1001 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1002 ends[0] = rman_get_end(rle->res); 1003 } else if (rman_get_start(rle->res) < starts[0] && 1004 starts[0] - rman_get_end(rle->res) < 1005 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1006 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1007 starts[0] = rman_get_start(rle->res); 1008 } else if (starts[1] == 0xffffffff) { 1009 starts[1] = rman_get_start(rle->res); 1010 ends[1] = rman_get_end(rle->res); 1011 prefetchable[1] = 1012 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1013 } else if (rman_get_end(rle->res) > ends[1] && 1014 rman_get_start(rle->res) - ends[1] < 1015 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1016 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1017 ends[1] = rman_get_end(rle->res); 1018 } else if (rman_get_start(rle->res) < starts[1] && 1019 starts[1] - rman_get_end(rle->res) < 1020 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1021 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1022 starts[1] = rman_get_start(rle->res); 1023 } else { 1024 uint32_t diffs[2]; 1025 int win; 1026 1027 diffs[0] = diffs[1] = 0xffffffff; 1028 if (rman_get_start(rle->res) > ends[0]) 1029 diffs[0] = rman_get_start(rle->res) - ends[0]; 1030 else if (rman_get_end(rle->res) < starts[0]) 1031 diffs[0] = starts[0] - rman_get_end(rle->res); 1032 if (rman_get_start(rle->res) > ends[1]) 1033 diffs[1] = rman_get_start(rle->res) - ends[1]; 1034 else if (rman_get_end(rle->res) < starts[1]) 1035 diffs[1] = starts[1] - rman_get_end(rle->res); 1036 1037 win = (diffs[0] <= diffs[1])?0:1; 1038 if (rman_get_start(rle->res) > ends[win]) 1039 ends[win] = rman_get_end(rle->res); 1040 else if (rman_get_end(rle->res) < starts[win]) 1041 starts[win] = rman_get_start(rle->res); 1042 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1043 prefetchable[win] = 0; 1044 } 1045 1046 if (starts[0] != 0xffffffff) 1047 starts[0] -= starts[0] % align; 1048 if (starts[1] != 0xffffffff) 1049 starts[1] -= starts[1] % align; 1050 if (ends[0] % align != 0) 1051 ends[0] += align - ends[0] % align - 1; 1052 if (ends[1] % align != 0) 1053 ends[1] += align - ends[1] % align - 1; 1054 } 1055 1056 if (type == SYS_RES_MEMORY) { 1057 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1058 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1059 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1060 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1061 CBBM_BRIDGECTRL_PREFETCH_1); 1062 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1063 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1064 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1065 } else if (type == SYS_RES_IOPORT) { 1066 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1067 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1068 } 1069 } 1070 1071 static int 1072 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1073 int rid, struct resource *res) 1074 { 1075 int ret; 1076 1077 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1078 type, rid, res); 1079 if (ret != 0) 1080 return (ret); 1081 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1082 return (0); 1083 } 1084 1085 static int 1086 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1087 int rid, struct resource *res) 1088 { 1089 int ret; 1090 1091 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1092 type, rid, res); 1093 if (ret != 0) 1094 return (ret); 1095 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1096 return (0); 1097 } 1098 1099 static struct resource * 1100 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1101 int *rid, u_long start, u_long end, u_long count, u_int flags) 1102 { 1103 struct cbb_softc *sc = device_get_softc(brdev); 1104 int tmp; 1105 struct resource *res; 1106 u_long align; 1107 1108 switch (type) { 1109 case SYS_RES_IRQ: 1110 tmp = rman_get_start(sc->irq_res); 1111 if (start > tmp || end < tmp || count != 1) { 1112 device_printf(child, "requested interrupt %ld-%ld," 1113 "count = %ld not supported by cbb\n", 1114 start, end, count); 1115 return (NULL); 1116 } 1117 start = end = tmp; 1118 flags |= RF_SHAREABLE; 1119 break; 1120 case SYS_RES_IOPORT: 1121 if (start <= cbb_start_32_io) 1122 start = cbb_start_32_io; 1123 if (end < start) 1124 end = start; 1125 break; 1126 case SYS_RES_MEMORY: 1127 if (start <= cbb_start_mem) 1128 start = cbb_start_mem; 1129 if (end < start) 1130 end = start; 1131 if (count < CBB_MEMALIGN) 1132 align = CBB_MEMALIGN; 1133 else 1134 align = count; 1135 if (align > (1 << RF_ALIGNMENT(flags))) 1136 flags = (flags & ~RF_ALIGNMENT_MASK) | 1137 rman_make_alignment_flags(align); 1138 break; 1139 } 1140 1141 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1142 start, end, count, flags & ~RF_ACTIVE); 1143 if (res == NULL) { 1144 printf("cbb alloc res fail\n"); 1145 return (NULL); 1146 } 1147 cbb_insert_res(sc, res, type, *rid); 1148 if (flags & RF_ACTIVE) 1149 if (bus_activate_resource(child, type, *rid, res) != 0) { 1150 bus_release_resource(child, type, *rid, res); 1151 return (NULL); 1152 } 1153 1154 return (res); 1155 } 1156 1157 static int 1158 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1159 int rid, struct resource *res) 1160 { 1161 struct cbb_softc *sc = device_get_softc(brdev); 1162 int error; 1163 1164 if (rman_get_flags(res) & RF_ACTIVE) { 1165 error = bus_deactivate_resource(child, type, rid, res); 1166 if (error != 0) 1167 return (error); 1168 } 1169 cbb_remove_res(sc, res); 1170 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1171 type, rid, res)); 1172 } 1173 1174 /************************************************************************/ 1175 /* PC Card Power Functions */ 1176 /************************************************************************/ 1177 1178 static int 1179 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1180 { 1181 struct cbb_softc *sc = device_get_softc(brdev); 1182 int err; 1183 1184 DPRINTF(("cbb_pcic_socket_enable:\n")); 1185 1186 /* power down/up the socket to reset */ 1187 err = cbb_do_power(brdev); 1188 if (err) 1189 return (err); 1190 exca_reset(&sc->exca[0], child); 1191 1192 return (0); 1193 } 1194 1195 static void 1196 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1197 { 1198 struct cbb_softc *sc = device_get_softc(brdev); 1199 1200 DPRINTF(("cbb_pcic_socket_disable\n")); 1201 1202 /* reset signal asserting... */ 1203 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 1204 DELAY(2*1000); 1205 1206 /* power down the socket */ 1207 cbb_power(brdev, CARD_OFF); 1208 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 1209 1210 /* wait 300ms until power fails (Tpf). */ 1211 DELAY(300 * 1000); 1212 } 1213 1214 /************************************************************************/ 1215 /* POWER methods */ 1216 /************************************************************************/ 1217 1218 int 1219 cbb_power_enable_socket(device_t brdev, device_t child) 1220 { 1221 struct cbb_softc *sc = device_get_softc(brdev); 1222 1223 if (sc->flags & CBB_16BIT_CARD) 1224 return (cbb_pcic_power_enable_socket(brdev, child)); 1225 else 1226 return (cbb_cardbus_power_enable_socket(brdev, child)); 1227 } 1228 1229 void 1230 cbb_power_disable_socket(device_t brdev, device_t child) 1231 { 1232 struct cbb_softc *sc = device_get_softc(brdev); 1233 if (sc->flags & CBB_16BIT_CARD) 1234 cbb_pcic_power_disable_socket(brdev, child); 1235 else 1236 cbb_cardbus_power_disable_socket(brdev, child); 1237 } 1238 1239 static int 1240 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1241 struct resource *res) 1242 { 1243 struct cbb_softc *sc = device_get_softc(brdev); 1244 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1245 } 1246 1247 static int 1248 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1249 int rid, struct resource *res) 1250 { 1251 struct cbb_softc *sc = device_get_softc(brdev); 1252 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1253 } 1254 1255 static struct resource * 1256 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1257 u_long start, u_long end, u_long count, u_int flags) 1258 { 1259 struct resource *res = NULL; 1260 struct cbb_softc *sc = device_get_softc(brdev); 1261 int align; 1262 int tmp; 1263 1264 switch (type) { 1265 case SYS_RES_MEMORY: 1266 if (start < cbb_start_mem) 1267 start = cbb_start_mem; 1268 if (end < start) 1269 end = start; 1270 if (count < CBB_MEMALIGN) 1271 align = CBB_MEMALIGN; 1272 else 1273 align = count; 1274 if (align > (1 << RF_ALIGNMENT(flags))) 1275 flags = (flags & ~RF_ALIGNMENT_MASK) | 1276 rman_make_alignment_flags(align); 1277 break; 1278 case SYS_RES_IOPORT: 1279 if (start < cbb_start_16_io) 1280 start = cbb_start_16_io; 1281 if (end < start) 1282 end = start; 1283 break; 1284 case SYS_RES_IRQ: 1285 tmp = rman_get_start(sc->irq_res); 1286 if (start > tmp || end < tmp || count != 1) { 1287 device_printf(child, "requested interrupt %ld-%ld," 1288 "count = %ld not supported by cbb\n", 1289 start, end, count); 1290 return (NULL); 1291 } 1292 flags |= RF_SHAREABLE; 1293 start = end = rman_get_start(sc->irq_res); 1294 break; 1295 } 1296 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1297 start, end, count, flags & ~RF_ACTIVE); 1298 if (res == NULL) 1299 return (NULL); 1300 cbb_insert_res(sc, res, type, *rid); 1301 if (flags & RF_ACTIVE) { 1302 if (bus_activate_resource(child, type, *rid, res) != 0) { 1303 bus_release_resource(child, type, *rid, res); 1304 return (NULL); 1305 } 1306 } 1307 1308 return (res); 1309 } 1310 1311 static int 1312 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1313 int rid, struct resource *res) 1314 { 1315 struct cbb_softc *sc = device_get_softc(brdev); 1316 int error; 1317 1318 if (rman_get_flags(res) & RF_ACTIVE) { 1319 error = bus_deactivate_resource(child, type, rid, res); 1320 if (error != 0) 1321 return (error); 1322 } 1323 cbb_remove_res(sc, res); 1324 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1325 type, rid, res)); 1326 } 1327 1328 /************************************************************************/ 1329 /* PC Card methods */ 1330 /************************************************************************/ 1331 1332 int 1333 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1334 uint32_t flags) 1335 { 1336 struct cbb_softc *sc = device_get_softc(brdev); 1337 struct resource *res; 1338 1339 if (type != SYS_RES_MEMORY) 1340 return (EINVAL); 1341 res = cbb_find_res(sc, type, rid); 1342 if (res == NULL) { 1343 device_printf(brdev, 1344 "set_res_flags: specified rid not found\n"); 1345 return (ENOENT); 1346 } 1347 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1348 } 1349 1350 int 1351 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1352 uint32_t cardaddr, uint32_t *deltap) 1353 { 1354 struct cbb_softc *sc = device_get_softc(brdev); 1355 struct resource *res; 1356 1357 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1358 if (res == NULL) { 1359 device_printf(brdev, 1360 "set_memory_offset: specified rid not found\n"); 1361 return (ENOENT); 1362 } 1363 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1364 } 1365 1366 /************************************************************************/ 1367 /* BUS Methods */ 1368 /************************************************************************/ 1369 1370 1371 int 1372 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1373 struct resource *r) 1374 { 1375 struct cbb_softc *sc = device_get_softc(brdev); 1376 1377 if (sc->flags & CBB_16BIT_CARD) 1378 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1379 else 1380 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1381 r)); 1382 } 1383 1384 int 1385 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1386 int rid, struct resource *r) 1387 { 1388 struct cbb_softc *sc = device_get_softc(brdev); 1389 1390 if (sc->flags & CBB_16BIT_CARD) 1391 return (cbb_pcic_deactivate_resource(brdev, child, type, 1392 rid, r)); 1393 else 1394 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1395 rid, r)); 1396 } 1397 1398 struct resource * 1399 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1400 u_long start, u_long end, u_long count, u_int flags) 1401 { 1402 struct cbb_softc *sc = device_get_softc(brdev); 1403 1404 if (sc->flags & CBB_16BIT_CARD) 1405 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1406 start, end, count, flags)); 1407 else 1408 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1409 start, end, count, flags)); 1410 } 1411 1412 int 1413 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1414 struct resource *r) 1415 { 1416 struct cbb_softc *sc = device_get_softc(brdev); 1417 1418 if (sc->flags & CBB_16BIT_CARD) 1419 return (cbb_pcic_release_resource(brdev, child, type, 1420 rid, r)); 1421 else 1422 return (cbb_cardbus_release_resource(brdev, child, type, 1423 rid, r)); 1424 } 1425 1426 int 1427 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1428 { 1429 struct cbb_softc *sc = device_get_softc(brdev); 1430 1431 switch (which) { 1432 case PCIB_IVAR_BUS: 1433 *result = sc->secbus; 1434 return (0); 1435 } 1436 return (ENOENT); 1437 } 1438 1439 int 1440 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1441 { 1442 struct cbb_softc *sc = device_get_softc(brdev); 1443 1444 switch (which) { 1445 case PCIB_IVAR_BUS: 1446 sc->secbus = value; 1447 break; 1448 } 1449 return (ENOENT); 1450 } 1451 1452 /************************************************************************/ 1453 /* PCI compat methods */ 1454 /************************************************************************/ 1455 1456 int 1457 cbb_maxslots(device_t brdev) 1458 { 1459 return (0); 1460 } 1461 1462 uint32_t 1463 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1464 { 1465 uint32_t rv; 1466 1467 /* 1468 * Pass through to the next ppb up the chain (i.e. our grandparent). 1469 */ 1470 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1471 b, s, f, reg, width); 1472 return (rv); 1473 } 1474 1475 void 1476 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1477 int width) 1478 { 1479 /* 1480 * Pass through to the next ppb up the chain (i.e. our grandparent). 1481 */ 1482 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1483 b, s, f, reg, val, width); 1484 } 1485 1486 int 1487 cbb_suspend(device_t self) 1488 { 1489 int error = 0; 1490 struct cbb_softc *sc = device_get_softc(self); 1491 1492 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1493 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1494 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1495 error = bus_generic_suspend(self); 1496 return (error); 1497 } 1498 1499 int 1500 cbb_resume(device_t self) 1501 { 1502 int error = 0; 1503 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1504 uint32_t tmp; 1505 1506 /* 1507 * Some BIOSes will not save the BARs for the pci chips, so we 1508 * must do it ourselves. If the BAR is reset to 0 for an I/O 1509 * device, it will read back as 0x1, so no explicit test for 1510 * memory devices are needed. 1511 * 1512 * Note: The PCI bus code should do this automatically for us on 1513 * suspend/resume, but until it does, we have to cope. 1514 */ 1515 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1516 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1517 rman_get_start(sc->base_res))); 1518 1519 sc->chipinit(sc); 1520 1521 /* reset interrupt -- Do we really need to do this? */ 1522 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1523 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1524 1525 /* re-establish the interrupt. */ 1526 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 1527 cbb_intr, sc, &sc->intrhand)) { 1528 device_printf(self, "couldn't re-establish interrupt"); 1529 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1530 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1531 sc->base_res); 1532 sc->irq_res = NULL; 1533 sc->base_res = NULL; 1534 return (ENOMEM); 1535 } 1536 1537 /* CSC Interrupt: Card detect interrupt on */ 1538 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1539 1540 /* Signal the thread to wakeup. */ 1541 mtx_lock(&sc->mtx); 1542 cv_signal(&sc->cv); 1543 mtx_unlock(&sc->mtx); 1544 1545 error = bus_generic_resume(self); 1546 1547 return (error); 1548 } 1549 1550 int 1551 cbb_child_present(device_t self) 1552 { 1553 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1554 uint32_t sockstate; 1555 1556 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1557 return (CBB_CARD_PRESENT(sockstate) && 1558 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1559 } 1560