1 /* 2 * Copyright (c) 2002 M. Warner Losh. 3 * Copyright (c) 2000,2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 1998, 1999 and 2000 34 * HAYAKAWA Koichi. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by HAYAKAWA Koichi. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for PCI to CardBus Bridge chips 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 93 #include <pci/pcireg.h> 94 #include <pci/pcivar.h> 95 #include <machine/clock.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 #define CBB_START_MEM 0x88000000 120 #define CBB_START_32_IO 0x1000 121 #define CBB_START_16_IO 0x100 122 123 struct yenta_chipinfo { 124 uint32_t yc_id; 125 const char *yc_name; 126 int yc_chiptype; 127 } yc_chipsets[] = { 128 /* Texas Instruments chips */ 129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 132 133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 154 155 /* Ricoh chips */ 156 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 157 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 158 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 159 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 160 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 161 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 162 163 /* Toshiba products */ 164 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 165 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 166 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 167 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 168 169 /* Cirrus Logic */ 170 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 171 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 172 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 173 174 /* 02Micro */ 175 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_CIRRUS}, 176 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_CIRRUS}, 177 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_CIRRUS}, 178 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_CIRRUS}, 179 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_CIRRUS}, 180 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_CIRRUS}, 181 182 /* sentinel */ 183 {0 /* null id */, "unknown", CB_UNKNOWN}, 184 }; 185 186 /* sysctl vars */ 187 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 188 189 /* There's no way to say TUNEABLE_LONG to get the right types */ 190 u_long cbb_start_mem = CBB_START_MEM; 191 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 192 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 193 &cbb_start_mem, CBB_START_MEM, 194 "Starting address for memory allocations"); 195 196 u_long cbb_start_16_io = CBB_START_16_IO; 197 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 198 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 199 &cbb_start_16_io, CBB_START_16_IO, 200 "Starting ioport for 16-bit cards"); 201 202 u_long cbb_start_32_io = CBB_START_32_IO; 203 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 204 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 205 &cbb_start_32_io, CBB_START_32_IO, 206 "Starting ioport for 32-bit cards"); 207 208 int cbb_debug = 0; 209 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 210 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 211 "Verbose cardbus bridge debugging"); 212 213 static int cbb_chipset(uint32_t pci_id, const char **namep); 214 static int cbb_probe(device_t brdev); 215 static void cbb_chipinit(struct cbb_softc *sc); 216 static int cbb_attach(device_t brdev); 217 static int cbb_detach(device_t brdev); 218 static int cbb_shutdown(device_t brdev); 219 static void cbb_driver_added(device_t brdev, driver_t *driver); 220 static void cbb_child_detached(device_t brdev, device_t child); 221 static void cbb_event_thread(void *arg); 222 static void cbb_insert(struct cbb_softc *sc); 223 static void cbb_removal(struct cbb_softc *sc); 224 static void cbb_intr(void *arg); 225 static int cbb_detect_voltage(device_t brdev); 226 static int cbb_power(device_t brdev, int volts); 227 static void cbb_cardbus_reset(device_t brdev); 228 static int cbb_cardbus_power_enable_socket(device_t brdev, 229 device_t child); 230 static void cbb_cardbus_power_disable_socket(device_t brdev, 231 device_t child); 232 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 233 uint32_t end); 234 static int cbb_cardbus_mem_open(device_t brdev, int win, 235 uint32_t start, uint32_t end); 236 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 237 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 238 int type, int rid, struct resource *res); 239 static int cbb_cardbus_deactivate_resource(device_t brdev, 240 device_t child, int type, int rid, struct resource *res); 241 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 242 device_t child, int type, int *rid, u_long start, 243 u_long end, u_long count, uint flags); 244 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 245 int type, int rid, struct resource *res); 246 static int cbb_power_enable_socket(device_t brdev, device_t child); 247 static void cbb_power_disable_socket(device_t brdev, device_t child); 248 static int cbb_activate_resource(device_t brdev, device_t child, 249 int type, int rid, struct resource *r); 250 static int cbb_deactivate_resource(device_t brdev, device_t child, 251 int type, int rid, struct resource *r); 252 static struct resource *cbb_alloc_resource(device_t brdev, device_t child, 253 int type, int *rid, u_long start, u_long end, u_long count, 254 uint flags); 255 static int cbb_release_resource(device_t brdev, device_t child, 256 int type, int rid, struct resource *r); 257 static int cbb_read_ivar(device_t brdev, device_t child, int which, 258 uintptr_t *result); 259 static int cbb_write_ivar(device_t brdev, device_t child, int which, 260 uintptr_t value); 261 static int cbb_maxslots(device_t brdev); 262 static uint32_t cbb_read_config(device_t brdev, int b, int s, int f, 263 int reg, int width); 264 static void cbb_write_config(device_t brdev, int b, int s, int f, 265 int reg, uint32_t val, int width); 266 267 /* 268 */ 269 static __inline void 270 cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val) 271 { 272 bus_space_write_4(sc->bst, sc->bsh, reg, val); 273 } 274 275 static __inline uint32_t 276 cbb_get(struct cbb_softc *sc, uint32_t reg) 277 { 278 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 279 } 280 281 static __inline void 282 cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 283 { 284 cbb_set(sc, reg, cbb_get(sc, reg) | bits); 285 } 286 287 static __inline void 288 cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits) 289 { 290 cbb_set(sc, reg, cbb_get(sc, reg) & ~bits); 291 } 292 293 static void 294 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 295 { 296 struct cbb_reslist *rle; 297 298 SLIST_FOREACH(rle, &sc->rl, link) { 299 if (rle->res == res) { 300 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 301 free(rle, M_DEVBUF); 302 return; 303 } 304 } 305 } 306 307 static struct resource * 308 cbb_find_res(struct cbb_softc *sc, int type, int rid) 309 { 310 struct cbb_reslist *rle; 311 312 SLIST_FOREACH(rle, &sc->rl, link) 313 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 314 return (rle->res); 315 return (NULL); 316 } 317 318 static void 319 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 320 int rid) 321 { 322 struct cbb_reslist *rle; 323 324 /* 325 * Need to record allocated resource so we can iterate through 326 * it later. 327 */ 328 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 329 if (!res) 330 panic("cbb_cardbus_alloc_resource: can't record entry!"); 331 rle->res = res; 332 rle->type = type; 333 rle->rid = rid; 334 SLIST_INSERT_HEAD(&sc->rl, rle, link); 335 } 336 337 static void 338 cbb_destroy_res(struct cbb_softc *sc) 339 { 340 struct cbb_reslist *rle; 341 342 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 343 device_printf(sc->dev, "Danger Will Robinson: Resource " 344 "left allocated! This is a bug... " 345 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 346 rman_get_start(rle->res)); 347 SLIST_REMOVE_HEAD(&sc->rl, link); 348 free(rle, M_DEVBUF); 349 } 350 } 351 352 /************************************************************************/ 353 /* Probe/Attach */ 354 /************************************************************************/ 355 356 static int 357 cbb_chipset(uint32_t pci_id, const char **namep) 358 { 359 struct yenta_chipinfo *ycp; 360 361 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 362 continue; 363 if (namep != NULL) 364 *namep = ycp->yc_name; 365 return (ycp->yc_chiptype); 366 } 367 368 static int 369 cbb_probe(device_t brdev) 370 { 371 const char *name; 372 uint32_t progif; 373 uint32_t subclass; 374 375 /* 376 * Do we know that we support the chipset? If so, then we 377 * accept the device. 378 */ 379 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 380 device_set_desc(brdev, name); 381 return (0); 382 } 383 384 /* 385 * We do support generic CardBus bridges. All that we've seen 386 * to date have progif 0 (the Yenta spec, and successors mandate 387 * this). We do not support PCI PCMCIA bridges (with one exception) 388 * with this driver since they generally are I/O mapped. Those 389 * are supported by the pcic driver. This should help us be more 390 * future proof. 391 */ 392 subclass = pci_get_subclass(brdev); 393 progif = pci_get_progif(brdev); 394 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 395 device_set_desc(brdev, "PCI-CardBus Bridge"); 396 return (0); 397 } 398 return (ENXIO); 399 } 400 401 402 static void 403 cbb_chipinit(struct cbb_softc *sc) 404 { 405 uint32_t mux, sysctrl; 406 407 /* Set CardBus latency timer */ 408 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 409 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 410 411 /* Set PCI latency timer */ 412 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 413 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 414 415 /* Enable memory access */ 416 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 417 | PCIM_CMD_MEMEN 418 | PCIM_CMD_PORTEN 419 | PCIM_CMD_BUSMASTEREN, 2); 420 421 /* disable Legacy IO */ 422 switch (sc->chipset) { 423 case CB_RF5C46X: 424 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 425 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 426 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 427 break; 428 default: 429 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 430 break; 431 } 432 433 /* Use PCI interrupt for interrupt routing */ 434 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 435 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 436 CBBM_BRIDGECTRL_INTR_IREQ_EN), 437 | CBBM_BRIDGECTRL_WRITE_POST_EN, 438 2); 439 440 /* 441 * XXX this should be a function table, ala OLDCARD. This means 442 * that we could more easily support ISA interrupts for pccard 443 * cards if we had to. 444 */ 445 switch (sc->chipset) { 446 case CB_TI113X: 447 /* 448 * The TI 1031, TI 1130 and TI 1131 all require another bit 449 * be set to enable PCI routing of interrupts, and then 450 * a bit for each of the CSC and Function interrupts we 451 * want routed. 452 */ 453 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 454 | CBBM_CBCTRL_113X_PCI_INTR | 455 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 456 1); 457 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 458 & ~(CBBM_DEVCTRL_INT_SERIAL | 459 CBBM_DEVCTRL_INT_PCI), 1); 460 break; 461 case CB_TI12XX: 462 /* 463 * Some TI 12xx (and [14][45]xx) based pci cards 464 * sometimes have issues with the MFUNC register not 465 * being initialized due to a bad EEPROM on board. 466 * Laptops that this matters on have this register 467 * properly initialized. 468 * 469 * The TI125X parts have a different register. 470 */ 471 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 472 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 473 if (mux == 0) { 474 mux = (mux & ~CBBM_MFUNC_PIN0) | 475 CBBM_MFUNC_PIN0_INTA; 476 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 477 mux = (mux & ~CBBM_MFUNC_PIN1) | 478 CBBM_MFUNC_PIN1_INTB; 479 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 480 } 481 /*FALLTHROUGH*/ 482 case CB_TI125X: 483 /* 484 * Disable zoom video. Some machines initialize this 485 * improperly and exerpience has shown that this helps 486 * on some machines. 487 */ 488 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 489 break; 490 case CB_TOPIC97: 491 /* 492 * Disable Zoom Video, ToPIC 97, 100. 493 */ 494 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1); 495 /* 496 * ToPIC 97, 100 497 * At offset 0xa1: INTERRUPT CONTROL register 498 * 0x1: Turn on INT interrupts. 499 */ 500 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL, 501 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1); 502 goto topic_common; 503 case CB_TOPIC95: 504 /* 505 * SOCKETCTRL appears to be TOPIC 95/B specific 506 */ 507 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL, 508 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 509 510 topic_common:; 511 /* 512 * At offset 0xa0: SLOT CONTROL 513 * 0x80 Enable CardBus Functionality 514 * 0x40 Enable CardBus and PC Card registers 515 * 0x20 Lock ID in exca regs 516 * 0x10 Write protect ID in config regs 517 * Clear the rest of the bits, which defaults the slot 518 * in legacy mode to 0x3e0 and offset 0. (legacy 519 * mode is determined elsewhere) 520 */ 521 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL, 522 CBBM_TOPIC_SLOTCTRL_SLOTON | 523 CBBM_TOPIC_SLOTCTRL_SLOTEN | 524 CBBM_TOPIC_SLOTCTRL_ID_LOCK | 525 CBBM_TOPIC_SLOTCTRL_ID_WP, 1); 526 527 /* 528 * At offset 0xa3 Card Detect Control Register 529 * 0x80 CARDBUS enbale 530 * 0x01 Cleared for hardware change detect 531 */ 532 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC, 533 | CBBM_TOPIC_CDC_CARDBUS, 534 & ~CBBM_TOPIC_CDC_SWDETECT, 4); 535 break; 536 } 537 538 /* 539 * Need to tell ExCA registers to route via PCI interrupts. There 540 * are two ways to do this. Once is to set INTR_ENABLE and the 541 * other is to set CSC to 0. Since both methods are mutually 542 * compatible, we do both. 543 */ 544 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 545 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 546 547 /* close all memory and io windows */ 548 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 549 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 550 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 551 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 552 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 553 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 554 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 555 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 556 } 557 558 static int 559 cbb_attach(device_t brdev) 560 { 561 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 562 int rid; 563 564 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 565 cv_init(&sc->cv, "cbb cv"); 566 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 567 sc->dev = brdev; 568 sc->cbdev = NULL; 569 sc->pccarddev = NULL; 570 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 571 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 572 SLIST_INIT(&sc->rl); 573 STAILQ_INIT(&sc->intr_handlers); 574 575 #ifndef BURN_THE_BOATS 576 /* 577 * The PCI bus code should assign us memory in the absense 578 * of the BIOS doing so. However, 'should' isn't 'is,' so we kludge 579 * up something here until the PCI/acpi code properly assigns the 580 * resource. 581 */ 582 #endif 583 rid = CBBR_SOCKBASE; 584 sc->base_res = bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 585 0, ~0, 1, RF_ACTIVE); 586 if (!sc->base_res) { 587 #ifdef BURN_THE_BOATS 588 device_printf(brdev, "Could not map register memory\n"); 589 mtx_destroy(&sc->mtx); 590 cv_destroy(&sc->cv); 591 return (ENOMEM); 592 #else 593 uint32_t sockbase; 594 /* 595 * Generally, the BIOS will assign this memory for us. 596 * However, newer BIOSes do not because the MS design 597 * documents have mandated that this is for the OS 598 * to assign rather than the BIOS. This driver shouldn't 599 * be doing this, but until the pci bus code (or acpi) 600 * does this, we allow CardBus bridges to work on more 601 * machines. 602 */ 603 pci_write_config(brdev, rid, 0xfffffffful, 4); 604 sockbase = pci_read_config(brdev, rid, 4); 605 sockbase = (sockbase & 0xfffffff0ul) & 606 -(sockbase & 0xfffffff0ul); 607 sc->base_res = bus_generic_alloc_resource( 608 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 609 &rid, cbb_start_mem, ~0, sockbase, 610 RF_ACTIVE | rman_make_alignment_flags(sockbase)); 611 if (!sc->base_res) { 612 device_printf(brdev, 613 "Could not grab register memory\n"); 614 mtx_destroy(&sc->mtx); 615 cv_destroy(&sc->cv); 616 return (ENOMEM); 617 } 618 sc->flags |= CBB_KLUDGE_ALLOC; 619 pci_write_config(brdev, CBBR_SOCKBASE, 620 rman_get_start(sc->base_res), 4); 621 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 622 rman_get_start(sc->base_res))); 623 #endif 624 } 625 626 sc->bst = rman_get_bustag(sc->base_res); 627 sc->bsh = rman_get_bushandle(sc->base_res); 628 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 629 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 630 sc->exca.chipset = EXCA_CARDBUS; 631 cbb_chipinit(sc); 632 633 /* attach children */ 634 sc->cbdev = device_add_child(brdev, "cardbus", -1); 635 if (sc->cbdev == NULL) 636 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 637 else if (device_probe_and_attach(sc->cbdev) != 0) { 638 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 639 sc->cbdev = NULL; 640 } 641 642 sc->pccarddev = device_add_child(brdev, "pccard", -1); 643 if (sc->pccarddev == NULL) 644 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 645 else if (device_probe_and_attach(sc->pccarddev) != 0) { 646 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 647 sc->pccarddev = NULL; 648 } 649 650 /* Map and establish the interrupt. */ 651 rid = 0; 652 sc->irq_res = bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 653 RF_SHAREABLE | RF_ACTIVE); 654 if (sc->irq_res == NULL) { 655 printf("cbb: Unable to map IRQ...\n"); 656 goto err; 657 } 658 659 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 660 &sc->intrhand)) { 661 device_printf(brdev, "couldn't establish interrupt"); 662 goto err; 663 } 664 665 /* reset 16-bit pcmcia bus */ 666 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 667 668 /* turn off power */ 669 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 670 671 /* CSC Interrupt: Card detect interrupt on */ 672 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 673 674 /* reset interrupt */ 675 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 676 677 /* Start the thread */ 678 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 679 "%s%d", device_get_name(sc->dev), device_get_unit(sc->dev))) { 680 device_printf (sc->dev, "unable to create event thread.\n"); 681 panic ("cbb_create_event_thread"); 682 } 683 684 return (0); 685 err: 686 if (sc->irq_res) 687 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 688 if (sc->base_res) { 689 if (sc->flags & CBB_KLUDGE_ALLOC) 690 bus_generic_release_resource(device_get_parent(brdev), 691 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 692 sc->base_res); 693 else 694 bus_release_resource(brdev, SYS_RES_MEMORY, 695 CBBR_SOCKBASE, sc->base_res); 696 } 697 mtx_destroy(&sc->mtx); 698 cv_destroy(&sc->cv); 699 return (ENOMEM); 700 } 701 702 static int 703 cbb_detach(device_t brdev) 704 { 705 struct cbb_softc *sc = device_get_softc(brdev); 706 int numdevs; 707 device_t *devlist; 708 int tmp; 709 int error; 710 711 device_get_children(brdev, &devlist, &numdevs); 712 713 error = 0; 714 for (tmp = 0; tmp < numdevs; tmp++) { 715 if (device_detach(devlist[tmp]) == 0) 716 device_delete_child(brdev, devlist[tmp]); 717 else 718 error++; 719 } 720 free(devlist, M_TEMP); 721 if (error > 0) 722 return (ENXIO); 723 724 mtx_lock(&sc->mtx); 725 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 726 sc->flags |= CBB_KTHREAD_DONE; 727 if (sc->flags & CBB_KTHREAD_RUNNING) { 728 cv_broadcast(&sc->cv); 729 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 730 } 731 mtx_unlock(&sc->mtx); 732 733 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 734 if (sc->flags & CBB_KLUDGE_ALLOC) 735 bus_generic_release_resource(device_get_parent(brdev), 736 brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, sc->base_res); 737 else 738 bus_release_resource(brdev, SYS_RES_MEMORY, 739 CBBR_SOCKBASE, sc->base_res); 740 mtx_destroy(&sc->mtx); 741 cv_destroy(&sc->cv); 742 return (0); 743 } 744 745 static int 746 cbb_shutdown(device_t brdev) 747 { 748 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 749 /* properly reset everything at shutdown */ 750 751 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 752 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 753 754 cbb_set(sc, CBB_SOCKET_MASK, 0); 755 756 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 757 758 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 759 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 760 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 761 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 762 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 763 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 764 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 765 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 766 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 767 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 768 return (0); 769 } 770 771 static int 772 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 773 int flags, driver_intr_t *intr, void *arg, void **cookiep) 774 { 775 struct cbb_intrhand *ih; 776 struct cbb_softc *sc = device_get_softc(dev); 777 778 /* 779 * You aren't allowed to have fast interrupts for pccard/cardbus 780 * things since those interrupts are PCI and shared. Since we use 781 * the PCI interrupt for the status change interrupts, it can't be 782 * free for use by the driver. Fast interrupts must not be shared. 783 */ 784 if ((flags & INTR_FAST) != 0) 785 return (EINVAL); 786 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 787 if (ih == NULL) 788 return (ENOMEM); 789 *cookiep = ih; 790 ih->intr = intr; 791 ih->arg = arg; 792 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 793 /* 794 * XXX need to turn on ISA interrupts, if we ever support them, but 795 * XXX for now that's all we need to do. 796 */ 797 return (0); 798 } 799 800 static int 801 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 802 void *cookie) 803 { 804 struct cbb_intrhand *ih; 805 struct cbb_softc *sc = device_get_softc(dev); 806 807 /* XXX Need to do different things for ISA interrupts. */ 808 ih = (struct cbb_intrhand *) cookie; 809 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 810 free(ih, M_DEVBUF); 811 return (0); 812 } 813 814 815 static void 816 cbb_driver_added(device_t brdev, driver_t *driver) 817 { 818 struct cbb_softc *sc = device_get_softc(brdev); 819 device_t *devlist; 820 device_t dev; 821 int tmp; 822 int numdevs; 823 int wake = 0; 824 825 DEVICE_IDENTIFY(driver, brdev); 826 device_get_children(brdev, &devlist, &numdevs); 827 for (tmp = 0; tmp < numdevs; tmp++) { 828 dev = devlist[tmp]; 829 if (device_get_state(dev) == DS_NOTPRESENT && 830 device_probe_and_attach(dev) == 0) 831 wake++; 832 } 833 free(devlist, M_TEMP); 834 835 if (wake > 0) { 836 mtx_lock(&sc->mtx); 837 cv_signal(&sc->cv); 838 mtx_unlock(&sc->mtx); 839 } 840 } 841 842 static void 843 cbb_child_detached(device_t brdev, device_t child) 844 { 845 struct cbb_softc *sc = device_get_softc(brdev); 846 847 if (child != sc->cbdev && child != sc->pccarddev) 848 device_printf(brdev, "Unknown child detached: %s\n", 849 device_get_nameunit(child)); 850 } 851 852 /************************************************************************/ 853 /* Kthreads */ 854 /************************************************************************/ 855 856 static void 857 cbb_event_thread(void *arg) 858 { 859 struct cbb_softc *sc = arg; 860 uint32_t status; 861 int err; 862 863 /* 864 * We take out Giant here because we need it deep, down in 865 * the bowels of the vm system for mapping the memory we need 866 * to read the CIS. We also need it for kthread_exit, which 867 * drops it. 868 */ 869 sc->flags |= CBB_KTHREAD_RUNNING; 870 while (1) { 871 /* 872 * Check to see if we have anything first so that 873 * if there's a card already inserted, we do the 874 * right thing. 875 */ 876 if (sc->flags & CBB_KTHREAD_DONE) 877 break; 878 879 status = cbb_get(sc, CBB_SOCKET_STATE); 880 mtx_lock(&Giant); 881 if ((status & CBB_SOCKET_STAT_CD) == 0) 882 cbb_insert(sc); 883 else 884 cbb_removal(sc); 885 mtx_unlock(&Giant); 886 887 /* 888 * Wait until it has been 1s since the last time we 889 * get an interrupt. We handle the rest of the interrupt 890 * at the top of the loop. 891 */ 892 mtx_lock(&sc->mtx); 893 cv_wait(&sc->cv, &sc->mtx); 894 err = 0; 895 while (err != EWOULDBLOCK && 896 (sc->flags & CBB_KTHREAD_DONE) == 0) 897 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 898 mtx_unlock(&sc->mtx); 899 } 900 sc->flags &= ~CBB_KTHREAD_RUNNING; 901 mtx_lock(&Giant); 902 kthread_exit(0); 903 } 904 905 /************************************************************************/ 906 /* Insert/removal */ 907 /************************************************************************/ 908 909 static void 910 cbb_insert(struct cbb_softc *sc) 911 { 912 uint32_t sockevent, sockstate; 913 914 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 915 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 916 917 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 918 sockevent, sockstate)); 919 920 if (sockstate & CBB_SOCKET_STAT_16BIT) { 921 if (sc->pccarddev != NULL) { 922 sc->flags |= CBB_16BIT_CARD; 923 sc->flags |= CBB_CARD_OK; 924 if (CARD_ATTACH_CARD(sc->pccarddev) != 0) 925 device_printf(sc->dev, 926 "PC Card card activation failed\n"); 927 } else { 928 device_printf(sc->dev, 929 "PC Card inserted, but no pccard bus.\n"); 930 } 931 } else if (sockstate & CBB_SOCKET_STAT_CB) { 932 if (sc->cbdev != NULL) { 933 sc->flags &= ~CBB_16BIT_CARD; 934 sc->flags |= CBB_CARD_OK; 935 if (CARD_ATTACH_CARD(sc->cbdev) != 0) 936 device_printf(sc->dev, 937 "CardBus card activation failed\n"); 938 } else { 939 device_printf(sc->dev, 940 "CardBus card inserted, but no cardbus bus.\n"); 941 } 942 } else { 943 /* 944 * We should power the card down, and try again a couple of 945 * times if this happens. XXX 946 */ 947 device_printf(sc->dev, "Unsupported card type detected\n"); 948 } 949 } 950 951 static void 952 cbb_removal(struct cbb_softc *sc) 953 { 954 if (sc->flags & CBB_16BIT_CARD) { 955 if (sc->pccarddev != NULL) 956 CARD_DETACH_CARD(sc->pccarddev); 957 } else { 958 if (sc->cbdev != NULL) 959 CARD_DETACH_CARD(sc->cbdev); 960 } 961 cbb_destroy_res(sc); 962 } 963 964 /************************************************************************/ 965 /* Interrupt Handler */ 966 /************************************************************************/ 967 968 static void 969 cbb_intr(void *arg) 970 { 971 struct cbb_softc *sc = arg; 972 uint32_t sockevent; 973 struct cbb_intrhand *ih; 974 975 /* 976 * This ISR needs work XXX 977 */ 978 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 979 if (sockevent) { 980 /* ack the interrupt */ 981 cbb_setb(sc, CBB_SOCKET_EVENT, sockevent); 982 983 /* 984 * If anything has happened to the socket, we assume that 985 * the card is no longer OK, and we shouldn't call its 986 * ISR. We set CARD_OK as soon as we've attached the 987 * card. This helps in a noisy eject, which happens 988 * all too often when users are ejecting their PC Cards. 989 * 990 * We use this method in preference to checking to see if 991 * the card is still there because the check suffers from 992 * a race condition in the bouncing case. Prior versions 993 * of the pccard software used a similar trick and achieved 994 * excellent results. 995 */ 996 if (sockevent & CBB_SOCKET_EVENT_CD) { 997 mtx_lock(&sc->mtx); 998 sc->flags &= ~CBB_CARD_OK; 999 cv_signal(&sc->cv); 1000 mtx_unlock(&sc->mtx); 1001 } 1002 if (sockevent & CBB_SOCKET_EVENT_CSTS) { 1003 DPRINTF((" cstsevent occured: 0x%08x\n", 1004 cbb_get(sc, CBB_SOCKET_STATE))); 1005 } 1006 if (sockevent & CBB_SOCKET_EVENT_POWER) { 1007 DPRINTF((" pwrevent occured: 0x%08x\n", 1008 cbb_get(sc, CBB_SOCKET_STATE))); 1009 } 1010 /* Other bits? */ 1011 } 1012 if (sc->flags & CBB_CARD_OK) { 1013 STAILQ_FOREACH(ih, &sc->intr_handlers, entries) { 1014 (*ih->intr)(ih->arg); 1015 } 1016 } 1017 } 1018 1019 /************************************************************************/ 1020 /* Generic Power functions */ 1021 /************************************************************************/ 1022 1023 static int 1024 cbb_detect_voltage(device_t brdev) 1025 { 1026 struct cbb_softc *sc = device_get_softc(brdev); 1027 uint32_t psr; 1028 int vol = CARD_UKN_CARD; 1029 1030 psr = cbb_get(sc, CBB_SOCKET_STATE); 1031 1032 if (psr & CBB_SOCKET_STAT_5VCARD) 1033 vol |= CARD_5V_CARD; 1034 if (psr & CBB_SOCKET_STAT_3VCARD) 1035 vol |= CARD_3V_CARD; 1036 if (psr & CBB_SOCKET_STAT_XVCARD) 1037 vol |= CARD_XV_CARD; 1038 if (psr & CBB_SOCKET_STAT_YVCARD) 1039 vol |= CARD_YV_CARD; 1040 1041 return (vol); 1042 } 1043 1044 static int 1045 cbb_power(device_t brdev, int volts) 1046 { 1047 uint32_t status, sock_ctrl; 1048 struct cbb_softc *sc = device_get_softc(brdev); 1049 int timeout; 1050 uint32_t sockevent; 1051 1052 DEVPRINTF((sc->dev, "cbb_power: %s and %s [%x]\n", 1053 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 1054 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 1055 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 1056 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 1057 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 1058 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 1059 "VCC-UNKNOWN", 1060 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 1061 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V" : 1062 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC" : 1063 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1064 "VPP-UNKNOWN", 1065 volts)); 1066 1067 status = cbb_get(sc, CBB_SOCKET_STATE); 1068 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 1069 1070 switch (volts & CARD_VCCMASK) { 1071 case CARD_VCC_UC: 1072 break; 1073 case CARD_VCC_5V: 1074 if (CBB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1075 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1076 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 1077 } else { 1078 device_printf(sc->dev, 1079 "BAD voltage request: no 5 V card\n"); 1080 } 1081 break; 1082 case CARD_VCC_3V: 1083 if (CBB_SOCKET_STAT_3VCARD & status) { 1084 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1085 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 1086 } else { 1087 device_printf(sc->dev, 1088 "BAD voltage request: no 3.3 V card\n"); 1089 } 1090 break; 1091 case CARD_VCC_0V: 1092 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 1093 break; 1094 default: 1095 return (0); /* power NEVER changed */ 1096 } 1097 1098 switch (volts & CARD_VPPMASK) { 1099 case CARD_VPP_UC: 1100 break; 1101 case CARD_VPP_0V: 1102 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1103 break; 1104 case CARD_VPP_VCC: 1105 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1106 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1107 break; 1108 case CARD_VPP_12V: 1109 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 1110 sock_ctrl |= CBB_SOCKET_CTRL_VPP_12V; 1111 break; 1112 } 1113 1114 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 1115 return (1); /* no change necessary */ 1116 1117 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 1118 status = cbb_get(sc, CBB_SOCKET_STATE); 1119 1120 /* 1121 * XXX This busy wait is bogus. We should wait for a power 1122 * interrupt and then whine if the status is bad. If we're 1123 * worried about the card not coming up, then we should also 1124 * schedule a timeout which we can cacel in the power interrupt. 1125 */ 1126 timeout = 20; 1127 do { 1128 DELAY(20*1000); 1129 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 1130 } while (!(sockevent & CBB_SOCKET_EVENT_POWER) && --timeout > 0); 1131 /* reset event status */ 1132 /* XXX should only reset EVENT_POWER */ 1133 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 1134 if (timeout < 0) { 1135 printf ("VCC supply failed.\n"); 1136 return (0); 1137 } 1138 1139 /* XXX 1140 * delay 400 ms: thgough the standard defines that the Vcc set-up time 1141 * is 20 ms, some PC-Card bridge requires longer duration. 1142 * XXX Note: We should check the stutus AFTER the delay to give time 1143 * for things to stabilize. 1144 */ 1145 DELAY(400*1000); 1146 1147 if (status & CBB_SOCKET_STAT_BADVCC) { 1148 device_printf(sc->dev, 1149 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 1150 sock_ctrl ,status); 1151 printf("cbb_power: %s and %s [%x]\n", 1152 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 1153 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 1154 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 1155 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 1156 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 1157 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 1158 "VCC-UNKNOWN", 1159 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 1160 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V": 1161 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC": 1162 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1163 "VPP-UNKNOWN", 1164 volts); 1165 return (0); 1166 } 1167 return (1); /* power changed correctly */ 1168 } 1169 1170 /* 1171 * detect the voltage for the card, and set it. Since the power 1172 * used is the square of the voltage, lower voltages is a big win 1173 * and what Windows does (and what Microsoft prefers). The MS paper 1174 * also talks about preferring the CIS entry as well. 1175 */ 1176 static int 1177 cbb_do_power(device_t brdev) 1178 { 1179 int voltage; 1180 1181 /* Prefer lowest voltage supported */ 1182 voltage = cbb_detect_voltage(brdev); 1183 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1184 if (voltage & CARD_YV_CARD) 1185 cbb_power(brdev, CARD_VCC_YV | CARD_VPP_VCC); 1186 else if (voltage & CARD_XV_CARD) 1187 cbb_power(brdev, CARD_VCC_XV | CARD_VPP_VCC); 1188 else if (voltage & CARD_3V_CARD) 1189 cbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1190 else if (voltage & CARD_5V_CARD) 1191 cbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1192 else { 1193 device_printf(brdev, "Unknown card voltage\n"); 1194 return (ENXIO); 1195 } 1196 return (0); 1197 } 1198 1199 /************************************************************************/ 1200 /* CardBus power functions */ 1201 /************************************************************************/ 1202 1203 static void 1204 cbb_cardbus_reset(device_t brdev) 1205 { 1206 struct cbb_softc *sc = device_get_softc(brdev); 1207 int delay_us; 1208 1209 delay_us = sc->chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1210 1211 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 1212 1213 DELAY(delay_us); 1214 1215 /* If a card exists, unreset it! */ 1216 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 0) { 1217 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 1218 &~CBBM_BRIDGECTRL_RESET, 2); 1219 DELAY(delay_us); 1220 } 1221 } 1222 1223 static int 1224 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1225 { 1226 struct cbb_softc *sc = device_get_softc(brdev); 1227 int err; 1228 1229 if ((cbb_get(sc, CBB_SOCKET_STATE) & CBB_SOCKET_STAT_CD) == 1230 CBB_SOCKET_STAT_CD) 1231 return (ENODEV); 1232 1233 err = cbb_do_power(brdev); 1234 if (err) 1235 return (err); 1236 cbb_cardbus_reset(brdev); 1237 return (0); 1238 } 1239 1240 static void 1241 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1242 { 1243 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1244 cbb_cardbus_reset(brdev); 1245 } 1246 1247 /************************************************************************/ 1248 /* CardBus Resource */ 1249 /************************************************************************/ 1250 1251 static int 1252 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 1253 { 1254 int basereg; 1255 int limitreg; 1256 1257 if ((win < 0) || (win > 1)) { 1258 DEVPRINTF((brdev, 1259 "cbb_cardbus_io_open: window out of range %d\n", win)); 1260 return (EINVAL); 1261 } 1262 1263 basereg = win * 8 + CBBR_IOBASE0; 1264 limitreg = win * 8 + CBBR_IOLIMIT0; 1265 1266 pci_write_config(brdev, basereg, start, 4); 1267 pci_write_config(brdev, limitreg, end, 4); 1268 return (0); 1269 } 1270 1271 static int 1272 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1273 { 1274 int basereg; 1275 int limitreg; 1276 1277 if ((win < 0) || (win > 1)) { 1278 DEVPRINTF((brdev, 1279 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1280 return (EINVAL); 1281 } 1282 1283 basereg = win*8 + CBBR_MEMBASE0; 1284 limitreg = win*8 + CBBR_MEMLIMIT0; 1285 1286 pci_write_config(brdev, basereg, start, 4); 1287 pci_write_config(brdev, limitreg, end, 4); 1288 return (0); 1289 } 1290 1291 /* 1292 * XXX The following function belongs in the pci bus layer. 1293 */ 1294 static void 1295 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1296 { 1297 uint32_t starts[2]; 1298 uint32_t ends[2]; 1299 struct cbb_reslist *rle; 1300 int align; 1301 int prefetchable[2]; 1302 uint32_t reg; 1303 1304 starts[0] = starts[1] = 0xffffffff; 1305 ends[0] = ends[1] = 0; 1306 1307 if (type == SYS_RES_MEMORY) 1308 align = CBB_MEMALIGN; 1309 else if (type == SYS_RES_IOPORT) 1310 align = CBB_IOALIGN; 1311 else 1312 align = 1; 1313 1314 SLIST_FOREACH(rle, &sc->rl, link) { 1315 if (rle->type != type) 1316 ; 1317 else if (rle->res == NULL) { 1318 device_printf(sc->dev, "WARNING: Resource not reserved? " 1319 "(type=%d, addr=%lx)\n", 1320 rle->type, rman_get_start(rle->res)); 1321 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1322 /* XXX */ 1323 } else if (starts[0] == 0xffffffff) { 1324 starts[0] = rman_get_start(rle->res); 1325 ends[0] = rman_get_end(rle->res); 1326 prefetchable[0] = 1327 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1328 } else if (rman_get_end(rle->res) > ends[0] && 1329 rman_get_start(rle->res) - ends[0] < 1330 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1331 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1332 ends[0] = rman_get_end(rle->res); 1333 } else if (rman_get_start(rle->res) < starts[0] && 1334 starts[0] - rman_get_end(rle->res) < 1335 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1336 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1337 starts[0] = rman_get_start(rle->res); 1338 } else if (starts[1] == 0xffffffff) { 1339 starts[1] = rman_get_start(rle->res); 1340 ends[1] = rman_get_end(rle->res); 1341 prefetchable[1] = 1342 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1343 } else if (rman_get_end(rle->res) > ends[1] && 1344 rman_get_start(rle->res) - ends[1] < 1345 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1346 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1347 ends[1] = rman_get_end(rle->res); 1348 } else if (rman_get_start(rle->res) < starts[1] && 1349 starts[1] - rman_get_end(rle->res) < 1350 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1351 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1352 starts[1] = rman_get_start(rle->res); 1353 } else { 1354 uint32_t diffs[2]; 1355 int win; 1356 1357 diffs[0] = diffs[1] = 0xffffffff; 1358 if (rman_get_start(rle->res) > ends[0]) 1359 diffs[0] = rman_get_start(rle->res) - ends[0]; 1360 else if (rman_get_end(rle->res) < starts[0]) 1361 diffs[0] = starts[0] - rman_get_end(rle->res); 1362 if (rman_get_start(rle->res) > ends[1]) 1363 diffs[1] = rman_get_start(rle->res) - ends[1]; 1364 else if (rman_get_end(rle->res) < starts[1]) 1365 diffs[1] = starts[1] - rman_get_end(rle->res); 1366 1367 win = (diffs[0] <= diffs[1])?0:1; 1368 if (rman_get_start(rle->res) > ends[win]) 1369 ends[win] = rman_get_end(rle->res); 1370 else if (rman_get_end(rle->res) < starts[win]) 1371 starts[win] = rman_get_start(rle->res); 1372 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1373 prefetchable[win] = 0; 1374 } 1375 1376 if (starts[0] != 0xffffffff) 1377 starts[0] -= starts[0] % align; 1378 if (starts[1] != 0xffffffff) 1379 starts[1] -= starts[1] % align; 1380 if (ends[0] % align != 0) 1381 ends[0] += align - ends[0]%align - 1; 1382 if (ends[1] % align != 0) 1383 ends[1] += align - ends[1]%align - 1; 1384 } 1385 1386 if (type == SYS_RES_MEMORY) { 1387 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1388 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1389 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1390 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1391 CBBM_BRIDGECTRL_PREFETCH_1); 1392 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1393 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1394 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1395 } else if (type == SYS_RES_IOPORT) { 1396 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1397 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1398 } 1399 } 1400 1401 static int 1402 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1403 int rid, struct resource *res) 1404 { 1405 int ret; 1406 1407 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1408 type, rid, res); 1409 if (ret != 0) 1410 return (ret); 1411 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1412 return (0); 1413 } 1414 1415 static int 1416 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1417 int rid, struct resource *res) 1418 { 1419 int ret; 1420 1421 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1422 type, rid, res); 1423 if (ret != 0) 1424 return (ret); 1425 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1426 return (0); 1427 } 1428 1429 static struct resource * 1430 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1431 int *rid, u_long start, u_long end, u_long count, uint flags) 1432 { 1433 struct cbb_softc *sc = device_get_softc(brdev); 1434 int tmp; 1435 struct resource *res; 1436 1437 switch (type) { 1438 case SYS_RES_IRQ: 1439 tmp = rman_get_start(sc->irq_res); 1440 if (start > tmp || end < tmp || count != 1) { 1441 device_printf(child, "requested interrupt %ld-%ld," 1442 "count = %ld not supported by cbb\n", 1443 start, end, count); 1444 return (NULL); 1445 } 1446 start = end = tmp; 1447 flags |= RF_SHAREABLE; 1448 break; 1449 case SYS_RES_IOPORT: 1450 if (start <= cbb_start_32_io) 1451 start = cbb_start_32_io; 1452 if (end < start) 1453 end = start; 1454 break; 1455 case SYS_RES_MEMORY: 1456 if (start <= cbb_start_mem) 1457 start = cbb_start_mem; 1458 if (end < start) 1459 end = start; 1460 break; 1461 } 1462 1463 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1464 start, end, count, flags & ~RF_ACTIVE); 1465 if (res == NULL) { 1466 printf("cbb alloc res fail\n"); 1467 return (NULL); 1468 } 1469 cbb_insert_res(sc, res, type, *rid); 1470 if (flags & RF_ACTIVE) 1471 if (bus_activate_resource(child, type, *rid, res) != 0) { 1472 bus_release_resource(child, type, *rid, res); 1473 return (NULL); 1474 } 1475 1476 return (res); 1477 } 1478 1479 static int 1480 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1481 int rid, struct resource *res) 1482 { 1483 struct cbb_softc *sc = device_get_softc(brdev); 1484 int error; 1485 1486 if (rman_get_flags(res) & RF_ACTIVE) { 1487 error = bus_deactivate_resource(child, type, rid, res); 1488 if (error != 0) 1489 return (error); 1490 } 1491 cbb_remove_res(sc, res); 1492 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1493 type, rid, res)); 1494 } 1495 1496 /************************************************************************/ 1497 /* PC Card Power Functions */ 1498 /************************************************************************/ 1499 1500 static int 1501 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1502 { 1503 struct cbb_softc *sc = device_get_softc(brdev); 1504 int err; 1505 1506 DPRINTF(("cbb_pcic_socket_enable:\n")); 1507 1508 /* power down/up the socket to reset */ 1509 err = cbb_do_power(brdev); 1510 if (err) 1511 return (err); 1512 exca_reset(&sc->exca, child); 1513 1514 return (0); 1515 } 1516 1517 static void 1518 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1519 { 1520 struct cbb_softc *sc = device_get_softc(brdev); 1521 1522 DPRINTF(("cbb_pcic_socket_disable\n")); 1523 1524 /* reset signal asserting... */ 1525 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 1526 DELAY(2*1000); 1527 1528 /* power down the socket */ 1529 cbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1530 exca_clrb(&sc->exca, EXCA_PWRCTL, EXCA_PWRCTL_OE); 1531 1532 /* wait 300ms until power fails (Tpf). */ 1533 DELAY(300 * 1000); 1534 } 1535 1536 /************************************************************************/ 1537 /* POWER methods */ 1538 /************************************************************************/ 1539 1540 static int 1541 cbb_power_enable_socket(device_t brdev, device_t child) 1542 { 1543 struct cbb_softc *sc = device_get_softc(brdev); 1544 1545 if (sc->flags & CBB_16BIT_CARD) 1546 return (cbb_pcic_power_enable_socket(brdev, child)); 1547 else 1548 return (cbb_cardbus_power_enable_socket(brdev, child)); 1549 } 1550 1551 static void 1552 cbb_power_disable_socket(device_t brdev, device_t child) 1553 { 1554 struct cbb_softc *sc = device_get_softc(brdev); 1555 if (sc->flags & CBB_16BIT_CARD) 1556 cbb_pcic_power_disable_socket(brdev, child); 1557 else 1558 cbb_cardbus_power_disable_socket(brdev, child); 1559 } 1560 static int 1561 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1562 struct resource *res) 1563 { 1564 int err; 1565 struct cbb_softc *sc = device_get_softc(brdev); 1566 if (!(rman_get_flags(res) & RF_ACTIVE)) { /* not already activated */ 1567 switch (type) { 1568 case SYS_RES_IOPORT: 1569 err = exca_io_map(&sc->exca, 0, res); 1570 break; 1571 case SYS_RES_MEMORY: 1572 err = exca_mem_map(&sc->exca, 0, res); 1573 break; 1574 default: 1575 err = 0; 1576 break; 1577 } 1578 if (err) 1579 return (err); 1580 1581 } 1582 return (BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1583 type, rid, res)); 1584 } 1585 1586 static int 1587 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1588 int rid, struct resource *res) 1589 { 1590 struct cbb_softc *sc = device_get_softc(brdev); 1591 1592 if (rman_get_flags(res) & RF_ACTIVE) { /* if activated */ 1593 switch (type) { 1594 case SYS_RES_IOPORT: 1595 if (exca_io_unmap_res(&sc->exca, res)) 1596 return (ENOENT); 1597 break; 1598 case SYS_RES_MEMORY: 1599 if (exca_mem_unmap_res(&sc->exca, res)) 1600 return (ENOENT); 1601 break; 1602 } 1603 } 1604 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1605 type, rid, res)); 1606 } 1607 1608 static struct resource * 1609 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1610 u_long start, u_long end, u_long count, uint flags) 1611 { 1612 struct resource *res = NULL; 1613 struct cbb_softc *sc = device_get_softc(brdev); 1614 int tmp; 1615 1616 switch (type) { 1617 case SYS_RES_MEMORY: 1618 if (start < cbb_start_mem) 1619 start = cbb_start_mem; 1620 if (end < start) 1621 end = start; 1622 flags = (flags & ~RF_ALIGNMENT_MASK) | 1623 rman_make_alignment_flags(CBB_MEMALIGN); 1624 break; 1625 case SYS_RES_IOPORT: 1626 if (start < cbb_start_16_io) 1627 start = cbb_start_16_io; 1628 if (end < start) 1629 end = start; 1630 break; 1631 case SYS_RES_IRQ: 1632 tmp = rman_get_start(sc->irq_res); 1633 if (start > tmp || end < tmp || count != 1) { 1634 device_printf(child, "requested interrupt %ld-%ld," 1635 "count = %ld not supported by cbb\n", 1636 start, end, count); 1637 return (NULL); 1638 } 1639 flags |= RF_SHAREABLE; 1640 start = end = rman_get_start(sc->irq_res); 1641 break; 1642 } 1643 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1644 start, end, count, flags & ~RF_ACTIVE); 1645 if (res == NULL) 1646 return (NULL); 1647 cbb_insert_res(sc, res, type, *rid); 1648 if (flags & RF_ACTIVE) { 1649 if (bus_activate_resource(child, type, *rid, res) != 0) { 1650 bus_release_resource(child, type, *rid, res); 1651 return (NULL); 1652 } 1653 } 1654 1655 return (res); 1656 } 1657 1658 static int 1659 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1660 int rid, struct resource *res) 1661 { 1662 struct cbb_softc *sc = device_get_softc(brdev); 1663 int error; 1664 1665 if (rman_get_flags(res) & RF_ACTIVE) { 1666 error = bus_deactivate_resource(child, type, rid, res); 1667 if (error != 0) 1668 return (error); 1669 } 1670 cbb_remove_res(sc, res); 1671 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1672 type, rid, res)); 1673 } 1674 1675 /************************************************************************/ 1676 /* PC Card methods */ 1677 /************************************************************************/ 1678 1679 static int 1680 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1681 uint32_t flags) 1682 { 1683 struct cbb_softc *sc = device_get_softc(brdev); 1684 struct resource *res; 1685 1686 if (type != SYS_RES_MEMORY) 1687 return (EINVAL); 1688 res = cbb_find_res(sc, type, rid); 1689 if (res == NULL) { 1690 device_printf(brdev, 1691 "set_res_flags: specified rid not found\n"); 1692 return (ENOENT); 1693 } 1694 return (exca_mem_set_flags(&sc->exca, res, flags)); 1695 } 1696 1697 static int 1698 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1699 uint32_t cardaddr, uint32_t *deltap) 1700 { 1701 struct cbb_softc *sc = device_get_softc(brdev); 1702 struct resource *res; 1703 1704 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1705 if (res == NULL) { 1706 device_printf(brdev, 1707 "set_memory_offset: specified rid not found\n"); 1708 return (ENOENT); 1709 } 1710 return (exca_mem_set_offset(&sc->exca, res, cardaddr, deltap)); 1711 } 1712 1713 /************************************************************************/ 1714 /* BUS Methods */ 1715 /************************************************************************/ 1716 1717 1718 static int 1719 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1720 struct resource *r) 1721 { 1722 struct cbb_softc *sc = device_get_softc(brdev); 1723 1724 if (sc->flags & CBB_16BIT_CARD) 1725 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1726 else 1727 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1728 r)); 1729 } 1730 1731 static int 1732 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1733 int rid, struct resource *r) 1734 { 1735 struct cbb_softc *sc = device_get_softc(brdev); 1736 1737 if (sc->flags & CBB_16BIT_CARD) 1738 return (cbb_pcic_deactivate_resource(brdev, child, type, 1739 rid, r)); 1740 else 1741 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1742 rid, r)); 1743 } 1744 1745 static struct resource * 1746 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1747 u_long start, u_long end, u_long count, uint flags) 1748 { 1749 struct cbb_softc *sc = device_get_softc(brdev); 1750 1751 if (sc->flags & CBB_16BIT_CARD) 1752 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1753 start, end, count, flags)); 1754 else 1755 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1756 start, end, count, flags)); 1757 } 1758 1759 static int 1760 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1761 struct resource *r) 1762 { 1763 struct cbb_softc *sc = device_get_softc(brdev); 1764 1765 if (sc->flags & CBB_16BIT_CARD) 1766 return (cbb_pcic_release_resource(brdev, child, type, 1767 rid, r)); 1768 else 1769 return (cbb_cardbus_release_resource(brdev, child, type, 1770 rid, r)); 1771 } 1772 1773 static int 1774 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1775 { 1776 struct cbb_softc *sc = device_get_softc(brdev); 1777 1778 switch (which) { 1779 case PCIB_IVAR_BUS: 1780 *result = sc->secbus; 1781 return (0); 1782 } 1783 return (ENOENT); 1784 } 1785 1786 static int 1787 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1788 { 1789 struct cbb_softc *sc = device_get_softc(brdev); 1790 1791 switch (which) { 1792 case PCIB_IVAR_BUS: 1793 sc->secbus = value; 1794 break; 1795 } 1796 return (ENOENT); 1797 } 1798 1799 /************************************************************************/ 1800 /* PCI compat methods */ 1801 /************************************************************************/ 1802 1803 static int 1804 cbb_maxslots(device_t brdev) 1805 { 1806 return (0); 1807 } 1808 1809 static uint32_t 1810 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1811 { 1812 /* 1813 * Pass through to the next ppb up the chain (i.e. our grandparent). 1814 */ 1815 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1816 b, s, f, reg, width)); 1817 } 1818 1819 static void 1820 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1821 int width) 1822 { 1823 /* 1824 * Pass through to the next ppb up the chain (i.e. our grandparent). 1825 */ 1826 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1827 b, s, f, reg, val, width); 1828 } 1829 1830 static int 1831 cbb_suspend(device_t self) 1832 { 1833 int error = 0; 1834 struct cbb_softc *sc = device_get_softc(self); 1835 1836 cbb_setb(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1837 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1838 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1839 error = bus_generic_suspend(self); 1840 return (error); 1841 } 1842 1843 static int 1844 cbb_resume(device_t self) 1845 { 1846 int error = 0; 1847 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1848 uint32_t tmp; 1849 1850 /* 1851 * Some BIOSes will not save the BARs for the pci chips, so we 1852 * must do it ourselves. If the BAR is reset to 0 for an I/O 1853 * device, it will read back as 0x1, so no explicit test for 1854 * memory devices are needed. 1855 * 1856 * Note: The PCI bus code should do this automatically for us on 1857 * suspend/resume, but until it does, we have to cope. 1858 */ 1859 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1860 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1861 rman_get_start(sc->base_res))); 1862 1863 cbb_chipinit(sc); 1864 1865 /* reset interrupt -- Do we really need to do this? */ 1866 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1867 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1868 1869 /* re-establish the interrupt. */ 1870 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV, cbb_intr, sc, 1871 &sc->intrhand)) { 1872 device_printf(self, "couldn't re-establish interrupt"); 1873 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1874 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1875 sc->base_res); 1876 sc->irq_res = NULL; 1877 sc->base_res = NULL; 1878 return (ENOMEM); 1879 } 1880 1881 /* CSC Interrupt: Card detect interrupt on */ 1882 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1883 1884 /* Signal the thread to wakeup. */ 1885 mtx_lock(&sc->mtx); 1886 cv_signal(&sc->cv); 1887 mtx_unlock(&sc->mtx); 1888 1889 error = bus_generic_resume(self); 1890 1891 return (error); 1892 } 1893 1894 static int 1895 cbb_child_present(device_t self) 1896 { 1897 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1898 uint32_t sockstate; 1899 1900 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1901 return ((sockstate & CBB_SOCKET_STAT_CD) != 0 && 1902 (sc->flags & CBB_CARD_OK) != 0); 1903 } 1904 1905 static device_method_t cbb_methods[] = { 1906 /* Device interface */ 1907 DEVMETHOD(device_probe, cbb_probe), 1908 DEVMETHOD(device_attach, cbb_attach), 1909 DEVMETHOD(device_detach, cbb_detach), 1910 DEVMETHOD(device_shutdown, cbb_shutdown), 1911 DEVMETHOD(device_suspend, cbb_suspend), 1912 DEVMETHOD(device_resume, cbb_resume), 1913 1914 /* bus methods */ 1915 DEVMETHOD(bus_print_child, bus_generic_print_child), 1916 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 1917 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 1918 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 1919 DEVMETHOD(bus_release_resource, cbb_release_resource), 1920 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 1921 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 1922 DEVMETHOD(bus_driver_added, cbb_driver_added), 1923 DEVMETHOD(bus_child_detached, cbb_child_detached), 1924 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 1925 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 1926 DEVMETHOD(bus_child_present, cbb_child_present), 1927 1928 /* 16-bit card interface */ 1929 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 1930 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 1931 1932 /* power interface */ 1933 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 1934 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 1935 1936 /* pcib compatibility interface */ 1937 DEVMETHOD(pcib_maxslots, cbb_maxslots), 1938 DEVMETHOD(pcib_read_config, cbb_read_config), 1939 DEVMETHOD(pcib_write_config, cbb_write_config), 1940 {0,0} 1941 }; 1942 1943 static driver_t cbb_driver = { 1944 "cbb", 1945 cbb_methods, 1946 sizeof(struct cbb_softc) 1947 }; 1948 1949 static devclass_t cbb_devclass; 1950 1951 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 1952 MODULE_VERSION(cbb, 1); 1953 MODULE_DEPEND(cbb, exca, 1, 1, 1); 1954