1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * and PCI to PCMCIA Bridge chips 62 * and ISA to PCMCIA host adapters 63 * and C Bus to PCMCIA host adapters 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include <sys/param.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/module.h> 86 #include <sys/kthread.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mutex.h> 90 #include <sys/proc.h> 91 #include <sys/rman.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 #include <machine/bus.h> 95 #include <machine/resource.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <machine/clock.h> 100 101 #include <dev/pccard/pccardreg.h> 102 #include <dev/pccard/pccardvar.h> 103 104 #include <dev/exca/excareg.h> 105 #include <dev/exca/excavar.h> 106 107 #include <dev/pccbb/pccbbreg.h> 108 #include <dev/pccbb/pccbbvar.h> 109 110 #include "power_if.h" 111 #include "card_if.h" 112 #include "pcib_if.h" 113 114 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 115 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 116 117 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 118 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 119 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 120 pci_write_config(DEV, REG, ( \ 121 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 122 123 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 124 125 #define CBB_START_MEM 0x88000000 126 #define CBB_START_32_IO 0x1000 127 #define CBB_START_16_IO 0x100 128 129 devclass_t cbb_devclass; 130 131 /* sysctl vars */ 132 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 133 134 /* There's no way to say TUNEABLE_LONG to get the right types */ 135 u_long cbb_start_mem = CBB_START_MEM; 136 TUNABLE_INT("hw.cbb.start_memory", (int *)&cbb_start_mem); 137 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 138 &cbb_start_mem, CBB_START_MEM, 139 "Starting address for memory allocations"); 140 141 u_long cbb_start_16_io = CBB_START_16_IO; 142 TUNABLE_INT("hw.cbb.start_16_io", (int *)&cbb_start_16_io); 143 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 144 &cbb_start_16_io, CBB_START_16_IO, 145 "Starting ioport for 16-bit cards"); 146 147 u_long cbb_start_32_io = CBB_START_32_IO; 148 TUNABLE_INT("hw.cbb.start_32_io", (int *)&cbb_start_32_io); 149 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 150 &cbb_start_32_io, CBB_START_32_IO, 151 "Starting ioport for 32-bit cards"); 152 153 int cbb_debug = 0; 154 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 155 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 156 "Verbose cardbus bridge debugging"); 157 158 static void cbb_insert(struct cbb_softc *sc); 159 static void cbb_removal(struct cbb_softc *sc); 160 static uint32_t cbb_detect_voltage(device_t brdev); 161 static void cbb_cardbus_reset(device_t brdev); 162 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 163 uint32_t end); 164 static int cbb_cardbus_mem_open(device_t brdev, int win, 165 uint32_t start, uint32_t end); 166 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 167 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 168 int type, int rid, struct resource *res); 169 static int cbb_cardbus_deactivate_resource(device_t brdev, 170 device_t child, int type, int rid, struct resource *res); 171 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 172 device_t child, int type, int *rid, u_long start, 173 u_long end, u_long count, u_int flags); 174 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 175 int type, int rid, struct resource *res); 176 static int cbb_cardbus_power_enable_socket(device_t brdev, 177 device_t child); 178 static void cbb_cardbus_power_disable_socket(device_t brdev, 179 device_t child); 180 static void cbb_func_intr(void *arg); 181 182 static void 183 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 184 { 185 struct cbb_reslist *rle; 186 187 SLIST_FOREACH(rle, &sc->rl, link) { 188 if (rle->res == res) { 189 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 190 free(rle, M_DEVBUF); 191 return; 192 } 193 } 194 } 195 196 static struct resource * 197 cbb_find_res(struct cbb_softc *sc, int type, int rid) 198 { 199 struct cbb_reslist *rle; 200 201 SLIST_FOREACH(rle, &sc->rl, link) 202 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 203 return (rle->res); 204 return (NULL); 205 } 206 207 static void 208 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 209 int rid) 210 { 211 struct cbb_reslist *rle; 212 213 /* 214 * Need to record allocated resource so we can iterate through 215 * it later. 216 */ 217 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 218 if (rle == NULL) 219 panic("cbb_cardbus_alloc_resource: can't record entry!"); 220 rle->res = res; 221 rle->type = type; 222 rle->rid = rid; 223 SLIST_INSERT_HEAD(&sc->rl, rle, link); 224 } 225 226 static void 227 cbb_destroy_res(struct cbb_softc *sc) 228 { 229 struct cbb_reslist *rle; 230 231 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 232 device_printf(sc->dev, "Danger Will Robinson: Resource " 233 "left allocated! This is a bug... " 234 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 235 rman_get_start(rle->res)); 236 SLIST_REMOVE_HEAD(&sc->rl, link); 237 free(rle, M_DEVBUF); 238 } 239 } 240 241 /* 242 * Disable function interrupts by telling the bridge to generate IRQ1 243 * interrupts. These interrupts aren't really generated by the chip, since 244 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 245 * initialization, so this helps to work around the problem. 246 * 247 * XXX We can't do this workaround for all chipsets, because this 248 * XXX causes interference with the keyboard because somechipsets will 249 * XXX actually signal IRQ1 over their serial interrupt connections to 250 * XXX the south bridge. Disable it it for now. 251 */ 252 void 253 cbb_disable_func_intr(struct cbb_softc *sc) 254 { 255 #if 0 256 uint8_t reg; 257 258 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 259 EXCA_INTR_IRQ_RESERVED1; 260 exca_putb(&sc->exca[0], EXCA_INTR, reg); 261 #endif 262 } 263 264 /* 265 * Enable function interrupts. We turn on function interrupts when the card 266 * requests an interrupt. The PCMCIA standard says that we should set 267 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 268 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 269 * cards. 270 */ 271 static void 272 cbb_enable_func_intr(struct cbb_softc *sc) 273 { 274 uint8_t reg; 275 276 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 277 EXCA_INTR_IRQ_NONE; 278 exca_putb(&sc->exca[0], EXCA_INTR, reg); 279 } 280 281 int 282 cbb_detach(device_t brdev) 283 { 284 struct cbb_softc *sc = device_get_softc(brdev); 285 int numdevs; 286 device_t *devlist; 287 int tmp; 288 int error; 289 290 device_get_children(brdev, &devlist, &numdevs); 291 292 error = 0; 293 for (tmp = 0; tmp < numdevs; tmp++) { 294 if (device_detach(devlist[tmp]) == 0) 295 device_delete_child(brdev, devlist[tmp]); 296 else 297 error++; 298 } 299 free(devlist, M_TEMP); 300 if (error > 0) 301 return (ENXIO); 302 303 mtx_lock(&sc->mtx); 304 /* 305 * XXX do we teardown all the ones still registered to guard against 306 * XXX buggy client drivers? 307 */ 308 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 309 sc->flags |= CBB_KTHREAD_DONE; 310 if (sc->flags & CBB_KTHREAD_RUNNING) { 311 cv_broadcast(&sc->cv); 312 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 313 } 314 mtx_unlock(&sc->mtx); 315 316 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 317 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 318 sc->base_res); 319 mtx_destroy(&sc->mtx); 320 cv_destroy(&sc->cv); 321 cv_destroy(&sc->powercv); 322 return (0); 323 } 324 325 int 326 cbb_shutdown(device_t brdev) 327 { 328 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 329 /* properly reset everything at shutdown */ 330 331 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 332 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 333 334 cbb_set(sc, CBB_SOCKET_MASK, 0); 335 336 cbb_power(brdev, CARD_OFF); 337 338 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 339 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 340 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 341 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 342 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 343 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 344 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 345 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 346 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 347 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 348 return (0); 349 } 350 351 int 352 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 353 int flags, driver_intr_t *intr, void *arg, void **cookiep) 354 { 355 struct cbb_intrhand *ih; 356 struct cbb_softc *sc = device_get_softc(dev); 357 int err; 358 359 /* 360 * Well, this is no longer strictly true. You can have multiple 361 * FAST ISRs, but can't mix fast and slow, so we have to assume 362 * least common denominator until the base system supports mixing 363 * and matching better. 364 */ 365 if ((flags & INTR_FAST) != 0) 366 return (EINVAL); 367 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 368 if (ih == NULL) 369 return (ENOMEM); 370 *cookiep = ih; 371 ih->intr = intr; 372 ih->arg = arg; 373 ih->sc = sc; 374 /* 375 * XXX need to turn on ISA interrupts, if we ever support them, but 376 * XXX for now that's all we need to do. 377 */ 378 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 379 cbb_func_intr, ih, &ih->cookie); 380 if (err != 0) { 381 free(ih, M_DEVBUF); 382 return (err); 383 } 384 STAILQ_INSERT_TAIL(&sc->intr_handlers, ih, entries); 385 cbb_enable_func_intr(sc); 386 sc->flags |= CBB_CARD_OK; 387 return 0; 388 } 389 390 int 391 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 392 void *cookie) 393 { 394 struct cbb_intrhand *ih; 395 struct cbb_softc *sc = device_get_softc(dev); 396 int err; 397 398 /* XXX Need to do different things for ISA interrupts. */ 399 ih = (struct cbb_intrhand *) cookie; 400 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 401 ih->cookie); 402 if (err != 0) 403 return (err); 404 STAILQ_REMOVE(&sc->intr_handlers, ih, cbb_intrhand, entries); 405 free(ih, M_DEVBUF); 406 return (0); 407 } 408 409 410 void 411 cbb_driver_added(device_t brdev, driver_t *driver) 412 { 413 struct cbb_softc *sc = device_get_softc(brdev); 414 device_t *devlist; 415 device_t dev; 416 int tmp; 417 int numdevs; 418 int wake = 0; 419 420 DEVICE_IDENTIFY(driver, brdev); 421 device_get_children(brdev, &devlist, &numdevs); 422 for (tmp = 0; tmp < numdevs; tmp++) { 423 dev = devlist[tmp]; 424 if (device_get_state(dev) == DS_NOTPRESENT && 425 device_probe_and_attach(dev) == 0) 426 wake++; 427 } 428 free(devlist, M_TEMP); 429 430 if (wake > 0) { 431 mtx_lock(&sc->mtx); 432 cv_signal(&sc->cv); 433 mtx_unlock(&sc->mtx); 434 } 435 } 436 437 void 438 cbb_child_detached(device_t brdev, device_t child) 439 { 440 struct cbb_softc *sc = device_get_softc(brdev); 441 442 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 443 device_printf(brdev, "Unknown child detached: %s\n", 444 device_get_nameunit(child)); 445 } 446 447 /************************************************************************/ 448 /* Kthreads */ 449 /************************************************************************/ 450 451 void 452 cbb_event_thread(void *arg) 453 { 454 struct cbb_softc *sc = arg; 455 uint32_t status; 456 int err; 457 int not_a_card = 0; 458 459 sc->flags |= CBB_KTHREAD_RUNNING; 460 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 461 /* 462 * We take out Giant here because we need it deep, 463 * down in the bowels of the vm system for mapping the 464 * memory we need to read the CIS. In addition, since 465 * we are adding/deleting devices from the dev tree, 466 * and that code isn't MP safe, we have to hold Giant. 467 */ 468 mtx_lock(&Giant); 469 status = cbb_get(sc, CBB_SOCKET_STATE); 470 DPRINTF(("Status is 0x%x\n", status)); 471 if (!CBB_CARD_PRESENT(status)) { 472 not_a_card = 0; /* We know card type */ 473 cbb_removal(sc); 474 } else if (status & CBB_STATE_NOT_A_CARD) { 475 /* 476 * Up to 20 times, try to rescan the card when we 477 * see NOT_A_CARD. 478 */ 479 if (not_a_card++ < 20) { 480 DEVPRINTF((sc->dev, 481 "Not a card bit set, rescanning\n")); 482 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 483 } else { 484 device_printf(sc->dev, 485 "Can't determine card type\n"); 486 } 487 } else { 488 not_a_card = 0; /* We know card type */ 489 cbb_insert(sc); 490 } 491 mtx_unlock(&Giant); 492 493 /* 494 * Wait until it has been 1s since the last time we 495 * get an interrupt. We handle the rest of the interrupt 496 * at the top of the loop. Although we clear the bit in the 497 * ISR, we signal sc->cv from the detach path after we've 498 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 499 * 1s sleep here. 500 * 501 * In our ISR, we turn off the card changed interrupt. Turn 502 * them back on here before we wait for them to happen. We 503 * turn them on/off so that we can tolerate a large latency 504 * between the time we signal cbb_event_thread and it gets 505 * a chance to run. 506 */ 507 mtx_lock(&sc->mtx); 508 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 509 cv_wait(&sc->cv, &sc->mtx); 510 err = 0; 511 while (err != EWOULDBLOCK && 512 (sc->flags & CBB_KTHREAD_DONE) == 0) 513 err = cv_timedwait(&sc->cv, &sc->mtx, 1 * hz); 514 mtx_unlock(&sc->mtx); 515 } 516 sc->flags &= ~CBB_KTHREAD_RUNNING; 517 kthread_exit(0); 518 } 519 520 /************************************************************************/ 521 /* Insert/removal */ 522 /************************************************************************/ 523 524 static void 525 cbb_insert(struct cbb_softc *sc) 526 { 527 uint32_t sockevent, sockstate; 528 529 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 530 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 531 532 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 533 sockevent, sockstate)); 534 535 if (sockstate & CBB_STATE_R2_CARD) { 536 if (sc->exca[0].pccarddev) { 537 sc->flags |= CBB_16BIT_CARD; 538 exca_insert(&sc->exca[0]); 539 } else { 540 device_printf(sc->dev, 541 "16-bit card inserted, but no pccard bus.\n"); 542 } 543 } else if (sockstate & CBB_STATE_CB_CARD) { 544 if (sc->cbdev != NULL) { 545 sc->flags &= ~CBB_16BIT_CARD; 546 CARD_ATTACH_CARD(sc->cbdev); 547 } else { 548 device_printf(sc->dev, 549 "CardBus card inserted, but no cardbus bus.\n"); 550 } 551 } else { 552 /* 553 * We should power the card down, and try again a couple of 554 * times if this happens. XXX 555 */ 556 device_printf(sc->dev, "Unsupported card type detected\n"); 557 } 558 } 559 560 static void 561 cbb_removal(struct cbb_softc *sc) 562 { 563 sc->flags &= ~CBB_CARD_OK; 564 if (sc->flags & CBB_16BIT_CARD) { 565 exca_removal(&sc->exca[0]); 566 } else { 567 if (sc->cbdev != NULL) 568 CARD_DETACH_CARD(sc->cbdev); 569 } 570 cbb_destroy_res(sc); 571 } 572 573 /************************************************************************/ 574 /* Interrupt Handler */ 575 /************************************************************************/ 576 577 /* 578 * Since we touch hardware in the worst case, we don't need to use atomic 579 * ops on the CARD_OK tests. They would save us a trip to the hardware 580 * if CARD_OK was recently cleared and the caches haven't updated yet. 581 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 582 * machine, this is about 33-66ns, whereas a trip the the hardware 583 * is about that. On slower machines, the cost is even higher, so the 584 * trip to the hardware is cheaper and achieves the same ends that 585 * a fully locked operation would give us. 586 * 587 * This is a separate routine because we'd have to use locking and/or 588 * other synchronization in cbb_intr to do this there. That would be 589 * even more expensive. 590 * 591 * I need to investigate what this means for a SMP machine with multiple 592 * CPUs servicing the ISR when an eject happens. In the case of a dirty 593 * eject, CD glitches and we might read 'card present' from the hardware 594 * due to this jitter. If we assumed that cbb_intr() ran before 595 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 596 * CD changes were clear there, then we'd know the card was gone. 597 */ 598 static void 599 cbb_func_intr(void *arg) 600 { 601 struct cbb_intrhand *ih = (struct cbb_intrhand *)arg; 602 struct cbb_softc *sc = ih->sc; 603 604 /* 605 * Make sure that the card is really there. 606 */ 607 if ((sc->flags & CBB_CARD_OK) == 0) 608 return; 609 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 610 sc->flags &= ~CBB_CARD_OK; 611 return; 612 } 613 614 /* 615 * nb: don't have to check for giant or not, since that's done 616 * in the ISR dispatch 617 */ 618 (*ih->intr)(ih->arg); 619 } 620 621 void 622 cbb_intr(void *arg) 623 { 624 struct cbb_softc *sc = arg; 625 uint32_t sockevent; 626 627 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 628 if (sockevent != 0) { 629 /* ack the interrupt */ 630 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 631 632 /* 633 * If anything has happened to the socket, we assume that 634 * the card is no longer OK, and we shouldn't call its 635 * ISR. We set CARD_OK as soon as we've attached the 636 * card. This helps in a noisy eject, which happens 637 * all too often when users are ejecting their PC Cards. 638 * 639 * We use this method in preference to checking to see if 640 * the card is still there because the check suffers from 641 * a race condition in the bouncing case. Prior versions 642 * of the pccard software used a similar trick and achieved 643 * excellent results. 644 */ 645 if (sockevent & CBB_SOCKET_EVENT_CD) { 646 mtx_lock(&sc->mtx); 647 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 648 sc->flags &= ~CBB_CARD_OK; 649 cbb_disable_func_intr(sc); 650 cv_signal(&sc->cv); 651 mtx_unlock(&sc->mtx); 652 } 653 /* 654 * If we get a power interrupt, wakeup anybody that might 655 * be waiting for one. 656 */ 657 if (sockevent & CBB_SOCKET_EVENT_POWER) { 658 mtx_lock(&sc->mtx); 659 sc->powerintr++; 660 cv_signal(&sc->powercv); 661 mtx_unlock(&sc->mtx); 662 } 663 } 664 /* 665 * Some chips also require us to read the old ExCA registe for 666 * card status change when we route CSC vis PCI. This isn't supposed 667 * to be required, but it clears the interrupt state on some chipsets. 668 * Maybe there's a setting that would obviate its need. Maybe we 669 * should test the status bits and deal with them, but so far we've 670 * not found any machines that don't also give us the socket status 671 * indication above. 672 * 673 * We have to call this unconditionally because some bridges deliver 674 * the even independent of the CBB_SOCKET_EVENT_CD above. 675 */ 676 exca_getb(&sc->exca[0], EXCA_CSC); 677 } 678 679 /************************************************************************/ 680 /* Generic Power functions */ 681 /************************************************************************/ 682 683 static uint32_t 684 cbb_detect_voltage(device_t brdev) 685 { 686 struct cbb_softc *sc = device_get_softc(brdev); 687 uint32_t psr; 688 uint32_t vol = CARD_UKN_CARD; 689 690 psr = cbb_get(sc, CBB_SOCKET_STATE); 691 692 if (psr & CBB_STATE_5VCARD) 693 vol |= CARD_5V_CARD; 694 if (psr & CBB_STATE_3VCARD) 695 vol |= CARD_3V_CARD; 696 if (psr & CBB_STATE_XVCARD) 697 vol |= CARD_XV_CARD; 698 if (psr & CBB_STATE_YVCARD) 699 vol |= CARD_YV_CARD; 700 701 return (vol); 702 } 703 704 static uint8_t 705 cbb_o2micro_power_hack(struct cbb_softc *sc) 706 { 707 uint8_t reg; 708 709 /* 710 * Issue #2: INT# not qualified with IRQ Routing Bit. An 711 * unexpected PCI INT# may be generated during PC-Card 712 * initialization even with the IRQ Routing Bit Set with some 713 * PC-Cards. 714 * 715 * This is a two part issue. The first part is that some of 716 * our older controllers have an issue in which the slot's PCI 717 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 718 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 719 * is selected (ExCA register 03h bits 3:0, of the slot, are 720 * cleared) we will generate INT# if IREQ# is asserted. The 721 * second part is because some PC-Cards prematurally assert 722 * IREQ# before the ExCA registers are fully programmed. This 723 * in turn asserts INT# because ExCA register 03h bits 3:0 724 * (ISA IRQ Select) are not yet programmed. 725 * 726 * The fix for this issue, which will work for any controller 727 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 728 * (select IRQ1), of the slot, before turning on slot power. 729 * Selecting IRQ1 will result in INT# NOT being asserted 730 * (because IRQ1 is selected), and IRQ1 won't be asserted 731 * because our controllers don't generate IRQ1. 732 * 733 * Other, non O2Micro controllers will generate irq 1 in some 734 * situations, so we can't do this hack for everybody. Reports of 735 * keyboard controller's interrupts being suppressed occurred when 736 * we did this. 737 */ 738 reg = exca_getb(&sc->exca[0], EXCA_INTR); 739 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 740 return (reg); 741 } 742 743 /* 744 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 745 * we don't have an interrupt storm on power on. This has the efect of 746 * disabling card status change interrupts for the duration of poweron. 747 */ 748 static void 749 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 750 { 751 exca_putb(&sc->exca[0], EXCA_INTR, reg); 752 } 753 754 int 755 cbb_power(device_t brdev, int volts) 756 { 757 uint32_t status, sock_ctrl, mask; 758 struct cbb_softc *sc = device_get_softc(brdev); 759 int cnt, sane; 760 int retval = 0; 761 int on = 0; 762 uint8_t reg = 0; 763 764 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 765 766 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 767 switch (volts & CARD_VCCMASK) { 768 case 5: 769 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 770 on++; 771 break; 772 case 3: 773 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 774 on++; 775 break; 776 case XV: 777 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 778 on++; 779 break; 780 case YV: 781 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 782 on++; 783 break; 784 case 0: 785 break; 786 default: 787 return (0); /* power NEVER changed */ 788 } 789 790 /* VPP == VCC */ 791 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 792 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 793 794 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 795 return (1); /* no change necessary */ 796 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 797 if (volts != 0 && sc->chipset == CB_O2MICRO) 798 reg = cbb_o2micro_power_hack(sc); 799 800 /* 801 * We have to mask the card change detect interrupt while we're 802 * messing with the power. It is allowed to bounce while we're 803 * messing with power as things settle down. In addition, we mask off 804 * the card's function interrupt by routing it via the ISA bus. This 805 * bit generally only affects 16bit cards. Some bridges allow one to 806 * set another bit to have it also affect 32bit cards. Since 32bit 807 * cards are required to be better behaved, we don't bother to get 808 * into those bridge specific features. 809 */ 810 mask = cbb_get(sc, CBB_SOCKET_MASK); 811 mask |= CBB_SOCKET_MASK_POWER; 812 mask &= ~CBB_SOCKET_MASK_CD; 813 cbb_set(sc, CBB_SOCKET_MASK, mask); 814 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 815 |CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 816 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 817 if (on) { 818 mtx_lock(&sc->mtx); 819 cnt = sc->powerintr; 820 sane = 200; 821 while (!(cbb_get(sc, CBB_SOCKET_STATE) & CBB_STATE_POWER_CYCLE) && 822 cnt == sc->powerintr && sane-- > 0) 823 cv_timedwait(&sc->powercv, &sc->mtx, hz / 10); 824 mtx_unlock(&sc->mtx); 825 if (sane <= 0) 826 device_printf(sc->dev, "power timeout, doom?\n"); 827 } 828 829 /* 830 * After the power is good, we can turn off the power interrupt. 831 * However, the PC Card standard says that we must delay turning the 832 * CD bit back on for a bit to allow for bouncyness on power down 833 * (recall that we don't wait above for a power down, since we don't 834 * get an interrupt for that). We're called either from the suspend 835 * code in which case we don't want to turn card change on again, or 836 * we're called from the card insertion code, in which case the cbb 837 * thread will turn it on for us before it waits to be woken by a 838 * change event. 839 */ 840 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_POWER); 841 status = cbb_get(sc, CBB_SOCKET_STATE); 842 if (on) { 843 if ((status & CBB_STATE_POWER_CYCLE) == 0) 844 device_printf(sc->dev, "Power not on?\n"); 845 } 846 if (status & CBB_STATE_BAD_VCC_REQ) { 847 device_printf(sc->dev, "Bad Vcc requested\n"); 848 /* XXX Do we want to do something to mitigate things here? */ 849 goto done; 850 } 851 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 852 & ~CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 853 retval = 1; 854 done:; 855 if (volts != 0 && sc->chipset == CB_O2MICRO) 856 cbb_o2micro_power_hack2(sc, reg); 857 return (retval); 858 } 859 860 static int 861 cbb_current_voltage(device_t brdev) 862 { 863 struct cbb_softc *sc = device_get_softc(brdev); 864 uint32_t ctrl; 865 866 ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 867 switch (ctrl & CBB_SOCKET_CTRL_VCCMASK) { 868 case CBB_SOCKET_CTRL_VCC_5V: 869 return CARD_5V_CARD; 870 case CBB_SOCKET_CTRL_VCC_3V: 871 return CARD_3V_CARD; 872 case CBB_SOCKET_CTRL_VCC_XV: 873 return CARD_XV_CARD; 874 case CBB_SOCKET_CTRL_VCC_YV: 875 return CARD_YV_CARD; 876 } 877 return 0; 878 } 879 880 /* 881 * detect the voltage for the card, and set it. Since the power 882 * used is the square of the voltage, lower voltages is a big win 883 * and what Windows does (and what Microsoft prefers). The MS paper 884 * also talks about preferring the CIS entry as well, but that has 885 * to be done elsewhere. We also optimize power sequencing here 886 * and don't change things if we're already powered up at a supported 887 * voltage. 888 * 889 * In addition, we power up with OE disabled. We'll set it later 890 * in the power up sequence. 891 */ 892 static int 893 cbb_do_power(device_t brdev) 894 { 895 struct cbb_softc *sc = device_get_softc(brdev); 896 uint32_t voltage, curpwr; 897 uint32_t status; 898 899 /* Don't enable OE (output enable) until power stable */ 900 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 901 902 voltage = cbb_detect_voltage(brdev); 903 curpwr = cbb_current_voltage(brdev); 904 status = cbb_get(sc, CBB_SOCKET_STATE); 905 if ((status & CBB_STATE_POWER_CYCLE) && (voltage & curpwr)) 906 return 0; 907 /* Prefer lowest voltage supported */ 908 cbb_power(brdev, CARD_OFF); 909 if (voltage & CARD_YV_CARD) 910 cbb_power(brdev, CARD_VCC(YV)); 911 else if (voltage & CARD_XV_CARD) 912 cbb_power(brdev, CARD_VCC(XV)); 913 else if (voltage & CARD_3V_CARD) 914 cbb_power(brdev, CARD_VCC(3)); 915 else if (voltage & CARD_5V_CARD) 916 cbb_power(brdev, CARD_VCC(5)); 917 else { 918 device_printf(brdev, "Unknown card voltage\n"); 919 return (ENXIO); 920 } 921 return (0); 922 } 923 924 /************************************************************************/ 925 /* CardBus power functions */ 926 /************************************************************************/ 927 928 static void 929 cbb_cardbus_reset(device_t brdev) 930 { 931 struct cbb_softc *sc = device_get_softc(brdev); 932 int delay; 933 934 /* 935 * 20ms is necessary for most bridges. For some reason, the Ricoh 936 * RF5C47x bridges need 400ms. 937 */ 938 delay = sc->chipset == CB_RF5C47X ? 400 : 20; 939 940 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 941 942 tsleep(sc, PZERO, "cbbP3", hz * delay / 1000); 943 944 /* If a card exists, unreset it! */ 945 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 946 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 947 &~CBBM_BRIDGECTRL_RESET, 2); 948 tsleep(sc, PZERO, "cbbP3", hz * delay / 1000); 949 } 950 } 951 952 static int 953 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 954 { 955 struct cbb_softc *sc = device_get_softc(brdev); 956 int err; 957 958 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 959 return (ENODEV); 960 961 err = cbb_do_power(brdev); 962 if (err) 963 return (err); 964 cbb_cardbus_reset(brdev); 965 return (0); 966 } 967 968 static void 969 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 970 { 971 cbb_power(brdev, CARD_OFF); 972 cbb_cardbus_reset(brdev); 973 } 974 975 /************************************************************************/ 976 /* CardBus Resource */ 977 /************************************************************************/ 978 979 static int 980 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 981 { 982 int basereg; 983 int limitreg; 984 985 if ((win < 0) || (win > 1)) { 986 DEVPRINTF((brdev, 987 "cbb_cardbus_io_open: window out of range %d\n", win)); 988 return (EINVAL); 989 } 990 991 basereg = win * 8 + CBBR_IOBASE0; 992 limitreg = win * 8 + CBBR_IOLIMIT0; 993 994 pci_write_config(brdev, basereg, start, 4); 995 pci_write_config(brdev, limitreg, end, 4); 996 return (0); 997 } 998 999 static int 1000 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 1001 { 1002 int basereg; 1003 int limitreg; 1004 1005 if ((win < 0) || (win > 1)) { 1006 DEVPRINTF((brdev, 1007 "cbb_cardbus_mem_open: window out of range %d\n", win)); 1008 return (EINVAL); 1009 } 1010 1011 basereg = win*8 + CBBR_MEMBASE0; 1012 limitreg = win*8 + CBBR_MEMLIMIT0; 1013 1014 pci_write_config(brdev, basereg, start, 4); 1015 pci_write_config(brdev, limitreg, end, 4); 1016 return (0); 1017 } 1018 1019 /* 1020 * XXX The following function belongs in the pci bus layer. 1021 */ 1022 static void 1023 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1024 { 1025 uint32_t starts[2]; 1026 uint32_t ends[2]; 1027 struct cbb_reslist *rle; 1028 int align; 1029 int prefetchable[2]; 1030 uint32_t reg; 1031 1032 starts[0] = starts[1] = 0xffffffff; 1033 ends[0] = ends[1] = 0; 1034 1035 if (type == SYS_RES_MEMORY) 1036 align = CBB_MEMALIGN; 1037 else if (type == SYS_RES_IOPORT) 1038 align = CBB_IOALIGN; 1039 else 1040 align = 1; 1041 1042 /* 1043 * This looks somewhat bogus, and doesn't seem to really respect 1044 * alignment. The alignment stuff is happening too late (it 1045 * should happen at allocation time, not activation time) and 1046 * this code looks generally to be too complex for the purpose 1047 * it surves. 1048 */ 1049 SLIST_FOREACH(rle, &sc->rl, link) { 1050 if (rle->type != type) 1051 ; 1052 else if (rle->res == NULL) { 1053 device_printf(sc->dev, "WARNING: Resource not reserved? " 1054 "(type=%d, addr=%lx)\n", 1055 rle->type, rman_get_start(rle->res)); 1056 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1057 /* XXX */ 1058 } else if (starts[0] == 0xffffffff) { 1059 starts[0] = rman_get_start(rle->res); 1060 ends[0] = rman_get_end(rle->res); 1061 prefetchable[0] = 1062 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1063 } else if (rman_get_end(rle->res) > ends[0] && 1064 rman_get_start(rle->res) - ends[0] < 1065 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1066 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1067 ends[0] = rman_get_end(rle->res); 1068 } else if (rman_get_start(rle->res) < starts[0] && 1069 starts[0] - rman_get_end(rle->res) < 1070 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1071 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1072 starts[0] = rman_get_start(rle->res); 1073 } else if (starts[1] == 0xffffffff) { 1074 starts[1] = rman_get_start(rle->res); 1075 ends[1] = rman_get_end(rle->res); 1076 prefetchable[1] = 1077 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1078 } else if (rman_get_end(rle->res) > ends[1] && 1079 rman_get_start(rle->res) - ends[1] < 1080 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1081 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1082 ends[1] = rman_get_end(rle->res); 1083 } else if (rman_get_start(rle->res) < starts[1] && 1084 starts[1] - rman_get_end(rle->res) < 1085 CBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1086 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1087 starts[1] = rman_get_start(rle->res); 1088 } else { 1089 uint32_t diffs[2]; 1090 int win; 1091 1092 diffs[0] = diffs[1] = 0xffffffff; 1093 if (rman_get_start(rle->res) > ends[0]) 1094 diffs[0] = rman_get_start(rle->res) - ends[0]; 1095 else if (rman_get_end(rle->res) < starts[0]) 1096 diffs[0] = starts[0] - rman_get_end(rle->res); 1097 if (rman_get_start(rle->res) > ends[1]) 1098 diffs[1] = rman_get_start(rle->res) - ends[1]; 1099 else if (rman_get_end(rle->res) < starts[1]) 1100 diffs[1] = starts[1] - rman_get_end(rle->res); 1101 1102 win = (diffs[0] <= diffs[1])?0:1; 1103 if (rman_get_start(rle->res) > ends[win]) 1104 ends[win] = rman_get_end(rle->res); 1105 else if (rman_get_end(rle->res) < starts[win]) 1106 starts[win] = rman_get_start(rle->res); 1107 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1108 prefetchable[win] = 0; 1109 } 1110 1111 if (starts[0] != 0xffffffff) 1112 starts[0] -= starts[0] % align; 1113 if (starts[1] != 0xffffffff) 1114 starts[1] -= starts[1] % align; 1115 if (ends[0] % align != 0) 1116 ends[0] += align - ends[0] % align - 1; 1117 if (ends[1] % align != 0) 1118 ends[1] += align - ends[1] % align - 1; 1119 } 1120 1121 if (type == SYS_RES_MEMORY) { 1122 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1123 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1124 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1125 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0| 1126 CBBM_BRIDGECTRL_PREFETCH_1); 1127 reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)| 1128 (prefetchable[1]?CBBM_BRIDGECTRL_PREFETCH_1:0); 1129 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1130 } else if (type == SYS_RES_IOPORT) { 1131 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1132 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1133 } 1134 } 1135 1136 static int 1137 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1138 int rid, struct resource *res) 1139 { 1140 int ret; 1141 1142 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1143 type, rid, res); 1144 if (ret != 0) 1145 return (ret); 1146 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1147 return (0); 1148 } 1149 1150 static int 1151 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1152 int rid, struct resource *res) 1153 { 1154 int ret; 1155 1156 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1157 type, rid, res); 1158 if (ret != 0) 1159 return (ret); 1160 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1161 return (0); 1162 } 1163 1164 static struct resource * 1165 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1166 int *rid, u_long start, u_long end, u_long count, u_int flags) 1167 { 1168 struct cbb_softc *sc = device_get_softc(brdev); 1169 int tmp; 1170 struct resource *res; 1171 u_long align; 1172 1173 switch (type) { 1174 case SYS_RES_IRQ: 1175 tmp = rman_get_start(sc->irq_res); 1176 if (start > tmp || end < tmp || count != 1) { 1177 device_printf(child, "requested interrupt %ld-%ld," 1178 "count = %ld not supported by cbb\n", 1179 start, end, count); 1180 return (NULL); 1181 } 1182 start = end = tmp; 1183 flags |= RF_SHAREABLE; 1184 break; 1185 case SYS_RES_IOPORT: 1186 if (start <= cbb_start_32_io) 1187 start = cbb_start_32_io; 1188 if (end < start) 1189 end = start; 1190 break; 1191 case SYS_RES_MEMORY: 1192 if (start <= cbb_start_mem) 1193 start = cbb_start_mem; 1194 if (end < start) 1195 end = start; 1196 if (count < CBB_MEMALIGN) 1197 align = CBB_MEMALIGN; 1198 else 1199 align = count; 1200 if (align > (1 << RF_ALIGNMENT(flags))) 1201 flags = (flags & ~RF_ALIGNMENT_MASK) | 1202 rman_make_alignment_flags(align); 1203 break; 1204 } 1205 1206 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1207 start, end, count, flags & ~RF_ACTIVE); 1208 if (res == NULL) { 1209 printf("cbb alloc res fail\n"); 1210 return (NULL); 1211 } 1212 cbb_insert_res(sc, res, type, *rid); 1213 if (flags & RF_ACTIVE) 1214 if (bus_activate_resource(child, type, *rid, res) != 0) { 1215 bus_release_resource(child, type, *rid, res); 1216 return (NULL); 1217 } 1218 1219 return (res); 1220 } 1221 1222 static int 1223 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1224 int rid, struct resource *res) 1225 { 1226 struct cbb_softc *sc = device_get_softc(brdev); 1227 int error; 1228 1229 if (rman_get_flags(res) & RF_ACTIVE) { 1230 error = bus_deactivate_resource(child, type, rid, res); 1231 if (error != 0) 1232 return (error); 1233 } 1234 cbb_remove_res(sc, res); 1235 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1236 type, rid, res)); 1237 } 1238 1239 /************************************************************************/ 1240 /* PC Card Power Functions */ 1241 /************************************************************************/ 1242 1243 static int 1244 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1245 { 1246 struct cbb_softc *sc = device_get_softc(brdev); 1247 int err; 1248 1249 DPRINTF(("cbb_pcic_socket_enable:\n")); 1250 1251 /* power down/up the socket to reset */ 1252 err = cbb_do_power(brdev); 1253 if (err) 1254 return (err); 1255 exca_reset(&sc->exca[0], child); 1256 1257 return (0); 1258 } 1259 1260 static void 1261 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1262 { 1263 struct cbb_softc *sc = device_get_softc(brdev); 1264 1265 DPRINTF(("cbb_pcic_socket_disable\n")); 1266 1267 /* reset signal asserting... */ 1268 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 1269 tsleep(sc, PZERO, "cbbP1", hz / 100); 1270 1271 /* power down the socket */ 1272 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 1273 cbb_power(brdev, CARD_OFF); 1274 1275 /* wait 300ms until power fails (Tpf). */ 1276 tsleep(sc, PZERO, "cbbP1", hz * 300 / 1000); 1277 } 1278 1279 /************************************************************************/ 1280 /* POWER methods */ 1281 /************************************************************************/ 1282 1283 int 1284 cbb_power_enable_socket(device_t brdev, device_t child) 1285 { 1286 struct cbb_softc *sc = device_get_softc(brdev); 1287 1288 if (sc->flags & CBB_16BIT_CARD) 1289 return (cbb_pcic_power_enable_socket(brdev, child)); 1290 else 1291 return (cbb_cardbus_power_enable_socket(brdev, child)); 1292 } 1293 1294 void 1295 cbb_power_disable_socket(device_t brdev, device_t child) 1296 { 1297 struct cbb_softc *sc = device_get_softc(brdev); 1298 if (sc->flags & CBB_16BIT_CARD) 1299 cbb_pcic_power_disable_socket(brdev, child); 1300 else 1301 cbb_cardbus_power_disable_socket(brdev, child); 1302 } 1303 1304 static int 1305 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1306 struct resource *res) 1307 { 1308 struct cbb_softc *sc = device_get_softc(brdev); 1309 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1310 } 1311 1312 static int 1313 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1314 int rid, struct resource *res) 1315 { 1316 struct cbb_softc *sc = device_get_softc(brdev); 1317 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1318 } 1319 1320 static struct resource * 1321 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1322 u_long start, u_long end, u_long count, u_int flags) 1323 { 1324 struct resource *res = NULL; 1325 struct cbb_softc *sc = device_get_softc(brdev); 1326 int align; 1327 int tmp; 1328 1329 switch (type) { 1330 case SYS_RES_MEMORY: 1331 if (start < cbb_start_mem) 1332 start = cbb_start_mem; 1333 if (end < start) 1334 end = start; 1335 if (count < CBB_MEMALIGN) 1336 align = CBB_MEMALIGN; 1337 else 1338 align = count; 1339 if (align > (1 << RF_ALIGNMENT(flags))) 1340 flags = (flags & ~RF_ALIGNMENT_MASK) | 1341 rman_make_alignment_flags(align); 1342 break; 1343 case SYS_RES_IOPORT: 1344 if (start < cbb_start_16_io) 1345 start = cbb_start_16_io; 1346 if (end < start) 1347 end = start; 1348 break; 1349 case SYS_RES_IRQ: 1350 tmp = rman_get_start(sc->irq_res); 1351 if (start > tmp || end < tmp || count != 1) { 1352 device_printf(child, "requested interrupt %ld-%ld," 1353 "count = %ld not supported by cbb\n", 1354 start, end, count); 1355 return (NULL); 1356 } 1357 flags |= RF_SHAREABLE; 1358 start = end = rman_get_start(sc->irq_res); 1359 break; 1360 } 1361 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1362 start, end, count, flags & ~RF_ACTIVE); 1363 if (res == NULL) 1364 return (NULL); 1365 cbb_insert_res(sc, res, type, *rid); 1366 if (flags & RF_ACTIVE) { 1367 if (bus_activate_resource(child, type, *rid, res) != 0) { 1368 bus_release_resource(child, type, *rid, res); 1369 return (NULL); 1370 } 1371 } 1372 1373 return (res); 1374 } 1375 1376 static int 1377 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1378 int rid, struct resource *res) 1379 { 1380 struct cbb_softc *sc = device_get_softc(brdev); 1381 int error; 1382 1383 if (rman_get_flags(res) & RF_ACTIVE) { 1384 error = bus_deactivate_resource(child, type, rid, res); 1385 if (error != 0) 1386 return (error); 1387 } 1388 cbb_remove_res(sc, res); 1389 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1390 type, rid, res)); 1391 } 1392 1393 /************************************************************************/ 1394 /* PC Card methods */ 1395 /************************************************************************/ 1396 1397 int 1398 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1399 uint32_t flags) 1400 { 1401 struct cbb_softc *sc = device_get_softc(brdev); 1402 struct resource *res; 1403 1404 if (type != SYS_RES_MEMORY) 1405 return (EINVAL); 1406 res = cbb_find_res(sc, type, rid); 1407 if (res == NULL) { 1408 device_printf(brdev, 1409 "set_res_flags: specified rid not found\n"); 1410 return (ENOENT); 1411 } 1412 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1413 } 1414 1415 int 1416 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1417 uint32_t cardaddr, uint32_t *deltap) 1418 { 1419 struct cbb_softc *sc = device_get_softc(brdev); 1420 struct resource *res; 1421 1422 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1423 if (res == NULL) { 1424 device_printf(brdev, 1425 "set_memory_offset: specified rid not found\n"); 1426 return (ENOENT); 1427 } 1428 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1429 } 1430 1431 /************************************************************************/ 1432 /* BUS Methods */ 1433 /************************************************************************/ 1434 1435 1436 int 1437 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1438 struct resource *r) 1439 { 1440 struct cbb_softc *sc = device_get_softc(brdev); 1441 1442 if (sc->flags & CBB_16BIT_CARD) 1443 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1444 else 1445 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1446 r)); 1447 } 1448 1449 int 1450 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1451 int rid, struct resource *r) 1452 { 1453 struct cbb_softc *sc = device_get_softc(brdev); 1454 1455 if (sc->flags & CBB_16BIT_CARD) 1456 return (cbb_pcic_deactivate_resource(brdev, child, type, 1457 rid, r)); 1458 else 1459 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1460 rid, r)); 1461 } 1462 1463 struct resource * 1464 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1465 u_long start, u_long end, u_long count, u_int flags) 1466 { 1467 struct cbb_softc *sc = device_get_softc(brdev); 1468 1469 if (sc->flags & CBB_16BIT_CARD) 1470 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1471 start, end, count, flags)); 1472 else 1473 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1474 start, end, count, flags)); 1475 } 1476 1477 int 1478 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1479 struct resource *r) 1480 { 1481 struct cbb_softc *sc = device_get_softc(brdev); 1482 1483 if (sc->flags & CBB_16BIT_CARD) 1484 return (cbb_pcic_release_resource(brdev, child, type, 1485 rid, r)); 1486 else 1487 return (cbb_cardbus_release_resource(brdev, child, type, 1488 rid, r)); 1489 } 1490 1491 int 1492 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1493 { 1494 struct cbb_softc *sc = device_get_softc(brdev); 1495 1496 switch (which) { 1497 case PCIB_IVAR_BUS: 1498 *result = sc->secbus; 1499 return (0); 1500 } 1501 return (ENOENT); 1502 } 1503 1504 int 1505 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1506 { 1507 struct cbb_softc *sc = device_get_softc(brdev); 1508 1509 switch (which) { 1510 case PCIB_IVAR_BUS: 1511 sc->secbus = value; 1512 break; 1513 } 1514 return (ENOENT); 1515 } 1516 1517 /************************************************************************/ 1518 /* PCI compat methods */ 1519 /************************************************************************/ 1520 1521 int 1522 cbb_maxslots(device_t brdev) 1523 { 1524 return (0); 1525 } 1526 1527 uint32_t 1528 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 1529 { 1530 uint32_t rv; 1531 1532 /* 1533 * Pass through to the next ppb up the chain (i.e. our grandparent). 1534 */ 1535 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 1536 b, s, f, reg, width); 1537 return (rv); 1538 } 1539 1540 void 1541 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 1542 int width) 1543 { 1544 /* 1545 * Pass through to the next ppb up the chain (i.e. our grandparent). 1546 */ 1547 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 1548 b, s, f, reg, val, width); 1549 } 1550 1551 int 1552 cbb_suspend(device_t self) 1553 { 1554 int error = 0; 1555 struct cbb_softc *sc = device_get_softc(self); 1556 1557 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1558 bus_teardown_intr(self, sc->irq_res, sc->intrhand); 1559 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1560 error = bus_generic_suspend(self); 1561 return (error); 1562 } 1563 1564 int 1565 cbb_resume(device_t self) 1566 { 1567 int error = 0; 1568 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1569 uint32_t tmp; 1570 1571 /* 1572 * Some BIOSes will not save the BARs for the pci chips, so we 1573 * must do it ourselves. If the BAR is reset to 0 for an I/O 1574 * device, it will read back as 0x1, so no explicit test for 1575 * memory devices are needed. 1576 * 1577 * Note: The PCI bus code should do this automatically for us on 1578 * suspend/resume, but until it does, we have to cope. 1579 */ 1580 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1581 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1582 rman_get_start(sc->base_res))); 1583 1584 sc->chipinit(sc); 1585 1586 /* reset interrupt -- Do we really need to do this? */ 1587 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1588 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1589 1590 /* re-establish the interrupt. */ 1591 if (bus_setup_intr(self, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 1592 cbb_intr, sc, &sc->intrhand)) { 1593 device_printf(self, "couldn't re-establish interrupt"); 1594 bus_release_resource(self, SYS_RES_IRQ, 0, sc->irq_res); 1595 bus_release_resource(self, SYS_RES_MEMORY, CBBR_SOCKBASE, 1596 sc->base_res); 1597 sc->irq_res = NULL; 1598 sc->base_res = NULL; 1599 return (ENOMEM); 1600 } 1601 1602 /* CSC Interrupt: Card detect interrupt on */ 1603 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1604 1605 /* Signal the thread to wakeup. */ 1606 mtx_lock(&sc->mtx); 1607 cv_signal(&sc->cv); 1608 mtx_unlock(&sc->mtx); 1609 1610 error = bus_generic_resume(self); 1611 1612 return (error); 1613 } 1614 1615 int 1616 cbb_child_present(device_t self) 1617 { 1618 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1619 uint32_t sockstate; 1620 1621 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1622 return (CBB_CARD_PRESENT(sockstate) && 1623 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1624 } 1625