1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * and PCI to PCMCIA Bridge chips 62 * and ISA to PCMCIA host adapters 63 * and C Bus to PCMCIA host adapters 64 * 65 * References: 66 * TI Datasheets: 67 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 68 * 69 * Written by Jonathan Chen <jon@freebsd.org> 70 * The author would like to acknowledge: 71 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 72 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 73 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 74 * * David Cross: Author of the initial ugly hack for a specific cardbus card 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include <sys/param.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/module.h> 86 #include <sys/kthread.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mutex.h> 90 #include <sys/proc.h> 91 #include <sys/rman.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 #include <machine/bus.h> 95 #include <machine/resource.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #include <dev/pccard/pccardreg.h> 101 #include <dev/pccard/pccardvar.h> 102 103 #include <dev/exca/excareg.h> 104 #include <dev/exca/excavar.h> 105 106 #include <dev/pccbb/pccbbreg.h> 107 #include <dev/pccbb/pccbbvar.h> 108 109 #include "power_if.h" 110 #include "card_if.h" 111 #include "pcib_if.h" 112 113 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 114 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 115 116 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 117 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 118 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 119 pci_write_config(DEV, REG, ( \ 120 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 121 122 #define CBB_CARD_PRESENT(s) ((s & CBB_STATE_CD) == 0) 123 124 #define CBB_START_MEM 0x88000000 125 #define CBB_START_32_IO 0x1000 126 #define CBB_START_16_IO 0x100 127 128 devclass_t cbb_devclass; 129 130 /* sysctl vars */ 131 SYSCTL_NODE(_hw, OID_AUTO, cbb, CTLFLAG_RD, 0, "CBB parameters"); 132 133 /* There's no way to say TUNEABLE_LONG to get the right types */ 134 u_long cbb_start_mem = CBB_START_MEM; 135 TUNABLE_ULONG("hw.cbb.start_memory", &cbb_start_mem); 136 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_memory, CTLFLAG_RW, 137 &cbb_start_mem, CBB_START_MEM, 138 "Starting address for memory allocations"); 139 140 u_long cbb_start_16_io = CBB_START_16_IO; 141 TUNABLE_ULONG("hw.cbb.start_16_io", &cbb_start_16_io); 142 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_16_io, CTLFLAG_RW, 143 &cbb_start_16_io, CBB_START_16_IO, 144 "Starting ioport for 16-bit cards"); 145 146 u_long cbb_start_32_io = CBB_START_32_IO; 147 TUNABLE_ULONG("hw.cbb.start_32_io", &cbb_start_32_io); 148 SYSCTL_ULONG(_hw_cbb, OID_AUTO, start_32_io, CTLFLAG_RW, 149 &cbb_start_32_io, CBB_START_32_IO, 150 "Starting ioport for 32-bit cards"); 151 152 int cbb_debug = 0; 153 TUNABLE_INT("hw.cbb.debug", &cbb_debug); 154 SYSCTL_ULONG(_hw_cbb, OID_AUTO, debug, CTLFLAG_RW, &cbb_debug, 0, 155 "Verbose cardbus bridge debugging"); 156 157 static void cbb_insert(struct cbb_softc *sc); 158 static void cbb_removal(struct cbb_softc *sc); 159 static uint32_t cbb_detect_voltage(device_t brdev); 160 static void cbb_cardbus_reset(device_t brdev); 161 static int cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, 162 uint32_t end); 163 static int cbb_cardbus_mem_open(device_t brdev, int win, 164 uint32_t start, uint32_t end); 165 static void cbb_cardbus_auto_open(struct cbb_softc *sc, int type); 166 static int cbb_cardbus_activate_resource(device_t brdev, device_t child, 167 int type, int rid, struct resource *res); 168 static int cbb_cardbus_deactivate_resource(device_t brdev, 169 device_t child, int type, int rid, struct resource *res); 170 static struct resource *cbb_cardbus_alloc_resource(device_t brdev, 171 device_t child, int type, int *rid, u_long start, 172 u_long end, u_long count, u_int flags); 173 static int cbb_cardbus_release_resource(device_t brdev, device_t child, 174 int type, int rid, struct resource *res); 175 static int cbb_cardbus_power_enable_socket(device_t brdev, 176 device_t child); 177 static void cbb_cardbus_power_disable_socket(device_t brdev, 178 device_t child); 179 static void cbb_func_intr(void *arg); 180 181 static void 182 cbb_remove_res(struct cbb_softc *sc, struct resource *res) 183 { 184 struct cbb_reslist *rle; 185 186 SLIST_FOREACH(rle, &sc->rl, link) { 187 if (rle->res == res) { 188 SLIST_REMOVE(&sc->rl, rle, cbb_reslist, link); 189 free(rle, M_DEVBUF); 190 return; 191 } 192 } 193 } 194 195 static struct resource * 196 cbb_find_res(struct cbb_softc *sc, int type, int rid) 197 { 198 struct cbb_reslist *rle; 199 200 SLIST_FOREACH(rle, &sc->rl, link) 201 if (SYS_RES_MEMORY == rle->type && rid == rle->rid) 202 return (rle->res); 203 return (NULL); 204 } 205 206 static void 207 cbb_insert_res(struct cbb_softc *sc, struct resource *res, int type, 208 int rid) 209 { 210 struct cbb_reslist *rle; 211 212 /* 213 * Need to record allocated resource so we can iterate through 214 * it later. 215 */ 216 rle = malloc(sizeof(struct cbb_reslist), M_DEVBUF, M_NOWAIT); 217 if (rle == NULL) 218 panic("cbb_cardbus_alloc_resource: can't record entry!"); 219 rle->res = res; 220 rle->type = type; 221 rle->rid = rid; 222 SLIST_INSERT_HEAD(&sc->rl, rle, link); 223 } 224 225 static void 226 cbb_destroy_res(struct cbb_softc *sc) 227 { 228 struct cbb_reslist *rle; 229 230 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 231 device_printf(sc->dev, "Danger Will Robinson: Resource " 232 "left allocated! This is a bug... " 233 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 234 rman_get_start(rle->res)); 235 SLIST_REMOVE_HEAD(&sc->rl, link); 236 free(rle, M_DEVBUF); 237 } 238 } 239 240 /* 241 * Disable function interrupts by telling the bridge to generate IRQ1 242 * interrupts. These interrupts aren't really generated by the chip, since 243 * IRQ1 is reserved. Some chipsets assert INTA# inappropriately during 244 * initialization, so this helps to work around the problem. 245 * 246 * XXX We can't do this workaround for all chipsets, because this 247 * XXX causes interference with the keyboard because somechipsets will 248 * XXX actually signal IRQ1 over their serial interrupt connections to 249 * XXX the south bridge. Disable it it for now. 250 */ 251 void 252 cbb_disable_func_intr(struct cbb_softc *sc) 253 { 254 #if 0 255 uint8_t reg; 256 257 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 258 EXCA_INTR_IRQ_RESERVED1; 259 exca_putb(&sc->exca[0], EXCA_INTR, reg); 260 #endif 261 } 262 263 /* 264 * Enable function interrupts. We turn on function interrupts when the card 265 * requests an interrupt. The PCMCIA standard says that we should set 266 * the lower 4 bits to 0 to route via PCI. Note: we call this for both 267 * CardBus and R2 (PC Card) cases, but it should have no effect on CardBus 268 * cards. 269 */ 270 static void 271 cbb_enable_func_intr(struct cbb_softc *sc) 272 { 273 uint8_t reg; 274 275 reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) | 276 EXCA_INTR_IRQ_NONE; 277 exca_putb(&sc->exca[0], EXCA_INTR, reg); 278 } 279 280 int 281 cbb_detach(device_t brdev) 282 { 283 struct cbb_softc *sc = device_get_softc(brdev); 284 device_t *devlist; 285 int tmp, tries, error, numdevs; 286 287 /* 288 * Before we delete the children (which we have to do because 289 * attach doesn't check for children busses correctly), we have 290 * to detach the children. Even if we didn't need to delete the 291 * children, we have to detach them. 292 */ 293 error = bus_generic_detach(brdev); 294 if (error != 0) 295 return (error); 296 297 /* 298 * Since the attach routine doesn't search for children before it 299 * attaches them to this device, we must delete them here in order 300 * for the kldload/unload case to work. If we failed to do that, then 301 * we'd get duplicate devices when cbb.ko was reloaded. 302 */ 303 tries = 10; 304 do { 305 error = device_get_children(brdev, &devlist, &numdevs); 306 if (error == 0) 307 break; 308 /* 309 * Try hard to cope with low memory. 310 */ 311 if (error == ENOMEM) { 312 pause("cbbnomem", 1); 313 continue; 314 } 315 } while (tries-- > 0); 316 for (tmp = 0; tmp < numdevs; tmp++) 317 device_delete_child(brdev, devlist[tmp]); 318 free(devlist, M_TEMP); 319 320 /* Turn off the interrupts */ 321 cbb_set(sc, CBB_SOCKET_MASK, 0); 322 323 /* reset 16-bit pcmcia bus */ 324 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 325 326 /* turn off power */ 327 cbb_power(brdev, CARD_OFF); 328 329 /* Ack the interrupt */ 330 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 331 332 /* 333 * Wait for the thread to die. kthread_exit will do a wakeup 334 * on the event thread's struct thread * so that we know it is 335 * save to proceed. IF the thread is running, set the please 336 * die flag and wait for it to comply. Since the wakeup on 337 * the event thread happens only in kthread_exit, we don't 338 * need to loop here. 339 */ 340 mtx_lock(&sc->mtx); 341 bus_teardown_intr(brdev, sc->irq_res, sc->intrhand); 342 sc->flags |= CBB_KTHREAD_DONE; 343 while (sc->flags & CBB_KTHREAD_RUNNING) { 344 DEVPRINTF((sc->dev, "Waiting for thread to die\n")); 345 cv_broadcast(&sc->cv); 346 msleep(sc->event_thread, &sc->mtx, PWAIT, "cbbun", 0); 347 } 348 mtx_unlock(&sc->mtx); 349 350 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 351 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 352 sc->base_res); 353 mtx_destroy(&sc->mtx); 354 cv_destroy(&sc->cv); 355 cv_destroy(&sc->powercv); 356 return (0); 357 } 358 359 int 360 cbb_setup_intr(device_t dev, device_t child, struct resource *irq, 361 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 362 void **cookiep) 363 { 364 struct cbb_intrhand *ih; 365 struct cbb_softc *sc = device_get_softc(dev); 366 int err; 367 368 /* 369 * Well, this is no longer strictly true. You can have multiple 370 * FAST ISRs, but can't mix fast and slow, so we have to assume 371 * least common denominator until the base system supports mixing 372 * and matching better. 373 */ 374 if (filt != NULL) 375 return (EINVAL); 376 ih = malloc(sizeof(struct cbb_intrhand), M_DEVBUF, M_NOWAIT); 377 if (ih == NULL) 378 return (ENOMEM); 379 *cookiep = ih; 380 ih->intr = intr; 381 ih->arg = arg; 382 ih->sc = sc; 383 /* 384 * XXX need to turn on ISA interrupts, if we ever support them, but 385 * XXX for now that's all we need to do. 386 */ 387 err = BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, 388 NULL, cbb_func_intr, ih, &ih->cookie); 389 if (err != 0) { 390 free(ih, M_DEVBUF); 391 return (err); 392 } 393 cbb_enable_func_intr(sc); 394 sc->flags |= CBB_CARD_OK; 395 return 0; 396 } 397 398 int 399 cbb_teardown_intr(device_t dev, device_t child, struct resource *irq, 400 void *cookie) 401 { 402 struct cbb_intrhand *ih; 403 int err; 404 405 /* XXX Need to do different things for ISA interrupts. */ 406 ih = (struct cbb_intrhand *) cookie; 407 err = BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, 408 ih->cookie); 409 if (err != 0) 410 return (err); 411 free(ih, M_DEVBUF); 412 return (0); 413 } 414 415 416 void 417 cbb_driver_added(device_t brdev, driver_t *driver) 418 { 419 struct cbb_softc *sc = device_get_softc(brdev); 420 device_t *devlist; 421 device_t dev; 422 int tmp; 423 int numdevs; 424 int wake = 0; 425 426 DEVICE_IDENTIFY(driver, brdev); 427 tmp = device_get_children(brdev, &devlist, &numdevs); 428 if (tmp != 0) { 429 device_printf(brdev, "Cannot get children list, no reprobe\n"); 430 return; 431 } 432 for (tmp = 0; tmp < numdevs; tmp++) { 433 dev = devlist[tmp]; 434 if (device_get_state(dev) == DS_NOTPRESENT && 435 device_probe_and_attach(dev) == 0) 436 wake++; 437 } 438 free(devlist, M_TEMP); 439 440 if (wake > 0) { 441 mtx_lock(&sc->mtx); 442 cv_signal(&sc->cv); 443 mtx_unlock(&sc->mtx); 444 } 445 } 446 447 void 448 cbb_child_detached(device_t brdev, device_t child) 449 { 450 struct cbb_softc *sc = device_get_softc(brdev); 451 452 /* I'm not sure we even need this */ 453 if (child != sc->cbdev && child != sc->exca[0].pccarddev) 454 device_printf(brdev, "Unknown child detached: %s\n", 455 device_get_nameunit(child)); 456 } 457 458 /************************************************************************/ 459 /* Kthreads */ 460 /************************************************************************/ 461 462 void 463 cbb_event_thread(void *arg) 464 { 465 struct cbb_softc *sc = arg; 466 uint32_t status; 467 int err; 468 int not_a_card = 0; 469 470 mtx_lock(&sc->mtx); 471 sc->flags |= CBB_KTHREAD_RUNNING; 472 mtx_unlock(&sc->mtx); 473 while ((sc->flags & CBB_KTHREAD_DONE) == 0) { 474 /* 475 * We take out Giant here because we need it deep, 476 * down in the bowels of the vm system for mapping the 477 * memory we need to read the CIS. In addition, since 478 * we are adding/deleting devices from the dev tree, 479 * and that code isn't MP safe, we have to hold Giant. 480 */ 481 mtx_lock(&Giant); 482 status = cbb_get(sc, CBB_SOCKET_STATE); 483 DPRINTF(("Status is 0x%x\n", status)); 484 if (!CBB_CARD_PRESENT(status)) { 485 not_a_card = 0; /* We know card type */ 486 cbb_removal(sc); 487 } else if (status & CBB_STATE_NOT_A_CARD) { 488 /* 489 * Up to 20 times, try to rescan the card when we 490 * see NOT_A_CARD. 491 */ 492 if (not_a_card++ < 20) { 493 DEVPRINTF((sc->dev, 494 "Not a card bit set, rescanning\n")); 495 cbb_setb(sc, CBB_SOCKET_FORCE, CBB_FORCE_CV_TEST); 496 } else { 497 device_printf(sc->dev, 498 "Can't determine card type\n"); 499 } 500 } else { 501 not_a_card = 0; /* We know card type */ 502 cbb_insert(sc); 503 } 504 mtx_unlock(&Giant); 505 506 /* 507 * Wait until it has been 1s since the last time we 508 * get an interrupt. We handle the rest of the interrupt 509 * at the top of the loop. Although we clear the bit in the 510 * ISR, we signal sc->cv from the detach path after we've 511 * set the CBB_KTHREAD_DONE bit, so we can't do a simple 512 * 1s sleep here. 513 * 514 * In our ISR, we turn off the card changed interrupt. Turn 515 * them back on here before we wait for them to happen. We 516 * turn them on/off so that we can tolerate a large latency 517 * between the time we signal cbb_event_thread and it gets 518 * a chance to run. 519 */ 520 mtx_lock(&sc->mtx); 521 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 522 cv_wait(&sc->cv, &sc->mtx); 523 err = 0; 524 while (err != EWOULDBLOCK && 525 (sc->flags & CBB_KTHREAD_DONE) == 0) 526 err = cv_timedwait(&sc->cv, &sc->mtx, hz / 4); 527 mtx_unlock(&sc->mtx); 528 } 529 DEVPRINTF((sc->dev, "Thread terminating\n")); 530 mtx_lock(&sc->mtx); 531 sc->flags &= ~CBB_KTHREAD_RUNNING; 532 mtx_unlock(&sc->mtx); 533 kthread_exit(0); 534 } 535 536 /************************************************************************/ 537 /* Insert/removal */ 538 /************************************************************************/ 539 540 static void 541 cbb_insert(struct cbb_softc *sc) 542 { 543 uint32_t sockevent, sockstate; 544 545 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 546 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 547 548 DEVPRINTF((sc->dev, "card inserted: event=0x%08x, state=%08x\n", 549 sockevent, sockstate)); 550 551 if (sockstate & CBB_STATE_R2_CARD) { 552 if (device_is_attached(sc->exca[0].pccarddev)) { 553 sc->flags |= CBB_16BIT_CARD; 554 exca_insert(&sc->exca[0]); 555 } else { 556 device_printf(sc->dev, 557 "16-bit card inserted, but no pccard bus.\n"); 558 } 559 } else if (sockstate & CBB_STATE_CB_CARD) { 560 if (device_is_attached(sc->cbdev)) { 561 sc->flags &= ~CBB_16BIT_CARD; 562 CARD_ATTACH_CARD(sc->cbdev); 563 } else { 564 device_printf(sc->dev, 565 "CardBus card inserted, but no cardbus bus.\n"); 566 } 567 } else { 568 /* 569 * We should power the card down, and try again a couple of 570 * times if this happens. XXX 571 */ 572 device_printf(sc->dev, "Unsupported card type detected\n"); 573 } 574 } 575 576 static void 577 cbb_removal(struct cbb_softc *sc) 578 { 579 sc->flags &= ~CBB_CARD_OK; 580 if (sc->flags & CBB_16BIT_CARD) { 581 exca_removal(&sc->exca[0]); 582 } else { 583 if (device_is_attached(sc->cbdev)) 584 CARD_DETACH_CARD(sc->cbdev); 585 } 586 cbb_destroy_res(sc); 587 } 588 589 /************************************************************************/ 590 /* Interrupt Handler */ 591 /************************************************************************/ 592 593 /* 594 * Since we touch hardware in the worst case, we don't need to use atomic 595 * ops on the CARD_OK tests. They would save us a trip to the hardware 596 * if CARD_OK was recently cleared and the caches haven't updated yet. 597 * However, an atomic op costs between 100-200 CPU cycles. On a 3GHz 598 * machine, this is about 33-66ns, whereas a trip the the hardware 599 * is about that. On slower machines, the cost is even higher, so the 600 * trip to the hardware is cheaper and achieves the same ends that 601 * a fully locked operation would give us. 602 * 603 * This is a separate routine because we'd have to use locking and/or 604 * other synchronization in cbb_intr to do this there. That would be 605 * even more expensive. 606 * 607 * I need to investigate what this means for a SMP machine with multiple 608 * CPUs servicing the ISR when an eject happens. In the case of a dirty 609 * eject, CD glitches and we might read 'card present' from the hardware 610 * due to this jitter. If we assumed that cbb_intr() ran before 611 * cbb_func_intr(), we could just check the SOCKET_MASK register and if 612 * CD changes were clear there, then we'd know the card was gone. 613 */ 614 static void 615 cbb_func_intr(void *arg) 616 { 617 struct cbb_intrhand *ih = (struct cbb_intrhand *)arg; 618 struct cbb_softc *sc = ih->sc; 619 620 /* 621 * Make sure that the card is really there. 622 */ 623 if ((sc->flags & CBB_CARD_OK) == 0) 624 return; 625 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 626 sc->flags &= ~CBB_CARD_OK; 627 return; 628 } 629 630 /* 631 * nb: don't have to check for giant or not, since that's done 632 * in the ISR dispatch 633 */ 634 (*ih->intr)(ih->arg); 635 } 636 637 /************************************************************************/ 638 /* Generic Power functions */ 639 /************************************************************************/ 640 641 static uint32_t 642 cbb_detect_voltage(device_t brdev) 643 { 644 struct cbb_softc *sc = device_get_softc(brdev); 645 uint32_t psr; 646 uint32_t vol = CARD_UKN_CARD; 647 648 psr = cbb_get(sc, CBB_SOCKET_STATE); 649 650 if (psr & CBB_STATE_5VCARD && psr & CBB_STATE_5VSOCK) 651 vol |= CARD_5V_CARD; 652 if (psr & CBB_STATE_3VCARD && psr & CBB_STATE_3VSOCK) 653 vol |= CARD_3V_CARD; 654 if (psr & CBB_STATE_XVCARD && psr & CBB_STATE_XVSOCK) 655 vol |= CARD_XV_CARD; 656 if (psr & CBB_STATE_YVCARD && psr & CBB_STATE_YVSOCK) 657 vol |= CARD_YV_CARD; 658 659 return (vol); 660 } 661 662 static uint8_t 663 cbb_o2micro_power_hack(struct cbb_softc *sc) 664 { 665 uint8_t reg; 666 667 /* 668 * Issue #2: INT# not qualified with IRQ Routing Bit. An 669 * unexpected PCI INT# may be generated during PC Card 670 * initialization even with the IRQ Routing Bit Set with some 671 * PC Cards. 672 * 673 * This is a two part issue. The first part is that some of 674 * our older controllers have an issue in which the slot's PCI 675 * INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh 676 * bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ 677 * is selected (ExCA register 03h bits 3:0, of the slot, are 678 * cleared) we will generate INT# if IREQ# is asserted. The 679 * second part is because some PC Cards prematurally assert 680 * IREQ# before the ExCA registers are fully programmed. This 681 * in turn asserts INT# because ExCA register 03h bits 3:0 682 * (ISA IRQ Select) are not yet programmed. 683 * 684 * The fix for this issue, which will work for any controller 685 * (old or new), is to set ExCA register 03h bits 3:0 = 0001b 686 * (select IRQ1), of the slot, before turning on slot power. 687 * Selecting IRQ1 will result in INT# NOT being asserted 688 * (because IRQ1 is selected), and IRQ1 won't be asserted 689 * because our controllers don't generate IRQ1. 690 * 691 * Other, non O2Micro controllers will generate irq 1 in some 692 * situations, so we can't do this hack for everybody. Reports of 693 * keyboard controller's interrupts being suppressed occurred when 694 * we did this. 695 */ 696 reg = exca_getb(&sc->exca[0], EXCA_INTR); 697 exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1); 698 return (reg); 699 } 700 701 /* 702 * Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so 703 * we don't have an interrupt storm on power on. This has the efect of 704 * disabling card status change interrupts for the duration of poweron. 705 */ 706 static void 707 cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg) 708 { 709 exca_putb(&sc->exca[0], EXCA_INTR, reg); 710 } 711 712 int 713 cbb_power(device_t brdev, int volts) 714 { 715 uint32_t status, sock_ctrl, reg_ctrl, mask; 716 struct cbb_softc *sc = device_get_softc(brdev); 717 int cnt, sane; 718 int retval = 0; 719 int on = 0; 720 uint8_t reg = 0; 721 722 sock_ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 723 724 sock_ctrl &= ~CBB_SOCKET_CTRL_VCCMASK; 725 switch (volts & CARD_VCCMASK) { 726 case 5: 727 sock_ctrl |= CBB_SOCKET_CTRL_VCC_5V; 728 on++; 729 break; 730 case 3: 731 sock_ctrl |= CBB_SOCKET_CTRL_VCC_3V; 732 on++; 733 break; 734 case XV: 735 sock_ctrl |= CBB_SOCKET_CTRL_VCC_XV; 736 on++; 737 break; 738 case YV: 739 sock_ctrl |= CBB_SOCKET_CTRL_VCC_YV; 740 on++; 741 break; 742 case 0: 743 break; 744 default: 745 return (0); /* power NEVER changed */ 746 } 747 748 /* VPP == VCC */ 749 sock_ctrl &= ~CBB_SOCKET_CTRL_VPPMASK; 750 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 751 752 if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl) 753 return (1); /* no change necessary */ 754 DEVPRINTF((sc->dev, "cbb_power: %dV\n", volts)); 755 if (volts != 0 && sc->chipset == CB_O2MICRO) 756 reg = cbb_o2micro_power_hack(sc); 757 758 /* 759 * We have to mask the card change detect interrupt while 760 * we're messing with the power. It is allowed to bounce 761 * while we're messing with power as things settle down. In 762 * addition, we mask off the card's function interrupt by 763 * routing it via the ISA bus. This bit generally only 764 * affects 16-bit cards. Some bridges allow one to set 765 * another bit to have it also affect 32-bit cards. Since 766 * 32-bit cards are required to be better behaved, we don't 767 * bother to get into those bridge specific features. 768 */ 769 mask = cbb_get(sc, CBB_SOCKET_MASK); 770 mask |= CBB_SOCKET_MASK_POWER; 771 mask &= ~CBB_SOCKET_MASK_CD; 772 cbb_set(sc, CBB_SOCKET_MASK, mask); 773 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 774 |CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 775 cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl); 776 if (on) { 777 mtx_lock(&sc->mtx); 778 cnt = sc->powerintr; 779 /* 780 * We have a shortish timeout of 500ms here. Some 781 * bridges do not generate a POWER_CYCLE event for 782 * 16-bit cards. In those cases, we have to cope the 783 * best we can, and having only a short delay is 784 * better than the alternatives. 785 */ 786 sane = 10; 787 while (!(cbb_get(sc, CBB_SOCKET_STATE) & CBB_STATE_POWER_CYCLE) && 788 cnt == sc->powerintr && sane-- > 0) 789 cv_timedwait(&sc->powercv, &sc->mtx, hz / 20); 790 mtx_unlock(&sc->mtx); 791 /* 792 * The TOPIC95B requires a little bit extra time to get 793 * its act together, so delay for an additional 100ms. Also 794 * as documented below, it doesn't seem to set the POWER_CYCLE 795 * bit, so don't whine if it never came on. 796 */ 797 if (sc->chipset == CB_TOPIC95) { 798 pause("cbb95B", hz / 10); 799 } else if (sane <= 0) { 800 device_printf(sc->dev, "power timeout, doom?\n"); 801 } 802 } 803 804 /* 805 * After the power is good, we can turn off the power interrupt. 806 * However, the PC Card standard says that we must delay turning the 807 * CD bit back on for a bit to allow for bouncyness on power down 808 * (recall that we don't wait above for a power down, since we don't 809 * get an interrupt for that). We're called either from the suspend 810 * code in which case we don't want to turn card change on again, or 811 * we're called from the card insertion code, in which case the cbb 812 * thread will turn it on for us before it waits to be woken by a 813 * change event. 814 * 815 * NB: Topic95B doesn't set the power cycle bit. we assume that 816 * both it and the TOPIC95 behave the same. 817 */ 818 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_POWER); 819 status = cbb_get(sc, CBB_SOCKET_STATE); 820 if (on && sc->chipset != CB_TOPIC95) { 821 if ((status & CBB_STATE_POWER_CYCLE) == 0) 822 device_printf(sc->dev, "Power not on?\n"); 823 } 824 if (status & CBB_STATE_BAD_VCC_REQ) { 825 device_printf(sc->dev, "Bad Vcc requested\n"); 826 /* XXX Do we want to do something to mitigate things here? */ 827 goto done; 828 } 829 if (sc->chipset == CB_TOPIC97) { 830 reg_ctrl = pci_read_config(sc->dev, TOPIC_REG_CTRL, 4); 831 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 832 if (on) 833 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 834 else 835 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 836 pci_write_config(sc->dev, TOPIC_REG_CTRL, reg_ctrl, 4); 837 } 838 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 839 & ~CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN, 2); 840 retval = 1; 841 done:; 842 if (volts != 0 && sc->chipset == CB_O2MICRO) 843 cbb_o2micro_power_hack2(sc, reg); 844 return (retval); 845 } 846 847 static int 848 cbb_current_voltage(device_t brdev) 849 { 850 struct cbb_softc *sc = device_get_softc(brdev); 851 uint32_t ctrl; 852 853 ctrl = cbb_get(sc, CBB_SOCKET_CONTROL); 854 switch (ctrl & CBB_SOCKET_CTRL_VCCMASK) { 855 case CBB_SOCKET_CTRL_VCC_5V: 856 return CARD_5V_CARD; 857 case CBB_SOCKET_CTRL_VCC_3V: 858 return CARD_3V_CARD; 859 case CBB_SOCKET_CTRL_VCC_XV: 860 return CARD_XV_CARD; 861 case CBB_SOCKET_CTRL_VCC_YV: 862 return CARD_YV_CARD; 863 } 864 return 0; 865 } 866 867 /* 868 * detect the voltage for the card, and set it. Since the power 869 * used is the square of the voltage, lower voltages is a big win 870 * and what Windows does (and what Microsoft prefers). The MS paper 871 * also talks about preferring the CIS entry as well, but that has 872 * to be done elsewhere. We also optimize power sequencing here 873 * and don't change things if we're already powered up at a supported 874 * voltage. 875 * 876 * In addition, we power up with OE disabled. We'll set it later 877 * in the power up sequence. 878 */ 879 static int 880 cbb_do_power(device_t brdev) 881 { 882 struct cbb_softc *sc = device_get_softc(brdev); 883 uint32_t voltage, curpwr; 884 uint32_t status; 885 886 /* Don't enable OE (output enable) until power stable */ 887 exca_clrb(&sc->exca[0], EXCA_PWRCTL, EXCA_PWRCTL_OE); 888 889 voltage = cbb_detect_voltage(brdev); 890 curpwr = cbb_current_voltage(brdev); 891 status = cbb_get(sc, CBB_SOCKET_STATE); 892 if ((status & CBB_STATE_POWER_CYCLE) && (voltage & curpwr)) 893 return 0; 894 /* Prefer lowest voltage supported */ 895 cbb_power(brdev, CARD_OFF); 896 if (voltage & CARD_YV_CARD) 897 cbb_power(brdev, CARD_VCC(YV)); 898 else if (voltage & CARD_XV_CARD) 899 cbb_power(brdev, CARD_VCC(XV)); 900 else if (voltage & CARD_3V_CARD) 901 cbb_power(brdev, CARD_VCC(3)); 902 else if (voltage & CARD_5V_CARD) 903 cbb_power(brdev, CARD_VCC(5)); 904 else { 905 device_printf(brdev, "Unknown card voltage\n"); 906 return (ENXIO); 907 } 908 return (0); 909 } 910 911 /************************************************************************/ 912 /* CardBus power functions */ 913 /************************************************************************/ 914 915 static void 916 cbb_cardbus_reset(device_t brdev) 917 { 918 struct cbb_softc *sc = device_get_softc(brdev); 919 int delay; 920 921 /* 922 * 20ms is necessary for most bridges. For some reason, the Ricoh 923 * RF5C47x bridges need 400ms. 924 */ 925 delay = sc->chipset == CB_RF5C47X ? 400 : 20; 926 927 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 928 929 pause("cbbP3", hz * delay / 1000); 930 931 /* If a card exists, unreset it! */ 932 if (CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) { 933 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, 934 &~CBBM_BRIDGECTRL_RESET, 2); 935 pause("cbbP4", hz * delay / 1000); 936 } 937 } 938 939 static int 940 cbb_cardbus_power_enable_socket(device_t brdev, device_t child) 941 { 942 struct cbb_softc *sc = device_get_softc(brdev); 943 int err; 944 945 if (!CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) 946 return (ENODEV); 947 948 err = cbb_do_power(brdev); 949 if (err) 950 return (err); 951 cbb_cardbus_reset(brdev); 952 return (0); 953 } 954 955 static void 956 cbb_cardbus_power_disable_socket(device_t brdev, device_t child) 957 { 958 cbb_power(brdev, CARD_OFF); 959 cbb_cardbus_reset(brdev); 960 } 961 962 /************************************************************************/ 963 /* CardBus Resource */ 964 /************************************************************************/ 965 966 static int 967 cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end) 968 { 969 int basereg; 970 int limitreg; 971 972 if ((win < 0) || (win > 1)) { 973 DEVPRINTF((brdev, 974 "cbb_cardbus_io_open: window out of range %d\n", win)); 975 return (EINVAL); 976 } 977 978 basereg = win * 8 + CBBR_IOBASE0; 979 limitreg = win * 8 + CBBR_IOLIMIT0; 980 981 pci_write_config(brdev, basereg, start, 4); 982 pci_write_config(brdev, limitreg, end, 4); 983 return (0); 984 } 985 986 static int 987 cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end) 988 { 989 int basereg; 990 int limitreg; 991 992 if ((win < 0) || (win > 1)) { 993 DEVPRINTF((brdev, 994 "cbb_cardbus_mem_open: window out of range %d\n", win)); 995 return (EINVAL); 996 } 997 998 basereg = win*8 + CBBR_MEMBASE0; 999 limitreg = win*8 + CBBR_MEMLIMIT0; 1000 1001 pci_write_config(brdev, basereg, start, 4); 1002 pci_write_config(brdev, limitreg, end, 4); 1003 return (0); 1004 } 1005 1006 #define START_NONE 0xffffffff 1007 #define END_NONE 0 1008 1009 static void 1010 cbb_cardbus_auto_open(struct cbb_softc *sc, int type) 1011 { 1012 uint32_t starts[2]; 1013 uint32_t ends[2]; 1014 struct cbb_reslist *rle; 1015 int align, i; 1016 uint32_t reg; 1017 1018 starts[0] = starts[1] = START_NONE; 1019 ends[0] = ends[1] = END_NONE; 1020 1021 if (type == SYS_RES_MEMORY) 1022 align = CBB_MEMALIGN; 1023 else if (type == SYS_RES_IOPORT) 1024 align = CBB_IOALIGN; 1025 else 1026 align = 1; 1027 1028 SLIST_FOREACH(rle, &sc->rl, link) { 1029 if (rle->type != type) 1030 continue; 1031 if (rle->res == NULL) 1032 continue; 1033 if (!(rman_get_flags(rle->res) & RF_ACTIVE)) 1034 continue; 1035 if (rman_get_flags(rle->res) & RF_PREFETCHABLE) 1036 i = 1; 1037 else 1038 i = 0; 1039 if (rman_get_start(rle->res) < starts[i]) 1040 starts[i] = rman_get_start(rle->res); 1041 if (rman_get_end(rle->res) > ends[i]) 1042 ends[i] = rman_get_end(rle->res); 1043 } 1044 for (i = 0; i < 2; i++) { 1045 if (starts[i] == START_NONE) 1046 continue; 1047 starts[i] &= ~(align - 1); 1048 ends[i] = ((ends[i] + align - 1) & ~(align - 1)) - 1; 1049 } 1050 if (starts[0] != START_NONE && starts[1] != START_NONE) { 1051 if (starts[0] < starts[1]) { 1052 if (ends[0] > starts[1]) { 1053 device_printf(sc->dev, "Overlapping ranges" 1054 " for prefetch and non-prefetch memory\n"); 1055 return; 1056 } 1057 } else { 1058 if (ends[1] > starts[0]) { 1059 device_printf(sc->dev, "Overlapping ranges" 1060 " for prefetch and non-prefetch memory\n"); 1061 return; 1062 } 1063 } 1064 } 1065 1066 if (type == SYS_RES_MEMORY) { 1067 cbb_cardbus_mem_open(sc->dev, 0, starts[0], ends[0]); 1068 cbb_cardbus_mem_open(sc->dev, 1, starts[1], ends[1]); 1069 reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2); 1070 reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0 | 1071 CBBM_BRIDGECTRL_PREFETCH_1); 1072 if (starts[1] != START_NONE) 1073 reg |= CBBM_BRIDGECTRL_PREFETCH_1; 1074 pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2); 1075 if (bootverbose) { 1076 device_printf(sc->dev, "Opening memory:\n"); 1077 if (starts[0] != START_NONE) 1078 device_printf(sc->dev, "Normal: %#x-%#x\n", 1079 starts[0], ends[0]); 1080 if (starts[1] != START_NONE) 1081 device_printf(sc->dev, "Prefetch: %#x-%#x\n", 1082 starts[1], ends[1]); 1083 } 1084 } else if (type == SYS_RES_IOPORT) { 1085 cbb_cardbus_io_open(sc->dev, 0, starts[0], ends[0]); 1086 cbb_cardbus_io_open(sc->dev, 1, starts[1], ends[1]); 1087 if (bootverbose && starts[0] != START_NONE) 1088 device_printf(sc->dev, "Opening I/O: %#x-%#x\n", 1089 starts[0], ends[0]); 1090 } 1091 } 1092 1093 static int 1094 cbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1095 int rid, struct resource *res) 1096 { 1097 int ret; 1098 1099 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1100 type, rid, res); 1101 if (ret != 0) 1102 return (ret); 1103 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1104 return (0); 1105 } 1106 1107 static int 1108 cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1109 int rid, struct resource *res) 1110 { 1111 int ret; 1112 1113 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1114 type, rid, res); 1115 if (ret != 0) 1116 return (ret); 1117 cbb_cardbus_auto_open(device_get_softc(brdev), type); 1118 return (0); 1119 } 1120 1121 static struct resource * 1122 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, 1123 int *rid, u_long start, u_long end, u_long count, u_int flags) 1124 { 1125 struct cbb_softc *sc = device_get_softc(brdev); 1126 int tmp; 1127 struct resource *res; 1128 u_long align; 1129 1130 switch (type) { 1131 case SYS_RES_IRQ: 1132 tmp = rman_get_start(sc->irq_res); 1133 if (start > tmp || end < tmp || count != 1) { 1134 device_printf(child, "requested interrupt %ld-%ld," 1135 "count = %ld not supported by cbb\n", 1136 start, end, count); 1137 return (NULL); 1138 } 1139 start = end = tmp; 1140 flags |= RF_SHAREABLE; 1141 break; 1142 case SYS_RES_IOPORT: 1143 if (start <= cbb_start_32_io) 1144 start = cbb_start_32_io; 1145 if (end < start) 1146 end = start; 1147 if (count > (1 << RF_ALIGNMENT(flags))) 1148 flags = (flags & ~RF_ALIGNMENT_MASK) | 1149 rman_make_alignment_flags(count); 1150 break; 1151 case SYS_RES_MEMORY: 1152 if (start <= cbb_start_mem) 1153 start = cbb_start_mem; 1154 if (end < start) 1155 end = start; 1156 if (count < CBB_MEMALIGN) 1157 align = CBB_MEMALIGN; 1158 else 1159 align = count; 1160 if (align > (1 << RF_ALIGNMENT(flags))) 1161 flags = (flags & ~RF_ALIGNMENT_MASK) | 1162 rman_make_alignment_flags(align); 1163 break; 1164 } 1165 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1166 start, end, count, flags & ~RF_ACTIVE); 1167 if (res == NULL) { 1168 printf("cbb alloc res fail\n"); 1169 return (NULL); 1170 } 1171 cbb_insert_res(sc, res, type, *rid); 1172 if (flags & RF_ACTIVE) 1173 if (bus_activate_resource(child, type, *rid, res) != 0) { 1174 bus_release_resource(child, type, *rid, res); 1175 return (NULL); 1176 } 1177 1178 return (res); 1179 } 1180 1181 static int 1182 cbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1183 int rid, struct resource *res) 1184 { 1185 struct cbb_softc *sc = device_get_softc(brdev); 1186 int error; 1187 1188 if (rman_get_flags(res) & RF_ACTIVE) { 1189 error = bus_deactivate_resource(child, type, rid, res); 1190 if (error != 0) 1191 return (error); 1192 } 1193 cbb_remove_res(sc, res); 1194 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1195 type, rid, res)); 1196 } 1197 1198 /************************************************************************/ 1199 /* PC Card Power Functions */ 1200 /************************************************************************/ 1201 1202 static int 1203 cbb_pcic_power_enable_socket(device_t brdev, device_t child) 1204 { 1205 struct cbb_softc *sc = device_get_softc(brdev); 1206 int err; 1207 1208 DPRINTF(("cbb_pcic_socket_enable:\n")); 1209 1210 /* power down/up the socket to reset */ 1211 err = cbb_do_power(brdev); 1212 if (err) 1213 return (err); 1214 exca_reset(&sc->exca[0], child); 1215 1216 return (0); 1217 } 1218 1219 static void 1220 cbb_pcic_power_disable_socket(device_t brdev, device_t child) 1221 { 1222 struct cbb_softc *sc = device_get_softc(brdev); 1223 1224 DPRINTF(("cbb_pcic_socket_disable\n")); 1225 1226 /* Turn off the card's interrupt and leave it in reset */ 1227 exca_putb(&sc->exca[0], EXCA_INTR, 0); 1228 pause("cbbP1", hz / 100); 1229 1230 /* power down the socket */ 1231 cbb_power(brdev, CARD_OFF); 1232 exca_putb(&sc->exca[0], EXCA_PWRCTL, 0); 1233 1234 /* wait 300ms until power fails (Tpf). */ 1235 pause("cbbP1", hz * 300 / 1000); 1236 1237 /* enable CSC interrupts */ 1238 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 1239 } 1240 1241 /************************************************************************/ 1242 /* POWER methods */ 1243 /************************************************************************/ 1244 1245 int 1246 cbb_power_enable_socket(device_t brdev, device_t child) 1247 { 1248 struct cbb_softc *sc = device_get_softc(brdev); 1249 1250 if (sc->flags & CBB_16BIT_CARD) 1251 return (cbb_pcic_power_enable_socket(brdev, child)); 1252 else 1253 return (cbb_cardbus_power_enable_socket(brdev, child)); 1254 } 1255 1256 void 1257 cbb_power_disable_socket(device_t brdev, device_t child) 1258 { 1259 struct cbb_softc *sc = device_get_softc(brdev); 1260 if (sc->flags & CBB_16BIT_CARD) 1261 cbb_pcic_power_disable_socket(brdev, child); 1262 else 1263 cbb_cardbus_power_disable_socket(brdev, child); 1264 } 1265 1266 static int 1267 cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1268 struct resource *res) 1269 { 1270 struct cbb_softc *sc = device_get_softc(brdev); 1271 return (exca_activate_resource(&sc->exca[0], child, type, rid, res)); 1272 } 1273 1274 static int 1275 cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1276 int rid, struct resource *res) 1277 { 1278 struct cbb_softc *sc = device_get_softc(brdev); 1279 return (exca_deactivate_resource(&sc->exca[0], child, type, rid, res)); 1280 } 1281 1282 static struct resource * 1283 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1284 u_long start, u_long end, u_long count, u_int flags) 1285 { 1286 struct resource *res = NULL; 1287 struct cbb_softc *sc = device_get_softc(brdev); 1288 int align; 1289 int tmp; 1290 1291 switch (type) { 1292 case SYS_RES_MEMORY: 1293 if (start < cbb_start_mem) 1294 start = cbb_start_mem; 1295 if (end < start) 1296 end = start; 1297 if (count < CBB_MEMALIGN) 1298 align = CBB_MEMALIGN; 1299 else 1300 align = count; 1301 if (align > (1 << RF_ALIGNMENT(flags))) 1302 flags = (flags & ~RF_ALIGNMENT_MASK) | 1303 rman_make_alignment_flags(align); 1304 break; 1305 case SYS_RES_IOPORT: 1306 if (start < cbb_start_16_io) 1307 start = cbb_start_16_io; 1308 if (end < start) 1309 end = start; 1310 break; 1311 case SYS_RES_IRQ: 1312 tmp = rman_get_start(sc->irq_res); 1313 if (start > tmp || end < tmp || count != 1) { 1314 device_printf(child, "requested interrupt %ld-%ld," 1315 "count = %ld not supported by cbb\n", 1316 start, end, count); 1317 return (NULL); 1318 } 1319 flags |= RF_SHAREABLE; 1320 start = end = rman_get_start(sc->irq_res); 1321 break; 1322 } 1323 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1324 start, end, count, flags & ~RF_ACTIVE); 1325 if (res == NULL) 1326 return (NULL); 1327 cbb_insert_res(sc, res, type, *rid); 1328 if (flags & RF_ACTIVE) { 1329 if (bus_activate_resource(child, type, *rid, res) != 0) { 1330 bus_release_resource(child, type, *rid, res); 1331 return (NULL); 1332 } 1333 } 1334 1335 return (res); 1336 } 1337 1338 static int 1339 cbb_pcic_release_resource(device_t brdev, device_t child, int type, 1340 int rid, struct resource *res) 1341 { 1342 struct cbb_softc *sc = device_get_softc(brdev); 1343 int error; 1344 1345 if (rman_get_flags(res) & RF_ACTIVE) { 1346 error = bus_deactivate_resource(child, type, rid, res); 1347 if (error != 0) 1348 return (error); 1349 } 1350 cbb_remove_res(sc, res); 1351 return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1352 type, rid, res)); 1353 } 1354 1355 /************************************************************************/ 1356 /* PC Card methods */ 1357 /************************************************************************/ 1358 1359 int 1360 cbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1361 uint32_t flags) 1362 { 1363 struct cbb_softc *sc = device_get_softc(brdev); 1364 struct resource *res; 1365 1366 if (type != SYS_RES_MEMORY) 1367 return (EINVAL); 1368 res = cbb_find_res(sc, type, rid); 1369 if (res == NULL) { 1370 device_printf(brdev, 1371 "set_res_flags: specified rid not found\n"); 1372 return (ENOENT); 1373 } 1374 return (exca_mem_set_flags(&sc->exca[0], res, flags)); 1375 } 1376 1377 int 1378 cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1379 uint32_t cardaddr, uint32_t *deltap) 1380 { 1381 struct cbb_softc *sc = device_get_softc(brdev); 1382 struct resource *res; 1383 1384 res = cbb_find_res(sc, SYS_RES_MEMORY, rid); 1385 if (res == NULL) { 1386 device_printf(brdev, 1387 "set_memory_offset: specified rid not found\n"); 1388 return (ENOENT); 1389 } 1390 return (exca_mem_set_offset(&sc->exca[0], res, cardaddr, deltap)); 1391 } 1392 1393 /************************************************************************/ 1394 /* BUS Methods */ 1395 /************************************************************************/ 1396 1397 1398 int 1399 cbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1400 struct resource *r) 1401 { 1402 struct cbb_softc *sc = device_get_softc(brdev); 1403 1404 if (sc->flags & CBB_16BIT_CARD) 1405 return (cbb_pcic_activate_resource(brdev, child, type, rid, r)); 1406 else 1407 return (cbb_cardbus_activate_resource(brdev, child, type, rid, 1408 r)); 1409 } 1410 1411 int 1412 cbb_deactivate_resource(device_t brdev, device_t child, int type, 1413 int rid, struct resource *r) 1414 { 1415 struct cbb_softc *sc = device_get_softc(brdev); 1416 1417 if (sc->flags & CBB_16BIT_CARD) 1418 return (cbb_pcic_deactivate_resource(brdev, child, type, 1419 rid, r)); 1420 else 1421 return (cbb_cardbus_deactivate_resource(brdev, child, type, 1422 rid, r)); 1423 } 1424 1425 struct resource * 1426 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1427 u_long start, u_long end, u_long count, u_int flags) 1428 { 1429 struct cbb_softc *sc = device_get_softc(brdev); 1430 1431 if (sc->flags & CBB_16BIT_CARD) 1432 return (cbb_pcic_alloc_resource(brdev, child, type, rid, 1433 start, end, count, flags)); 1434 else 1435 return (cbb_cardbus_alloc_resource(brdev, child, type, rid, 1436 start, end, count, flags)); 1437 } 1438 1439 int 1440 cbb_release_resource(device_t brdev, device_t child, int type, int rid, 1441 struct resource *r) 1442 { 1443 struct cbb_softc *sc = device_get_softc(brdev); 1444 1445 if (sc->flags & CBB_16BIT_CARD) 1446 return (cbb_pcic_release_resource(brdev, child, type, 1447 rid, r)); 1448 else 1449 return (cbb_cardbus_release_resource(brdev, child, type, 1450 rid, r)); 1451 } 1452 1453 int 1454 cbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 1455 { 1456 struct cbb_softc *sc = device_get_softc(brdev); 1457 1458 switch (which) { 1459 case PCIB_IVAR_BUS: 1460 *result = sc->secbus; 1461 return (0); 1462 } 1463 return (ENOENT); 1464 } 1465 1466 int 1467 cbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 1468 { 1469 struct cbb_softc *sc = device_get_softc(brdev); 1470 1471 switch (which) { 1472 case PCIB_IVAR_BUS: 1473 sc->secbus = value; 1474 return (0); 1475 } 1476 return (ENOENT); 1477 } 1478 1479 int 1480 cbb_suspend(device_t self) 1481 { 1482 int error = 0; 1483 struct cbb_softc *sc = device_get_softc(self); 1484 1485 error = bus_generic_suspend(self); 1486 if (error != 0) 1487 return (error); 1488 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 1489 sc->flags &= ~CBB_CARD_OK; /* Card is bogus now */ 1490 return (0); 1491 } 1492 1493 int 1494 cbb_resume(device_t self) 1495 { 1496 int error = 0; 1497 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1498 uint32_t tmp; 1499 1500 /* 1501 * Some BIOSes will not save the BARs for the pci chips, so we 1502 * must do it ourselves. If the BAR is reset to 0 for an I/O 1503 * device, it will read back as 0x1, so no explicit test for 1504 * memory devices are needed. 1505 * 1506 * Note: The PCI bus code should do this automatically for us on 1507 * suspend/resume, but until it does, we have to cope. 1508 */ 1509 pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); 1510 DEVPRINTF((self, "PCI Memory allocated: %08lx\n", 1511 rman_get_start(sc->base_res))); 1512 1513 sc->chipinit(sc); 1514 1515 /* reset interrupt -- Do we really need to do this? */ 1516 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 1517 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 1518 1519 /* CSC Interrupt: Card detect interrupt on */ 1520 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 1521 1522 /* Signal the thread to wakeup. */ 1523 mtx_lock(&sc->mtx); 1524 cv_signal(&sc->cv); 1525 mtx_unlock(&sc->mtx); 1526 1527 error = bus_generic_resume(self); 1528 1529 return (error); 1530 } 1531 1532 int 1533 cbb_child_present(device_t self) 1534 { 1535 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(self); 1536 uint32_t sockstate; 1537 1538 sockstate = cbb_get(sc, CBB_SOCKET_STATE); 1539 return (CBB_CARD_PRESENT(sockstate) && 1540 (sc->flags & CBB_CARD_OK) == CBB_CARD_OK); 1541 } 1542