1 /* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Driver for PCI to Cardbus Bridge chips 33 * 34 * References: 35 * TI Datasheets: 36 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 37 * Much of the 16-bit PC Card compatibility code stolen from dev/pcic/i82365.c 38 * XXX and should be cleaned up to share as much as possible. 39 * 40 * Written by Jonathan Chen <jon@freebsd.org> 41 * The author would like to acknowledge: 42 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 43 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 44 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 45 * * David Cross: Author of the initial ugly hack for a specific cardbus card 46 */ 47 48 #define CBB_DEBUG 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/kernel.h> 54 #include <sys/kthread.h> 55 #include <sys/lock.h> 56 #include <sys/malloc.h> 57 #include <sys/mutex.h> 58 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 64 #include <pci/pcireg.h> 65 #include <pci/pcivar.h> 66 #include <machine/clock.h> 67 68 #include <dev/pccard/pccardreg.h> 69 #include <dev/pccard/pccardvar.h> 70 #include <dev/pcic/i82365reg.h> 71 72 #include <dev/pccbb/pccbbreg.h> 73 #include <dev/pccbb/pccbbvar.h> 74 75 #include "power_if.h" 76 #include "card_if.h" 77 #include "pcib_if.h" 78 79 #if defined CBB_DEBUG 80 #define DPRINTF(x) printf x 81 #define DEVPRINTF(x) device_printf x 82 #else 83 #define DPRINTF(x) 84 #define DEVPRINTF(x) 85 #endif 86 87 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 88 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 89 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 90 pci_write_config(DEV, REG, ( \ 91 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 92 93 /* 94 * XXX all the pcic code really doesn't belong here and needs to be 95 * XXX migrated to its own file, shared with the 16-bit code 96 */ 97 #define PCIC_READ(SC,REG) \ 98 (((u_int8_t*)((SC)->sc_socketreg))[0x800+(REG)]) 99 #define PCIC_WRITE(SC,REG,val) \ 100 (((u_int8_t*)((SC)->sc_socketreg))[0x800+(REG)]) = (val) 101 #define PCIC_MASK(SC,REG,MASK) \ 102 PCIC_WRITE(SC,REG,PCIC_READ(SC,REG) MASK) 103 #define PCIC_MASK2(SC,REG,MASK,MASK2) \ 104 PCIC_WRITE(SC,REG,(PCIC_READ(SC,REG) MASK) MASK2) 105 106 struct pccbb_sclist { 107 struct pccbb_softc *sc; 108 STAILQ_ENTRY(pccbb_sclist) entries; 109 }; 110 111 static STAILQ_HEAD(, pccbb_sclist) softcs; 112 static int softcs_init = 0; 113 114 115 struct yenta_chipinfo { 116 u_int32_t yc_id; 117 const char *yc_name; 118 int yc_chiptype; 119 int yc_flags; 120 } yc_chipsets[] = { 121 /* Texas Instruments chips */ 122 {PCI_DEVICE_ID_PCIC_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X, 123 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 124 {PCI_DEVICE_ID_PCIC_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X, 125 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 126 127 {PCI_DEVICE_ID_PCIC_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX, 128 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 129 {PCI_DEVICE_ID_PCIC_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX, 130 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 131 {PCI_DEVICE_ID_PCIC_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX, 132 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 133 {PCI_DEVICE_ID_PCIC_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX, 134 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 135 {PCI_DEVICE_ID_PCIC_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI12XX, 136 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 137 {PCI_DEVICE_ID_PCIC_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI12XX, 138 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 139 {PCI_DEVICE_ID_PCIC_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI12XX, 140 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 141 {PCI_DEVICE_ID_PCIC_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX, 142 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 143 {PCI_DEVICE_ID_PCIC_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX, 144 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 145 {PCI_DEVICE_ID_PCIC_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI12XX, 146 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 147 {PCI_DEVICE_ID_PCIC_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX, 148 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 149 {PCI_DEVICE_ID_PCIC_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX, 150 PCCBB_PCIC_IO_RELOC | PCCBB_PCIC_MEM_32}, 151 152 /* Ricoh chips */ 153 {PCI_DEVICE_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", 154 CB_RF5C46X, PCCBB_PCIC_MEM_32}, 155 {PCI_DEVICE_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", 156 CB_RF5C46X, PCCBB_PCIC_MEM_32}, 157 {PCI_DEVICE_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", 158 CB_RF5C47X, PCCBB_PCIC_MEM_32}, 159 {PCI_DEVICE_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", 160 CB_RF5C47X, PCCBB_PCIC_MEM_32}, 161 {PCI_DEVICE_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", 162 CB_RF5C47X, PCCBB_PCIC_MEM_32}, 163 164 /* Toshiba products */ 165 {PCI_DEVICE_ID_TOSHIBA_TOPIC95, "ToPIC95 PCI-CardBus Bridge", 166 CB_TOPIC95, PCCBB_PCIC_MEM_32}, 167 {PCI_DEVICE_ID_TOSHIBA_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", 168 CB_TOPIC95B, PCCBB_PCIC_MEM_32}, 169 {PCI_DEVICE_ID_TOSHIBA_TOPIC97, "ToPIC97 PCI-CardBus Bridge", 170 CB_TOPIC97, PCCBB_PCIC_MEM_32}, 171 {PCI_DEVICE_ID_TOSHIBA_TOPIC100, "ToPIC100 PCI-CardBus Bridge", 172 CB_TOPIC97, PCCBB_PCIC_MEM_32}, 173 174 /* Cirrus Logic */ 175 {PCI_DEVICE_ID_PCIC_CLPD6832, "CLPD6832 PCI-CardBus Bridge", 176 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 177 {PCI_DEVICE_ID_PCIC_CLPD6833, "CLPD6833 PCI-CardBus Bridge", 178 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 179 180 /* 02Micro */ 181 {PCI_DEVICE_ID_PCIC_OZ6832, "O2Mirco OZ6832/6833 PCI-CardBus Bridge", 182 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 183 {PCI_DEVICE_ID_PCIC_OZ6860, "O2Mirco OZ6836/6860 PCI-CardBus Bridge", 184 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 185 {PCI_DEVICE_ID_PCIC_OZ6872, "O2Mirco OZ6812/6872 PCI-CardBus Bridge", 186 CB_CIRRUS, PCCBB_PCIC_MEM_32}, 187 188 /* sentinel */ 189 {0 /* null id */, "unknown", 190 CB_UNKNOWN, 0}, 191 }; 192 193 static int cb_chipset(u_int32_t pci_id, const char **namep, int *flagp); 194 static int pccbb_probe(device_t brdev); 195 static void pccbb_chipinit(struct pccbb_softc *sc); 196 static int pccbb_attach(device_t brdev); 197 static int pccbb_detach(device_t brdev); 198 static int pccbb_shutdown(device_t brdev); 199 static void pccbb_driver_added(device_t brdev, driver_t *driver); 200 static void pccbb_child_detached(device_t brdev, device_t child); 201 static int pccbb_card_reprobe(device_t brdev, device_t busdev); 202 static void pccbb_event_thread(void *arg); 203 static void pccbb_create_event_thread(struct pccbb_softc *sc); 204 static void pccbb_start_threads(void *arg); 205 static void pccbb_insert(struct pccbb_softc *sc); 206 static void pccbb_removal(struct pccbb_softc *sc); 207 static void pccbb_intr(void *arg); 208 static int pccbb_detect_voltage(device_t brdev); 209 static int pccbb_power(device_t brdev, int volts); 210 static void pccbb_cardbus_reset(device_t brdev); 211 static int pccbb_cardbus_power_enable_socket(device_t brdev, 212 device_t child); 213 static void pccbb_cardbus_power_disable_socket(device_t brdev, 214 device_t child); 215 static int pccbb_cardbus_io_open(device_t brdev, int win, u_int32_t start, 216 u_int32_t end); 217 static int pccbb_cardbus_mem_open(device_t brdev, int win, 218 u_int32_t start, u_int32_t end); 219 static void pccbb_cardbus_auto_open(struct pccbb_softc *sc, int type); 220 static int pccbb_cardbus_activate_resource(device_t brdev, device_t child, 221 int type, int rid, struct resource *res); 222 static int pccbb_cardbus_deactivate_resource(device_t brdev, 223 device_t child, int type, int rid, struct resource *res); 224 static struct resource *pccbb_cardbus_alloc_resource(device_t brdev, 225 device_t child, int type, int *rid, u_long start, 226 u_long end, u_long count, u_int flags); 227 static int pccbb_cardbus_release_resource(device_t brdev, device_t child, 228 int type, int rid, struct resource *res); 229 static int pccbb_pcic_power_enable_socket(device_t brdev, device_t child); 230 static void pccbb_pcic_power_disable_socket(device_t brdev, device_t child); 231 static void pccbb_pcic_wait_ready(struct pccbb_softc *sc); 232 static void pccbb_pcic_do_mem_map(struct pccbb_softc *sc, int win); 233 static int pccbb_pcic_mem_map(struct pccbb_softc *sc, int kind, 234 struct resource *res); 235 static void pccbb_pcic_mem_unmap(struct pccbb_softc *sc, int window); 236 static int pccbb_pcic_mem_findmap(struct pccbb_softc *sc, 237 struct resource *res); 238 static void pccbb_pcic_do_io_map(struct pccbb_softc *sc, int win); 239 static int pccbb_pcic_io_map(struct pccbb_softc *sc, int width, 240 struct resource *r); 241 static void pccbb_pcic_io_unmap(struct pccbb_softc *sc, int window); 242 static int pccbb_pcic_io_findmap(struct pccbb_softc *sc, 243 struct resource *res); 244 static int pccbb_pcic_activate_resource(device_t brdev, device_t child, 245 int type, int rid, struct resource *res); 246 static int pccbb_pcic_deactivate_resource(device_t brdev, device_t child, 247 int type, int rid, struct resource *res); 248 static struct resource *pccbb_pcic_alloc_resource(device_t brdev, 249 device_t child, int type, int *rid, u_long start, 250 u_long end, u_long count, u_int flags); 251 static int pccbb_pcic_release_resource(device_t brdev, device_t child, 252 int type, int rid, struct resource *res); 253 static int pccbb_pcic_set_res_flags(device_t brdev, device_t child, 254 int type, int rid, u_int32_t flags); 255 static int pccbb_pcic_set_memory_offset(device_t brdev, device_t child, 256 int rid, u_int32_t cardaddr, u_int32_t *deltap); 257 static int pccbb_power_enable_socket(device_t brdev, device_t child); 258 static void pccbb_power_disable_socket(device_t brdev, device_t child); 259 static int pccbb_activate_resource(device_t brdev, device_t child, 260 int type, int rid, struct resource *r); 261 static int pccbb_deactivate_resource(device_t brdev, device_t child, 262 int type, int rid, struct resource *r); 263 static struct resource *pccbb_alloc_resource(device_t brdev, device_t child, 264 int type, int *rid, u_long start, u_long end, u_long count, 265 u_int flags); 266 static int pccbb_release_resource(device_t brdev, device_t child, 267 int type, int rid, struct resource *r); 268 static int pccbb_read_ivar(device_t brdev, device_t child, int which, 269 uintptr_t *result); 270 static int pccbb_write_ivar(device_t brdev, device_t child, int which, 271 uintptr_t value); 272 static int pccbb_maxslots(device_t brdev); 273 static u_int32_t pccbb_read_config(device_t brdev, int b, int s, int f, 274 int reg, int width); 275 static void pccbb_write_config(device_t brdev, int b, int s, int f, 276 int reg, u_int32_t val, int width); 277 278 /************************************************************************/ 279 /* Probe/Attach */ 280 /************************************************************************/ 281 282 static int 283 cb_chipset(u_int32_t pci_id, const char **namep, int *flagp) 284 { 285 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 286 struct yenta_chipinfo *ycp, *ycend; 287 ycend = yc_chipsets + loopend; 288 289 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 290 if (ycp == ycend) { 291 /* not found */ 292 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 293 } 294 if (namep != NULL) { 295 *namep = ycp->yc_name; 296 } 297 if (flagp != NULL) { 298 *flagp = ycp->yc_flags; 299 } 300 return ycp->yc_chiptype; 301 } 302 303 static int 304 pccbb_probe(device_t brdev) 305 { 306 const char *name; 307 308 if (cb_chipset(pci_get_devid(brdev), &name, NULL) == CB_UNKNOWN) 309 return ENXIO; 310 device_set_desc(brdev, name); 311 return 0; 312 } 313 314 static void 315 pccbb_chipinit(struct pccbb_softc *sc) 316 { 317 /* Set CardBus latency timer */ 318 if (pci_read_config(sc->sc_dev, PCIR_SECLAT_1, 1) < 0x20) 319 pci_write_config(sc->sc_dev, PCIR_SECLAT_1, 0x20, 1); 320 321 /* Set PCI latency timer */ 322 if (pci_read_config(sc->sc_dev, PCIR_LATTIMER, 1) < 0x20) 323 pci_write_config(sc->sc_dev, PCIR_LATTIMER, 0x20, 1); 324 325 /* Enable memory access */ 326 PCI_MASK_CONFIG(sc->sc_dev, PCIR_COMMAND, 327 | PCIM_CMD_MEMEN 328 | PCIM_CMD_PORTEN 329 | PCIM_CMD_BUSMASTEREN, 2); 330 331 /* disable Legacy IO */ 332 switch (sc->sc_chipset) { 333 case CB_RF5C46X: 334 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL, 335 & ~(PCCBBM_BRIDGECTRL_RL_3E0_EN | 336 PCCBBM_BRIDGECTRL_RL_3E2_EN), 2); 337 break; 338 default: 339 pci_write_config(sc->sc_dev, PCCBBR_LEGACY, 0x0, 4); 340 break; 341 } 342 343 /* Use PCI interrupt for interrupt routing */ 344 PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL, 345 & ~(PCCBBM_BRIDGECTRL_MASTER_ABORT | 346 PCCBBM_BRIDGECTRL_INTR_IREQ_EN), 347 | PCCBBM_BRIDGECTRL_WRITE_POST_EN, 348 2); 349 350 /* XXX this should be a function table, ala OLDCARD. */ 351 switch (sc->sc_chipset) { 352 case CB_TI113X: 353 /* 354 * The TI 1030, TI 1130 and TI 1131 all require another bit 355 * be set to enable PCI routing of interrupts, and then 356 * a bit for each of the CSC and Function interrupts we 357 * want routed. 358 */ 359 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_CBCTRL, 360 | PCCBBM_CBCTRL_113X_PCI_INTR | 361 PCCBBM_CBCTRL_113X_PCI_CSC | PCCBBM_CBCTRL_113X_PCI_IRQ_EN, 362 1); 363 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_DEVCTRL, 364 & ~(PCCBBM_DEVCTRL_INT_SERIAL | 365 PCCBBM_DEVCTRL_INT_PCI), 1); 366 PCIC_WRITE(sc, PCIC_INTR, PCIC_INTR_ENABLE); 367 PCIC_WRITE(sc, PCIC_CSC_INTR, 0); 368 break; 369 case CB_TI12XX: 370 PCIC_WRITE(sc, PCIC_INTR, PCIC_INTR_ENABLE); 371 PCIC_WRITE(sc, PCIC_CSC_INTR, 0); 372 break; 373 case CB_TOPIC95B: 374 PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_TOPIC_SOCKETCTRL, 375 | PCCBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4); 376 PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_TOPIC_SLOTCTRL, 377 | PCCBBM_TOPIC_SLOTCTRL_SLOTON | 378 PCCBBM_TOPIC_SLOTCTRL_SLOTEN | 379 PCCBBM_TOPIC_SLOTCTRL_ID_LOCK | 380 PCCBBM_TOPIC_SLOTCTRL_CARDBUS, 381 & ~PCCBBM_TOPIC_SLOTCTRL_SWDETECT, 4); 382 break; 383 } 384 385 /* close all memory and io windows */ 386 pci_write_config(sc->sc_dev, PCCBBR_MEMBASE0, 0xffffffff, 4); 387 pci_write_config(sc->sc_dev, PCCBBR_MEMLIMIT0, 0, 4); 388 pci_write_config(sc->sc_dev, PCCBBR_MEMBASE1, 0xffffffff, 4); 389 pci_write_config(sc->sc_dev, PCCBBR_MEMLIMIT1, 0, 4); 390 pci_write_config(sc->sc_dev, PCCBBR_IOBASE0, 0xffffffff, 4); 391 pci_write_config(sc->sc_dev, PCCBBR_IOLIMIT0, 0, 4); 392 pci_write_config(sc->sc_dev, PCCBBR_IOBASE1, 0xffffffff, 4); 393 pci_write_config(sc->sc_dev, PCCBBR_IOLIMIT1, 0, 4); 394 } 395 396 static int 397 pccbb_attach(device_t brdev) 398 { 399 struct pccbb_softc *sc = (struct pccbb_softc *)device_get_softc(brdev); 400 int rid; 401 u_int32_t tmp; 402 403 if (!softcs_init) { 404 softcs_init = 1; 405 STAILQ_INIT(&softcs); 406 } 407 mtx_init(&sc->sc_mtx, device_get_nameunit(brdev), MTX_DEF); 408 sc->sc_chipset = cb_chipset(pci_get_devid(brdev), NULL, &sc->sc_flags); 409 sc->sc_dev = brdev; 410 sc->sc_cbdev = NULL; 411 sc->sc_pccarddev = NULL; 412 sc->sc_secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 413 sc->sc_subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 414 sc->memalloc = 0; 415 sc->ioalloc = 0; 416 SLIST_INIT(&sc->rl); 417 418 /* Ths PCI bus should have given me memory... right? */ 419 rid=PCCBBR_SOCKBASE; 420 sc->sc_base_res=bus_alloc_resource(brdev, SYS_RES_MEMORY, &rid, 421 0,~0,1, RF_ACTIVE); 422 if (!sc->sc_base_res) { 423 /* 424 * XXX EVILE HACK BAD THING! XXX 425 * The pci bus device should do this for us. 426 * Some BIOSes doesn't assign a memory space properly. 427 * So we try to manually put one in... 428 */ 429 u_int32_t sockbase; 430 431 sockbase = pci_read_config(brdev, rid, 4); 432 if (sockbase < 0x100000 || sockbase >= 0xfffffff0) { 433 pci_write_config(brdev, rid, 0xffffffff, 4); 434 sockbase = pci_read_config(brdev, rid, 4); 435 sockbase = (sockbase & 0xfffffff0) & 436 -(sockbase & 0xfffffff0); 437 sc->sc_base_res = bus_generic_alloc_resource( 438 device_get_parent(brdev), brdev, SYS_RES_MEMORY, 439 &rid, 0x10000000, ~0, sockbase, 440 RF_ACTIVE|rman_make_alignment_flags(sockbase)); 441 if (!sc->sc_base_res){ 442 device_printf(brdev, 443 "Could not grab register memory\n"); 444 mtx_destroy(&sc->sc_mtx); 445 return ENOMEM; 446 } 447 pci_write_config(brdev, PCCBBR_SOCKBASE, 448 rman_get_start(sc->sc_base_res), 4); 449 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n", 450 rman_get_start(sc->sc_base_res))); 451 } else { 452 device_printf(brdev, "Could not map register memory\n"); 453 mtx_destroy(&sc->sc_mtx); 454 return ENOMEM; 455 } 456 } 457 458 sc->sc_socketreg = 459 (struct pccbb_socketreg *)rman_get_virtual(sc->sc_base_res); 460 pccbb_chipinit(sc); 461 462 /* CSC Interrupt: Card detect interrupt on */ 463 sc->sc_socketreg->socket_mask |= PCCBB_SOCKET_MASK_CD; 464 465 /* reset interrupt */ 466 tmp = sc->sc_socketreg->socket_event; 467 sc->sc_socketreg->socket_event = tmp; 468 469 /* Map and establish the interrupt. */ 470 rid=0; 471 sc->sc_irq_res=bus_alloc_resource(brdev, SYS_RES_IRQ, &rid, 0, ~0, 1, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->sc_irq_res == NULL) { 474 printf("pccbb: Unable to map IRQ...\n"); 475 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 476 sc->sc_base_res); 477 mtx_destroy(&sc->sc_mtx); 478 return ENOMEM; 479 } 480 481 if (bus_setup_intr(brdev, sc->sc_irq_res, INTR_TYPE_BIO, pccbb_intr, sc, 482 &(sc->sc_intrhand))) { 483 device_printf(brdev, "couldn't establish interrupt"); 484 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->sc_irq_res); 485 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 486 sc->sc_base_res); 487 mtx_destroy(&sc->sc_mtx); 488 return ENOMEM; 489 } 490 491 /* attach children */ 492 sc->sc_cbdev = device_add_child(brdev, "cardbus", -1); 493 if (sc->sc_cbdev == NULL) 494 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 495 else if (device_probe_and_attach(sc->sc_cbdev) != 0) { 496 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 497 sc->sc_cbdev = NULL; 498 } 499 500 sc->sc_pccarddev = device_add_child(brdev, "pccard", -1); 501 if (sc->sc_pccarddev == NULL) 502 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 503 else if (device_probe_and_attach(sc->sc_pccarddev) != 0) { 504 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 505 sc->sc_pccarddev = NULL; 506 } 507 508 #ifndef KLD_MODULE 509 if (sc->sc_cbdev == NULL && sc->sc_pccarddev == NULL) { 510 device_printf(brdev, 511 "ERROR: Failed to attach cardbus/pccard bus!\n"); 512 bus_teardown_intr(brdev, sc->sc_irq_res, sc->sc_intrhand); 513 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->sc_irq_res); 514 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 515 sc->sc_base_res); 516 mtx_destroy(&sc->sc_mtx); 517 return ENOMEM; 518 } 519 #endif 520 521 { 522 struct pccbb_sclist *sclist; 523 sclist = malloc(sizeof(struct pccbb_sclist), M_DEVBUF, 524 M_WAITOK); 525 sclist->sc = sc; 526 STAILQ_INSERT_TAIL(&softcs, sclist, entries); 527 } 528 return 0; 529 } 530 531 static int 532 pccbb_detach(device_t brdev) 533 { 534 struct pccbb_softc *sc = device_get_softc(brdev); 535 int numdevs; 536 device_t *devlist; 537 int tmp; 538 int error; 539 540 device_get_children(brdev, &devlist, &numdevs); 541 542 error = 0; 543 for (tmp = 0; tmp < numdevs; tmp++) { 544 if (device_detach(devlist[tmp]) == 0) 545 device_delete_child(brdev, devlist[tmp]); 546 else 547 error++; 548 } 549 free(devlist, M_TEMP); 550 if (error > 0) 551 return ENXIO; 552 553 mtx_lock(&sc->sc_mtx); 554 bus_teardown_intr(brdev, sc->sc_irq_res, sc->sc_intrhand); 555 556 sc->sc_flags |= PCCBB_KTHREAD_DONE; 557 if (sc->sc_flags & PCCBB_KTHREAD_RUNNING) { 558 wakeup(sc); 559 mtx_unlock(&sc->sc_mtx); 560 DEVPRINTF((brdev, "waiting for kthread exit...")); 561 error = tsleep(sc, PWAIT, "pccbb-detach-wait", 60 * hz); 562 if (error) 563 DPRINTF(("timeout\n")); 564 else 565 DPRINTF(("done\n")); 566 } else 567 mtx_unlock(&sc->sc_mtx); 568 569 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->sc_irq_res); 570 bus_release_resource(brdev, SYS_RES_MEMORY, PCCBBR_SOCKBASE, 571 sc->sc_base_res); 572 mtx_destroy(&sc->sc_mtx); 573 return 0; 574 } 575 576 static int 577 pccbb_shutdown(device_t brdev) 578 { 579 struct pccbb_softc *sc = (struct pccbb_softc *)device_get_softc(brdev); 580 /* properly reset everything at shutdown */ 581 582 PCI_MASK_CONFIG(brdev, PCCBBR_BRIDGECTRL, |PCCBBM_BRIDGECTRL_RESET, 2); 583 PCIC_MASK(sc, PCIC_INTR, & ~PCIC_INTR_RESET); 584 585 sc->sc_socketreg->socket_mask = 0; 586 587 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 588 589 PCIC_WRITE(sc, PCIC_ADDRWIN_ENABLE, 0); 590 pci_write_config(brdev, PCCBBR_MEMBASE0, 0, 4); 591 pci_write_config(brdev, PCCBBR_MEMLIMIT0, 0, 4); 592 pci_write_config(brdev, PCCBBR_MEMBASE1, 0, 4); 593 pci_write_config(brdev, PCCBBR_MEMLIMIT1, 0, 4); 594 pci_write_config(brdev, PCCBBR_IOBASE0, 0, 4); 595 pci_write_config(brdev, PCCBBR_IOLIMIT0, 0, 4); 596 pci_write_config(brdev, PCCBBR_IOBASE1, 0, 4); 597 pci_write_config(brdev, PCCBBR_IOLIMIT1, 0, 4); 598 pci_write_config(brdev, PCIR_COMMAND, 0, 2); 599 return 0; 600 } 601 602 static void 603 pccbb_driver_added(device_t brdev, driver_t *driver) 604 { 605 struct pccbb_softc *sc = device_get_softc(brdev); 606 device_t *devlist; 607 int tmp; 608 int numdevs; 609 int wake; 610 u_int32_t sockstate; 611 612 DEVICE_IDENTIFY(driver, brdev); 613 device_get_children(brdev, &devlist, &numdevs); 614 wake = 0; 615 sockstate = sc->sc_socketreg->socket_state; 616 for (tmp = 0; tmp < numdevs; tmp++) { 617 if (device_get_state(devlist[tmp]) == DS_NOTPRESENT && 618 device_probe_and_attach(devlist[tmp]) == 0) { 619 if (devlist[tmp] == NULL) 620 /* NOTHING */; 621 else if (strcmp(driver->name, "cardbus") == 0) { 622 sc->sc_cbdev = devlist[tmp]; 623 if (((sockstate & PCCBB_SOCKET_STAT_CD) == 0) && 624 (sockstate & PCCBB_SOCKET_STAT_CB)) 625 wake++; 626 } else if (strcmp(driver->name, "pccard") == 0) { 627 sc->sc_pccarddev = devlist[tmp]; 628 if (((sockstate & PCCBB_SOCKET_STAT_CD) == 0) && 629 (sockstate & PCCBB_SOCKET_STAT_16BIT)) 630 wake++; 631 } else 632 device_printf(brdev, 633 "Unsupported child bus: %s\n", 634 driver->name); 635 } 636 } 637 free(devlist, M_TEMP); 638 639 if (wake > 0) { 640 if ((sc->sc_socketreg->socket_state & PCCBB_SOCKET_STAT_CD) == 641 0) { 642 mtx_lock(&sc->sc_mtx); 643 wakeup(sc); 644 mtx_unlock(&sc->sc_mtx); 645 } 646 } 647 } 648 649 static void 650 pccbb_child_detached(device_t brdev, device_t child) 651 { 652 struct pccbb_softc *sc = device_get_softc(brdev); 653 if (child == sc->sc_cbdev) 654 sc->sc_cbdev = NULL; 655 else if (child == sc->sc_pccarddev) 656 sc->sc_pccarddev = NULL; 657 else 658 device_printf(brdev, "Unknown child detached: %s %p/%p\n", 659 device_get_nameunit(child), sc->sc_cbdev, sc->sc_pccarddev); 660 } 661 662 static int 663 pccbb_card_reprobe(device_t brdev, device_t busdev) { 664 struct pccbb_softc *sc = device_get_softc(brdev); 665 int wake = 0; 666 u_int32_t sockstate; 667 668 sockstate = sc->sc_socketreg->socket_state; 669 670 if ((sockstate & PCCBB_SOCKET_STAT_CD) == 0) { 671 if (busdev == sc->sc_cbdev && 672 (sockstate & PCCBB_SOCKET_STAT_CB)) 673 wake++; 674 else if (busdev == sc->sc_pccarddev && 675 (sockstate & PCCBB_SOCKET_STAT_16BIT)) 676 wake++; 677 678 if (wake > 0) { 679 mtx_lock(&sc->sc_mtx); 680 wakeup(sc); 681 mtx_unlock(&sc->sc_mtx); 682 return 0; 683 } 684 return EBUSY; 685 } 686 return ENOENT; 687 } 688 689 /************************************************************************/ 690 /* Kthreads */ 691 /************************************************************************/ 692 693 static void 694 pccbb_event_thread(void *arg) 695 { 696 struct pccbb_softc *sc = arg; 697 u_int32_t status; 698 699 mtx_lock(&Giant); 700 for(;;) { 701 if (!(sc->sc_flags & PCCBB_KTHREAD_RUNNING)) 702 sc->sc_flags |= PCCBB_KTHREAD_RUNNING; 703 else { 704 tsleep (sc, PWAIT, "pccbbev", 0); 705 /* 706 * Delay 1 second, make sure the user is done with 707 * whatever he is doing. We tsleep on sc->sc_flags, 708 * which should never be woken up. 709 * 710 * XXX Note: This can cause problems on card 711 * removal. See OLDCARD's ISR for how you may 712 * have to deal with the debouncing problem. The 713 * crux of the issue is interrupts delivered to 714 * the card after eject are unstable. 715 */ 716 tsleep (&sc->sc_flags, PWAIT, "pccbbev", 1*hz); 717 } 718 mtx_lock(&sc->sc_mtx); 719 if (sc->sc_flags & PCCBB_KTHREAD_DONE) 720 break; 721 722 status = sc->sc_socketreg->socket_state; 723 if ((status & PCCBB_SOCKET_STAT_CD) == 0) { 724 pccbb_insert(sc); 725 } else { 726 pccbb_removal(sc); 727 } 728 mtx_unlock(&sc->sc_mtx); 729 } 730 mtx_unlock(&sc->sc_mtx); 731 sc->sc_flags &= ~PCCBB_KTHREAD_RUNNING; 732 wakeup(sc); 733 kthread_exit(0); 734 } 735 736 static void 737 pccbb_create_event_thread(struct pccbb_softc *sc) 738 { 739 if (kthread_create(pccbb_event_thread, sc, &sc->event_thread, 740 0, "%s%d", device_get_name(sc->sc_dev), 741 device_get_unit(sc->sc_dev))) { 742 device_printf (sc->sc_dev, "unable to create event thread.\n"); 743 panic ("pccbb_create_event_thread"); 744 } 745 } 746 747 static void 748 pccbb_start_threads(void *arg) 749 { 750 struct pccbb_sclist *sclist; 751 752 STAILQ_FOREACH(sclist, &softcs, entries) { 753 pccbb_create_event_thread(sclist->sc); 754 } 755 } 756 757 /************************************************************************/ 758 /* Insert/removal */ 759 /************************************************************************/ 760 761 static void 762 pccbb_insert(struct pccbb_softc *sc) 763 { 764 u_int32_t sockevent, sockstate; 765 int timeout = 30; 766 767 do { 768 sockevent = sc->sc_socketreg->socket_event; 769 sockstate = sc->sc_socketreg->socket_state; 770 } while (sockstate & PCCBB_SOCKET_STAT_CD && --timeout > 0); 771 772 if (timeout < 0) { 773 device_printf (sc->sc_dev, "insert timeout"); 774 return; 775 } 776 777 DEVPRINTF((sc->sc_dev, "card inserted: event=0x%08x, state=%08x\n", 778 sockevent, sockstate)); 779 780 if (sockstate & PCCBB_SOCKET_STAT_16BIT && sc->sc_pccarddev != NULL) { 781 sc->sc_flags |= PCCBB_16BIT_CARD; 782 if (CARD_ATTACH_CARD(sc->sc_pccarddev) != 0) 783 device_printf(sc->sc_dev, "card activation failed\n"); 784 } else if (sockstate & PCCBB_SOCKET_STAT_CB && sc->sc_cbdev != NULL) { 785 sc->sc_flags &= ~PCCBB_16BIT_CARD; 786 if (CARD_ATTACH_CARD(sc->sc_cbdev) != 0) 787 device_printf(sc->sc_dev, "card activation failed\n"); 788 } else { 789 device_printf (sc->sc_dev, "Unsupported card type detected\n"); 790 } 791 } 792 793 static void 794 pccbb_removal(struct pccbb_softc *sc) 795 { 796 struct pccbb_reslist *rle; 797 798 if (sc->sc_flags & PCCBB_16BIT_CARD && sc->sc_pccarddev != NULL) 799 CARD_DETACH_CARD(sc->sc_pccarddev, DETACH_FORCE); 800 else if ((!(sc->sc_flags & PCCBB_16BIT_CARD)) && sc->sc_cbdev != NULL) 801 CARD_DETACH_CARD(sc->sc_cbdev, DETACH_FORCE); 802 803 while ((rle = SLIST_FIRST(&sc->rl)) != NULL) { 804 device_printf(sc->sc_dev, "Danger Will Robinson: Resource " 805 "left allocated! This is a bug... " 806 "(rid=%x, type=%d, addr=%lx)\n", rle->rid, rle->type, 807 rman_get_start(rle->res)); 808 SLIST_REMOVE_HEAD(&sc->rl, link); 809 free(rle, M_DEVBUF); 810 } 811 } 812 813 /************************************************************************/ 814 /* Interrupt Handler */ 815 /************************************************************************/ 816 817 static void 818 pccbb_intr(void *arg) 819 { 820 struct pccbb_softc *sc = arg; 821 u_int32_t sockevent; 822 823 if (!(sockevent = sc->sc_socketreg->socket_event)) { 824 /* not for me. */ 825 return; 826 } 827 828 /* reset bit */ 829 sc->sc_socketreg->socket_event = sockevent | 0x01; 830 831 if (sockevent & PCCBB_SOCKET_EVENT_CD) { 832 mtx_lock(&sc->sc_mtx); 833 wakeup(sc); 834 mtx_unlock(&sc->sc_mtx); 835 } else { 836 if (sockevent & PCCBB_SOCKET_EVENT_CSTS) { 837 DPRINTF((" cstsevent occures, 0x%08x\n", 838 sc->sc_socketreg->socket_state)); 839 } 840 if (sockevent & PCCBB_SOCKET_EVENT_POWER) { 841 DPRINTF((" pwrevent occures, 0x%08x\n", 842 sc->sc_socketreg->socket_state)); 843 } 844 } 845 846 return; 847 } 848 849 /************************************************************************/ 850 /* Generic Power functions */ 851 /************************************************************************/ 852 853 static int 854 pccbb_detect_voltage(device_t brdev) 855 { 856 struct pccbb_softc *sc = device_get_softc(brdev); 857 u_int32_t psr; 858 int vol = CARD_UKN_CARD; 859 860 psr = sc->sc_socketreg->socket_state; 861 862 if (psr & PCCBB_SOCKET_STAT_5VCARD) { 863 vol |= CARD_5V_CARD; 864 } 865 if (psr & PCCBB_SOCKET_STAT_3VCARD) { 866 vol |= CARD_3V_CARD; 867 } 868 if (psr & PCCBB_SOCKET_STAT_XVCARD) { 869 vol |= CARD_XV_CARD; 870 } 871 if (psr & PCCBB_SOCKET_STAT_YVCARD) { 872 vol |= CARD_YV_CARD; 873 } 874 875 return vol; 876 } 877 878 static int 879 pccbb_power(device_t brdev, int volts) 880 { 881 u_int32_t status, sock_ctrl; 882 struct pccbb_softc *sc = device_get_softc(brdev); 883 884 DEVPRINTF((sc->sc_dev, "pccbb_power: %s and %s [%x]\n", 885 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 886 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 887 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 888 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 889 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 890 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 891 "VCC-UNKNOWN", 892 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 893 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V" : 894 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC" : 895 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 896 "VPP-UNKNOWN", 897 volts)); 898 899 status = sc->sc_socketreg->socket_state; 900 sock_ctrl = sc->sc_socketreg->socket_control; 901 902 switch (volts & CARD_VCCMASK) { 903 case CARD_VCC_UC: 904 break; 905 case CARD_VCC_5V: 906 if (PCCBB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 907 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VCCMASK; 908 sock_ctrl |= PCCBB_SOCKET_CTRL_VCC_5V; 909 } else { 910 device_printf(sc->sc_dev, 911 "BAD voltage request: no 5 V card\n"); 912 } 913 break; 914 case CARD_VCC_3V: 915 if (PCCBB_SOCKET_STAT_3VCARD & status) { 916 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VCCMASK; 917 sock_ctrl |= PCCBB_SOCKET_CTRL_VCC_3V; 918 } else { 919 device_printf(sc->sc_dev, 920 "BAD voltage request: no 3.3 V card\n"); 921 } 922 break; 923 case CARD_VCC_0V: 924 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VCCMASK; 925 break; 926 default: 927 return 0; /* power NEVER changed */ 928 break; 929 } 930 931 switch (volts & CARD_VPPMASK) { 932 case CARD_VPP_UC: 933 break; 934 case CARD_VPP_0V: 935 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VPPMASK; 936 break; 937 case CARD_VPP_VCC: 938 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VPPMASK; 939 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 940 break; 941 case CARD_VPP_12V: 942 sock_ctrl &= ~PCCBB_SOCKET_CTRL_VPPMASK; 943 sock_ctrl |= PCCBB_SOCKET_CTRL_VPP_12V; 944 break; 945 } 946 947 if (sc->sc_socketreg->socket_control == sock_ctrl) 948 return 1; /* no change necessary */ 949 950 sc->sc_socketreg->socket_control = sock_ctrl; 951 status = sc->sc_socketreg->socket_state; 952 953 /* 954 * XXX This busy wait is bogus. We should wait for a power 955 * interrupt and then whine if the status is bad. If we're 956 * worried about the card not coming up, then we should also 957 * schedule a timeout which we can cacel in the power interrupt. 958 */ 959 960 { 961 int timeout = 20; 962 u_int32_t sockevent; 963 do { 964 DELAY(20*1000); 965 sockevent = sc->sc_socketreg->socket_event; 966 } while (!(sockevent & PCCBB_SOCKET_EVENT_POWER) && 967 --timeout > 0); 968 /* reset event status */ 969 /* XXX should only reset EVENT_POWER */ 970 sc->sc_socketreg->socket_event = sockevent; 971 if (timeout < 0) { 972 printf ("VCC supply failed.\n"); 973 return 0; 974 } 975 } 976 /* XXX 977 * delay 400 ms: thgough the standard defines that the Vcc set-up time 978 * is 20 ms, some PC-Card bridge requires longer duration. 979 * XXX Note: We should check the stutus AFTER the delay to give time 980 * for things to stabilize. 981 */ 982 DELAY(400*1000); 983 984 if (status & PCCBB_SOCKET_STAT_BADVCC) { 985 device_printf(sc->sc_dev, 986 "bad Vcc request. ctrl=0x%x, status=0x%x\n", 987 sock_ctrl ,status); 988 printf("pccbb_power: %s and %s [%x]\n", 989 (volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" : 990 (volts & CARD_VCCMASK) == CARD_VCC_5V ? "CARD_VCC_5V" : 991 (volts & CARD_VCCMASK) == CARD_VCC_3V ? "CARD_VCC_3V" : 992 (volts & CARD_VCCMASK) == CARD_VCC_XV ? "CARD_VCC_XV" : 993 (volts & CARD_VCCMASK) == CARD_VCC_YV ? "CARD_VCC_YV" : 994 (volts & CARD_VCCMASK) == CARD_VCC_0V ? "CARD_VCC_0V" : 995 "VCC-UNKNOWN", 996 (volts & CARD_VPPMASK) == CARD_VPP_UC ? "CARD_VPP_UC" : 997 (volts & CARD_VPPMASK) == CARD_VPP_12V ? "CARD_VPP_12V": 998 (volts & CARD_VPPMASK) == CARD_VPP_VCC ? "CARD_VPP_VCC": 999 (volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" : 1000 "VPP-UNKNOWN", 1001 volts); 1002 return 0; 1003 } 1004 return 1; /* power changed correctly */ 1005 } 1006 1007 /************************************************************************/ 1008 /* Cardbus power functions */ 1009 /************************************************************************/ 1010 1011 static void 1012 pccbb_cardbus_reset(device_t brdev) 1013 { 1014 struct pccbb_softc *sc = device_get_softc(brdev); 1015 int delay_us; 1016 1017 delay_us = sc->sc_chipset == CB_RF5C47X ? 400*1000 : 20*1000; 1018 1019 PCI_MASK_CONFIG(brdev, PCCBBR_BRIDGECTRL, |PCCBBM_BRIDGECTRL_RESET, 2); 1020 1021 DELAY(delay_us); 1022 1023 /* If a card exists, unreset it! */ 1024 if ((sc->sc_socketreg->socket_state & PCCBB_SOCKET_STAT_CD) == 0) { 1025 PCI_MASK_CONFIG(brdev, PCCBBR_BRIDGECTRL, 1026 &~PCCBBM_BRIDGECTRL_RESET, 2); 1027 DELAY(delay_us); 1028 } 1029 } 1030 1031 static int 1032 pccbb_cardbus_power_enable_socket(device_t brdev, device_t child) 1033 { 1034 struct pccbb_softc *sc = device_get_softc(brdev); 1035 int voltage; 1036 1037 if ((sc->sc_socketreg->socket_state & PCCBB_SOCKET_STAT_CD) == 1038 PCCBB_SOCKET_STAT_CD) 1039 return ENODEV; 1040 1041 voltage = pccbb_detect_voltage(brdev); 1042 1043 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1044 if (voltage & CARD_5V_CARD) 1045 pccbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1046 else if (voltage & CARD_3V_CARD) 1047 pccbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1048 else { 1049 device_printf(brdev, "Unknown card voltage\n"); 1050 return ENXIO; 1051 } 1052 1053 pccbb_cardbus_reset(brdev); 1054 return 0; 1055 } 1056 1057 static void 1058 pccbb_cardbus_power_disable_socket(device_t brdev, device_t child) 1059 { 1060 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1061 pccbb_cardbus_reset(brdev); 1062 } 1063 1064 /************************************************************************/ 1065 /* Cardbus Resource */ 1066 /************************************************************************/ 1067 1068 static int 1069 pccbb_cardbus_io_open(device_t brdev, int win, u_int32_t start, u_int32_t end) 1070 { 1071 int basereg; 1072 int limitreg; 1073 1074 if ((win < 0) || (win > 1)) { 1075 DEVPRINTF((brdev, 1076 "pccbb_cardbus_io_open: window out of range %d\n", win)); 1077 return EINVAL; 1078 } 1079 1080 basereg = win*8 + PCCBBR_IOBASE0; 1081 limitreg = win*8 + PCCBBR_IOLIMIT0; 1082 1083 pci_write_config(brdev, basereg, start, 4); 1084 pci_write_config(brdev, limitreg, end, 4); 1085 return 0; 1086 } 1087 1088 static int 1089 pccbb_cardbus_mem_open(device_t brdev, int win, u_int32_t start, u_int32_t end) 1090 { 1091 int basereg; 1092 int limitreg; 1093 1094 if ((win < 0) || (win > 1)) { 1095 DEVPRINTF((brdev, 1096 "pccbb_cardbus_mem_open: window out of range %d\n", win)); 1097 return EINVAL; 1098 } 1099 1100 basereg = win*8 + PCCBBR_MEMBASE0; 1101 limitreg = win*8 + PCCBBR_MEMLIMIT0; 1102 1103 pci_write_config(brdev, basereg, start, 4); 1104 pci_write_config(brdev, limitreg, end, 4); 1105 return 0; 1106 } 1107 1108 static void 1109 pccbb_cardbus_auto_open(struct pccbb_softc *sc, int type) 1110 { 1111 u_int32_t starts[2]; 1112 u_int32_t ends[2]; 1113 struct pccbb_reslist *rle; 1114 int align; 1115 int prefetchable[2]; 1116 1117 starts[0] = starts[1] = 0xffffffff; 1118 ends[0] = ends[1] = 0; 1119 1120 if (type == SYS_RES_MEMORY) 1121 align = PCCBB_MEMALIGN; 1122 else if (type == SYS_RES_IOPORT) 1123 align = PCCBB_IOALIGN; 1124 else 1125 align = 1; 1126 1127 SLIST_FOREACH(rle, &sc->rl, link) { 1128 if (rle->type != type) 1129 ; 1130 else if (rle->res == NULL) { 1131 device_printf(sc->sc_dev, "WARNING: Resource not reserved? " 1132 "(type=%d, addr=%lx)\n", 1133 rle->type, rman_get_start(rle->res)); 1134 } else if (!(rman_get_flags(rle->res) & RF_ACTIVE)) { 1135 } else if (starts[0] == 0xffffffff) { 1136 starts[0] = rman_get_start(rle->res); 1137 ends[0] = rman_get_end(rle->res); 1138 prefetchable[0] = 1139 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1140 } else if (rman_get_end(rle->res) > ends[0] && 1141 rman_get_start(rle->res) - ends[0] < 1142 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1143 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1144 ends[0] = rman_get_end(rle->res); 1145 } else if (rman_get_start(rle->res) < starts[0] && 1146 starts[0] - rman_get_end(rle->res) < 1147 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[0] == 1148 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1149 starts[0] = rman_get_start(rle->res); 1150 } else if (starts[1] == 0xffffffff) { 1151 starts[1] = rman_get_start(rle->res); 1152 ends[1] = rman_get_end(rle->res); 1153 prefetchable[1] = 1154 rman_get_flags(rle->res) & RF_PREFETCHABLE; 1155 } else if (rman_get_end(rle->res) > ends[1] && 1156 rman_get_start(rle->res) - ends[1] < 1157 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1158 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1159 ends[1] = rman_get_end(rle->res); 1160 } else if (rman_get_start(rle->res) < starts[1] && 1161 starts[1] - rman_get_end(rle->res) < 1162 PCCBB_AUTO_OPEN_SMALLHOLE && prefetchable[1] == 1163 (rman_get_flags(rle->res) & RF_PREFETCHABLE)) { 1164 starts[1] = rman_get_start(rle->res); 1165 } else { 1166 u_int32_t diffs[2]; 1167 int win; 1168 1169 diffs[0] = diffs[1] = 0xffffffff; 1170 if (rman_get_start(rle->res) > ends[0]) 1171 diffs[0] = rman_get_start(rle->res) - ends[0]; 1172 else if (rman_get_end(rle->res) < starts[0]) 1173 diffs[0] = starts[0] - rman_get_end(rle->res); 1174 if (rman_get_start(rle->res) > ends[1]) 1175 diffs[1] = rman_get_start(rle->res) - ends[1]; 1176 else if (rman_get_end(rle->res) < starts[1]) 1177 diffs[1] = starts[1] - rman_get_end(rle->res); 1178 1179 win = (diffs[0] <= diffs[1])?0:1; 1180 if (rman_get_start(rle->res) > ends[win]) 1181 ends[win] = rman_get_end(rle->res); 1182 else if (rman_get_end(rle->res) < starts[win]) 1183 starts[win] = rman_get_start(rle->res); 1184 if (!(rman_get_flags(rle->res) & RF_PREFETCHABLE)) 1185 prefetchable[win] = 0; 1186 } 1187 1188 if (starts[0] != 0xffffffff) 1189 starts[0] -= starts[0] % align; 1190 if (starts[1] != 0xffffffff) 1191 starts[1] -= starts[1] % align; 1192 if (ends[0] % align != 0) 1193 ends[0] += align - ends[0]%align - 1; 1194 if (ends[1] % align != 0) 1195 ends[1] += align - ends[1]%align - 1; 1196 } 1197 1198 if (type == SYS_RES_MEMORY) { 1199 u_int32_t reg; 1200 1201 pccbb_cardbus_mem_open(sc->sc_dev, 0, starts[0], ends[0]); 1202 pccbb_cardbus_mem_open(sc->sc_dev, 1, starts[1], ends[1]); 1203 reg = pci_read_config(sc->sc_dev, PCCBBR_BRIDGECTRL, 2); 1204 reg &= ~(PCCBBM_BRIDGECTRL_PREFETCH_0| 1205 PCCBBM_BRIDGECTRL_PREFETCH_1); 1206 reg |= (prefetchable[0]?PCCBBM_BRIDGECTRL_PREFETCH_0:0)| 1207 (prefetchable[1]?PCCBBM_BRIDGECTRL_PREFETCH_1:0); 1208 pci_write_config(sc->sc_dev, PCCBBR_BRIDGECTRL, reg, 2); 1209 } else if (type == SYS_RES_IOPORT) { 1210 pccbb_cardbus_io_open(sc->sc_dev, 0, starts[0], ends[0]); 1211 pccbb_cardbus_io_open(sc->sc_dev, 1, starts[1], ends[1]); 1212 } 1213 } 1214 1215 static int 1216 pccbb_cardbus_activate_resource(device_t brdev, device_t child, int type, 1217 int rid, struct resource *res) 1218 { 1219 int ret; 1220 1221 ret = BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1222 type, rid, res); 1223 if (ret != 0) return ret; 1224 pccbb_cardbus_auto_open(device_get_softc(brdev), type); 1225 return 0; 1226 } 1227 1228 static int 1229 pccbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type, 1230 int rid, struct resource *res) 1231 { 1232 int ret; 1233 1234 ret = BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1235 type, rid, res); 1236 if (ret != 0) return ret; 1237 pccbb_cardbus_auto_open(device_get_softc(brdev), type); 1238 return 0; 1239 } 1240 1241 static struct resource * 1242 pccbb_cardbus_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1243 u_long start, u_long end, u_long count, u_int flags) 1244 { 1245 struct pccbb_softc *sc = device_get_softc(brdev); 1246 struct pccbb_reslist *rle; 1247 int tmp; 1248 struct resource *res; 1249 1250 switch (type) { 1251 case SYS_RES_IRQ: 1252 tmp = rman_get_start(sc->sc_irq_res); 1253 if (start > tmp || end < tmp || count != 1) { 1254 device_printf(child, "requested interrupt %ld-%ld," 1255 "count = %ld not supported by pccbb\n", 1256 start, end, count); 1257 return NULL; 1258 } 1259 start = end = tmp; 1260 break; 1261 case SYS_RES_IOPORT: 1262 if (start <= 0x1000) 1263 start = 0x1000; 1264 if (end < start) 1265 end = start; 1266 break; 1267 case SYS_RES_MEMORY: 1268 if (start <= 0x44000000) 1269 start = 0x44000000; 1270 if (end < start) 1271 end = start; 1272 break; 1273 } 1274 1275 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1276 start, end, count, flags & ~RF_ACTIVE); 1277 if (res == NULL) { 1278 printf("pccbb alloc res fail\n"); 1279 return NULL; 1280 } 1281 1282 /* 1283 * Need to record allocated resource so we can iterate through 1284 * it later. 1285 */ 1286 rle = malloc(sizeof(struct pccbb_reslist), M_DEVBUF, M_NOWAIT); 1287 if (!res) 1288 panic("pccbb_cardbus_alloc_resource: can't record entry!"); 1289 rle->res = res; 1290 rle->type = type; 1291 rle->rid = *rid; 1292 rle->cardaddr = 0; 1293 SLIST_INSERT_HEAD(&sc->rl, rle, link); 1294 1295 if (flags & RF_ACTIVE) 1296 if (bus_activate_resource(child, type, *rid, res) != 0) { 1297 bus_release_resource(child, type, *rid, res); 1298 return NULL; 1299 } 1300 1301 return res; 1302 } 1303 1304 static int 1305 pccbb_cardbus_release_resource(device_t brdev, device_t child, int type, 1306 int rid, struct resource *res) 1307 { 1308 struct pccbb_softc *sc = device_get_softc(brdev); 1309 struct pccbb_reslist *rle; 1310 1311 if (rman_get_flags(res) & RF_ACTIVE) { 1312 int error; 1313 error = bus_deactivate_resource(child, type, rid, res); 1314 if (error != 0) 1315 return error; 1316 } 1317 1318 SLIST_FOREACH(rle, &sc->rl, link) { 1319 if (rle->res == res) { 1320 SLIST_REMOVE(&sc->rl, rle, pccbb_reslist, link); 1321 free(rle, M_DEVBUF); 1322 break; 1323 } 1324 } 1325 1326 return BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1327 type, rid, res); 1328 } 1329 1330 /************************************************************************/ 1331 /* PC Card Power Functions */ 1332 /************************************************************************/ 1333 1334 static int 1335 pccbb_pcic_power_enable_socket(device_t brdev, device_t child) 1336 { 1337 struct pccbb_softc *sc = device_get_softc(brdev); 1338 1339 DPRINTF(("pccbb_pcic_socket_enable:\n")); 1340 1341 /* power down/up the socket to reset */ 1342 { 1343 int voltage = pccbb_detect_voltage(brdev); 1344 1345 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1346 if (voltage & CARD_5V_CARD) 1347 pccbb_power(brdev, CARD_VCC_5V | CARD_VPP_VCC); 1348 else if (voltage & CARD_3V_CARD) 1349 pccbb_power(brdev, CARD_VCC_3V | CARD_VPP_VCC); 1350 else { 1351 device_printf(brdev, "Unknown card voltage\n"); 1352 return ENXIO; 1353 } 1354 } 1355 1356 /* enable socket i/o */ 1357 PCIC_MASK(sc, PCIC_PWRCTL, | PCIC_PWRCTL_OE); 1358 1359 PCIC_WRITE(sc, PCIC_INTR, PCIC_INTR_ENABLE); 1360 /* hold reset for 30ms */ 1361 DELAY(30*1000); 1362 /* clear the reset flag */ 1363 PCIC_MASK(sc, PCIC_INTR, | PCIC_INTR_RESET); 1364 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1365 DELAY(20*1000); 1366 1367 pccbb_pcic_wait_ready(sc); 1368 1369 /* disable all address windows */ 1370 PCIC_WRITE(sc, PCIC_ADDRWIN_ENABLE, 0); 1371 1372 { 1373 int cardtype; 1374 CARD_GET_TYPE(child, &cardtype); 1375 PCIC_MASK(sc, PCIC_INTR, | ((cardtype == PCCARD_IFTYPE_IO) ? 1376 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM)); 1377 DEVPRINTF((sc->sc_dev, "card type is %s\n", 1378 (cardtype == PCCARD_IFTYPE_IO) ? "io" : "mem")); 1379 } 1380 1381 /* reinstall all the memory and io mappings */ 1382 { 1383 int win; 1384 1385 for (win = 0; win < PCIC_MEM_WINS; ++win) { 1386 if (sc->memalloc & (1 << win)) { 1387 pccbb_pcic_do_mem_map(sc, win); 1388 } 1389 } 1390 for (win = 0; win < PCIC_IO_WINS; ++win) { 1391 if (sc->ioalloc & (1 << win)) { 1392 pccbb_pcic_do_io_map(sc, win); 1393 } 1394 } 1395 } 1396 return 0; 1397 } 1398 1399 static void 1400 pccbb_pcic_power_disable_socket(device_t brdev, device_t child) 1401 { 1402 struct pccbb_softc *sc = device_get_softc(brdev); 1403 1404 DPRINTF(("pccbb_pcic_socket_disable\n")); 1405 1406 /* reset signal asserting... */ 1407 PCIC_MASK(sc, PCIC_INTR, & ~PCIC_INTR_RESET); 1408 DELAY(2*1000); 1409 1410 /* power down the socket */ 1411 pccbb_power(brdev, CARD_VCC_0V | CARD_VPP_0V); 1412 PCIC_MASK(sc, PCIC_PWRCTL, &~PCIC_PWRCTL_OE); 1413 1414 /* wait 300ms until power fails (Tpf). */ 1415 DELAY(300 * 1000); 1416 } 1417 1418 /************************************************************************/ 1419 /* PC Card Resource Functions */ 1420 /************************************************************************/ 1421 1422 static void 1423 pccbb_pcic_wait_ready(struct pccbb_softc *sc) 1424 { 1425 int i; 1426 DEVPRINTF((sc->sc_dev, "pccbb_pcic_wait_ready: status 0x%02x\n", 1427 PCIC_READ(sc, PCIC_IF_STATUS))); 1428 for (i = 0; i < 10000; i++) { 1429 if (PCIC_READ(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1430 return; 1431 } 1432 DELAY(500); 1433 } 1434 device_printf(sc->sc_dev, "ready never happened, status = %02x\n", 1435 PCIC_READ(sc, PCIC_IF_STATUS)); 1436 } 1437 1438 #define PCIC_MEMINFO(NUM) { \ 1439 PCIC_SYSMEM_ADDR ## NUM ## _START_LSB, \ 1440 PCIC_SYSMEM_ADDR ## NUM ## _START_MSB, \ 1441 PCIC_SYSMEM_ADDR ## NUM ## _STOP_LSB, \ 1442 PCIC_SYSMEM_ADDR ## NUM ## _STOP_MSB, \ 1443 PCIC_SYSMEM_ADDR ## NUM ## _WIN, \ 1444 PCIC_CARDMEM_ADDR ## NUM ## _LSB, \ 1445 PCIC_CARDMEM_ADDR ## NUM ## _MSB, \ 1446 PCIC_ADDRWIN_ENABLE_MEM ## NUM ##, \ 1447 } 1448 1449 static struct mem_map_index_st { 1450 int sysmem_start_lsb; 1451 int sysmem_start_msb; 1452 int sysmem_stop_lsb; 1453 int sysmem_stop_msb; 1454 int sysmem_win; 1455 int cardmem_lsb; 1456 int cardmem_msb; 1457 int memenable; 1458 } mem_map_index[] = { 1459 PCIC_MEMINFO(0), 1460 PCIC_MEMINFO(1), 1461 PCIC_MEMINFO(2), 1462 PCIC_MEMINFO(3), 1463 PCIC_MEMINFO(4), 1464 }; 1465 #undef PCIC_MEMINFO 1466 1467 static void 1468 pccbb_pcic_do_mem_map(struct pccbb_softc *sc, int win) 1469 { 1470 PCIC_WRITE(sc, mem_map_index[win].sysmem_start_lsb, 1471 (sc->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1472 PCIC_WRITE(sc, mem_map_index[win].sysmem_start_msb, 1473 ((sc->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1474 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 0x80); 1475 1476 PCIC_WRITE(sc, mem_map_index[win].sysmem_stop_lsb, 1477 ((sc->mem[win].addr + sc->mem[win].realsize - 1) >> 1478 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1479 PCIC_WRITE(sc, mem_map_index[win].sysmem_stop_msb, 1480 (((sc->mem[win].addr + sc->mem[win].realsize - 1) >> 1481 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1482 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 1483 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 1484 1485 PCIC_WRITE(sc, mem_map_index[win].sysmem_win, 1486 (sc->mem[win].addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff); 1487 1488 PCIC_WRITE(sc, mem_map_index[win].cardmem_lsb, 1489 (sc->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 1490 PCIC_WRITE(sc, mem_map_index[win].cardmem_msb, 1491 ((sc->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 1492 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 1493 ((sc->mem[win].kind == PCCARD_MEM_ATTR) ? 1494 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 1495 1496 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, | PCIC_ADDRWIN_ENABLE_MEMCS16 | 1497 mem_map_index[win].memenable); 1498 1499 DELAY(100); 1500 1501 #ifdef CBB_DEBUG 1502 { 1503 int r1, r2, r3, r4, r5, r6, r7; 1504 r1 = PCIC_READ(sc, mem_map_index[win].sysmem_start_msb); 1505 r2 = PCIC_READ(sc, mem_map_index[win].sysmem_start_lsb); 1506 r3 = PCIC_READ(sc, mem_map_index[win].sysmem_stop_msb); 1507 r4 = PCIC_READ(sc, mem_map_index[win].sysmem_stop_lsb); 1508 r5 = PCIC_READ(sc, mem_map_index[win].cardmem_msb); 1509 r6 = PCIC_READ(sc, mem_map_index[win].cardmem_lsb); 1510 r7 = PCIC_READ(sc, mem_map_index[win].sysmem_win); 1511 DPRINTF(("pccbb_pcic_do_mem_map window %d: %02x%02x %02x%02x " 1512 "%02x%02x %02x (%08x+%08x.%08x*%08lx)\n", 1513 win, r1, r2, r3, r4, r5, r6, r7, 1514 sc->mem[win].addr, sc->mem[win].size, sc->mem[win].realsize, 1515 sc->mem[win].offset)); 1516 } 1517 #endif 1518 } 1519 1520 static int 1521 pccbb_pcic_mem_map(struct pccbb_softc *sc, int kind, struct resource *res) 1522 { 1523 int win; 1524 struct pccbb_reslist *rle; 1525 bus_addr_t card_addr; 1526 1527 for (win = 0; win < PCIC_MEM_WINS; win++) { 1528 if ((sc->memalloc & (1 << win)) == 0) { 1529 sc->memalloc |= (1 << win); 1530 break; 1531 } 1532 } 1533 if (win >= PCIC_MEM_WINS) 1534 return (1); 1535 1536 SLIST_FOREACH(rle, &sc->rl, link) { 1537 if (rle->res == res) 1538 break; 1539 } 1540 if (!rle) { 1541 device_printf(sc->sc_dev, 1542 "pcic_map_mem: Memory resource not found\n"); 1543 return ENXIO; 1544 } 1545 card_addr = rle->cardaddr - rle->cardaddr % PCIC_MEM_PAGESIZE; 1546 sc->mem[win].memt = rman_get_bustag(res); 1547 sc->mem[win].memh = rman_get_bushandle(res); 1548 sc->mem[win].addr = rman_get_start(res); 1549 sc->mem[win].size = rman_get_end(res) - sc->mem[win].addr + 1; 1550 sc->mem[win].realsize = sc->mem[win].size + PCIC_MEM_PAGESIZE - 1; 1551 sc->mem[win].realsize = sc->mem[win].realsize - 1552 (sc->mem[win].realsize % PCIC_MEM_PAGESIZE); 1553 sc->mem[win].offset = ((long)card_addr) - 1554 ((long)(sc->mem[win].addr)); 1555 sc->mem[win].kind = kind; 1556 1557 DPRINTF(("pccbb_pcic_mem_map window %d bus %x+%x+%lx card addr %x\n", 1558 win, sc->mem[win].addr, sc->mem[win].size, 1559 sc->mem[win].offset, card_addr)); 1560 1561 pccbb_pcic_do_mem_map(sc, win); 1562 1563 return (0); 1564 } 1565 1566 static void 1567 pccbb_pcic_mem_unmap(struct pccbb_softc *sc, int window) 1568 { 1569 if (window >= PCIC_MEM_WINS) 1570 panic("pccbb_pcic_mem_unmap: window out of range"); 1571 1572 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, & ~mem_map_index[window].memenable); 1573 sc->memalloc &= ~(1 << window); 1574 } 1575 1576 static int 1577 pccbb_pcic_mem_findmap(struct pccbb_softc *sc, struct resource *res) 1578 { 1579 int win; 1580 1581 for (win = 0; win < PCIC_MEM_WINS; win++) { 1582 if (sc->mem[win].memt == rman_get_bustag(res) && 1583 sc->mem[win].addr == rman_get_start(res) && 1584 sc->mem[win].size == rman_get_size(res)) 1585 return win; 1586 } 1587 device_printf(sc->sc_dev, "Memory map not found!\n"); 1588 return -1; 1589 } 1590 1591 #define PCIC_IOINFO(NUM) { \ 1592 PCIC_IOADDR ## NUM ## _START_LSB, \ 1593 PCIC_IOADDR ## NUM ## _START_MSB, \ 1594 PCIC_IOADDR ## NUM ## _STOP_LSB, \ 1595 PCIC_IOADDR ## NUM ## _STOP_MSB, \ 1596 PCIC_ADDRWIN_ENABLE_IO ## NUM ##, \ 1597 PCIC_IOCTL_IO ## NUM ## _WAITSTATE \ 1598 | PCIC_IOCTL_IO ## NUM ## _ZEROWAIT \ 1599 | PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_MASK \ 1600 | PCIC_IOCTL_IO ## NUM ## _DATASIZE_MASK, \ 1601 { \ 1602 PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_CARD, \ 1603 PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_DATASIZE \ 1604 | PCIC_IOCTL_IO ## NUM ## _DATASIZE_8BIT, \ 1605 PCIC_IOCTL_IO ## NUM ## _IOCS16SRC_DATASIZE \ 1606 | PCIC_IOCTL_IO ## NUM ## _DATASIZE_16BIT, \ 1607 } \ 1608 } 1609 1610 static struct io_map_index_st { 1611 int start_lsb; 1612 int start_msb; 1613 int stop_lsb; 1614 int stop_msb; 1615 int ioenable; 1616 int ioctlmask; 1617 int ioctlbits[3]; /* indexed by PCCARD_WIDTH_* */ 1618 } io_map_index[] = { 1619 PCIC_IOINFO(0), 1620 PCIC_IOINFO(1), 1621 }; 1622 #undef PCIC_IOINFO 1623 1624 static void 1625 pccbb_pcic_do_io_map(struct pccbb_softc *sc, int win) 1626 { 1627 PCIC_WRITE(sc, io_map_index[win].start_lsb, sc->io[win].addr & 0xff); 1628 PCIC_WRITE(sc, io_map_index[win].start_msb, 1629 (sc->io[win].addr >> 8) & 0xff); 1630 1631 PCIC_WRITE(sc, io_map_index[win].stop_lsb, 1632 (sc->io[win].addr + sc->io[win].size - 1) & 0xff); 1633 PCIC_WRITE(sc, io_map_index[win].stop_msb, 1634 ((sc->io[win].addr + sc->io[win].size - 1) >> 8) & 0xff); 1635 1636 PCIC_MASK2(sc, PCIC_IOCTL, 1637 & ~io_map_index[win].ioctlmask, 1638 | io_map_index[win].ioctlbits[sc->io[win].width]); 1639 1640 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, | io_map_index[win].ioenable); 1641 #ifdef CBB_DEBUG 1642 { 1643 int r1, r2, r3, r4; 1644 r1 = PCIC_READ(sc, io_map_index[win].start_msb); 1645 r2 = PCIC_READ(sc, io_map_index[win].start_lsb); 1646 r3 = PCIC_READ(sc, io_map_index[win].stop_msb); 1647 r4 = PCIC_READ(sc, io_map_index[win].stop_lsb); 1648 DPRINTF(("pccbb_pcic_do_io_map window %d: %02x%02x %02x%02x " 1649 "(%08x+%08x)\n", win, r1, r2, r3, r4, 1650 sc->io[win].addr, sc->io[win].size)); 1651 } 1652 #endif 1653 } 1654 1655 static int 1656 pccbb_pcic_io_map(struct pccbb_softc *sc, int width, struct resource *r) 1657 { 1658 int win; 1659 #ifdef CBB_DEBUG 1660 static char *width_names[] = { "auto", "io8", "io16"}; 1661 #endif 1662 1663 for (win=0; win < PCIC_IO_WINS; win++) { 1664 if ((sc->ioalloc & (1 << win)) == 0) { 1665 sc->ioalloc |= (1 << win); 1666 break; 1667 } 1668 } 1669 if (win >= PCIC_IO_WINS) 1670 return (1); 1671 1672 sc->io[win].iot = rman_get_bustag(r); 1673 sc->io[win].ioh = rman_get_bushandle(r); 1674 sc->io[win].addr = rman_get_start(r); 1675 sc->io[win].size = rman_get_end(r) - sc->io[win].addr + 1; 1676 sc->io[win].flags = 0; 1677 sc->io[win].width = width; 1678 1679 DPRINTF(("pccbb_pcic_io_map window %d %s port %x+%x\n", 1680 win, width_names[width], sc->io[win].addr, 1681 sc->io[win].size)); 1682 1683 pccbb_pcic_do_io_map(sc, win); 1684 1685 return (0); 1686 } 1687 1688 static void 1689 pccbb_pcic_io_unmap(struct pccbb_softc *sc, int window) 1690 { 1691 if (window >= PCIC_IO_WINS) 1692 panic("pccbb_pcic_io_unmap: window out of range"); 1693 1694 PCIC_MASK(sc, PCIC_ADDRWIN_ENABLE, & ~io_map_index[window].ioenable); 1695 1696 sc->ioalloc &= ~(1 << window); 1697 1698 sc->io[window].iot = 0; 1699 sc->io[window].ioh = 0; 1700 sc->io[window].addr = 0; 1701 sc->io[window].size = 0; 1702 sc->io[window].flags = 0; 1703 sc->io[window].width = 0; 1704 } 1705 1706 static int 1707 pccbb_pcic_io_findmap(struct pccbb_softc *sc, struct resource *res) 1708 { 1709 int win; 1710 1711 for (win = 0; win < PCIC_IO_WINS; win++) { 1712 if (sc->io[win].iot == rman_get_bustag(res) && 1713 sc->io[win].addr == rman_get_start(res) && 1714 sc->io[win].size == rman_get_size(res)) 1715 return win; 1716 } 1717 device_printf(sc->sc_dev, "IO map not found!\n"); 1718 return -1; 1719 } 1720 1721 static int 1722 pccbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid, 1723 struct resource *res) 1724 { 1725 int err; 1726 struct pccbb_softc *sc = device_get_softc(brdev); 1727 if (!(rman_get_flags(res) & RF_ACTIVE)) { /* not already activated */ 1728 switch (type) { 1729 case SYS_RES_IOPORT: 1730 err = pccbb_pcic_io_map(sc, 0, res); 1731 break; 1732 case SYS_RES_MEMORY: 1733 err = pccbb_pcic_mem_map(sc, 0, res); 1734 break; 1735 default: 1736 err = 0; 1737 break; 1738 } 1739 if (err) 1740 return err; 1741 1742 } 1743 return BUS_ACTIVATE_RESOURCE(device_get_parent(brdev), child, 1744 type, rid, res); 1745 } 1746 1747 static int 1748 pccbb_pcic_deactivate_resource(device_t brdev, device_t child, int type, 1749 int rid, struct resource *res) 1750 { 1751 struct pccbb_softc *sc = device_get_softc(brdev); 1752 int win; 1753 1754 if (rman_get_flags(res) & RF_ACTIVE) { /* if activated */ 1755 switch (type) { 1756 case SYS_RES_IOPORT: 1757 win = pccbb_pcic_io_findmap(sc, res); 1758 if (win >= 0) 1759 pccbb_pcic_io_unmap(sc, win); 1760 else 1761 return ENOENT; 1762 break; 1763 case SYS_RES_MEMORY: 1764 win = pccbb_pcic_mem_findmap(sc, res); 1765 if (win >= 0) 1766 pccbb_pcic_mem_unmap(sc, win); 1767 else 1768 return ENOENT; 1769 break; 1770 } 1771 } 1772 return BUS_DEACTIVATE_RESOURCE(device_get_parent(brdev), child, 1773 type, rid, res); 1774 } 1775 1776 static struct resource * 1777 pccbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid, 1778 u_long start, u_long end, u_long count, u_int flags) 1779 { 1780 struct resource *res = NULL; 1781 struct pccbb_softc *sc = device_get_softc(brdev); 1782 struct pccbb_reslist *rle; 1783 int tmp; 1784 1785 if ((sc->sc_flags & PCCBB_PCIC_MEM_32) == 0) { 1786 /* XXX: how do we do this? */ 1787 panic("PCCBB bridge cannot handle non MEM_32 bridges\n"); 1788 } 1789 1790 switch (type) { 1791 case SYS_RES_MEMORY: 1792 if (start < 0x10000000) 1793 start = 0x10000000; /* XXX tweakable? */ 1794 if (end < start) 1795 end = start; 1796 flags = (flags & ~RF_ALIGNMENT_MASK) | 1797 rman_make_alignment_flags(PCCBB_MEMALIGN); 1798 break; 1799 case SYS_RES_IOPORT: 1800 if (start < 0x100) 1801 start = 0x100; /* XXX tweakable? */ 1802 if (end < start) 1803 end = start; 1804 break; 1805 case SYS_RES_IRQ: 1806 tmp = rman_get_start(sc->sc_irq_res); 1807 if (start > tmp || end < tmp || count != 1) { 1808 device_printf(child, "requested interrupt %ld-%ld," 1809 "count = %ld not supported by pccbb\n", 1810 start, end, count); 1811 return NULL; 1812 } 1813 flags |= RF_SHAREABLE; 1814 start = end = rman_get_start(sc->sc_irq_res); 1815 break; 1816 } 1817 res = BUS_ALLOC_RESOURCE(device_get_parent(brdev), child, type, rid, 1818 start, end, count, flags & ~RF_ACTIVE); 1819 if (res == NULL) 1820 return NULL; 1821 1822 rle = malloc(sizeof(struct pccbb_reslist), M_DEVBUF, M_NOWAIT); 1823 if (!rle) 1824 panic("pccbb_pcic_alloc_resource: can't record entry!"); 1825 rle->res = res; 1826 rle->type = type; 1827 rle->rid = *rid; 1828 rle->cardaddr = 0; 1829 SLIST_INSERT_HEAD(&sc->rl, rle, link); 1830 1831 if (flags & RF_ACTIVE) { 1832 if (bus_activate_resource(child, type, *rid, res) != 0) { 1833 bus_release_resource(child, type, *rid, res); 1834 return NULL; 1835 } 1836 } 1837 1838 return res; 1839 } 1840 1841 static int 1842 pccbb_pcic_release_resource(device_t brdev, device_t child, int type, 1843 int rid, struct resource *res) 1844 { 1845 struct pccbb_softc *sc = device_get_softc(brdev); 1846 struct pccbb_reslist *rle; 1847 1848 if (rman_get_flags(res) & RF_ACTIVE) { 1849 int error; 1850 error = bus_deactivate_resource(child, type, rid, res); 1851 if (error != 0) 1852 return error; 1853 } 1854 1855 SLIST_FOREACH(rle, &sc->rl, link) { 1856 if (rle->res == res) { 1857 SLIST_REMOVE(&sc->rl, rle, pccbb_reslist, link); 1858 free(rle, M_DEVBUF); 1859 break; 1860 } 1861 } 1862 1863 return BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, 1864 type, rid, res); 1865 } 1866 1867 /************************************************************************/ 1868 /* PC Card methods */ 1869 /************************************************************************/ 1870 1871 static int 1872 pccbb_pcic_set_res_flags(device_t brdev, device_t child, int type, int rid, 1873 u_int32_t flags) 1874 { 1875 struct pccbb_softc *sc = device_get_softc(brdev); 1876 struct resource *res; 1877 struct pccbb_reslist *rle; 1878 int win; 1879 1880 res = NULL; 1881 if (type != SYS_RES_MEMORY) 1882 return (EINVAL); 1883 SLIST_FOREACH(rle, &sc->rl, link) { 1884 if (SYS_RES_MEMORY == rle->type && rid == rle->rid && 1885 child == rle->res->r_dev) { 1886 res = rle->res; 1887 break; 1888 } 1889 } 1890 1891 if (res == NULL) { 1892 device_printf(brdev, 1893 "set_res_flags: specified rid not found\n"); 1894 return ENOENT; 1895 } 1896 win = pccbb_pcic_mem_findmap(sc, res); 1897 if (win < 0) { 1898 device_printf(brdev, 1899 "set_res_flags: specified resource not active\n"); 1900 return ENOENT; 1901 } 1902 1903 sc->mem[win].kind = flags; 1904 pccbb_pcic_do_mem_map(sc, win); 1905 return 0; 1906 } 1907 1908 static int 1909 pccbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid, 1910 u_int32_t cardaddr, u_int32_t *deltap) 1911 { 1912 struct pccbb_softc *sc = device_get_softc(brdev); 1913 int win; 1914 struct pccbb_reslist *rle; 1915 struct resource *res; 1916 u_int32_t delta; 1917 1918 win = -1; 1919 1920 res = NULL; 1921 SLIST_FOREACH(rle, &sc->rl, link) { 1922 if (SYS_RES_MEMORY == rle->type && rid == rle->rid && 1923 child == rle->res->r_dev) { 1924 res = rle->res; 1925 rle->cardaddr = cardaddr; 1926 break; 1927 } 1928 } 1929 1930 if (res == NULL) { 1931 device_printf(brdev, 1932 "set_memory_offset: specified rid not found\n"); 1933 return ENOENT; 1934 } 1935 win = pccbb_pcic_mem_findmap(sc, res); 1936 if (win < 0) { 1937 device_printf(brdev, 1938 "set_memory_offset: specified resource not active\n"); 1939 return ENOENT; 1940 } 1941 1942 delta = cardaddr % PCIC_MEM_PAGESIZE; 1943 if (deltap) 1944 *deltap = delta; 1945 cardaddr -= delta; 1946 sc->mem[win].realsize = sc->mem[win].size + delta + 1947 PCIC_MEM_PAGESIZE - 1; 1948 sc->mem[win].realsize = sc->mem[win].realsize - 1949 (sc->mem[win].realsize % PCIC_MEM_PAGESIZE); 1950 sc->mem[win].offset = cardaddr - sc->mem[win].addr; 1951 pccbb_pcic_do_mem_map(sc, win); 1952 1953 return 0; 1954 } 1955 1956 /************************************************************************/ 1957 /* POWER methods */ 1958 /************************************************************************/ 1959 1960 static int 1961 pccbb_power_enable_socket(device_t brdev, device_t child) 1962 { 1963 struct pccbb_softc *sc = device_get_softc(brdev); 1964 1965 if (sc->sc_flags & PCCBB_16BIT_CARD) 1966 return pccbb_pcic_power_enable_socket(brdev, child); 1967 else 1968 return pccbb_cardbus_power_enable_socket(brdev, child); 1969 } 1970 1971 static void 1972 pccbb_power_disable_socket(device_t brdev, device_t child) 1973 { 1974 struct pccbb_softc *sc = device_get_softc(brdev); 1975 if (sc->sc_flags & PCCBB_16BIT_CARD) 1976 pccbb_pcic_power_disable_socket(brdev, child); 1977 else 1978 pccbb_cardbus_power_disable_socket(brdev, child); 1979 } 1980 /************************************************************************/ 1981 /* BUS Methods */ 1982 /************************************************************************/ 1983 1984 1985 static int 1986 pccbb_activate_resource(device_t brdev, device_t child, int type, int rid, 1987 struct resource *r) 1988 { 1989 struct pccbb_softc *sc = device_get_softc(brdev); 1990 1991 if (sc->sc_flags & PCCBB_16BIT_CARD) 1992 return pccbb_pcic_activate_resource(brdev, child, type, rid, r); 1993 else 1994 return pccbb_cardbus_activate_resource(brdev, child, type, rid, 1995 r); 1996 } 1997 1998 static int 1999 pccbb_deactivate_resource(device_t brdev, device_t child, int type, 2000 int rid, struct resource *r) 2001 { 2002 struct pccbb_softc *sc = device_get_softc(brdev); 2003 2004 if (sc->sc_flags & PCCBB_16BIT_CARD) 2005 return pccbb_pcic_deactivate_resource(brdev, child, type, 2006 rid, r); 2007 else 2008 return pccbb_cardbus_deactivate_resource(brdev, child, type, 2009 rid, r); 2010 } 2011 2012 static struct resource * 2013 pccbb_alloc_resource(device_t brdev, device_t child, int type, int *rid, 2014 u_long start, u_long end, u_long count, u_int flags) 2015 { 2016 struct pccbb_softc *sc = device_get_softc(brdev); 2017 2018 if (sc->sc_flags & PCCBB_16BIT_CARD) 2019 return pccbb_pcic_alloc_resource(brdev, child, type, rid, 2020 start, end, count, flags); 2021 else 2022 return pccbb_cardbus_alloc_resource(brdev, child, type, rid, 2023 start, end, count, flags); 2024 } 2025 2026 static int 2027 pccbb_release_resource(device_t brdev, device_t child, int type, int rid, 2028 struct resource *r) 2029 { 2030 struct pccbb_softc *sc = device_get_softc(brdev); 2031 2032 if (sc->sc_flags & PCCBB_16BIT_CARD) 2033 return pccbb_pcic_release_resource(brdev, child, type, 2034 rid, r); 2035 else 2036 return pccbb_cardbus_release_resource(brdev, child, type, 2037 rid, r); 2038 } 2039 2040 static int 2041 pccbb_read_ivar(device_t brdev, device_t child, int which, uintptr_t *result) 2042 { 2043 struct pccbb_softc *sc = device_get_softc(brdev); 2044 2045 switch (which) { 2046 case PCIB_IVAR_BUS: 2047 *result = sc->sc_secbus; 2048 return(0); 2049 } 2050 return(ENOENT); 2051 } 2052 2053 static int 2054 pccbb_write_ivar(device_t brdev, device_t child, int which, uintptr_t value) 2055 { 2056 struct pccbb_softc *sc = device_get_softc(brdev); 2057 2058 switch (which) { 2059 case PCIB_IVAR_BUS: 2060 sc->sc_secbus = value; 2061 break; 2062 } 2063 return(ENOENT); 2064 } 2065 2066 /************************************************************************/ 2067 /* PCI compat methods */ 2068 /************************************************************************/ 2069 2070 static int 2071 pccbb_maxslots(device_t brdev) 2072 { 2073 return 0; 2074 } 2075 2076 static u_int32_t 2077 pccbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 2078 { 2079 /* 2080 * Pass through to the next ppb up the chain (i.e. our grandparent). 2081 */ 2082 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 2083 b, s, f, reg, width); 2084 } 2085 2086 static void 2087 pccbb_write_config(device_t brdev, int b, int s, int f, int reg, u_int32_t val, 2088 int width) 2089 { 2090 /* 2091 * Pass through to the next ppb up the chain (i.e. our grandparent). 2092 */ 2093 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 2094 b, s, f, reg, val, width); 2095 } 2096 2097 static device_method_t pccbb_methods[] = { 2098 /* Device interface */ 2099 DEVMETHOD(device_probe, pccbb_probe), 2100 DEVMETHOD(device_attach, pccbb_attach), 2101 DEVMETHOD(device_detach, pccbb_detach), 2102 DEVMETHOD(device_shutdown, pccbb_shutdown), 2103 DEVMETHOD(device_suspend, bus_generic_suspend), 2104 DEVMETHOD(device_resume, bus_generic_resume), 2105 2106 /* bus methods */ 2107 DEVMETHOD(bus_print_child, bus_generic_print_child), 2108 DEVMETHOD(bus_read_ivar, pccbb_read_ivar), 2109 DEVMETHOD(bus_write_ivar, pccbb_write_ivar), 2110 DEVMETHOD(bus_alloc_resource, pccbb_alloc_resource), 2111 DEVMETHOD(bus_release_resource, pccbb_release_resource), 2112 DEVMETHOD(bus_activate_resource, pccbb_activate_resource), 2113 DEVMETHOD(bus_deactivate_resource, pccbb_deactivate_resource), 2114 DEVMETHOD(bus_driver_added, pccbb_driver_added), 2115 DEVMETHOD(bus_child_detached, pccbb_child_detached), 2116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2118 2119 /* 16-bit card interface */ 2120 DEVMETHOD(card_set_res_flags, pccbb_pcic_set_res_flags), 2121 DEVMETHOD(card_set_memory_offset, pccbb_pcic_set_memory_offset), 2122 DEVMETHOD(card_reprobe_card, pccbb_card_reprobe), 2123 2124 /* power interface */ 2125 DEVMETHOD(power_enable_socket, pccbb_power_enable_socket), 2126 DEVMETHOD(power_disable_socket, pccbb_power_disable_socket), 2127 2128 /* pcib compatibility interface */ 2129 DEVMETHOD(pcib_maxslots, pccbb_maxslots), 2130 DEVMETHOD(pcib_read_config, pccbb_read_config), 2131 DEVMETHOD(pcib_write_config, pccbb_write_config), 2132 {0,0} 2133 }; 2134 2135 static driver_t pccbb_driver = { 2136 "pccbb", 2137 pccbb_methods, 2138 sizeof(struct pccbb_softc) 2139 }; 2140 2141 static devclass_t pccbb_devclass; 2142 2143 DRIVER_MODULE(pccbb, pci, pccbb_driver, pccbb_devclass, 0, 0); 2144 2145 SYSINIT(pccbb, SI_SUB_KTHREAD_IDLE, SI_ORDER_ANY, pccbb_start_threads, 0); 2146