1 /*- 2 * Copyright (c) 2018 Stormshield 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Implementation of Primary to Sideband bridge (P2SB), the documentation is available here : 29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c620-series-chipset-datasheet.pdf 30 * section 36.9 P2SB Bridge. 31 * This device exposes a 16MB memory block, this block is composed of 256 64KB blocks called ports. 32 * The indexes of this array (target port ID) can be found on the Table 36-10 of the documentation. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/module.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mutex.h> 43 #include <sys/bus.h> 44 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <machine/resource.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 52 #include "p2sb.h" 53 54 #define PCI_PRODUCT_LEWISBURG_P2SB 0xa1a08086 55 56 #define P2SB_PORT2ADDRESS_SHIFT 16 57 #define P2SB_PORT_ADDRESS(port) ((uint32_t)port << P2SB_PORT2ADDRESS_SHIFT) 58 59 static const uint8_t lbg_communities[] = { 60 0xAF, 0xAE, 0xAD, 0xAC, 0xAB, 0x11 61 }; 62 63 /* The softc holds our per-instance data. */ 64 struct p2sb_softc { 65 device_t dev; 66 int rid; 67 struct resource *res; 68 struct intel_community *communities; 69 int ncommunities; 70 struct mtx mutex; 71 }; 72 73 int 74 p2sb_get_port(device_t dev, int unit) 75 { 76 77 if (unit >= nitems(lbg_communities)) 78 return (EINVAL); 79 return (lbg_communities[unit]); 80 } 81 82 uint32_t 83 p2sb_port_read_4(device_t dev, uint8_t port, uint32_t reg) 84 { 85 struct p2sb_softc *sc; 86 87 KASSERT(reg < (1<<P2SB_PORT2ADDRESS_SHIFT), ("register out of port")); 88 sc = device_get_softc(dev); 89 return (bus_read_4(sc->res, P2SB_PORT_ADDRESS(port) + reg)); 90 } 91 92 void 93 p2sb_port_write_4(device_t dev, uint8_t port, uint32_t reg, uint32_t val) 94 { 95 struct p2sb_softc *sc; 96 97 KASSERT(reg < (1<<P2SB_PORT2ADDRESS_SHIFT), ("register out of port")); 98 sc = device_get_softc(dev); 99 bus_write_4(sc->res, P2SB_PORT_ADDRESS(port) + reg, val); 100 } 101 102 void 103 p2sb_lock(device_t dev) 104 { 105 struct p2sb_softc *sc; 106 107 sc = device_get_softc(dev); 108 mtx_lock_spin(&sc->mutex); 109 } 110 111 void 112 p2sb_unlock(device_t dev) 113 { 114 struct p2sb_softc *sc; 115 116 sc = device_get_softc(dev); 117 mtx_unlock_spin(&sc->mutex); 118 } 119 120 121 static int 122 p2sb_probe(device_t dev) 123 { 124 125 if (pci_get_devid(dev) == PCI_PRODUCT_LEWISBURG_P2SB) { 126 device_set_desc(dev, "Lewisburg P2SB"); 127 return (BUS_PROBE_DEFAULT); 128 } 129 return (ENXIO); 130 } 131 132 /* Attach function is only called if the probe is successful. */ 133 134 static int 135 p2sb_attach(device_t dev) 136 { 137 struct p2sb_softc *sc; 138 int i; 139 140 sc = device_get_softc(dev); 141 sc->dev = dev; 142 sc->rid = PCIR_BAR(0); 143 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, RF_ACTIVE); 144 if (sc->res == NULL) { 145 device_printf(dev, "Could not allocate memory.\n"); 146 return (ENXIO); 147 } 148 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 149 for (i = 0; i < nitems(lbg_communities); ++i) 150 device_add_child(dev, "lbggpiocm", i); 151 152 return (bus_generic_attach(dev)); 153 } 154 155 /* Detach device. */ 156 157 static int 158 p2sb_detach(device_t dev) 159 { 160 struct p2sb_softc *sc; 161 162 /* Teardown the state in our softc created in our attach routine. */ 163 device_delete_children(dev); 164 sc = device_get_softc(dev); 165 mtx_destroy(&sc->mutex); 166 if (sc->res != NULL) 167 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); 168 return (0); 169 } 170 171 /* Called during system shutdown after sync. */ 172 173 static int 174 p2sb_shutdown(device_t dev) 175 { 176 177 return (0); 178 } 179 180 /* 181 * Device suspend routine. 182 */ 183 static int 184 p2sb_suspend(device_t dev) 185 { 186 187 return (0); 188 } 189 190 /* 191 * Device resume routine. 192 */ 193 static int 194 p2sb_resume(device_t dev) 195 { 196 197 return (0); 198 } 199 200 static device_method_t p2sb_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, p2sb_probe), 203 DEVMETHOD(device_attach, p2sb_attach), 204 DEVMETHOD(device_detach, p2sb_detach), 205 DEVMETHOD(device_shutdown, p2sb_shutdown), 206 DEVMETHOD(device_suspend, p2sb_suspend), 207 DEVMETHOD(device_resume, p2sb_resume), 208 209 DEVMETHOD_END 210 }; 211 212 DEFINE_CLASS_0(p2sb, p2sb_driver, p2sb_methods, sizeof(struct p2sb_softc)); 213 DRIVER_MODULE(p2sb, pci, p2sb_driver, 0, 0); 214