1 /*- 2 * Copyright (c) 2015 M. Warner Losh <imp@FreeBSD.org> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include "opt_platform.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/gpio.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/gpio/gpiobusvar.h> 48 #include "gpiobus_if.h" 49 50 #include <dev/ow/owll.h> 51 52 #define OW_PIN 0 53 54 #define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 55 #define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 56 #define OWC_GPIOBUS_LOCK_INIT(_sc) \ 57 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 58 "owc_gpiobus", MTX_DEF) 59 #define OWC_GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 60 61 struct owc_gpiobus_softc 62 { 63 device_t sc_dev; 64 device_t sc_busdev; 65 struct mtx sc_mtx; 66 }; 67 68 static int owc_gpiobus_probe(device_t); 69 static int owc_gpiobus_attach(device_t); 70 static int owc_gpiobus_detach(device_t); 71 72 #ifdef FDT 73 static void 74 owc_gpiobus_identify(driver_t *driver, device_t bus) 75 { 76 phandle_t w1, root; 77 78 /* 79 * Find all the 1-wire bus pseudo-nodes that are 80 * at the top level of the FDT. Would be nice to 81 * somehow preserve the node name of these busses, 82 * but there's no good place to put it. The driver's 83 * name is used for the device name, and the 1-wire 84 * bus overwrites the description. 85 */ 86 root = OF_finddevice("/"); 87 if (root == -1) 88 return; 89 for (w1 = OF_child(root); w1 != 0; w1 = OF_peer(w1)) { 90 if (!fdt_is_compatible_strict(w1, "w1-gpio")) 91 continue; 92 if (!OF_hasprop(w1, "gpios")) 93 continue; 94 ofw_gpiobus_add_fdt_child(bus, driver->name, w1); 95 } 96 } 97 #endif 98 99 static int 100 owc_gpiobus_probe(device_t dev) 101 { 102 #ifdef FDT 103 if (!ofw_bus_status_okay(dev)) 104 return (ENXIO); 105 106 if (ofw_bus_is_compatible(dev, "w1-gpio")) { 107 device_set_desc(dev, "FDT GPIO attached one-wire bus"); 108 return (BUS_PROBE_DEFAULT); 109 } 110 111 return (ENXIO); 112 #else 113 device_set_desc(dev, "GPIO attached one-wire bus"); 114 return 0; 115 #endif 116 } 117 118 static int 119 owc_gpiobus_attach(device_t dev) 120 { 121 struct owc_gpiobus_softc *sc; 122 device_t *kids; 123 int nkid; 124 125 sc = device_get_softc(dev); 126 sc->sc_dev = dev; 127 sc->sc_busdev = device_get_parent(dev); 128 OWC_GPIOBUS_LOCK_INIT(sc); 129 nkid = 0; 130 if (device_get_children(dev, &kids, &nkid) == 0) 131 free(kids, M_TEMP); 132 if (nkid == 0) 133 device_add_child(dev, "ow", -1); 134 return (bus_delayed_attach_children(dev)); 135 } 136 137 static int 138 owc_gpiobus_detach(device_t dev) 139 { 140 struct owc_gpiobus_softc *sc; 141 142 sc = device_get_softc(dev); 143 OWC_GPIOBUS_LOCK_DESTROY(sc); 144 bus_generic_detach(dev); 145 return (0); 146 } 147 148 /* 149 * In the diagrams below, R is driven by the resistor pullup, M is driven by the 150 * master, and S is driven by the slave / target. 151 */ 152 153 /* 154 * These macros let what why we're doing stuff shine in the code 155 * below, and let the how be confined to here. 156 */ 157 #define GETBUS(sc) GPIOBUS_ACQUIRE_BUS((sc)->sc_busdev, \ 158 (sc)->sc_dev, GPIOBUS_WAIT) 159 #define RELBUS(sc) GPIOBUS_RELEASE_BUS((sc)->sc_busdev, \ 160 (sc)->sc_dev) 161 #define OUTPIN(sc) GPIOBUS_PIN_SETFLAGS((sc)->sc_busdev, \ 162 (sc)->sc_dev, OW_PIN, GPIO_PIN_OUTPUT) 163 #define INPIN(sc) GPIOBUS_PIN_SETFLAGS((sc)->sc_busdev, \ 164 (sc)->sc_dev, OW_PIN, GPIO_PIN_INPUT) 165 #define GETPIN(sc, bit) GPIOBUS_PIN_GET((sc)->sc_busdev, \ 166 (sc)->sc_dev, OW_PIN, bit) 167 #define LOW(sc) GPIOBUS_PIN_SET((sc)->sc_busdev, \ 168 (sc)->sc_dev, OW_PIN, GPIO_PIN_LOW) 169 170 /* 171 * WRITE-ONE (see owll_if.m for timings) From Figure 4-1 AN-937 172 * 173 * |<---------tSLOT---->|<-tREC->| 174 * High RRRRM | RRRRRRRRRRRR|RRRRRRRRM 175 * M | R | | | M 176 * M| R | | | M 177 * Low MMMMMMM | | | MMMMMM... 178 * |<-tLOW1->| | | 179 * |<------15us--->| | 180 * |<--------60us---->| 181 */ 182 static int 183 owc_gpiobus_write_one(device_t dev, struct ow_timing *t) 184 { 185 struct owc_gpiobus_softc *sc; 186 int error; 187 188 sc = device_get_softc(dev); 189 error = GETBUS(sc); 190 if (error != 0) 191 return (error); 192 193 critical_enter(); 194 195 /* Force low */ 196 OUTPIN(sc); 197 LOW(sc); 198 DELAY(t->t_low1); 199 200 /* Allow resistor to float line high */ 201 INPIN(sc); 202 DELAY(t->t_slot - t->t_low1 + t->t_rec); 203 204 critical_exit(); 205 206 RELBUS(sc); 207 208 return (0); 209 } 210 211 /* 212 * WRITE-ZERO (see owll_if.m for timings) From Figure 4-2 AN-937 213 * 214 * |<---------tSLOT------>|<-tREC->| 215 * High RRRRM | | |RRRRRRRM 216 * M | | R M 217 * M| | | |R M 218 * Low MMMMMMMMMMMMMMMMMMMMMR MMMMMM... 219 * |<--15us->| | | 220 * |<------60us--->| | 221 * |<-------tLOW0------>| 222 */ 223 static int 224 owc_gpiobus_write_zero(device_t dev, struct ow_timing *t) 225 { 226 struct owc_gpiobus_softc *sc; 227 int error; 228 229 sc = device_get_softc(dev); 230 error = GETBUS(sc); 231 if (error != 0) 232 return (error); 233 234 critical_enter(); 235 236 /* Force low */ 237 OUTPIN(sc); 238 LOW(sc); 239 DELAY(t->t_low0); 240 241 /* Allow resistor to float line high */ 242 INPIN(sc); 243 DELAY(t->t_slot - t->t_low0 + t->t_rec); 244 245 critical_exit(); 246 247 RELBUS(sc); 248 249 return (0); 250 } 251 252 /* 253 * READ-DATA (see owll_if.m for timings) From Figure 4-3 AN-937 254 * 255 * |<---------tSLOT------>|<-tREC->| 256 * High RRRRM | rrrrrrrrrrrrrrrRRRRRRRM 257 * M | r | R M 258 * M| r | |R M 259 * Low MMMMMMMSSSSSSSSSSSSSSR MMMMMM... 260 * |<tLOWR>< sample > | 261 * |<------tRDV---->| | 262 * ->| |<-tRELEASE 263 * 264 * r -- allowed to pull high via the resitor when slave writes a 1-bit 265 * 266 */ 267 static int 268 owc_gpiobus_read_data(device_t dev, struct ow_timing *t, int *bit) 269 { 270 struct owc_gpiobus_softc *sc; 271 int error, sample; 272 sbintime_t then, now; 273 274 sc = device_get_softc(dev); 275 error = GETBUS(sc); 276 if (error != 0) 277 return (error); 278 279 critical_enter(); 280 281 /* Force low for t_lowr microseconds */ 282 then = sbinuptime(); 283 OUTPIN(sc); 284 LOW(sc); 285 DELAY(t->t_lowr); 286 287 /* 288 * Slave is supposed to hold the line low for t_rdv microseconds for 0 289 * and immediately float it high for a 1. This is measured from the 290 * master's pushing the line low. 291 */ 292 INPIN(sc); 293 do { 294 now = sbinuptime(); 295 GETPIN(sc, &sample); 296 } while (now - then < (t->t_rdv + 2) * SBT_1US && sample == 0); 297 critical_exit(); 298 299 if (now - then < t->t_rdv * SBT_1US) 300 *bit = 1; 301 else 302 *bit = 0; 303 304 /* Wait out the rest of t_slot */ 305 do { 306 now = sbinuptime(); 307 } while (now - then < (t->t_slot + t->t_rec) * SBT_1US); 308 309 RELBUS(sc); 310 311 return (error); 312 } 313 314 /* 315 * RESET AND PRESENCE PULSE (see owll_if.m for timings) From Figure 4-4 AN-937 316 * 317 * |<---------tRSTH------------>| 318 * High RRRM | | RRRRRRRS | RRRR RRM 319 * M | |R| |S | R M 320 * M| R | | S |R M 321 * Low MMMMMMMM MMMMMM| | | SSSSSSSSSS MMMMMM 322 * |<----tRSTL--->| | |<-tPDL---->| 323 * | ->| |<-tR | | 324 * |<tPDH>| 325 * 326 * Note: for Regular Speed operations, tRSTL + tR should be less than 960us to 327 * avoid interferring with other devices on the bus 328 */ 329 static int 330 owc_gpiobus_reset_and_presence(device_t dev, struct ow_timing *t, int *bit) 331 { 332 struct owc_gpiobus_softc *sc; 333 int error; 334 int buf = -1; 335 336 sc = device_get_softc(dev); 337 error = GETBUS(sc); 338 if (error != 0) 339 return (error); 340 341 /* 342 * Read the current state of the bus. The steady state of an idle bus is 343 * high. Badly wired buses that are missing the required pull up, or 344 * that have a short circuit to ground cause all kinds of mischief when 345 * we try to read them later. Return EIO and release the bus if the bus 346 * is currently low. 347 */ 348 INPIN(sc); 349 GETPIN(sc, &buf); 350 if (buf == 0) { 351 *bit = -1; 352 RELBUS(sc); 353 return (EIO); 354 } 355 356 critical_enter(); 357 358 /* Force low */ 359 OUTPIN(sc); 360 LOW(sc); 361 DELAY(t->t_rstl); 362 363 /* Allow resistor to float line high and then wait for reset pulse */ 364 INPIN(sc); 365 DELAY(t->t_pdh + t->t_pdl / 2); 366 367 /* Read presence pulse */ 368 GETPIN(sc, &buf); 369 *bit = !!buf; 370 371 critical_exit(); 372 373 DELAY(t->t_rsth - (t->t_pdh + t->t_pdl / 2)); /* Timing not critical for this one */ 374 375 /* 376 * Read the state of the bus after we've waited past the end of the rest 377 * window. It should return to high. If it is low, then we have some 378 * problem and should abort the reset. 379 */ 380 GETPIN(sc, &buf); 381 if (buf == 0) { 382 *bit = -1; 383 RELBUS(sc); 384 return (EIO); 385 } 386 387 RELBUS(sc); 388 389 return (0); 390 } 391 392 static devclass_t owc_gpiobus_devclass; 393 394 static device_method_t owc_gpiobus_methods[] = { 395 /* Device interface */ 396 #ifdef FDT 397 DEVMETHOD(device_identify, owc_gpiobus_identify), 398 #endif 399 DEVMETHOD(device_probe, owc_gpiobus_probe), 400 DEVMETHOD(device_attach, owc_gpiobus_attach), 401 DEVMETHOD(device_detach, owc_gpiobus_detach), 402 403 DEVMETHOD(owll_write_one, owc_gpiobus_write_one), 404 DEVMETHOD(owll_write_zero, owc_gpiobus_write_zero), 405 DEVMETHOD(owll_read_data, owc_gpiobus_read_data), 406 DEVMETHOD(owll_reset_and_presence, owc_gpiobus_reset_and_presence), 407 { 0, 0 } 408 }; 409 410 static driver_t owc_gpiobus_driver = { 411 "owc", 412 owc_gpiobus_methods, 413 sizeof(struct owc_gpiobus_softc), 414 }; 415 416 DRIVER_MODULE(owc_gpiobus, gpiobus, owc_gpiobus_driver, owc_gpiobus_devclass, 0, 0); 417 MODULE_DEPEND(owc_gpiobus, ow, 1, 1, 1); 418 MODULE_DEPEND(owc_gpiobus, gpiobus, 1, 1, 1); 419 MODULE_VERSION(owc_gpiobus, 1); 420