1 /* $OpenBSD: if_otusreg.h,v 1.9 2013/11/26 20:33:18 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2007-2008 Atheros Communications, Inc. 6 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 #ifndef __IF_OTUSREG_H__ 21 #define __IF_OTUSREG_H__ 22 23 /* USB Endpoints addresses. */ 24 #define AR_EPT_BULK_TX_NO (UE_DIR_OUT | 1) 25 #define AR_EPT_BULK_RX_NO (UE_DIR_IN | 2) 26 #define AR_EPT_INTR_RX_NO (UE_DIR_IN | 3) 27 #define AR_EPT_INTR_TX_NO (UE_DIR_OUT | 4) 28 29 /* USB Requests. */ 30 #define AR_FW_DOWNLOAD 0x30 31 #define AR_FW_DOWNLOAD_COMPLETE 0x31 32 33 /* Maximum number of writes that can fit in a single FW command is 7. */ 34 #define AR_MAX_WRITE_IDX 6 /* 56 bytes */ 35 36 #define AR_FW_INIT_ADDR 0x102800 37 #define AR_FW_MAIN_ADDR 0x200000 38 #define AR_USB_MODE_CTRL 0x1e1108 39 40 /* 41 * AR9170 MAC registers. 42 */ 43 #define AR_MAC_REG_BASE 0x1c3000 44 #define AR_MAC_REG_DMA_TRIGGER (AR_MAC_REG_BASE + 0xd30) 45 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610) 46 #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614) 47 #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618) 48 #define AR_MAC_REG_BSSID_H (AR_MAC_REG_BASE + 0x61c) 49 #define AR_MAC_REG_GROUP_HASH_TBL_L (AR_MAC_REG_BASE + 0x624) 50 #define AR_MAC_REG_GROUP_HASH_TBL_H (AR_MAC_REG_BASE + 0x628) 51 #define AR_MAC_REG_RX_TIMEOUT (AR_MAC_REG_BASE + 0x62c) 52 #define AR_MAC_REG_BASIC_RATE (AR_MAC_REG_BASE + 0x630) 53 #define AR_MAC_REG_MANDATORY_RATE (AR_MAC_REG_BASE + 0x634) 54 #define AR_MAC_REG_RTS_CTS_RATE (AR_MAC_REG_BASE + 0x638) 55 #define AR_MAC_REG_BACKOFF_PROTECT (AR_MAC_REG_BASE + 0x63c) 56 #define AR_MAC_REG_RX_THRESHOLD (AR_MAC_REG_BASE + 0x640) 57 #define AR_MAC_REG_RX_PE_DELAY (AR_MAC_REG_BASE + 0x64c) 58 #define AR_MAC_REG_DYNAMIC_SIFS_ACK (AR_MAC_REG_BASE + 0x658) 59 #define AR_MAC_REG_SNIFFER (AR_MAC_REG_BASE + 0x674) 60 #define AR_MAC_SNIFFER_DEFAULTS 0x02000000 61 #define AR_MAC_SNIFFER_ENABLE_PROMISC 0x1 62 #define AR_MAC_REG_ENCRYPTION (AR_MAC_REG_BASE + 0x678) 63 #define AR_MAC_REG_MISC_680 (AR_MAC_REG_BASE + 0x680) 64 #define AR_MAC_REG_FRAMETYPE_FILTER (AR_MAC_REG_BASE + 0x68c) 65 #define AR_MAC_REG_ACK_EXTENSION (AR_MAC_REG_BASE + 0x690) 66 #define AR_MAC_REG_ACK_TPC (AR_MAC_REG_BASE + 0x694) 67 #define AR_MAC_REG_EIFS_AND_SIFS (AR_MAC_REG_BASE + 0x698) 68 #define AR_MAC_REG_BUSY (AR_MAC_REG_BASE + 0x6e8) 69 #define AR_MAC_REG_BUSY_EXT (AR_MAC_REG_BASE + 0x6ec) 70 #define AR_MAC_REG_SLOT_TIME (AR_MAC_REG_BASE + 0x6f0) 71 #define AR_MAC_REG_CAM_MODE (AR_MAC_REG_BASE + 0x700) 72 #define AR_MAC_CAM_DEFAULTS (0xf << 24) 73 #define AR_MAC_CAM_IBSS 0xe0 74 #define AR_MAC_CAM_AP 0xa1 75 #define AR_MAC_CAM_STA 0x2 76 #define AR_MAC_CAM_AP_WDS 0x3 77 #define AR_MAC_REG_AC0_CW (AR_MAC_REG_BASE + 0xb00) 78 #define AR_MAC_REG_AC1_CW (AR_MAC_REG_BASE + 0xb04) 79 #define AR_MAC_REG_AC2_CW (AR_MAC_REG_BASE + 0xb08) 80 #define AR_MAC_REG_AC3_CW (AR_MAC_REG_BASE + 0xb0c) 81 #define AR_MAC_REG_AC4_CW (AR_MAC_REG_BASE + 0xb10) 82 #define AR_MAC_REG_AC1_AC0_AIFS (AR_MAC_REG_BASE + 0xb14) 83 #define AR_MAC_REG_AC3_AC2_AIFS (AR_MAC_REG_BASE + 0xb18) 84 #define AR_MAC_REG_RETRY_MAX (AR_MAC_REG_BASE + 0xb28) 85 #define AR_MAC_REG_TID_CFACK_CFEND_RATE (AR_MAC_REG_BASE + 0xb2c) 86 #define AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION \ 87 (AR_MAC_REG_BASE + 0xb30) 88 #define AR_MAC_REG_TXOP_DURATION (AR_MAC_REG_BASE + 0xb38) 89 #define AR_MAC_REG_AC1_AC0_TXOP (AR_MAC_REG_BASE + 0xb44) 90 #define AR_MAC_REG_AC3_AC2_TXOP (AR_MAC_REG_BASE + 0xb48) 91 #define AR_MAC_REG_AMPDU_FACTOR (AR_MAC_REG_BASE + 0xb9c) 92 #define AR_MAC_REG_FCS_SELECT (AR_MAC_REG_BASE + 0xbb0) 93 #define AR_MAC_REG_RX_CONTROL (AR_MAC_REG_BASE + 0xc40) 94 #define AR_MAC_RX_CTRL_DEAGG 0x1 95 #define AR_MAC_RX_CTRL_SHORT_FILTER 0x2 96 #define AR_MAC_RX_CTRL_SA_DA_SEARCH 0x20 97 #define AR_MAC_RX_CTRL_PASS_TO_HOST (1 << 28) 98 #define AR_MAC_RX_CTRL_ACK_IN_SNIFFER (1 << 30) 99 100 #define AR_MAC_REG_AMPDU_RX_THRESH (AR_MAC_REG_BASE + 0xc50) 101 #define AR_MAC_REG_OFDM_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb4) 102 #define AR_MAC_REG_CCK_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb8) 103 #define AR_MAC_REG_TXRX_MPI (AR_MAC_REG_BASE + 0xd7c) 104 #define AR_MAC_REG_BCN_HT1 (AR_MAC_REG_BASE + 0xda0) 105 106 /* Possible values for register AR_USB_MODE_CTRL. */ 107 #define AR_USB_DS_ENA (1 << 0) 108 #define AR_USB_US_ENA (1 << 1) 109 #define AR_USB_US_PACKET_MODE (1 << 3) 110 #define AR_USB_RX_STREAM_4K (0 << 4) 111 #define AR_USB_RX_STREAM_8K (1 << 4) 112 #define AR_USB_RX_STREAM_16K (2 << 4) 113 #define AR_USB_RX_STREAM_32K (3 << 4) 114 #define AR_USB_TX_STREAM_MODE (1 << 6) 115 116 #define AR_LED0_ON (1 << 0) 117 #define AR_LED1_ON (1 << 1) 118 119 /* 120 * PHY registers. 121 */ 122 #define AR_PHY_BASE 0x1c5800 123 #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4) 124 #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004) 125 #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028) 126 #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034) 127 #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044) 128 #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048) 129 #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050) 130 #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058) 131 #define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c) 132 #define AR_PHY_SFCORR (AR_PHY_BASE + 0x0068) 133 #define AR_PHY_SFCORR_LOW (AR_PHY_BASE + 0x006c) 134 #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) 135 #define AR_PHY_TIMING5 (AR_PHY_BASE + 0x0124) 136 #define AR_PHY_POWER_TX_RATE1 (AR_PHY_BASE + 0x0134) 137 #define AR_PHY_POWER_TX_RATE2 (AR_PHY_BASE + 0x0138) 138 #define AR_PHY_POWER_TX_RATE_MAX (AR_PHY_BASE + 0x013c) 139 #define AR_PHY_SWITCH_CHAIN_0 (AR_PHY_BASE + 0x0160) 140 #define AR_PHY_SWITCH_COM (AR_PHY_BASE + 0x0164) 141 #define AR_PHY_HEAVY_CLIP_ENABLE (AR_PHY_BASE + 0x01e0) 142 #define AR_PHY_CCK_DETECT (AR_PHY_BASE + 0x0a08) 143 #define AR_PHY_GAIN_2GHZ (AR_PHY_BASE + 0x0a0c) 144 #define AR_PHY_POWER_TX_RATE3 (AR_PHY_BASE + 0x0a34) 145 #define AR_PHY_POWER_TX_RATE4 (AR_PHY_BASE + 0x0a38) 146 #define AR_PHY_TPCRG1 (AR_PHY_BASE + 0x0a58) 147 #define AR_PHY_POWER_TX_RATE5 (AR_PHY_BASE + 0x0b8c) 148 #define AR_PHY_POWER_TX_RATE6 (AR_PHY_BASE + 0x0b90) 149 #define AR_PHY_POWER_TX_RATE7 (AR_PHY_BASE + 0x0bcc) 150 #define AR_PHY_POWER_TX_RATE8 (AR_PHY_BASE + 0x0bd0) 151 #define AR_PHY_POWER_TX_RATE9 (AR_PHY_BASE + 0x0bd4) 152 #define AR_PHY_CCA (AR_PHY_BASE + 0x3064) 153 154 #define AR_SEEPROM_HW_TYPE_OFFSET 0x1374 155 #define AR_EEPROM_OFFSET 0x1600 156 157 #define AR_BANK4_CHUP (1 << 0) 158 #define AR_BANK4_BMODE_LF_SYNTH_FREQ (1 << 1) 159 #define AR_BANK4_AMODE_REFSEL(x) ((x) << 2) 160 #define AR_BANK4_ADDR(x) ((x) << 5) 161 162 /* 163 * Random number generator. 164 */ 165 #define AR_RAND_REG_BASE 0x1d0000 166 167 /* 168 * GPIO. 169 */ 170 #define AR_GPIO_REG_BASE 0x1d0100 171 172 #define AR_GPIO_REG_PORT_TYPE (AR_GPIO_REG_BASE + 0x000) 173 #define AR_GPIO_REG_PORT_DATA (AR_GPIO_REG_BASE + 0x004) 174 #define AR_GPIO_PORT_LED_0 1 175 #define AR_GPIO_PORT_LED_1 2 176 /* WPS Button GPIO for TP-Link TL-WN821N */ 177 #define AR_GPIO_PORT_WPS_BUTTON_PRESSED 4 178 179 /* 180 * Power Management. 181 */ 182 #define AR_PWR_REG_BASE 0x1d4000 183 184 #define AR_PWR_REG_RESET (AR_PWR_REG_BASE + 0x004) 185 #define AR_PWR_REG_CLOCK_SEL (AR_PWR_REG_BASE + 0x008) 186 #define AR_PWR_REG_PLL_ADDAC (AR_PWR_REG_BASE + 0x014) 187 188 /* Tx descriptor. */ 189 struct ar_tx_head { 190 uint16_t len; 191 uint16_t macctl; 192 #define AR_TX_MAC_RTS (1 << 0) 193 #define AR_TX_MAC_CTS (1 << 1) 194 #define AR_TX_MAC_BACKOFF (1 << 3) 195 #define AR_TX_MAC_NOACK (1 << 2) 196 #define AR_TX_MAC_HW_DUR (1 << 9) 197 #define AR_TX_MAC_QID(qid) ((qid) << 10) 198 #define AR_TX_MAC_RATE_PROBING (1 << 15) 199 200 uint32_t phyctl; 201 /* Modulation type. */ 202 #define AR_TX_PHY_MT_SHIFT 0 /* 0:1 - PHY mode */ 203 #define AR_TX_PHY_MT_CCK 0 204 #define AR_TX_PHY_MT_OFDM 1 205 #define AR_TX_PHY_MT_HT 2 206 #define AR_TX_PHY_GF (1 << 2) /* 2 - greenfield */ 207 #define AR_TX_PHY_BW_SHIFT 3 /* 4:3 - bandwidth */ 208 #define AR_TX_PHY_BW_20MHZ 0 209 #define AR_TX_PHY_BW_40MHZ 2 210 #define AR_TX_PHY_BW_40MHZ_DUP 3 211 #define AR_TX_PHY_TX_HEAVY_CLIP_SHIFT 6 /* 9:6 - heavy clip */ 212 #define AR_TX_PHY_TPC_SHIFT 9 /* 14:9 - TX power */ 213 #define AR_TX_PHY_ANTMSK(msk) ((msk) << 15) 214 #define AR_TX_PHY_MCS(mcs) ((mcs) << 18) 215 #define AR_TX_PHY_SHGI (1U << 31) 216 } __packed; 217 218 /* USB Rx stream mode header. */ 219 struct ar_rx_head { 220 uint16_t len; 221 uint16_t tag; 222 #define AR_RX_HEAD_TAG 0x4e00 223 } __packed; 224 225 /* Rx descriptor. */ 226 227 struct ar_rx_macstatus { 228 uint8_t sa_idx; 229 uint8_t da_idx; 230 uint8_t error; 231 #define AR_RX_ERROR_TIMEOUT (1 << 0) 232 #define AR_RX_ERROR_OVERRUN (1 << 1) 233 #define AR_RX_ERROR_DECRYPT (1 << 2) 234 #define AR_RX_ERROR_FCS (1 << 3) 235 #define AR_RX_ERROR_BAD_RA (1 << 4) 236 #define AR_RX_ERROR_PLCP (1 << 5) 237 #define AR_RX_ERROR_MMIC (1 << 6) 238 uint8_t status; 239 /* Modulation type (same as AR_TX_PHY_MT). */ 240 #define AR_RX_STATUS_MT_MASK 0x3 241 #define AR_RX_STATUS_MT_CCK 0 242 #define AR_RX_STATUS_MT_OFDM 1 243 #define AR_RX_STATUS_MT_HT 2 244 #define AR_RX_STATUS_SHPREAMBLE (1 << 3) 245 #define AR_RX_STATUS_MPDU_MASK 0x30 246 #define AR_RX_STATUS_MPDU_SINGLE 0x00 247 #define AR_RX_STATUS_MPDU_LAST 0x10 248 #define AR_RX_STATUS_MPDU_FIRST 0x20 249 #define AR_RX_STATUS_MPDU_MIDDLE 0x30 250 } __packed; 251 252 struct ar_rx_phystatus { 253 uint8_t rssi_ant[3]; 254 uint8_t rssi_ant_ext[3]; 255 uint8_t rssi; /* Combined RSSI. */ 256 uint8_t evm[2][6]; /* Error Vector Magnitude. */ 257 uint8_t phy_err; 258 } __packed; 259 260 #define AR_PLCP_HDR_LEN 12 261 /* Magic PLCP header for firmware notifications through Rx bulk pipe. */ 262 static uint8_t AR_PLCP_HDR_INTR[] = { 263 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 264 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 265 }; 266 267 /* Firmware command/reply header. */ 268 struct ar_cmd_hdr { 269 uint8_t len; 270 uint8_t code; 271 #define AR_CMD_RREG 0x00 272 #define AR_CMD_WREG 0x01 273 #define AR_CMD_RMEM 0x02 274 #define AR_CMD_WMEM 0x03 275 #define AR_CMD_BITAND 0x04 276 #define AR_CMD_BITOR 0x05 277 #define AR_CMD_EKEY 0x28 278 #define AR_CMD_DKEY 0x29 279 #define AR_CMD_FREQUENCY 0x30 280 #define AR_CMD_RF_INIT 0x31 281 #define AR_CMD_SYNTH 0x32 282 #define AR_CMD_FREQ_STRAT 0x33 283 #define AR_CMD_ECHO 0x80 284 #define AR_CMD_TALLY 0x81 285 #define AR_CMD_TALLY_APD 0x82 286 #define AR_CMD_CONFIG 0x83 287 #define AR_CMD_RESET 0x90 288 #define AR_CMD_DKRESET 0x91 289 #define AR_CMD_DKTX_STATUS 0x92 290 #define AR_CMD_FDC 0xa0 291 #define AR_CMD_WREEPROM 0xb0 292 #define AR_CMD_WFLASH AR_CMD_WREEPROM 293 #define AR_CMD_FLASH_ERASE 0xb1 294 #define AR_CMD_FLASH_PROG 0xb2 295 #define AR_CMD_FLASH_CHKSUM 0xb3 296 #define AR_CMD_FLASH_READ 0xb4 297 #define AR_CMD_FW_DL_INIT 0xb5 298 #define AR_CMD_MEM_WREEPROM 0xbb 299 /* Those have the 2 MSB set to 1. */ 300 #define AR_EVT_BEACON 0x00 301 #define AR_EVT_TX_COMP 0x01 302 #define AR_EVT_TBTT 0x02 303 #define AR_EVT_ATIM 0x03 304 #define AR_EVT_DO_BB_RESET 0x09 305 306 uint16_t token; /* Driver private data. */ 307 } __packed; 308 309 /* Structure for command AR_CMD_RF_INIT/AR_CMD_FREQUENCY. */ 310 struct ar_cmd_frequency { 311 uint32_t freq; 312 uint32_t dynht2040; 313 uint32_t htena; 314 uint32_t dsc_exp; 315 uint32_t dsc_man; 316 uint32_t dsc_shgi_exp; 317 uint32_t dsc_shgi_man; 318 uint32_t check_loop_count; 319 } __packed; 320 321 /* Firmware reply for command AR_CMD_FREQUENCY. */ 322 struct ar_rsp_frequency { 323 uint32_t status; 324 #define AR_CAL_ERR_AGC (1 << 0) /* AGC cal unfinished. */ 325 #define AR_CAL_ERR_NF (1 << 1) /* Noise cal unfinished. */ 326 #define AR_CAL_ERR_NF_VAL (1 << 2) /* NF value unexpected. */ 327 328 uint32_t nf[3]; /* Noisefloor. */ 329 uint32_t nf_ext[3]; /* Noisefloor ext. */ 330 } __packed; 331 332 /* Structure for command AR_CMD_EKEY. */ 333 struct ar_cmd_ekey { 334 uint16_t uid; /* user ID */ 335 uint16_t kix; 336 uint16_t cipher; 337 #define AR_CIPHER_NONE 0 338 #define AR_CIPHER_WEP64 1 339 #define AR_CIPHER_TKIP 2 340 #define AR_CIPHER_AES 4 341 #define AR_CIPHER_WEP128 5 342 #define AR_CIPHER_WEP256 6 343 #define AR_CIPHER_CENC 7 344 345 uint8_t macaddr[IEEE80211_ADDR_LEN]; 346 uint8_t key[16]; 347 } __packed; 348 349 /* Structure for event AR_EVT_TX_COMP. */ 350 struct ar_evt_tx_comp { 351 uint8_t macaddr[IEEE80211_ADDR_LEN]; 352 uint32_t phy; 353 uint16_t status; 354 #define AR_TX_STATUS_COMP 0 355 #define AR_TX_STATUS_RETRY_COMP 1 356 #define AR_TX_STATUS_FAILED 2 357 } __packed; 358 359 /* List of supported channels. */ 360 static const uint8_t ar_chans[] = { 361 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 362 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 100, 104, 108, 363 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 364 }; 365 366 /* 367 * This data is automatically generated from the "otus.ini" file. 368 * It is stored in a different way though, to reduce kernel's .rodata 369 * section overhead (5.1KB instead of 8.5KB). 370 */ 371 372 /* NB: apply AR_PHY(). */ 373 static const uint16_t ar5416_phy_regs[] = { 374 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 0x008, 375 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 0x010, 0x011, 376 0x012, 0x013, 0x014, 0x015, 0x016, 0x017, 0x018, 0x01a, 0x01b, 377 0x040, 0x041, 0x042, 0x043, 0x045, 0x046, 0x047, 0x048, 0x049, 378 0x04a, 0x04b, 0x04d, 0x04e, 0x04f, 0x051, 0x052, 0x053, 0x055, 379 0x056, 0x058, 0x059, 0x05c, 0x05d, 0x05e, 0x05f, 0x060, 0x061, 380 0x062, 0x063, 0x064, 0x065, 0x066, 0x067, 0x068, 0x069, 0x06a, 381 0x06b, 0x06c, 0x06d, 0x070, 0x071, 0x072, 0x073, 0x074, 0x075, 382 0x076, 0x077, 0x078, 0x079, 0x07a, 0x07b, 0x07c, 0x07f, 0x080, 383 0x081, 0x082, 0x083, 0x084, 0x085, 0x086, 0x087, 0x088, 0x089, 384 0x08a, 0x08b, 0x08c, 0x08d, 0x08e, 0x08f, 0x090, 0x091, 0x092, 385 0x093, 0x094, 0x095, 0x096, 0x097, 0x098, 0x099, 0x09a, 0x09b, 386 0x09c, 0x09d, 0x09e, 0x09f, 0x0a0, 0x0a1, 0x0a2, 0x0a3, 0x0a4, 387 0x0a5, 0x0a6, 0x0a7, 0x0a8, 0x0a9, 0x0aa, 0x0ab, 0x0ac, 0x0ad, 388 0x0ae, 0x0af, 0x0b0, 0x0b1, 0x0b2, 0x0b3, 0x0b4, 0x0b5, 0x0b6, 389 0x0b7, 0x0b8, 0x0b9, 0x0ba, 0x0bb, 0x0bc, 0x0bd, 0x0be, 0x0bf, 390 0x0c0, 0x0c1, 0x0c2, 0x0c3, 0x0c4, 0x0c5, 0x0c6, 0x0c7, 0x0c8, 391 0x0c9, 0x0ca, 0x0cb, 0x0cc, 0x0cd, 0x0ce, 0x0cf, 0x0d0, 0x0d1, 392 0x0d2, 0x0d3, 0x0d4, 0x0d5, 0x0d6, 0x0d7, 0x0d8, 0x0d9, 0x0da, 393 0x0db, 0x0dc, 0x0dd, 0x0de, 0x0df, 0x0e0, 0x0e1, 0x0e2, 0x0e3, 394 0x0e4, 0x0e5, 0x0e6, 0x0e7, 0x0e8, 0x0e9, 0x0ea, 0x0eb, 0x0ec, 395 0x0ed, 0x0ee, 0x0ef, 0x0f0, 0x0f1, 0x0f2, 0x0f3, 0x0f4, 0x0f5, 396 0x0f6, 0x0f7, 0x0f8, 0x0f9, 0x0fa, 0x0fb, 0x0fc, 0x0fd, 0x0fe, 397 0x0ff, 0x100, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 398 0x10a, 0x10b, 0x10c, 0x10d, 0x10e, 0x10f, 0x13c, 0x13d, 0x13e, 399 0x13f, 0x280, 0x281, 0x282, 0x283, 0x284, 0x285, 0x286, 0x287, 400 0x288, 0x289, 0x28a, 0x28b, 0x28c, 0x28d, 0x28e, 0x28f, 0x290, 401 0x291, 0x292, 0x293, 0x294, 0x295, 0x296, 0x297, 0x298, 0x299, 402 0x29a, 0x29b, 0x29d, 0x29e, 0x29f, 0x2c0, 0x2c1, 0x2c2, 0x2c3, 403 0x2c4, 0x2c5, 0x2c6, 0x2c7, 0x2c8, 0x2c9, 0x2ca, 0x2cb, 0x2cc, 404 0x2cd, 0x2ce, 0x2cf, 0x2d0, 0x2d1, 0x2d2, 0x2d3, 0x2d4, 0x2d5, 405 0x2d6, 0x2e2, 0x2e3, 0x2e4, 0x2e5, 0x2e6, 0x2e7, 0x2e8, 0x2e9, 406 0x2ea, 0x2eb, 0x2ec, 0x2ed, 0x2ee, 0x2ef, 0x2f0, 0x2f1, 0x2f2, 407 0x2f3, 0x2f4, 0x2f5, 0x2f6, 0x2f7, 0x2f8, 0x412, 0x448, 0x458, 408 0x683, 0x69b, 0x812, 0x848, 0x858, 0xa83, 0xa9b, 0xc19, 0xc57, 409 0xc5a, 0xc6f, 0xe9c, 0xed7, 0xed8, 0xed9, 0xeda, 0xedb, 0xedc, 410 0xedd, 0xede, 0xedf, 0xee0, 0xee1 411 }; 412 413 static const uint32_t ar5416_phy_vals_5ghz_20mhz[] = { 414 0x00000007, 0x00000300, 0x00000000, 0xad848e19, 0x7d14e000, 415 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 416 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 417 0x00200400, 0x206a002e, 0x1372161e, 0x001a6a65, 0x1284233c, 418 0x6c48b4e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd10, 419 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 420 0x00000000, 0x000007d0, 0x00000118, 0x10000fff, 0x0510081c, 421 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 422 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 423 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 424 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 425 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 426 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 427 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 428 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 429 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 430 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1, 431 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8, 432 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009, 433 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0, 434 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011, 435 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038, 436 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 437 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 438 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 439 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 440 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 441 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 442 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 443 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 444 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 445 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 446 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 447 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 448 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 449 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 450 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 451 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 452 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 453 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 454 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 455 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 456 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 457 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 458 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 459 0x00000000, 0x00000008, 0x00000440, 0xd6be4788, 0x012e8160, 460 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 461 0x00000400, 0x000009b5, 0x00000000, 0x00000108, 0x3f3f3f3f, 462 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 463 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 464 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a9caa, 465 0x1ce739ce, 0x051701ce, 0x18010000, 0x30032602, 0x48073e06, 466 0x560b4c0a, 0x641a600f, 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 467 0xb51fa69f, 0xcb3fbd07, 0x0000d7bf, 0x00000000, 0x00000000, 468 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 469 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 470 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 471 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 472 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 473 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 474 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a65, 0x0510001c, 475 0x00009b40, 0x012e8160, 0x09249126, 0x00180a65, 0x0510001c, 476 0x00009b40, 0x012e8160, 0x09249126, 0x0001c600, 0x004b6a8e, 477 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 478 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 479 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 480 }; 481 482 static const uint32_t ar5416_phy_vals_5ghz_40mhz[] = { 483 0x00000007, 0x000003c4, 0x00000000, 0xad848e19, 0x7d14e000, 484 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 485 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 486 0x00200400, 0x206a002e, 0x13721c1e, 0x001a6a65, 0x1284233c, 487 0x6c48b4e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd10, 488 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 489 0x00000000, 0x000007d0, 0x00000230, 0x10000fff, 0x0510081c, 490 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 491 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 492 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 493 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 494 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 495 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 496 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 497 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 498 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 499 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1, 500 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8, 501 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009, 502 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0, 503 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011, 504 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038, 505 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 506 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 507 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 508 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 509 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 510 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 511 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 512 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 513 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 514 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 515 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 516 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 517 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 518 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 519 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 520 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 521 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 522 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 523 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 524 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 525 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 526 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 527 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 528 0x00000000, 0x00000008, 0x00000440, 0xd6be4788, 0x012e8160, 529 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 530 0x00000400, 0x000009b5, 0x00000000, 0x00000210, 0x3f3f3f3f, 531 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 532 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 533 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a9caa, 534 0x1ce739ce, 0x051701ce, 0x18010000, 0x30032602, 0x48073e06, 535 0x560b4c0a, 0x641a600f, 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 536 0xb51fa69f, 0xcb3fbcbf, 0x0000d7bf, 0x00000000, 0x00000000, 537 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 538 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 539 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 540 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 542 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 543 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a65, 0x0510001c, 544 0x00009b40, 0x012e8160, 0x09249126, 0x00180a65, 0x0510001c, 545 0x00009b40, 0x012e8160, 0x09249126, 0x0001c600, 0x004b6a8e, 546 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 547 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 548 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 549 }; 550 551 static const uint32_t ar5416_phy_vals_2ghz_40mhz[] = { 552 0x00000007, 0x000003c4, 0x00000000, 0xad848e19, 0x7d14e000, 553 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 554 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 555 0x00200400, 0x206a002e, 0x13721c24, 0x00197a68, 0x1284233c, 556 0x6c48b0e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd20, 557 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 558 0x00000000, 0x00000898, 0x00000268, 0x10000fff, 0x0510001c, 559 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 560 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 561 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 562 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 563 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 564 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 565 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 566 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 567 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 568 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181, 569 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8, 570 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9, 571 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0, 572 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191, 573 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8, 574 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199, 575 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 576 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 577 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 578 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 579 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 580 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 581 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 582 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 583 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 584 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 585 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 586 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 587 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 588 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 589 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 590 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 591 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 592 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 593 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 594 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 595 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 596 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 597 0x00000000, 0x0000000e, 0x00000440, 0xd03e4788, 0x012a8160, 598 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 599 0x00000400, 0x000009b5, 0x00000000, 0x00000210, 0x3f3f3f3f, 600 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 601 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 602 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a7caa, 603 0x1ce739ce, 0x051701ce, 0x18010000, 0x2e032402, 0x4a0a3c06, 604 0x621a540b, 0x764f6c1b, 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 605 0xbddfaf1f, 0xd1ffc93f, 0x00000000, 0x00000000, 0x00000000, 606 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 607 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 608 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 609 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 610 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 611 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 612 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a68, 0x0510001c, 613 0x00009b40, 0x012a8160, 0x09249126, 0x00180a68, 0x0510001c, 614 0x00009b40, 0x012a8160, 0x09249126, 0x0001c600, 0x004b6a8e, 615 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 616 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 617 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 618 }; 619 620 static const uint32_t ar5416_phy_vals_2ghz_20mhz[] = { 621 0x00000007, 0x00000300, 0x00000000, 0xad848e19, 0x7d14e000, 622 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 623 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 624 0x00200400, 0x206a002e, 0x137216a4, 0x00197a68, 0x1284233c, 625 0x6c48b0e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd20, 626 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 627 0x00000000, 0x00000898, 0x00000134, 0x10000fff, 0x0510001c, 628 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 629 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 630 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 631 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 632 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 633 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 634 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 635 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 636 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 637 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181, 638 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8, 639 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9, 640 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0, 641 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191, 642 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8, 643 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199, 644 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 645 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 646 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 647 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 648 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 649 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 650 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 651 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 652 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 653 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 654 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 655 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 656 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 657 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 658 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 659 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 660 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 661 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 662 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 663 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 664 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 665 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 666 0x00000000, 0x0000000e, 0x00000440, 0xd03e4788, 0x012a8160, 667 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 668 0x00000400, 0x000009b5, 0x00000000, 0x00000108, 0x3f3f3f3f, 669 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 670 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 671 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a7caa, 672 0x1ce739ce, 0x051701ce, 0x18010000, 0x2e032402, 0x4a0a3c06, 673 0x621a540b, 0x764f6c1b, 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 674 0xbddfaf1f, 0xd1ffc93f, 0x00000000, 0x00000000, 0x00000000, 675 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 676 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 677 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 678 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 679 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 680 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 681 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a68, 0x0510001c, 682 0x00009b40, 0x012a8160, 0x09249126, 0x00180a68, 0x0510001c, 683 0x00009b40, 0x012a8160, 0x09249126, 0x0001c600, 0x004b6a8e, 684 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 685 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 686 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 687 }; 688 689 /* NB: apply AR_PHY(). */ 690 static const uint8_t ar5416_banks_regs[] = { 691 0x2c, 0x38, 0x2c, 0x3b, 0x2c, 0x38, 0x3c, 0x2c, 0x3a, 0x2c, 0x39, 692 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 693 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 694 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 695 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 696 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x38, 0x2c, 0x2c, 697 0x2c, 0x3c 698 }; 699 700 static const uint32_t ar5416_banks_vals_5ghz[] = { 701 0x1e5795e5, 0x02008020, 0x02108421, 0x00000008, 0x0e73ff17, 702 0x00000420, 0x01400018, 0x000001a1, 0x00000001, 0x00000013, 703 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 704 0x00000000, 0x00004000, 0x00006c00, 0x00002c00, 0x00004800, 705 0x00004000, 0x00006000, 0x00001000, 0x00004000, 0x00007c00, 706 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00087c00, 707 0x00007c00, 0x00005400, 0x00000c00, 0x00001800, 0x00007c00, 708 0x00006c00, 0x00006c00, 0x00007c00, 0x00002c00, 0x00003c00, 709 0x00003800, 0x00001c00, 0x00000800, 0x00000408, 0x00004c15, 710 0x00004188, 0x0000201e, 0x00010408, 0x00000801, 0x00000c08, 711 0x0000181e, 0x00001016, 0x00002800, 0x00004010, 0x0000081c, 712 0x00000115, 0x00000015, 0x00000066, 0x0000001c, 0x00000000, 713 0x00000004, 0x00000015, 0x0000001f, 0x00000000, 0x000000a0, 714 0x00000000, 0x00000040, 0x0000001c 715 }; 716 717 static const uint32_t ar5416_banks_vals_2ghz[] = { 718 0x1e5795e5, 0x02008020, 0x02108421, 0x00000008, 0x0e73ff17, 719 0x00000420, 0x01c00018, 0x000001a1, 0x00000001, 0x00000013, 720 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 721 0x00000000, 0x00004000, 0x00006c00, 0x00002c00, 0x00004800, 722 0x00004000, 0x00006000, 0x00001000, 0x00004000, 0x00007c00, 723 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00087c00, 724 0x00007c00, 0x00005400, 0x00000c00, 0x00001800, 0x00007c00, 725 0x00006c00, 0x00006c00, 0x00007c00, 0x00002c00, 0x00003c00, 726 0x00003800, 0x00001c00, 0x00000800, 0x00000408, 0x00004c15, 727 0x00004188, 0x0000201e, 0x00010408, 0x00000801, 0x00000c08, 728 0x0000181e, 0x00001016, 0x00002800, 0x00004010, 0x0000081c, 729 0x00000115, 0x00000015, 0x00000066, 0x0000001c, 0x00000000, 730 0x00000004, 0x00000015, 0x0000001f, 0x00000400, 0x000000a0, 731 0x00000000, 0x00000040, 0x0000001c 732 }; 733 734 /* 735 * EEPROM. 736 */ 737 /* Possible flags for opCapFlags. */ 738 #define AR5416_OPFLAGS_11A 0x01 739 #define AR5416_OPFLAGS_11G 0x02 740 #define AR5416_OPFLAGS_5G_HT40 0x04 741 #define AR5416_OPFLAGS_2G_HT40 0x08 742 #define AR5416_OPFLAGS_5G_HT20 0x10 743 #define AR5416_OPFLAGS_2G_HT20 0x20 744 745 #define AR5416_NUM_5G_CAL_PIERS 8 746 #define AR5416_NUM_2G_CAL_PIERS 4 747 #define AR5416_NUM_5G_20_TARGET_POWERS 8 748 #define AR5416_NUM_5G_40_TARGET_POWERS 8 749 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 750 #define AR5416_NUM_2G_20_TARGET_POWERS 4 751 #define AR5416_NUM_2G_40_TARGET_POWERS 4 752 #define AR5416_NUM_CTLS 24 753 #define AR5416_NUM_BAND_EDGES 8 754 #define AR5416_NUM_PD_GAINS 4 755 #define AR5416_PD_GAIN_ICEPTS 5 756 #define AR5416_EEPROM_MODAL_SPURS 5 757 #define AR5416_MAX_CHAINS 2 758 759 struct BaseEepHeader { 760 uint16_t length; 761 uint16_t checksum; 762 uint16_t version; 763 uint8_t opCapFlags; 764 uint8_t eepMisc; 765 uint16_t regDmn[2]; 766 uint8_t macAddr[6]; 767 uint8_t rxMask; 768 uint8_t txMask; 769 uint16_t rfSilent; 770 uint16_t blueToothOptions; 771 uint16_t deviceCap; 772 uint32_t binBuildNumber; 773 uint8_t deviceType; 774 uint8_t futureBase[33]; 775 } __packed; 776 777 struct spurChanStruct { 778 uint16_t spurChan; 779 uint8_t spurRangeLow; 780 uint8_t spurRangeHigh; 781 } __packed; 782 783 struct ModalEepHeader { 784 uint32_t antCtrlChain[AR5416_MAX_CHAINS]; 785 uint32_t antCtrlCommon; 786 int8_t antennaGainCh[AR5416_MAX_CHAINS]; 787 uint8_t switchSettling; 788 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; 789 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; 790 uint8_t adcDesiredSize; 791 int8_t pgaDesiredSize; 792 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; 793 uint8_t txEndToXpaOff; 794 uint8_t txEndToRxOn; 795 uint8_t txFrameToXpaOn; 796 uint8_t thresh62; 797 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; 798 uint8_t xpdGain; 799 uint8_t xpd; 800 int8_t iqCalICh[AR5416_MAX_CHAINS]; 801 int8_t iqCalQCh[AR5416_MAX_CHAINS]; 802 uint8_t pdGainOverlap; 803 uint8_t ob; 804 uint8_t db; 805 uint8_t xpaBiasLvl; 806 uint8_t pwrDecreaseFor2Chain; 807 uint8_t pwrDecreaseFor3Chain; 808 uint8_t txFrameToDataStart; 809 uint8_t txFrameToPaOn; 810 uint8_t ht40PowerIncForPdadc; 811 uint8_t bswAtten[AR5416_MAX_CHAINS]; 812 uint8_t bswMargin[AR5416_MAX_CHAINS]; 813 uint8_t swSettleHt40; 814 uint8_t futureModal[22]; 815 struct spurChanStruct spurChans[AR5416_EEPROM_MODAL_SPURS]; 816 } __packed; 817 818 struct calDataPerFreq { 819 uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 820 uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 821 } __packed; 822 823 struct CalTargetPowerLegacy { 824 uint8_t bChannel; 825 uint8_t tPow2x[4]; 826 } __packed; 827 828 struct CalTargetPowerHt { 829 uint8_t bChannel; 830 uint8_t tPow2x[8]; 831 } __packed; 832 833 struct CalCtlEdges { 834 uint8_t bChannel; 835 uint8_t tPowerFlag; 836 } __packed; 837 838 struct CalCtlData { 839 struct CalCtlEdges ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 840 } __packed; 841 842 struct ar5416eeprom { 843 struct BaseEepHeader baseEepHeader; 844 uint8_t custData[64]; 845 struct ModalEepHeader modalHeader[2]; 846 uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 847 uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 848 struct calDataPerFreq calPierData5G[AR5416_MAX_CHAINS] 849 [AR5416_NUM_5G_CAL_PIERS]; 850 struct calDataPerFreq calPierData2G[AR5416_MAX_CHAINS] 851 [AR5416_NUM_2G_CAL_PIERS]; 852 struct CalTargetPowerLegacy calTPow5G[AR5416_NUM_5G_20_TARGET_POWERS]; 853 struct CalTargetPowerHt calTPow5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 854 struct CalTargetPowerHt calTPow5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 855 struct CalTargetPowerLegacy calTPowCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 856 struct CalTargetPowerLegacy calTPow2G[AR5416_NUM_2G_20_TARGET_POWERS]; 857 struct CalTargetPowerHt calTPow2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 858 struct CalTargetPowerHt calTPow2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 859 uint8_t ctlIndex[AR5416_NUM_CTLS]; 860 struct CalCtlData ctlData[AR5416_NUM_CTLS]; 861 uint8_t padding; 862 } __packed; 863 864 #define OTUS_NUM_CHAINS 2 865 866 #define OTUS_UID(aid) (IEEE80211_AID(aid) + 4) 867 868 #define OTUS_MAX_TXCMDSZ 64 869 #define OTUS_RXBUFSZ (8 * 1024) 870 /* Bumped for later A-MSDU and legacy fast-frames TX support */ 871 #define OTUS_TXBUFSZ (8 * 1024) 872 873 /* Default EDCA parameters for when QoS is disabled. */ 874 static const struct wmeParams otus_edca_def[WME_NUM_AC] = { 875 { 4, 10, 3, 0 }, 876 { 4, 10, 7, 0 }, 877 { 3, 4, 2, 94 }, 878 { 2, 3, 2, 47 } 879 }; 880 881 #define OTUS_RIDX_CCK1 0 882 #define OTUS_RIDX_OFDM6 4 883 #define OTUS_RIDX_OFDM24 8 884 #define OTUS_RIDX_MAX 11 885 static const struct otus_rate { 886 uint8_t rate; 887 uint8_t mcs; 888 } otus_rates[] = { 889 { 2, 0x0 }, 890 { 4, 0x1 }, 891 { 11, 0x2 }, 892 { 22, 0x3 }, 893 { 12, 0xb }, 894 { 18, 0xf }, 895 { 24, 0xa }, 896 { 36, 0xe }, 897 { 48, 0x9 }, 898 { 72, 0xd }, 899 { 96, 0x8 }, 900 { 108, 0xc } 901 }; 902 903 struct otus_rx_radiotap_header { 904 struct ieee80211_radiotap_header wr_ihdr; 905 uint8_t wr_flags; 906 uint8_t wr_rate; 907 uint16_t wr_chan_freq; 908 uint16_t wr_chan_flags; 909 uint8_t wr_antsignal; 910 } __packed __aligned(8); 911 912 #define OTUS_RX_RADIOTAP_PRESENT \ 913 (1 << IEEE80211_RADIOTAP_FLAGS | \ 914 1 << IEEE80211_RADIOTAP_RATE | \ 915 1 << IEEE80211_RADIOTAP_CHANNEL | \ 916 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) 917 918 struct otus_tx_radiotap_header { 919 struct ieee80211_radiotap_header wt_ihdr; 920 uint8_t wt_flags; 921 uint8_t wt_rate; 922 uint16_t wt_chan_freq; 923 uint16_t wt_chan_flags; 924 } __packed; 925 926 #define OTUS_TX_RADIOTAP_PRESENT \ 927 (1 << IEEE80211_RADIOTAP_FLAGS | \ 928 1 << IEEE80211_RADIOTAP_RATE | \ 929 1 << IEEE80211_RADIOTAP_CHANNEL) 930 931 struct otus_softc; 932 933 /* Firmware commands */ 934 struct otus_tx_cmd { 935 uint8_t *buf; 936 uint16_t buflen; 937 void *odata; 938 uint16_t odatalen; 939 uint16_t token; 940 STAILQ_ENTRY(otus_tx_cmd) next_cmd; 941 }; 942 943 /* TX, RX buffers */ 944 struct otus_data { 945 struct otus_softc *sc; 946 uint8_t *buf; 947 uint16_t buflen; 948 struct mbuf *m; 949 struct ieee80211_node *ni; 950 STAILQ_ENTRY(otus_data) next; 951 }; 952 953 struct otus_node { 954 struct ieee80211_node ni; 955 uint64_t tx_done; 956 uint64_t tx_err; 957 uint64_t tx_retries; 958 }; 959 960 #define OTUS_CONFIG_INDEX 0 961 #define OTUS_IFACE_INDEX 0 962 963 /* 964 * The carl9170 firmware has the following specification: 965 * 966 * 0 - USB control 967 * 1 - TX 968 * 2 - RX 969 * 3 - IRQ 970 * 4 - CMD 971 * .. 972 * 10 - end 973 */ 974 enum { 975 OTUS_BULK_TX, 976 OTUS_BULK_RX, 977 OTUS_BULK_IRQ, 978 OTUS_BULK_CMD, 979 OTUS_N_XFER 980 }; 981 982 struct otus_vap { 983 struct ieee80211vap vap; 984 int (*newstate)(struct ieee80211vap *, 985 enum ieee80211_state, int); 986 }; 987 #define OTUS_VAP(vap) ((struct otus_vap *)(vap)) 988 #define OTUS_NODE(ni) ((struct otus_node *)(ni)) 989 990 #define OTUS_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 991 #define OTUS_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 992 #define OTUS_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 993 #define OTUS_UNLOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_NOTOWNED) 994 995 /* XXX the TX/RX endpoint dump says it's 0x200, (512)? */ 996 #define OTUS_MAX_TXSZ 512 997 #define OTUS_MAX_RXSZ 512 998 /* intr/cmd endpoint dump says 0x40 */ 999 #define OTUS_MAX_CTRLSZ 64 1000 1001 #define OTUS_CMD_LIST_COUNT 32 1002 #define OTUS_RX_LIST_COUNT 128 1003 #define OTUS_TX_LIST_COUNT 32 1004 1005 struct otus_softc { 1006 struct ieee80211com sc_ic; 1007 struct ieee80211_ratectl_tx_stats sc_txs; 1008 struct mbufq sc_snd; 1009 device_t sc_dev; 1010 struct usb_device *sc_udev; 1011 int (*sc_newstate)(struct ieee80211com *, 1012 enum ieee80211_state, int); 1013 void (*sc_led_newstate)(struct otus_softc *); 1014 struct usbd_interface *sc_iface; 1015 struct mtx sc_mtx; 1016 1017 struct ar5416eeprom eeprom; 1018 uint8_t capflags; 1019 uint8_t rxmask; 1020 uint8_t txmask; 1021 bool sc_running:1, 1022 sc_calibrating:1, 1023 sc_scanning:1; 1024 1025 int sc_if_flags; 1026 int sc_tx_timer; 1027 int fixed_ridx; 1028 int bb_reset; 1029 1030 struct ieee80211_channel *sc_curchan; 1031 1032 struct task tx_task; 1033 struct timeout_task scan_to; 1034 struct timeout_task calib_to; 1035 1036 /* register batch writes */ 1037 int write_idx; 1038 1039 uint32_t led_state; 1040 1041 /* current firmware message serial / token number */ 1042 int token; 1043 1044 /* current noisefloor, from SET_FREQUENCY */ 1045 int sc_nf[OTUS_NUM_CHAINS]; 1046 1047 /* How many pending, active transmit frames */ 1048 int sc_tx_n_pending; 1049 int sc_tx_n_active; 1050 1051 const uint32_t *phy_vals; 1052 1053 struct { 1054 uint32_t reg; 1055 uint32_t val; 1056 } __packed write_buf[AR_MAX_WRITE_IDX + 1]; 1057 1058 struct otus_data sc_rx[OTUS_RX_LIST_COUNT]; 1059 struct otus_data sc_tx[OTUS_TX_LIST_COUNT]; 1060 struct otus_tx_cmd sc_cmd[OTUS_CMD_LIST_COUNT]; 1061 1062 struct usb_xfer *sc_xfer[OTUS_N_XFER]; 1063 1064 /* Last seen PLCP header; for A-MPDU decap */ 1065 uint8_t ar_last_rx_plcp[AR_PLCP_HDR_LEN]; 1066 1067 STAILQ_HEAD(, otus_data) sc_rx_active; 1068 STAILQ_HEAD(, otus_data) sc_rx_inactive; 1069 STAILQ_HEAD(, otus_data) sc_tx_active[OTUS_N_XFER]; 1070 STAILQ_HEAD(, otus_data) sc_tx_inactive; 1071 STAILQ_HEAD(, otus_data) sc_tx_pending[OTUS_N_XFER]; 1072 1073 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_active; 1074 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_inactive; 1075 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_pending; 1076 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_waiting; 1077 1078 union { 1079 struct otus_rx_radiotap_header th; 1080 uint8_t pad[64]; 1081 } sc_rxtapu; 1082 #define sc_rxtap sc_rxtapu.th 1083 1084 union { 1085 struct otus_tx_radiotap_header th; 1086 uint8_t pad[64]; 1087 } sc_txtapu; 1088 #define sc_txtap sc_txtapu.th 1089 }; 1090 1091 #endif /* __IF_OTUSREG_H__ */ 1092