1 /* $OpenBSD: if_otusreg.h,v 1.9 2013/11/26 20:33:18 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2007-2008 Atheros Communications, Inc. 6 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 * $FreeBSD$ 21 */ 22 #ifndef __IF_OTUSREG_H__ 23 #define __IF_OTUSREG_H__ 24 25 /* USB Endpoints addresses. */ 26 #define AR_EPT_BULK_TX_NO (UE_DIR_OUT | 1) 27 #define AR_EPT_BULK_RX_NO (UE_DIR_IN | 2) 28 #define AR_EPT_INTR_RX_NO (UE_DIR_IN | 3) 29 #define AR_EPT_INTR_TX_NO (UE_DIR_OUT | 4) 30 31 /* USB Requests. */ 32 #define AR_FW_DOWNLOAD 0x30 33 #define AR_FW_DOWNLOAD_COMPLETE 0x31 34 35 /* Maximum number of writes that can fit in a single FW command is 7. */ 36 #define AR_MAX_WRITE_IDX 6 /* 56 bytes */ 37 38 #define AR_FW_INIT_ADDR 0x102800 39 #define AR_FW_MAIN_ADDR 0x200000 40 #define AR_USB_MODE_CTRL 0x1e1108 41 42 /* 43 * AR9170 MAC registers. 44 */ 45 #define AR_MAC_REG_BASE 0x1c3000 46 #define AR_MAC_REG_DMA_TRIGGER (AR_MAC_REG_BASE + 0xd30) 47 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610) 48 #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614) 49 #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618) 50 #define AR_MAC_REG_BSSID_H (AR_MAC_REG_BASE + 0x61c) 51 #define AR_MAC_REG_GROUP_HASH_TBL_L (AR_MAC_REG_BASE + 0x624) 52 #define AR_MAC_REG_GROUP_HASH_TBL_H (AR_MAC_REG_BASE + 0x628) 53 #define AR_MAC_REG_RX_TIMEOUT (AR_MAC_REG_BASE + 0x62c) 54 #define AR_MAC_REG_BASIC_RATE (AR_MAC_REG_BASE + 0x630) 55 #define AR_MAC_REG_MANDATORY_RATE (AR_MAC_REG_BASE + 0x634) 56 #define AR_MAC_REG_RTS_CTS_RATE (AR_MAC_REG_BASE + 0x638) 57 #define AR_MAC_REG_BACKOFF_PROTECT (AR_MAC_REG_BASE + 0x63c) 58 #define AR_MAC_REG_RX_THRESHOLD (AR_MAC_REG_BASE + 0x640) 59 #define AR_MAC_REG_RX_PE_DELAY (AR_MAC_REG_BASE + 0x64c) 60 #define AR_MAC_REG_DYNAMIC_SIFS_ACK (AR_MAC_REG_BASE + 0x658) 61 #define AR_MAC_REG_SNIFFER (AR_MAC_REG_BASE + 0x674) 62 #define AR_MAC_SNIFFER_DEFAULTS 0x02000000 63 #define AR_MAC_SNIFFER_ENABLE_PROMISC 0x1 64 #define AR_MAC_REG_ENCRYPTION (AR_MAC_REG_BASE + 0x678) 65 #define AR_MAC_REG_MISC_680 (AR_MAC_REG_BASE + 0x680) 66 #define AR_MAC_REG_FRAMETYPE_FILTER (AR_MAC_REG_BASE + 0x68c) 67 #define AR_MAC_REG_ACK_EXTENSION (AR_MAC_REG_BASE + 0x690) 68 #define AR_MAC_REG_ACK_TPC (AR_MAC_REG_BASE + 0x694) 69 #define AR_MAC_REG_EIFS_AND_SIFS (AR_MAC_REG_BASE + 0x698) 70 #define AR_MAC_REG_BUSY (AR_MAC_REG_BASE + 0x6e8) 71 #define AR_MAC_REG_BUSY_EXT (AR_MAC_REG_BASE + 0x6ec) 72 #define AR_MAC_REG_SLOT_TIME (AR_MAC_REG_BASE + 0x6f0) 73 #define AR_MAC_REG_CAM_MODE (AR_MAC_REG_BASE + 0x700) 74 #define AR_MAC_CAM_DEFAULTS (0xf << 24) 75 #define AR_MAC_CAM_IBSS 0xe0 76 #define AR_MAC_CAM_AP 0xa1 77 #define AR_MAC_CAM_STA 0x2 78 #define AR_MAC_CAM_AP_WDS 0x3 79 #define AR_MAC_REG_AC0_CW (AR_MAC_REG_BASE + 0xb00) 80 #define AR_MAC_REG_AC1_CW (AR_MAC_REG_BASE + 0xb04) 81 #define AR_MAC_REG_AC2_CW (AR_MAC_REG_BASE + 0xb08) 82 #define AR_MAC_REG_AC3_CW (AR_MAC_REG_BASE + 0xb0c) 83 #define AR_MAC_REG_AC4_CW (AR_MAC_REG_BASE + 0xb10) 84 #define AR_MAC_REG_AC1_AC0_AIFS (AR_MAC_REG_BASE + 0xb14) 85 #define AR_MAC_REG_AC3_AC2_AIFS (AR_MAC_REG_BASE + 0xb18) 86 #define AR_MAC_REG_RETRY_MAX (AR_MAC_REG_BASE + 0xb28) 87 #define AR_MAC_REG_TID_CFACK_CFEND_RATE (AR_MAC_REG_BASE + 0xb2c) 88 #define AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION \ 89 (AR_MAC_REG_BASE + 0xb30) 90 #define AR_MAC_REG_TXOP_DURATION (AR_MAC_REG_BASE + 0xb38) 91 #define AR_MAC_REG_AC1_AC0_TXOP (AR_MAC_REG_BASE + 0xb44) 92 #define AR_MAC_REG_AC3_AC2_TXOP (AR_MAC_REG_BASE + 0xb48) 93 #define AR_MAC_REG_AMPDU_FACTOR (AR_MAC_REG_BASE + 0xb9c) 94 #define AR_MAC_REG_FCS_SELECT (AR_MAC_REG_BASE + 0xbb0) 95 #define AR_MAC_REG_RX_CONTROL (AR_MAC_REG_BASE + 0xc40) 96 #define AR_MAC_RX_CTRL_DEAGG 0x1 97 #define AR_MAC_RX_CTRL_SHORT_FILTER 0x2 98 #define AR_MAC_RX_CTRL_SA_DA_SEARCH 0x20 99 #define AR_MAC_RX_CTRL_PASS_TO_HOST (1 << 28) 100 #define AR_MAC_RX_CTRL_ACK_IN_SNIFFER (1 << 30) 101 102 #define AR_MAC_REG_AMPDU_RX_THRESH (AR_MAC_REG_BASE + 0xc50) 103 #define AR_MAC_REG_OFDM_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb4) 104 #define AR_MAC_REG_CCK_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb8) 105 #define AR_MAC_REG_TXRX_MPI (AR_MAC_REG_BASE + 0xd7c) 106 #define AR_MAC_REG_BCN_HT1 (AR_MAC_REG_BASE + 0xda0) 107 108 /* Possible values for register AR_USB_MODE_CTRL. */ 109 #define AR_USB_DS_ENA (1 << 0) 110 #define AR_USB_US_ENA (1 << 1) 111 #define AR_USB_US_PACKET_MODE (1 << 3) 112 #define AR_USB_RX_STREAM_4K (0 << 4) 113 #define AR_USB_RX_STREAM_8K (1 << 4) 114 #define AR_USB_RX_STREAM_16K (2 << 4) 115 #define AR_USB_RX_STREAM_32K (3 << 4) 116 #define AR_USB_TX_STREAM_MODE (1 << 6) 117 118 #define AR_LED0_ON (1 << 0) 119 #define AR_LED1_ON (1 << 1) 120 121 /* 122 * PHY registers. 123 */ 124 #define AR_PHY_BASE 0x1c5800 125 #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4) 126 #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004) 127 #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028) 128 #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034) 129 #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044) 130 #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048) 131 #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050) 132 #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058) 133 #define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c) 134 #define AR_PHY_SFCORR (AR_PHY_BASE + 0x0068) 135 #define AR_PHY_SFCORR_LOW (AR_PHY_BASE + 0x006c) 136 #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) 137 #define AR_PHY_TIMING5 (AR_PHY_BASE + 0x0124) 138 #define AR_PHY_POWER_TX_RATE1 (AR_PHY_BASE + 0x0134) 139 #define AR_PHY_POWER_TX_RATE2 (AR_PHY_BASE + 0x0138) 140 #define AR_PHY_POWER_TX_RATE_MAX (AR_PHY_BASE + 0x013c) 141 #define AR_PHY_SWITCH_CHAIN_0 (AR_PHY_BASE + 0x0160) 142 #define AR_PHY_SWITCH_COM (AR_PHY_BASE + 0x0164) 143 #define AR_PHY_HEAVY_CLIP_ENABLE (AR_PHY_BASE + 0x01e0) 144 #define AR_PHY_CCK_DETECT (AR_PHY_BASE + 0x0a08) 145 #define AR_PHY_GAIN_2GHZ (AR_PHY_BASE + 0x0a0c) 146 #define AR_PHY_POWER_TX_RATE3 (AR_PHY_BASE + 0x0a34) 147 #define AR_PHY_POWER_TX_RATE4 (AR_PHY_BASE + 0x0a38) 148 #define AR_PHY_TPCRG1 (AR_PHY_BASE + 0x0a58) 149 #define AR_PHY_POWER_TX_RATE5 (AR_PHY_BASE + 0x0b8c) 150 #define AR_PHY_POWER_TX_RATE6 (AR_PHY_BASE + 0x0b90) 151 #define AR_PHY_POWER_TX_RATE7 (AR_PHY_BASE + 0x0bcc) 152 #define AR_PHY_POWER_TX_RATE8 (AR_PHY_BASE + 0x0bd0) 153 #define AR_PHY_POWER_TX_RATE9 (AR_PHY_BASE + 0x0bd4) 154 #define AR_PHY_CCA (AR_PHY_BASE + 0x3064) 155 156 #define AR_SEEPROM_HW_TYPE_OFFSET 0x1374 157 #define AR_EEPROM_OFFSET 0x1600 158 159 #define AR_BANK4_CHUP (1 << 0) 160 #define AR_BANK4_BMODE_LF_SYNTH_FREQ (1 << 1) 161 #define AR_BANK4_AMODE_REFSEL(x) ((x) << 2) 162 #define AR_BANK4_ADDR(x) ((x) << 5) 163 164 /* 165 * Random number generator. 166 */ 167 #define AR_RAND_REG_BASE 0x1d0000 168 169 /* 170 * GPIO. 171 */ 172 #define AR_GPIO_REG_BASE 0x1d0100 173 174 #define AR_GPIO_REG_PORT_TYPE (AR_GPIO_REG_BASE + 0x000) 175 #define AR_GPIO_REG_PORT_DATA (AR_GPIO_REG_BASE + 0x004) 176 #define AR_GPIO_PORT_LED_0 1 177 #define AR_GPIO_PORT_LED_1 2 178 /* WPS Button GPIO for TP-Link TL-WN821N */ 179 #define AR_GPIO_PORT_WPS_BUTTON_PRESSED 4 180 181 /* 182 * Power Management. 183 */ 184 #define AR_PWR_REG_BASE 0x1d4000 185 186 #define AR_PWR_REG_RESET (AR_PWR_REG_BASE + 0x004) 187 #define AR_PWR_REG_CLOCK_SEL (AR_PWR_REG_BASE + 0x008) 188 #define AR_PWR_REG_PLL_ADDAC (AR_PWR_REG_BASE + 0x014) 189 190 /* Tx descriptor. */ 191 struct ar_tx_head { 192 uint16_t len; 193 uint16_t macctl; 194 #define AR_TX_MAC_RTS (1 << 0) 195 #define AR_TX_MAC_CTS (1 << 1) 196 #define AR_TX_MAC_BACKOFF (1 << 3) 197 #define AR_TX_MAC_NOACK (1 << 2) 198 #define AR_TX_MAC_HW_DUR (1 << 9) 199 #define AR_TX_MAC_QID(qid) ((qid) << 10) 200 #define AR_TX_MAC_RATE_PROBING (1 << 15) 201 202 uint32_t phyctl; 203 /* Modulation type. */ 204 #define AR_TX_PHY_MT_SHIFT 0 /* 0:1 - PHY mode */ 205 #define AR_TX_PHY_MT_CCK 0 206 #define AR_TX_PHY_MT_OFDM 1 207 #define AR_TX_PHY_MT_HT 2 208 #define AR_TX_PHY_GF (1 << 2) /* 2 - greenfield */ 209 #define AR_TX_PHY_BW_SHIFT 3 /* 4:3 - bandwidth */ 210 #define AR_TX_PHY_BW_20MHZ 0 211 #define AR_TX_PHY_BW_40MHZ 2 212 #define AR_TX_PHY_BW_40MHZ_DUP 3 213 #define AR_TX_PHY_TX_HEAVY_CLIP_SHIFT 6 /* 9:6 - heavy clip */ 214 #define AR_TX_PHY_TPC_SHIFT 9 /* 14:9 - TX power */ 215 #define AR_TX_PHY_ANTMSK(msk) ((msk) << 15) 216 #define AR_TX_PHY_MCS(mcs) ((mcs) << 18) 217 #define AR_TX_PHY_SHGI (1U << 31) 218 } __packed; 219 220 /* USB Rx stream mode header. */ 221 struct ar_rx_head { 222 uint16_t len; 223 uint16_t tag; 224 #define AR_RX_HEAD_TAG 0x4e00 225 } __packed; 226 227 /* Rx descriptor. */ 228 229 struct ar_rx_macstatus { 230 uint8_t sa_idx; 231 uint8_t da_idx; 232 uint8_t error; 233 #define AR_RX_ERROR_TIMEOUT (1 << 0) 234 #define AR_RX_ERROR_OVERRUN (1 << 1) 235 #define AR_RX_ERROR_DECRYPT (1 << 2) 236 #define AR_RX_ERROR_FCS (1 << 3) 237 #define AR_RX_ERROR_BAD_RA (1 << 4) 238 #define AR_RX_ERROR_PLCP (1 << 5) 239 #define AR_RX_ERROR_MMIC (1 << 6) 240 uint8_t status; 241 /* Modulation type (same as AR_TX_PHY_MT). */ 242 #define AR_RX_STATUS_MT_MASK 0x3 243 #define AR_RX_STATUS_MT_CCK 0 244 #define AR_RX_STATUS_MT_OFDM 1 245 #define AR_RX_STATUS_MT_HT 2 246 #define AR_RX_STATUS_SHPREAMBLE (1 << 3) 247 #define AR_RX_STATUS_MPDU_MASK 0x30 248 #define AR_RX_STATUS_MPDU_SINGLE 0x00 249 #define AR_RX_STATUS_MPDU_LAST 0x10 250 #define AR_RX_STATUS_MPDU_FIRST 0x20 251 #define AR_RX_STATUS_MPDU_MIDDLE 0x30 252 } __packed; 253 254 struct ar_rx_phystatus { 255 uint8_t rssi_ant[3]; 256 uint8_t rssi_ant_ext[3]; 257 uint8_t rssi; /* Combined RSSI. */ 258 uint8_t evm[2][6]; /* Error Vector Magnitude. */ 259 uint8_t phy_err; 260 } __packed; 261 262 #define AR_PLCP_HDR_LEN 12 263 /* Magic PLCP header for firmware notifications through Rx bulk pipe. */ 264 static uint8_t AR_PLCP_HDR_INTR[] = { 265 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 266 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 267 }; 268 269 /* Firmware command/reply header. */ 270 struct ar_cmd_hdr { 271 uint8_t len; 272 uint8_t code; 273 #define AR_CMD_RREG 0x00 274 #define AR_CMD_WREG 0x01 275 #define AR_CMD_RMEM 0x02 276 #define AR_CMD_WMEM 0x03 277 #define AR_CMD_BITAND 0x04 278 #define AR_CMD_BITOR 0x05 279 #define AR_CMD_EKEY 0x28 280 #define AR_CMD_DKEY 0x29 281 #define AR_CMD_FREQUENCY 0x30 282 #define AR_CMD_RF_INIT 0x31 283 #define AR_CMD_SYNTH 0x32 284 #define AR_CMD_FREQ_STRAT 0x33 285 #define AR_CMD_ECHO 0x80 286 #define AR_CMD_TALLY 0x81 287 #define AR_CMD_TALLY_APD 0x82 288 #define AR_CMD_CONFIG 0x83 289 #define AR_CMD_RESET 0x90 290 #define AR_CMD_DKRESET 0x91 291 #define AR_CMD_DKTX_STATUS 0x92 292 #define AR_CMD_FDC 0xa0 293 #define AR_CMD_WREEPROM 0xb0 294 #define AR_CMD_WFLASH AR_CMD_WREEPROM 295 #define AR_CMD_FLASH_ERASE 0xb1 296 #define AR_CMD_FLASH_PROG 0xb2 297 #define AR_CMD_FLASH_CHKSUM 0xb3 298 #define AR_CMD_FLASH_READ 0xb4 299 #define AR_CMD_FW_DL_INIT 0xb5 300 #define AR_CMD_MEM_WREEPROM 0xbb 301 /* Those have the 2 MSB set to 1. */ 302 #define AR_EVT_BEACON 0x00 303 #define AR_EVT_TX_COMP 0x01 304 #define AR_EVT_TBTT 0x02 305 #define AR_EVT_ATIM 0x03 306 #define AR_EVT_DO_BB_RESET 0x09 307 308 uint16_t token; /* Driver private data. */ 309 } __packed; 310 311 /* Structure for command AR_CMD_RF_INIT/AR_CMD_FREQUENCY. */ 312 struct ar_cmd_frequency { 313 uint32_t freq; 314 uint32_t dynht2040; 315 uint32_t htena; 316 uint32_t dsc_exp; 317 uint32_t dsc_man; 318 uint32_t dsc_shgi_exp; 319 uint32_t dsc_shgi_man; 320 uint32_t check_loop_count; 321 } __packed; 322 323 /* Firmware reply for command AR_CMD_FREQUENCY. */ 324 struct ar_rsp_frequency { 325 uint32_t status; 326 #define AR_CAL_ERR_AGC (1 << 0) /* AGC cal unfinished. */ 327 #define AR_CAL_ERR_NF (1 << 1) /* Noise cal unfinished. */ 328 #define AR_CAL_ERR_NF_VAL (1 << 2) /* NF value unexpected. */ 329 330 uint32_t nf[3]; /* Noisefloor. */ 331 uint32_t nf_ext[3]; /* Noisefloor ext. */ 332 } __packed; 333 334 /* Structure for command AR_CMD_EKEY. */ 335 struct ar_cmd_ekey { 336 uint16_t uid; /* user ID */ 337 uint16_t kix; 338 uint16_t cipher; 339 #define AR_CIPHER_NONE 0 340 #define AR_CIPHER_WEP64 1 341 #define AR_CIPHER_TKIP 2 342 #define AR_CIPHER_AES 4 343 #define AR_CIPHER_WEP128 5 344 #define AR_CIPHER_WEP256 6 345 #define AR_CIPHER_CENC 7 346 347 uint8_t macaddr[IEEE80211_ADDR_LEN]; 348 uint8_t key[16]; 349 } __packed; 350 351 /* Structure for event AR_EVT_TX_COMP. */ 352 struct ar_evt_tx_comp { 353 uint8_t macaddr[IEEE80211_ADDR_LEN]; 354 uint32_t phy; 355 uint16_t status; 356 #define AR_TX_STATUS_COMP 0 357 #define AR_TX_STATUS_RETRY_COMP 1 358 #define AR_TX_STATUS_FAILED 2 359 } __packed; 360 361 /* List of supported channels. */ 362 static const uint8_t ar_chans[] = { 363 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 364 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 100, 104, 108, 365 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 366 }; 367 368 /* 369 * This data is automatically generated from the "otus.ini" file. 370 * It is stored in a different way though, to reduce kernel's .rodata 371 * section overhead (5.1KB instead of 8.5KB). 372 */ 373 374 /* NB: apply AR_PHY(). */ 375 static const uint16_t ar5416_phy_regs[] = { 376 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 0x008, 377 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 0x010, 0x011, 378 0x012, 0x013, 0x014, 0x015, 0x016, 0x017, 0x018, 0x01a, 0x01b, 379 0x040, 0x041, 0x042, 0x043, 0x045, 0x046, 0x047, 0x048, 0x049, 380 0x04a, 0x04b, 0x04d, 0x04e, 0x04f, 0x051, 0x052, 0x053, 0x055, 381 0x056, 0x058, 0x059, 0x05c, 0x05d, 0x05e, 0x05f, 0x060, 0x061, 382 0x062, 0x063, 0x064, 0x065, 0x066, 0x067, 0x068, 0x069, 0x06a, 383 0x06b, 0x06c, 0x06d, 0x070, 0x071, 0x072, 0x073, 0x074, 0x075, 384 0x076, 0x077, 0x078, 0x079, 0x07a, 0x07b, 0x07c, 0x07f, 0x080, 385 0x081, 0x082, 0x083, 0x084, 0x085, 0x086, 0x087, 0x088, 0x089, 386 0x08a, 0x08b, 0x08c, 0x08d, 0x08e, 0x08f, 0x090, 0x091, 0x092, 387 0x093, 0x094, 0x095, 0x096, 0x097, 0x098, 0x099, 0x09a, 0x09b, 388 0x09c, 0x09d, 0x09e, 0x09f, 0x0a0, 0x0a1, 0x0a2, 0x0a3, 0x0a4, 389 0x0a5, 0x0a6, 0x0a7, 0x0a8, 0x0a9, 0x0aa, 0x0ab, 0x0ac, 0x0ad, 390 0x0ae, 0x0af, 0x0b0, 0x0b1, 0x0b2, 0x0b3, 0x0b4, 0x0b5, 0x0b6, 391 0x0b7, 0x0b8, 0x0b9, 0x0ba, 0x0bb, 0x0bc, 0x0bd, 0x0be, 0x0bf, 392 0x0c0, 0x0c1, 0x0c2, 0x0c3, 0x0c4, 0x0c5, 0x0c6, 0x0c7, 0x0c8, 393 0x0c9, 0x0ca, 0x0cb, 0x0cc, 0x0cd, 0x0ce, 0x0cf, 0x0d0, 0x0d1, 394 0x0d2, 0x0d3, 0x0d4, 0x0d5, 0x0d6, 0x0d7, 0x0d8, 0x0d9, 0x0da, 395 0x0db, 0x0dc, 0x0dd, 0x0de, 0x0df, 0x0e0, 0x0e1, 0x0e2, 0x0e3, 396 0x0e4, 0x0e5, 0x0e6, 0x0e7, 0x0e8, 0x0e9, 0x0ea, 0x0eb, 0x0ec, 397 0x0ed, 0x0ee, 0x0ef, 0x0f0, 0x0f1, 0x0f2, 0x0f3, 0x0f4, 0x0f5, 398 0x0f6, 0x0f7, 0x0f8, 0x0f9, 0x0fa, 0x0fb, 0x0fc, 0x0fd, 0x0fe, 399 0x0ff, 0x100, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 400 0x10a, 0x10b, 0x10c, 0x10d, 0x10e, 0x10f, 0x13c, 0x13d, 0x13e, 401 0x13f, 0x280, 0x281, 0x282, 0x283, 0x284, 0x285, 0x286, 0x287, 402 0x288, 0x289, 0x28a, 0x28b, 0x28c, 0x28d, 0x28e, 0x28f, 0x290, 403 0x291, 0x292, 0x293, 0x294, 0x295, 0x296, 0x297, 0x298, 0x299, 404 0x29a, 0x29b, 0x29d, 0x29e, 0x29f, 0x2c0, 0x2c1, 0x2c2, 0x2c3, 405 0x2c4, 0x2c5, 0x2c6, 0x2c7, 0x2c8, 0x2c9, 0x2ca, 0x2cb, 0x2cc, 406 0x2cd, 0x2ce, 0x2cf, 0x2d0, 0x2d1, 0x2d2, 0x2d3, 0x2d4, 0x2d5, 407 0x2d6, 0x2e2, 0x2e3, 0x2e4, 0x2e5, 0x2e6, 0x2e7, 0x2e8, 0x2e9, 408 0x2ea, 0x2eb, 0x2ec, 0x2ed, 0x2ee, 0x2ef, 0x2f0, 0x2f1, 0x2f2, 409 0x2f3, 0x2f4, 0x2f5, 0x2f6, 0x2f7, 0x2f8, 0x412, 0x448, 0x458, 410 0x683, 0x69b, 0x812, 0x848, 0x858, 0xa83, 0xa9b, 0xc19, 0xc57, 411 0xc5a, 0xc6f, 0xe9c, 0xed7, 0xed8, 0xed9, 0xeda, 0xedb, 0xedc, 412 0xedd, 0xede, 0xedf, 0xee0, 0xee1 413 }; 414 415 static const uint32_t ar5416_phy_vals_5ghz_20mhz[] = { 416 0x00000007, 0x00000300, 0x00000000, 0xad848e19, 0x7d14e000, 417 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 418 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 419 0x00200400, 0x206a002e, 0x1372161e, 0x001a6a65, 0x1284233c, 420 0x6c48b4e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd10, 421 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 422 0x00000000, 0x000007d0, 0x00000118, 0x10000fff, 0x0510081c, 423 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 424 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 425 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 426 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 427 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 428 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 429 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 430 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 431 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 432 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1, 433 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8, 434 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009, 435 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0, 436 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011, 437 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038, 438 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 439 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 440 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 441 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 442 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 443 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 444 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 445 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 446 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 447 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 448 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 449 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 450 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 451 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 452 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 453 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 454 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 455 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 456 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 457 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 458 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 459 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 460 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 461 0x00000000, 0x00000008, 0x00000440, 0xd6be4788, 0x012e8160, 462 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 463 0x00000400, 0x000009b5, 0x00000000, 0x00000108, 0x3f3f3f3f, 464 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 465 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 466 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a9caa, 467 0x1ce739ce, 0x051701ce, 0x18010000, 0x30032602, 0x48073e06, 468 0x560b4c0a, 0x641a600f, 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 469 0xb51fa69f, 0xcb3fbd07, 0x0000d7bf, 0x00000000, 0x00000000, 470 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 471 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 472 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 473 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 474 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 475 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 476 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a65, 0x0510001c, 477 0x00009b40, 0x012e8160, 0x09249126, 0x00180a65, 0x0510001c, 478 0x00009b40, 0x012e8160, 0x09249126, 0x0001c600, 0x004b6a8e, 479 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 480 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 481 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 482 }; 483 484 static const uint32_t ar5416_phy_vals_5ghz_40mhz[] = { 485 0x00000007, 0x000003c4, 0x00000000, 0xad848e19, 0x7d14e000, 486 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 487 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 488 0x00200400, 0x206a002e, 0x13721c1e, 0x001a6a65, 0x1284233c, 489 0x6c48b4e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd10, 490 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 491 0x00000000, 0x000007d0, 0x00000230, 0x10000fff, 0x0510081c, 492 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 493 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 494 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 495 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 496 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 497 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 498 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 499 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 500 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 501 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1, 502 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8, 503 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009, 504 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0, 505 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011, 506 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038, 507 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059, 508 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9, 509 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 510 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 511 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 512 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 513 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 514 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 515 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 516 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 517 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 518 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 519 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 520 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 521 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 522 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 523 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 524 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 525 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 526 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 527 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 528 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 529 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 530 0x00000000, 0x00000008, 0x00000440, 0xd6be4788, 0x012e8160, 531 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 532 0x00000400, 0x000009b5, 0x00000000, 0x00000210, 0x3f3f3f3f, 533 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 534 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 535 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a9caa, 536 0x1ce739ce, 0x051701ce, 0x18010000, 0x30032602, 0x48073e06, 537 0x560b4c0a, 0x641a600f, 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 538 0xb51fa69f, 0xcb3fbcbf, 0x0000d7bf, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 540 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 541 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 542 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 543 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 544 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 545 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a65, 0x0510001c, 546 0x00009b40, 0x012e8160, 0x09249126, 0x00180a65, 0x0510001c, 547 0x00009b40, 0x012e8160, 0x09249126, 0x0001c600, 0x004b6a8e, 548 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 549 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 550 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 551 }; 552 553 static const uint32_t ar5416_phy_vals_2ghz_40mhz[] = { 554 0x00000007, 0x000003c4, 0x00000000, 0xad848e19, 0x7d14e000, 555 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 556 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 557 0x00200400, 0x206a002e, 0x13721c24, 0x00197a68, 0x1284233c, 558 0x6c48b0e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd20, 559 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 560 0x00000000, 0x00000898, 0x00000268, 0x10000fff, 0x0510001c, 561 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 562 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 563 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 564 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 565 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 566 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 567 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 568 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 569 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 570 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181, 571 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8, 572 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9, 573 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0, 574 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191, 575 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8, 576 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199, 577 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 578 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 579 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 580 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 581 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 582 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 583 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 584 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 585 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 586 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 587 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 588 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 589 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 590 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 591 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 592 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 593 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 594 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 595 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 596 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 597 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 598 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 599 0x00000000, 0x0000000e, 0x00000440, 0xd03e4788, 0x012a8160, 600 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 601 0x00000400, 0x000009b5, 0x00000000, 0x00000210, 0x3f3f3f3f, 602 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 603 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 604 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a7caa, 605 0x1ce739ce, 0x051701ce, 0x18010000, 0x2e032402, 0x4a0a3c06, 606 0x621a540b, 0x764f6c1b, 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 607 0xbddfaf1f, 0xd1ffc93f, 0x00000000, 0x00000000, 0x00000000, 608 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 609 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 610 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 611 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 612 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 613 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 614 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a68, 0x0510001c, 615 0x00009b40, 0x012a8160, 0x09249126, 0x00180a68, 0x0510001c, 616 0x00009b40, 0x012a8160, 0x09249126, 0x0001c600, 0x004b6a8e, 617 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 618 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 619 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 620 }; 621 622 static const uint32_t ar5416_phy_vals_2ghz_20mhz[] = { 623 0x00000007, 0x00000300, 0x00000000, 0xad848e19, 0x7d14e000, 624 0x9c0a9f6b, 0x00000090, 0x00000000, 0x02020200, 0x00000e0e, 625 0x0a020001, 0x0000a000, 0x00000000, 0x00000e0e, 0x00000007, 626 0x00200400, 0x206a002e, 0x137216a4, 0x00197a68, 0x1284233c, 627 0x6c48b0e4, 0x00000859, 0x7ec80d2e, 0x31395c5e, 0x0004dd20, 628 0x409a4190, 0x050cb081, 0x00000000, 0x00000000, 0x00000000, 629 0x00000000, 0x00000898, 0x00000134, 0x10000fff, 0x0510001c, 630 0xd0058a15, 0x00000001, 0x00000004, 0x3f3f3f3f, 0x3f3f3f3f, 631 0x0000007f, 0xdfb81020, 0x9280b212, 0x00020028, 0x5d50e188, 632 0x00081fff, 0x00009b40, 0x00001120, 0x190fb515, 0x00000000, 633 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 634 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 635 0x00000000, 0x00000007, 0x001fff00, 0x006f00c4, 0x03051000, 636 0x00000820, 0x038919be, 0x06336f77, 0x60f6532c, 0x08f186c8, 637 0x00046384, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 638 0x64646464, 0x3c787878, 0x000000aa, 0x00000000, 0x00001042, 639 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181, 640 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8, 641 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9, 642 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0, 643 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191, 644 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8, 645 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199, 646 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9, 647 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 648 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 649 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 650 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 651 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x00000000, 652 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 653 0x00000008, 0x00000009, 0x0000000a, 0x0000000b, 0x0000000c, 654 0x0000000d, 0x00000010, 0x00000011, 0x00000012, 0x00000013, 655 0x00000014, 0x00000015, 0x00000018, 0x00000019, 0x0000001a, 656 0x0000001b, 0x0000001c, 0x0000001d, 0x00000020, 0x00000021, 657 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000028, 658 0x00000029, 0x0000002a, 0x0000002b, 0x0000002c, 0x0000002d, 659 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 660 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 661 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 662 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 663 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035, 664 0x00000035, 0x00000010, 0x0000001a, 0x00000000, 0x00000000, 665 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 666 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 667 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 668 0x00000000, 0x0000000e, 0x00000440, 0xd03e4788, 0x012a8160, 669 0x40806333, 0x00106c10, 0x009c4060, 0x1883800a, 0x018830c6, 670 0x00000400, 0x000009b5, 0x00000000, 0x00000108, 0x3f3f3f3f, 671 0x3f3f3f3f, 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 672 0x00000001, 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 673 0xdfa91f01, 0x00418a11, 0x00000000, 0x09249126, 0x0a1a7caa, 674 0x1ce739ce, 0x051701ce, 0x18010000, 0x2e032402, 0x4a0a3c06, 675 0x621a540b, 0x764f6c1b, 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 676 0xbddfaf1f, 0xd1ffc93f, 0x00000000, 0x00000000, 0x00000000, 677 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 678 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff, 0x79a8aa1f, 679 0x08000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x1ce739ce, 0x000001ce, 680 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 681 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 682 0x00000000, 0x00000000, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 683 0x00000000, 0x1ce739ce, 0x000000c0, 0x00180a68, 0x0510001c, 684 0x00009b40, 0x012a8160, 0x09249126, 0x00180a68, 0x0510001c, 685 0x00009b40, 0x012a8160, 0x09249126, 0x0001c600, 0x004b6a8e, 686 0x000003ce, 0x00181400, 0x00820820, 0x066c420f, 0x0f282207, 687 0x17601685, 0x1f801104, 0x37a00c03, 0x3fc40883, 0x57c00803, 688 0x5fd80682, 0x7fe00482, 0x7f3c7bba, 0xf3307ff0 689 }; 690 691 /* NB: apply AR_PHY(). */ 692 static const uint8_t ar5416_banks_regs[] = { 693 0x2c, 0x38, 0x2c, 0x3b, 0x2c, 0x38, 0x3c, 0x2c, 0x3a, 0x2c, 0x39, 694 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 695 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 696 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 697 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 698 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x38, 0x2c, 0x2c, 699 0x2c, 0x3c 700 }; 701 702 static const uint32_t ar5416_banks_vals_5ghz[] = { 703 0x1e5795e5, 0x02008020, 0x02108421, 0x00000008, 0x0e73ff17, 704 0x00000420, 0x01400018, 0x000001a1, 0x00000001, 0x00000013, 705 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 706 0x00000000, 0x00004000, 0x00006c00, 0x00002c00, 0x00004800, 707 0x00004000, 0x00006000, 0x00001000, 0x00004000, 0x00007c00, 708 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00087c00, 709 0x00007c00, 0x00005400, 0x00000c00, 0x00001800, 0x00007c00, 710 0x00006c00, 0x00006c00, 0x00007c00, 0x00002c00, 0x00003c00, 711 0x00003800, 0x00001c00, 0x00000800, 0x00000408, 0x00004c15, 712 0x00004188, 0x0000201e, 0x00010408, 0x00000801, 0x00000c08, 713 0x0000181e, 0x00001016, 0x00002800, 0x00004010, 0x0000081c, 714 0x00000115, 0x00000015, 0x00000066, 0x0000001c, 0x00000000, 715 0x00000004, 0x00000015, 0x0000001f, 0x00000000, 0x000000a0, 716 0x00000000, 0x00000040, 0x0000001c 717 }; 718 719 static const uint32_t ar5416_banks_vals_2ghz[] = { 720 0x1e5795e5, 0x02008020, 0x02108421, 0x00000008, 0x0e73ff17, 721 0x00000420, 0x01c00018, 0x000001a1, 0x00000001, 0x00000013, 722 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 723 0x00000000, 0x00004000, 0x00006c00, 0x00002c00, 0x00004800, 724 0x00004000, 0x00006000, 0x00001000, 0x00004000, 0x00007c00, 725 0x00007c00, 0x00007c00, 0x00007c00, 0x00007c00, 0x00087c00, 726 0x00007c00, 0x00005400, 0x00000c00, 0x00001800, 0x00007c00, 727 0x00006c00, 0x00006c00, 0x00007c00, 0x00002c00, 0x00003c00, 728 0x00003800, 0x00001c00, 0x00000800, 0x00000408, 0x00004c15, 729 0x00004188, 0x0000201e, 0x00010408, 0x00000801, 0x00000c08, 730 0x0000181e, 0x00001016, 0x00002800, 0x00004010, 0x0000081c, 731 0x00000115, 0x00000015, 0x00000066, 0x0000001c, 0x00000000, 732 0x00000004, 0x00000015, 0x0000001f, 0x00000400, 0x000000a0, 733 0x00000000, 0x00000040, 0x0000001c 734 }; 735 736 /* 737 * EEPROM. 738 */ 739 /* Possible flags for opCapFlags. */ 740 #define AR5416_OPFLAGS_11A 0x01 741 #define AR5416_OPFLAGS_11G 0x02 742 #define AR5416_OPFLAGS_5G_HT40 0x04 743 #define AR5416_OPFLAGS_2G_HT40 0x08 744 #define AR5416_OPFLAGS_5G_HT20 0x10 745 #define AR5416_OPFLAGS_2G_HT20 0x20 746 747 #define AR5416_NUM_5G_CAL_PIERS 8 748 #define AR5416_NUM_2G_CAL_PIERS 4 749 #define AR5416_NUM_5G_20_TARGET_POWERS 8 750 #define AR5416_NUM_5G_40_TARGET_POWERS 8 751 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 752 #define AR5416_NUM_2G_20_TARGET_POWERS 4 753 #define AR5416_NUM_2G_40_TARGET_POWERS 4 754 #define AR5416_NUM_CTLS 24 755 #define AR5416_NUM_BAND_EDGES 8 756 #define AR5416_NUM_PD_GAINS 4 757 #define AR5416_PD_GAIN_ICEPTS 5 758 #define AR5416_EEPROM_MODAL_SPURS 5 759 #define AR5416_MAX_CHAINS 2 760 761 struct BaseEepHeader { 762 uint16_t length; 763 uint16_t checksum; 764 uint16_t version; 765 uint8_t opCapFlags; 766 uint8_t eepMisc; 767 uint16_t regDmn[2]; 768 uint8_t macAddr[6]; 769 uint8_t rxMask; 770 uint8_t txMask; 771 uint16_t rfSilent; 772 uint16_t blueToothOptions; 773 uint16_t deviceCap; 774 uint32_t binBuildNumber; 775 uint8_t deviceType; 776 uint8_t futureBase[33]; 777 } __packed; 778 779 struct spurChanStruct { 780 uint16_t spurChan; 781 uint8_t spurRangeLow; 782 uint8_t spurRangeHigh; 783 } __packed; 784 785 struct ModalEepHeader { 786 uint32_t antCtrlChain[AR5416_MAX_CHAINS]; 787 uint32_t antCtrlCommon; 788 int8_t antennaGainCh[AR5416_MAX_CHAINS]; 789 uint8_t switchSettling; 790 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; 791 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; 792 uint8_t adcDesiredSize; 793 int8_t pgaDesiredSize; 794 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; 795 uint8_t txEndToXpaOff; 796 uint8_t txEndToRxOn; 797 uint8_t txFrameToXpaOn; 798 uint8_t thresh62; 799 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; 800 uint8_t xpdGain; 801 uint8_t xpd; 802 int8_t iqCalICh[AR5416_MAX_CHAINS]; 803 int8_t iqCalQCh[AR5416_MAX_CHAINS]; 804 uint8_t pdGainOverlap; 805 uint8_t ob; 806 uint8_t db; 807 uint8_t xpaBiasLvl; 808 uint8_t pwrDecreaseFor2Chain; 809 uint8_t pwrDecreaseFor3Chain; 810 uint8_t txFrameToDataStart; 811 uint8_t txFrameToPaOn; 812 uint8_t ht40PowerIncForPdadc; 813 uint8_t bswAtten[AR5416_MAX_CHAINS]; 814 uint8_t bswMargin[AR5416_MAX_CHAINS]; 815 uint8_t swSettleHt40; 816 uint8_t futureModal[22]; 817 struct spurChanStruct spurChans[AR5416_EEPROM_MODAL_SPURS]; 818 } __packed; 819 820 struct calDataPerFreq { 821 uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 822 uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 823 } __packed; 824 825 struct CalTargetPowerLegacy { 826 uint8_t bChannel; 827 uint8_t tPow2x[4]; 828 } __packed; 829 830 struct CalTargetPowerHt { 831 uint8_t bChannel; 832 uint8_t tPow2x[8]; 833 } __packed; 834 835 struct CalCtlEdges { 836 uint8_t bChannel; 837 uint8_t tPowerFlag; 838 } __packed; 839 840 struct CalCtlData { 841 struct CalCtlEdges ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 842 } __packed; 843 844 struct ar5416eeprom { 845 struct BaseEepHeader baseEepHeader; 846 uint8_t custData[64]; 847 struct ModalEepHeader modalHeader[2]; 848 uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 849 uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 850 struct calDataPerFreq calPierData5G[AR5416_MAX_CHAINS] 851 [AR5416_NUM_5G_CAL_PIERS]; 852 struct calDataPerFreq calPierData2G[AR5416_MAX_CHAINS] 853 [AR5416_NUM_2G_CAL_PIERS]; 854 struct CalTargetPowerLegacy calTPow5G[AR5416_NUM_5G_20_TARGET_POWERS]; 855 struct CalTargetPowerHt calTPow5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 856 struct CalTargetPowerHt calTPow5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 857 struct CalTargetPowerLegacy calTPowCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 858 struct CalTargetPowerLegacy calTPow2G[AR5416_NUM_2G_20_TARGET_POWERS]; 859 struct CalTargetPowerHt calTPow2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 860 struct CalTargetPowerHt calTPow2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 861 uint8_t ctlIndex[AR5416_NUM_CTLS]; 862 struct CalCtlData ctlData[AR5416_NUM_CTLS]; 863 uint8_t padding; 864 } __packed; 865 866 #define OTUS_NUM_CHAINS 2 867 868 #define OTUS_UID(aid) (IEEE80211_AID(aid) + 4) 869 870 #define OTUS_MAX_TXCMDSZ 64 871 #define OTUS_RXBUFSZ (8 * 1024) 872 /* Bumped for later A-MSDU and legacy fast-frames TX support */ 873 #define OTUS_TXBUFSZ (8 * 1024) 874 875 /* Default EDCA parameters for when QoS is disabled. */ 876 static const struct wmeParams otus_edca_def[WME_NUM_AC] = { 877 { 4, 10, 3, 0 }, 878 { 4, 10, 7, 0 }, 879 { 3, 4, 2, 94 }, 880 { 2, 3, 2, 47 } 881 }; 882 883 #define OTUS_RIDX_CCK1 0 884 #define OTUS_RIDX_OFDM6 4 885 #define OTUS_RIDX_OFDM24 8 886 #define OTUS_RIDX_MAX 11 887 static const struct otus_rate { 888 uint8_t rate; 889 uint8_t mcs; 890 } otus_rates[] = { 891 { 2, 0x0 }, 892 { 4, 0x1 }, 893 { 11, 0x2 }, 894 { 22, 0x3 }, 895 { 12, 0xb }, 896 { 18, 0xf }, 897 { 24, 0xa }, 898 { 36, 0xe }, 899 { 48, 0x9 }, 900 { 72, 0xd }, 901 { 96, 0x8 }, 902 { 108, 0xc } 903 }; 904 905 struct otus_rx_radiotap_header { 906 struct ieee80211_radiotap_header wr_ihdr; 907 uint8_t wr_flags; 908 uint8_t wr_rate; 909 uint16_t wr_chan_freq; 910 uint16_t wr_chan_flags; 911 uint8_t wr_antsignal; 912 } __packed __aligned(8); 913 914 #define OTUS_RX_RADIOTAP_PRESENT \ 915 (1 << IEEE80211_RADIOTAP_FLAGS | \ 916 1 << IEEE80211_RADIOTAP_RATE | \ 917 1 << IEEE80211_RADIOTAP_CHANNEL | \ 918 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) 919 920 struct otus_tx_radiotap_header { 921 struct ieee80211_radiotap_header wt_ihdr; 922 uint8_t wt_flags; 923 uint8_t wt_rate; 924 uint16_t wt_chan_freq; 925 uint16_t wt_chan_flags; 926 } __packed; 927 928 #define OTUS_TX_RADIOTAP_PRESENT \ 929 (1 << IEEE80211_RADIOTAP_FLAGS | \ 930 1 << IEEE80211_RADIOTAP_RATE | \ 931 1 << IEEE80211_RADIOTAP_CHANNEL) 932 933 struct otus_softc; 934 935 /* Firmware commands */ 936 struct otus_tx_cmd { 937 uint8_t *buf; 938 uint16_t buflen; 939 void *odata; 940 uint16_t odatalen; 941 uint16_t token; 942 STAILQ_ENTRY(otus_tx_cmd) next_cmd; 943 }; 944 945 /* TX, RX buffers */ 946 struct otus_data { 947 struct otus_softc *sc; 948 uint8_t *buf; 949 uint16_t buflen; 950 struct mbuf *m; 951 struct ieee80211_node *ni; 952 STAILQ_ENTRY(otus_data) next; 953 }; 954 955 struct otus_node { 956 struct ieee80211_node ni; 957 uint64_t tx_done; 958 uint64_t tx_err; 959 uint64_t tx_retries; 960 }; 961 962 #define OTUS_CONFIG_INDEX 0 963 #define OTUS_IFACE_INDEX 0 964 965 /* 966 * The carl9170 firmware has the following specification: 967 * 968 * 0 - USB control 969 * 1 - TX 970 * 2 - RX 971 * 3 - IRQ 972 * 4 - CMD 973 * .. 974 * 10 - end 975 */ 976 enum { 977 OTUS_BULK_TX, 978 OTUS_BULK_RX, 979 OTUS_BULK_IRQ, 980 OTUS_BULK_CMD, 981 OTUS_N_XFER 982 }; 983 984 struct otus_vap { 985 struct ieee80211vap vap; 986 int (*newstate)(struct ieee80211vap *, 987 enum ieee80211_state, int); 988 }; 989 #define OTUS_VAP(vap) ((struct otus_vap *)(vap)) 990 #define OTUS_NODE(ni) ((struct otus_node *)(ni)) 991 992 #define OTUS_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 993 #define OTUS_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 994 #define OTUS_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 995 #define OTUS_UNLOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_NOTOWNED) 996 997 /* XXX the TX/RX endpoint dump says it's 0x200, (512)? */ 998 #define OTUS_MAX_TXSZ 512 999 #define OTUS_MAX_RXSZ 512 1000 /* intr/cmd endpoint dump says 0x40 */ 1001 #define OTUS_MAX_CTRLSZ 64 1002 1003 #define OTUS_CMD_LIST_COUNT 32 1004 #define OTUS_RX_LIST_COUNT 128 1005 #define OTUS_TX_LIST_COUNT 32 1006 1007 struct otus_softc { 1008 struct ieee80211com sc_ic; 1009 struct ieee80211_ratectl_tx_stats sc_txs; 1010 struct mbufq sc_snd; 1011 device_t sc_dev; 1012 struct usb_device *sc_udev; 1013 int (*sc_newstate)(struct ieee80211com *, 1014 enum ieee80211_state, int); 1015 void (*sc_led_newstate)(struct otus_softc *); 1016 struct usbd_interface *sc_iface; 1017 struct mtx sc_mtx; 1018 1019 struct ar5416eeprom eeprom; 1020 uint8_t capflags; 1021 uint8_t rxmask; 1022 uint8_t txmask; 1023 int sc_running:1, 1024 sc_calibrating:1, 1025 sc_scanning:1; 1026 1027 int sc_if_flags; 1028 int sc_tx_timer; 1029 int fixed_ridx; 1030 int bb_reset; 1031 1032 struct ieee80211_channel *sc_curchan; 1033 1034 struct task tx_task; 1035 struct timeout_task scan_to; 1036 struct timeout_task calib_to; 1037 1038 /* register batch writes */ 1039 int write_idx; 1040 1041 uint32_t led_state; 1042 1043 /* current firmware message serial / token number */ 1044 int token; 1045 1046 /* current noisefloor, from SET_FREQUENCY */ 1047 int sc_nf[OTUS_NUM_CHAINS]; 1048 1049 /* How many pending, active transmit frames */ 1050 int sc_tx_n_pending; 1051 int sc_tx_n_active; 1052 1053 const uint32_t *phy_vals; 1054 1055 struct { 1056 uint32_t reg; 1057 uint32_t val; 1058 } __packed write_buf[AR_MAX_WRITE_IDX + 1]; 1059 1060 struct otus_data sc_rx[OTUS_RX_LIST_COUNT]; 1061 struct otus_data sc_tx[OTUS_TX_LIST_COUNT]; 1062 struct otus_tx_cmd sc_cmd[OTUS_CMD_LIST_COUNT]; 1063 1064 struct usb_xfer *sc_xfer[OTUS_N_XFER]; 1065 1066 /* Last seen PLCP header; for A-MPDU decap */ 1067 uint8_t ar_last_rx_plcp[AR_PLCP_HDR_LEN]; 1068 1069 STAILQ_HEAD(, otus_data) sc_rx_active; 1070 STAILQ_HEAD(, otus_data) sc_rx_inactive; 1071 STAILQ_HEAD(, otus_data) sc_tx_active[OTUS_N_XFER]; 1072 STAILQ_HEAD(, otus_data) sc_tx_inactive; 1073 STAILQ_HEAD(, otus_data) sc_tx_pending[OTUS_N_XFER]; 1074 1075 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_active; 1076 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_inactive; 1077 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_pending; 1078 STAILQ_HEAD(, otus_tx_cmd) sc_cmd_waiting; 1079 1080 union { 1081 struct otus_rx_radiotap_header th; 1082 uint8_t pad[64]; 1083 } sc_rxtapu; 1084 #define sc_rxtap sc_rxtapu.th 1085 1086 union { 1087 struct otus_tx_radiotap_header th; 1088 uint8_t pad[64]; 1089 } sc_txtapu; 1090 #define sc_txtap sc_txtapu.th 1091 }; 1092 1093 #endif /* __IF_OTUSREG_H__ */ 1094