1 /* $OpenBSD: if_otus.c,v 1.46 2015/03/14 03:38:49 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros AR9001U chipset. 22 */ 23 24 #include <sys/cdefs.h> 25 __FBSDID("$FreeBSD$"); 26 27 #include "opt_wlan.h" 28 29 #include <sys/param.h> 30 #include <sys/endian.h> 31 #include <sys/sockio.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/firmware.h> 40 #include <sys/module.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 46 #include <net/bpf.h> 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/if_ether.h> 58 #include <netinet/ip.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_regdomain.h> 62 #include <net80211/ieee80211_radiotap.h> 63 #include <net80211/ieee80211_ratectl.h> 64 #include <net80211/ieee80211_input.h> 65 #ifdef IEEE80211_SUPPORT_SUPERG 66 #include <net80211/ieee80211_superg.h> 67 #endif 68 69 #include <dev/usb/usb.h> 70 #include <dev/usb/usbdi.h> 71 #include "usbdevs.h" 72 73 #define USB_DEBUG_VAR otus_debug 74 #include <dev/usb/usb_debug.h> 75 76 #include "if_otusreg.h" 77 78 static int otus_debug = 0; 79 static SYSCTL_NODE(_hw_usb, OID_AUTO, otus, CTLFLAG_RW, 0, "USB otus"); 80 SYSCTL_INT(_hw_usb_otus, OID_AUTO, debug, CTLFLAG_RWTUN, &otus_debug, 0, 81 "Debug level"); 82 #define OTUS_DEBUG_XMIT 0x00000001 83 #define OTUS_DEBUG_RECV 0x00000002 84 #define OTUS_DEBUG_TXDONE 0x00000004 85 #define OTUS_DEBUG_RXDONE 0x00000008 86 #define OTUS_DEBUG_CMD 0x00000010 87 #define OTUS_DEBUG_CMDDONE 0x00000020 88 #define OTUS_DEBUG_RESET 0x00000040 89 #define OTUS_DEBUG_STATE 0x00000080 90 #define OTUS_DEBUG_CMDNOTIFY 0x00000100 91 #define OTUS_DEBUG_REGIO 0x00000200 92 #define OTUS_DEBUG_IRQ 0x00000400 93 #define OTUS_DEBUG_TXCOMP 0x00000800 94 #define OTUS_DEBUG_ANY 0xffffffff 95 96 #define OTUS_DPRINTF(sc, dm, ...) \ 97 do { \ 98 if ((dm == OTUS_DEBUG_ANY) || (dm & otus_debug)) \ 99 device_printf(sc->sc_dev, __VA_ARGS__); \ 100 } while (0) 101 102 #define OTUS_DEV(v, p) { USB_VPI(v, p, 0) } 103 static const STRUCT_USB_HOST_ID otus_devs[] = { 104 OTUS_DEV(USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512), 105 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275), 106 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N), 107 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170), 108 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612), 109 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2), 110 OTUS_DEV(USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN), 111 OTUS_DEV(USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX), 112 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1), 113 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1), 114 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2), 115 OTUS_DEV(USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2), 116 OTUS_DEV(USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG), 117 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2), 118 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000), 119 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100), 120 OTUS_DEV(USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300), 121 OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494), 122 OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600), 123 OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81), 124 OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82), 125 OTUS_DEV(USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221), 126 OTUS_DEV(USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N), 127 }; 128 129 static device_probe_t otus_match; 130 static device_attach_t otus_attach; 131 static device_detach_t otus_detach; 132 133 static int otus_attachhook(struct otus_softc *); 134 void otus_get_chanlist(struct otus_softc *); 135 int otus_load_firmware(struct otus_softc *, const char *, 136 uint32_t); 137 int otus_open_pipes(struct otus_softc *); 138 void otus_close_pipes(struct otus_softc *); 139 140 static int otus_alloc_tx_cmd_list(struct otus_softc *); 141 static void otus_free_tx_cmd_list(struct otus_softc *); 142 143 static int otus_alloc_rx_list(struct otus_softc *); 144 static void otus_free_rx_list(struct otus_softc *); 145 static int otus_alloc_tx_list(struct otus_softc *); 146 static void otus_free_tx_list(struct otus_softc *); 147 static void otus_free_list(struct otus_softc *, struct otus_data [], int); 148 static struct otus_data *_otus_getbuf(struct otus_softc *); 149 static struct otus_data *otus_getbuf(struct otus_softc *); 150 static void otus_freebuf(struct otus_softc *, struct otus_data *); 151 152 static struct otus_tx_cmd *_otus_get_txcmd(struct otus_softc *); 153 static struct otus_tx_cmd *otus_get_txcmd(struct otus_softc *); 154 static void otus_free_txcmd(struct otus_softc *, struct otus_tx_cmd *); 155 156 void otus_next_scan(void *, int); 157 static void otus_tx_task(void *, int pending); 158 static void otus_wme_update_task(void *, int pending); 159 void otus_do_async(struct otus_softc *, 160 void (*)(struct otus_softc *, void *), void *, int); 161 int otus_newstate(struct ieee80211vap *, enum ieee80211_state, 162 int); 163 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 164 void *, int); 165 void otus_write(struct otus_softc *, uint32_t, uint32_t); 166 int otus_write_barrier(struct otus_softc *); 167 static struct ieee80211_node *otus_node_alloc(struct ieee80211vap *vap, 168 const uint8_t mac[IEEE80211_ADDR_LEN]); 169 int otus_media_change(struct ifnet *); 170 int otus_read_eeprom(struct otus_softc *); 171 void otus_newassoc(struct ieee80211_node *, int); 172 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 173 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int, 174 struct mbufq *); 175 static int otus_tx(struct otus_softc *, struct ieee80211_node *, 176 struct mbuf *, struct otus_data *, 177 const struct ieee80211_bpf_params *); 178 int otus_ioctl(struct ifnet *, u_long, caddr_t); 179 int otus_set_multi(struct otus_softc *); 180 static void otus_updateedca(struct otus_softc *sc); 181 static void otus_updateslot(struct otus_softc *sc); 182 int otus_init_mac(struct otus_softc *); 183 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 184 int otus_set_board_values(struct otus_softc *, 185 struct ieee80211_channel *); 186 int otus_program_phy(struct otus_softc *, 187 struct ieee80211_channel *); 188 int otus_set_rf_bank4(struct otus_softc *, 189 struct ieee80211_channel *); 190 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 191 static int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 192 int); 193 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 194 struct ieee80211_key *); 195 void otus_set_key_cb(struct otus_softc *, void *); 196 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 197 struct ieee80211_key *); 198 void otus_delete_key_cb(struct otus_softc *, void *); 199 void otus_calibrate_to(void *, int); 200 int otus_set_bssid(struct otus_softc *, const uint8_t *); 201 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 202 void otus_led_newstate_type1(struct otus_softc *); 203 void otus_led_newstate_type2(struct otus_softc *); 204 void otus_led_newstate_type3(struct otus_softc *); 205 int otus_init(struct otus_softc *sc); 206 void otus_stop(struct otus_softc *sc); 207 208 static device_method_t otus_methods[] = { 209 DEVMETHOD(device_probe, otus_match), 210 DEVMETHOD(device_attach, otus_attach), 211 DEVMETHOD(device_detach, otus_detach), 212 213 DEVMETHOD_END 214 }; 215 216 static driver_t otus_driver = { 217 .name = "otus", 218 .methods = otus_methods, 219 .size = sizeof(struct otus_softc) 220 }; 221 222 static devclass_t otus_devclass; 223 224 DRIVER_MODULE(otus, uhub, otus_driver, otus_devclass, NULL, 0); 225 MODULE_DEPEND(otus, wlan, 1, 1, 1); 226 MODULE_DEPEND(otus, usb, 1, 1, 1); 227 MODULE_DEPEND(otus, firmware, 1, 1, 1); 228 MODULE_VERSION(otus, 1); 229 230 static usb_callback_t otus_bulk_tx_callback; 231 static usb_callback_t otus_bulk_rx_callback; 232 static usb_callback_t otus_bulk_irq_callback; 233 static usb_callback_t otus_bulk_cmd_callback; 234 235 static const struct usb_config otus_config[OTUS_N_XFER] = { 236 [OTUS_BULK_TX] = { 237 .type = UE_BULK, 238 .endpoint = UE_ADDR_ANY, 239 .direction = UE_DIR_OUT, 240 .bufsize = 0x200, 241 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 242 .callback = otus_bulk_tx_callback, 243 .timeout = 5000, /* ms */ 244 }, 245 [OTUS_BULK_RX] = { 246 .type = UE_BULK, 247 .endpoint = UE_ADDR_ANY, 248 .direction = UE_DIR_IN, 249 .bufsize = OTUS_RXBUFSZ, 250 .flags = { .ext_buffer = 1, .pipe_bof = 1,.short_xfer_ok = 1,}, 251 .callback = otus_bulk_rx_callback, 252 }, 253 [OTUS_BULK_IRQ] = { 254 .type = UE_INTERRUPT, 255 .endpoint = UE_ADDR_ANY, 256 .direction = UE_DIR_IN, 257 .bufsize = OTUS_MAX_CTRLSZ, 258 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 259 .callback = otus_bulk_irq_callback, 260 }, 261 [OTUS_BULK_CMD] = { 262 .type = UE_INTERRUPT, 263 .endpoint = UE_ADDR_ANY, 264 .direction = UE_DIR_OUT, 265 .bufsize = OTUS_MAX_CTRLSZ, 266 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 267 .callback = otus_bulk_cmd_callback, 268 .timeout = 5000, /* ms */ 269 }, 270 }; 271 272 static int 273 otus_match(device_t self) 274 { 275 struct usb_attach_arg *uaa = device_get_ivars(self); 276 277 if (uaa->usb_mode != USB_MODE_HOST || 278 uaa->info.bIfaceIndex != 0 || 279 uaa->info.bConfigIndex != 0) 280 return (ENXIO); 281 282 return (usbd_lookup_id_by_uaa(otus_devs, sizeof(otus_devs), uaa)); 283 } 284 285 static int 286 otus_attach(device_t self) 287 { 288 struct usb_attach_arg *uaa = device_get_ivars(self); 289 struct otus_softc *sc = device_get_softc(self); 290 int error; 291 uint8_t iface_index; 292 293 device_set_usb_desc(self); 294 sc->sc_udev = uaa->device; 295 sc->sc_dev = self; 296 297 mtx_init(&sc->sc_mtx, device_get_nameunit(self), MTX_NETWORK_LOCK, 298 MTX_DEF); 299 300 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->scan_to, 0, otus_next_scan, sc); 301 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->calib_to, 0, otus_calibrate_to, sc); 302 TASK_INIT(&sc->tx_task, 0, otus_tx_task, sc); 303 TASK_INIT(&sc->wme_update_task, 0, otus_wme_update_task, sc); 304 mbufq_init(&sc->sc_snd, ifqmaxlen); 305 306 iface_index = 0; 307 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 308 otus_config, OTUS_N_XFER, sc, &sc->sc_mtx); 309 if (error) { 310 device_printf(sc->sc_dev, 311 "could not allocate USB transfers, err=%s\n", 312 usbd_errstr(error)); 313 goto fail_usb; 314 } 315 316 if ((error = otus_open_pipes(sc)) != 0) { 317 device_printf(sc->sc_dev, "%s: could not open pipes\n", 318 __func__); 319 goto fail; 320 } 321 322 /* XXX check return status; fail out if appropriate */ 323 if (otus_attachhook(sc) != 0) 324 goto fail; 325 326 return (0); 327 328 fail: 329 otus_close_pipes(sc); 330 fail_usb: 331 mtx_destroy(&sc->sc_mtx); 332 return (ENXIO); 333 } 334 335 static int 336 otus_detach(device_t self) 337 { 338 struct otus_softc *sc = device_get_softc(self); 339 struct ieee80211com *ic = &sc->sc_ic; 340 341 otus_stop(sc); 342 343 usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); 344 345 taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); 346 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); 347 taskqueue_drain(taskqueue_thread, &sc->tx_task); 348 taskqueue_drain(taskqueue_thread, &sc->wme_update_task); 349 350 otus_close_pipes(sc); 351 #if 0 352 /* Wait for all queued asynchronous commands to complete. */ 353 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 354 355 usbd_ref_wait(sc->sc_udev); 356 #endif 357 358 ieee80211_ifdetach(ic); 359 mtx_destroy(&sc->sc_mtx); 360 return 0; 361 } 362 363 static void 364 otus_delay_ms(struct otus_softc *sc, int ms) 365 { 366 367 DELAY(1000 * ms); 368 } 369 370 static struct ieee80211vap * 371 otus_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 372 enum ieee80211_opmode opmode, int flags, 373 const uint8_t bssid[IEEE80211_ADDR_LEN], 374 const uint8_t mac[IEEE80211_ADDR_LEN]) 375 { 376 struct otus_vap *uvp; 377 struct ieee80211vap *vap; 378 379 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 380 return (NULL); 381 382 uvp = malloc(sizeof(struct otus_vap), M_80211_VAP, M_WAITOK | M_ZERO); 383 vap = &uvp->vap; 384 385 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 386 flags, bssid) != 0) { 387 /* out of memory */ 388 free(uvp, M_80211_VAP); 389 return (NULL); 390 } 391 392 /* override state transition machine */ 393 uvp->newstate = vap->iv_newstate; 394 vap->iv_newstate = otus_newstate; 395 396 /* XXX TODO: double-check */ 397 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 398 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_32K; 399 400 ieee80211_ratectl_init(vap); 401 402 /* complete setup */ 403 ieee80211_vap_attach(vap, ieee80211_media_change, 404 ieee80211_media_status, mac); 405 ic->ic_opmode = opmode; 406 407 return (vap); 408 } 409 410 static void 411 otus_vap_delete(struct ieee80211vap *vap) 412 { 413 struct otus_vap *uvp = OTUS_VAP(vap); 414 415 ieee80211_ratectl_deinit(vap); 416 ieee80211_vap_detach(vap); 417 free(uvp, M_80211_VAP); 418 } 419 420 static void 421 otus_parent(struct ieee80211com *ic) 422 { 423 struct otus_softc *sc = ic->ic_softc; 424 int startall = 0; 425 426 if (ic->ic_nrunning > 0) { 427 if (!sc->sc_running) { 428 otus_init(sc); 429 startall = 1; 430 } else { 431 (void) otus_set_multi(sc); 432 } 433 } else if (sc->sc_running) 434 otus_stop(sc); 435 436 if (startall) 437 ieee80211_start_all(ic); 438 } 439 440 static void 441 otus_drain_mbufq(struct otus_softc *sc) 442 { 443 struct mbuf *m; 444 struct ieee80211_node *ni; 445 446 OTUS_LOCK_ASSERT(sc); 447 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 448 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 449 m->m_pkthdr.rcvif = NULL; 450 ieee80211_free_node(ni); 451 m_freem(m); 452 } 453 } 454 455 static void 456 otus_tx_start(struct otus_softc *sc) 457 { 458 459 taskqueue_enqueue(taskqueue_thread, &sc->tx_task); 460 } 461 462 static int 463 otus_transmit(struct ieee80211com *ic, struct mbuf *m) 464 { 465 struct otus_softc *sc = ic->ic_softc; 466 int error; 467 468 OTUS_LOCK(sc); 469 if (! sc->sc_running) { 470 OTUS_UNLOCK(sc); 471 return (ENXIO); 472 } 473 474 /* XXX TODO: handle fragments */ 475 error = mbufq_enqueue(&sc->sc_snd, m); 476 if (error) { 477 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 478 "%s: mbufq_enqueue failed: %d\n", 479 __func__, 480 error); 481 OTUS_UNLOCK(sc); 482 return (error); 483 } 484 OTUS_UNLOCK(sc); 485 486 /* Kick TX */ 487 otus_tx_start(sc); 488 489 return (0); 490 } 491 492 static void 493 _otus_start(struct otus_softc *sc) 494 { 495 struct ieee80211_node *ni; 496 struct otus_data *bf; 497 struct mbuf *m; 498 499 OTUS_LOCK_ASSERT(sc); 500 501 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 502 bf = otus_getbuf(sc); 503 if (bf == NULL) { 504 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 505 "%s: failed to get buffer\n", __func__); 506 mbufq_prepend(&sc->sc_snd, m); 507 break; 508 } 509 510 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 511 m->m_pkthdr.rcvif = NULL; 512 513 if (otus_tx(sc, ni, m, bf, NULL) != 0) { 514 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 515 "%s: failed to transmit\n", __func__); 516 if_inc_counter(ni->ni_vap->iv_ifp, 517 IFCOUNTER_OERRORS, 1); 518 otus_freebuf(sc, bf); 519 ieee80211_free_node(ni); 520 m_freem(m); 521 break; 522 } 523 } 524 } 525 526 static void 527 otus_tx_task(void *arg, int pending) 528 { 529 struct otus_softc *sc = arg; 530 531 OTUS_LOCK(sc); 532 _otus_start(sc); 533 OTUS_UNLOCK(sc); 534 } 535 536 static int 537 otus_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 538 const struct ieee80211_bpf_params *params) 539 { 540 struct ieee80211com *ic= ni->ni_ic; 541 struct otus_softc *sc = ic->ic_softc; 542 struct otus_data *bf = NULL; 543 int error = 0; 544 545 /* Don't transmit if we're not running */ 546 OTUS_LOCK(sc); 547 if (! sc->sc_running) { 548 error = ENETDOWN; 549 goto error; 550 } 551 552 bf = otus_getbuf(sc); 553 if (bf == NULL) { 554 error = ENOBUFS; 555 goto error; 556 } 557 558 if (otus_tx(sc, ni, m, bf, params) != 0) { 559 error = EIO; 560 goto error; 561 } 562 563 OTUS_UNLOCK(sc); 564 return (0); 565 error: 566 if (bf) 567 otus_freebuf(sc, bf); 568 OTUS_UNLOCK(sc); 569 m_freem(m); 570 return (ENXIO); 571 } 572 573 static void 574 otus_update_chw(struct ieee80211com *ic) 575 { 576 577 printf("%s: TODO\n", __func__); 578 } 579 580 static void 581 otus_set_channel(struct ieee80211com *ic) 582 { 583 struct otus_softc *sc = ic->ic_softc; 584 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "%s: set channel: %d\n", 585 __func__, 586 ic->ic_curchan->ic_freq); 587 588 OTUS_LOCK(sc); 589 (void) otus_set_chan(sc, ic->ic_curchan, 0); 590 OTUS_UNLOCK(sc); 591 } 592 593 static void 594 otus_wme_update_task(void *arg, int pending) 595 { 596 struct otus_softc *sc = arg; 597 598 OTUS_LOCK(sc); 599 /* 600 * XXX TODO: take temporary copy of EDCA information 601 * when scheduling this so we have a more time-correct view 602 * of things. 603 */ 604 otus_updateedca(sc); 605 OTUS_UNLOCK(sc); 606 } 607 608 static void 609 otus_wme_schedule_update(struct otus_softc *sc) 610 { 611 612 taskqueue_enqueue(taskqueue_thread, &sc->wme_update_task); 613 } 614 615 /* 616 * This is called by net80211 in RX packet context, so we 617 * can't sleep here. 618 * 619 * TODO: have net80211 schedule an update itself for its 620 * own internal taskqueue. 621 */ 622 static int 623 otus_wme_update(struct ieee80211com *ic) 624 { 625 struct otus_softc *sc = ic->ic_softc; 626 627 otus_wme_schedule_update(sc); 628 return (0); 629 } 630 631 static int 632 otus_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 633 { 634 635 /* For now, no A-MPDU TX support in the driver */ 636 return (0); 637 } 638 639 static void 640 otus_scan_start(struct ieee80211com *ic) 641 { 642 643 // printf("%s: TODO\n", __func__); 644 } 645 646 static void 647 otus_scan_end(struct ieee80211com *ic) 648 { 649 650 // printf("%s: TODO\n", __func__); 651 } 652 653 static void 654 otus_update_mcast(struct ieee80211com *ic) 655 { 656 struct otus_softc *sc = ic->ic_softc; 657 658 (void) otus_set_multi(sc); 659 } 660 661 static int 662 otus_attachhook(struct otus_softc *sc) 663 { 664 struct ieee80211com *ic = &sc->sc_ic; 665 usb_device_request_t req; 666 uint32_t in, out; 667 int error; 668 uint8_t bands; 669 670 /* Not locked */ 671 error = otus_load_firmware(sc, "otusfw_init", AR_FW_INIT_ADDR); 672 if (error != 0) { 673 device_printf(sc->sc_dev, "%s: could not load %s firmware\n", 674 __func__, "init"); 675 return (ENXIO); 676 } 677 678 /* XXX not locked? */ 679 otus_delay_ms(sc, 1000); 680 681 /* Not locked */ 682 error = otus_load_firmware(sc, "otusfw_main", AR_FW_MAIN_ADDR); 683 if (error != 0) { 684 device_printf(sc->sc_dev, "%s: could not load %s firmware\n", 685 __func__, "main"); 686 return (ENXIO); 687 } 688 689 OTUS_LOCK(sc); 690 691 /* Tell device that firmware transfer is complete. */ 692 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 693 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 694 USETW(req.wValue, 0); 695 USETW(req.wIndex, 0); 696 USETW(req.wLength, 0); 697 if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, NULL, 698 0, NULL, 250) != 0) { 699 OTUS_UNLOCK(sc); 700 device_printf(sc->sc_dev, 701 "%s: firmware initialization failed\n", 702 __func__); 703 return (ENXIO); 704 } 705 706 /* Send an ECHO command to check that everything is settled. */ 707 in = 0xbadc0ffe; 708 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out, sizeof(out)) != 0) { 709 OTUS_UNLOCK(sc); 710 device_printf(sc->sc_dev, 711 "%s: echo command failed\n", __func__); 712 return (ENXIO); 713 } 714 if (in != out) { 715 OTUS_UNLOCK(sc); 716 device_printf(sc->sc_dev, 717 "%s: echo reply mismatch: 0x%08x!=0x%08x\n", 718 __func__, in, out); 719 return (ENXIO); 720 } 721 722 /* Read entire EEPROM. */ 723 if (otus_read_eeprom(sc) != 0) { 724 OTUS_UNLOCK(sc); 725 device_printf(sc->sc_dev, 726 "%s: could not read EEPROM\n", 727 __func__); 728 return (ENXIO); 729 } 730 731 OTUS_UNLOCK(sc); 732 733 sc->txmask = sc->eeprom.baseEepHeader.txMask; 734 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 735 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 736 IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->eeprom.baseEepHeader.macAddr); 737 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 738 739 device_printf(sc->sc_dev, 740 "MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 741 (sc->capflags & AR5416_OPFLAGS_11A) ? 742 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 743 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 744 ether_sprintf(ic->ic_macaddr)); 745 746 ic->ic_softc = sc; 747 ic->ic_name = device_get_nameunit(sc->sc_dev); 748 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 749 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 750 751 /* Set device capabilities. */ 752 ic->ic_caps = 753 IEEE80211_C_STA | /* station mode */ 754 #if 0 755 IEEE80211_C_BGSCAN | /* Background scan. */ 756 #endif 757 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 758 IEEE80211_C_WME | /* WME/QoS */ 759 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 760 IEEE80211_C_FF | /* Atheros fast-frames supported. */ 761 IEEE80211_C_MONITOR | 762 IEEE80211_C_WPA; /* WPA/RSN. */ 763 764 /* XXX TODO: 11n */ 765 766 #if 0 767 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 768 /* Set supported .11b and .11g rates. */ 769 ic->ic_sup_rates[IEEE80211_MODE_11B] = 770 ieee80211_std_rateset_11b; 771 ic->ic_sup_rates[IEEE80211_MODE_11G] = 772 ieee80211_std_rateset_11g; 773 } 774 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 775 /* Set supported .11a rates. */ 776 ic->ic_sup_rates[IEEE80211_MODE_11A] = 777 ieee80211_std_rateset_11a; 778 } 779 #endif 780 781 #if 0 782 /* Build the list of supported channels. */ 783 otus_get_chanlist(sc); 784 #else 785 /* Set supported .11b and .11g rates. */ 786 bands = 0; 787 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 788 setbit(&bands, IEEE80211_MODE_11B); 789 setbit(&bands, IEEE80211_MODE_11G); 790 } 791 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 792 setbit(&bands, IEEE80211_MODE_11A); 793 } 794 #if 0 795 if (sc->sc_ht) 796 setbit(&bands, IEEE80211_MODE_11NG); 797 #endif 798 ieee80211_init_channels(ic, NULL, &bands); 799 #endif 800 801 ieee80211_ifattach(ic); 802 ic->ic_raw_xmit = otus_raw_xmit; 803 ic->ic_scan_start = otus_scan_start; 804 ic->ic_scan_end = otus_scan_end; 805 ic->ic_set_channel = otus_set_channel; 806 ic->ic_vap_create = otus_vap_create; 807 ic->ic_vap_delete = otus_vap_delete; 808 ic->ic_update_mcast = otus_update_mcast; 809 ic->ic_update_promisc = otus_update_mcast; 810 ic->ic_parent = otus_parent; 811 ic->ic_transmit = otus_transmit; 812 ic->ic_update_chw = otus_update_chw; 813 ic->ic_ampdu_enable = otus_ampdu_enable; 814 ic->ic_wme.wme_update = otus_wme_update; 815 ic->ic_newassoc = otus_newassoc; 816 ic->ic_node_alloc = otus_node_alloc; 817 818 #ifdef notyet 819 ic->ic_set_key = otus_set_key; 820 ic->ic_delete_key = otus_delete_key; 821 #endif 822 823 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 824 sizeof(sc->sc_txtap), OTUS_TX_RADIOTAP_PRESENT, 825 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 826 OTUS_RX_RADIOTAP_PRESENT); 827 828 return (0); 829 } 830 831 void 832 otus_get_chanlist(struct otus_softc *sc) 833 { 834 struct ieee80211com *ic = &sc->sc_ic; 835 uint16_t domain; 836 uint8_t chan; 837 int i; 838 839 /* XXX regulatory domain. */ 840 domain = le16toh(sc->eeprom.baseEepHeader.regDmn[0]); 841 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "regdomain=0x%04x\n", domain); 842 843 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 844 for (i = 0; i < 14; i++) { 845 chan = ar_chans[i]; 846 ic->ic_channels[chan].ic_freq = 847 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 848 ic->ic_channels[chan].ic_flags = 849 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 850 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 851 } 852 } 853 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 854 for (i = 14; i < nitems(ar_chans); i++) { 855 chan = ar_chans[i]; 856 ic->ic_channels[chan].ic_freq = 857 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 858 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 859 } 860 } 861 } 862 863 int 864 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 865 { 866 usb_device_request_t req; 867 char *ptr; 868 const struct firmware *fw; 869 int mlen, error, size; 870 871 error = 0; 872 873 /* Read firmware image from the filesystem. */ 874 if ((fw = firmware_get(name)) == NULL) { 875 device_printf(sc->sc_dev, 876 "%s: failed loadfirmware of file %s\n", __func__, name); 877 return (ENXIO); 878 } 879 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 880 req.bRequest = AR_FW_DOWNLOAD; 881 USETW(req.wIndex, 0); 882 883 OTUS_LOCK(sc); 884 885 /* XXX const */ 886 ptr = __DECONST(char *, fw->data); 887 size = fw->datasize; 888 addr >>= 8; 889 while (size > 0) { 890 mlen = MIN(size, 4096); 891 892 USETW(req.wValue, addr); 893 USETW(req.wLength, mlen); 894 if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 895 &req, ptr, 0, NULL, 250) != 0) { 896 error = EIO; 897 break; 898 } 899 addr += mlen >> 8; 900 ptr += mlen; 901 size -= mlen; 902 } 903 904 OTUS_UNLOCK(sc); 905 906 firmware_put(fw, FIRMWARE_UNLOAD); 907 if (error != 0) 908 device_printf(sc->sc_dev, 909 "%s: %s: error=%d\n", __func__, name, error); 910 return error; 911 } 912 913 int 914 otus_open_pipes(struct otus_softc *sc) 915 { 916 #if 0 917 int isize, error; 918 int i; 919 #endif 920 int error; 921 922 OTUS_UNLOCK_ASSERT(sc); 923 924 if ((error = otus_alloc_tx_cmd_list(sc)) != 0) { 925 device_printf(sc->sc_dev, 926 "%s: could not allocate command xfer\n", 927 __func__); 928 goto fail; 929 } 930 931 if ((error = otus_alloc_tx_list(sc)) != 0) { 932 device_printf(sc->sc_dev, "%s: could not allocate Tx xfers\n", 933 __func__); 934 goto fail; 935 } 936 937 if ((error = otus_alloc_rx_list(sc)) != 0) { 938 device_printf(sc->sc_dev, "%s: could not allocate Rx xfers\n", 939 __func__); 940 goto fail; 941 } 942 943 /* Enable RX transfers; needed for initial firmware messages */ 944 OTUS_LOCK(sc); 945 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_RX]); 946 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_IRQ]); 947 OTUS_UNLOCK(sc); 948 return 0; 949 950 fail: otus_close_pipes(sc); 951 return error; 952 } 953 954 void 955 otus_close_pipes(struct otus_softc *sc) 956 { 957 958 OTUS_LOCK(sc); 959 otus_free_tx_cmd_list(sc); 960 otus_free_tx_list(sc); 961 otus_free_rx_list(sc); 962 OTUS_UNLOCK(sc); 963 964 usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); 965 } 966 967 static void 968 otus_free_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], int ndata) 969 { 970 int i; 971 972 /* XXX TODO: someone has to have waken up waiters! */ 973 for (i = 0; i < ndata; i++) { 974 struct otus_tx_cmd *dp = &cmd[i]; 975 976 if (dp->buf != NULL) { 977 free(dp->buf, M_USBDEV); 978 dp->buf = NULL; 979 } 980 } 981 } 982 983 static int 984 otus_alloc_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], 985 int ndata, int maxsz) 986 { 987 int i, error; 988 989 for (i = 0; i < ndata; i++) { 990 struct otus_tx_cmd *dp = &cmd[i]; 991 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 992 dp->odata = NULL; 993 if (dp->buf == NULL) { 994 device_printf(sc->sc_dev, 995 "could not allocate buffer\n"); 996 error = ENOMEM; 997 goto fail; 998 } 999 } 1000 1001 return (0); 1002 fail: 1003 otus_free_cmd_list(sc, cmd, ndata); 1004 return (error); 1005 } 1006 1007 static int 1008 otus_alloc_tx_cmd_list(struct otus_softc *sc) 1009 { 1010 int error, i; 1011 1012 error = otus_alloc_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT, 1013 OTUS_MAX_TXCMDSZ); 1014 if (error != 0) 1015 return (error); 1016 1017 STAILQ_INIT(&sc->sc_cmd_active); 1018 STAILQ_INIT(&sc->sc_cmd_inactive); 1019 STAILQ_INIT(&sc->sc_cmd_pending); 1020 STAILQ_INIT(&sc->sc_cmd_waiting); 1021 1022 for (i = 0; i < OTUS_CMD_LIST_COUNT; i++) 1023 STAILQ_INSERT_HEAD(&sc->sc_cmd_inactive, &sc->sc_cmd[i], 1024 next_cmd); 1025 1026 return (0); 1027 } 1028 1029 static void 1030 otus_free_tx_cmd_list(struct otus_softc *sc) 1031 { 1032 1033 /* 1034 * XXX TODO: something needs to wake up any pending/sleeping 1035 * waiters! 1036 */ 1037 STAILQ_INIT(&sc->sc_cmd_active); 1038 STAILQ_INIT(&sc->sc_cmd_inactive); 1039 STAILQ_INIT(&sc->sc_cmd_pending); 1040 STAILQ_INIT(&sc->sc_cmd_waiting); 1041 1042 otus_free_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT); 1043 } 1044 1045 static int 1046 otus_alloc_list(struct otus_softc *sc, struct otus_data data[], 1047 int ndata, int maxsz) 1048 { 1049 int i, error; 1050 1051 for (i = 0; i < ndata; i++) { 1052 struct otus_data *dp = &data[i]; 1053 dp->sc = sc; 1054 dp->m = NULL; 1055 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1056 if (dp->buf == NULL) { 1057 device_printf(sc->sc_dev, 1058 "could not allocate buffer\n"); 1059 error = ENOMEM; 1060 goto fail; 1061 } 1062 dp->ni = NULL; 1063 } 1064 1065 return (0); 1066 fail: 1067 otus_free_list(sc, data, ndata); 1068 return (error); 1069 } 1070 1071 static int 1072 otus_alloc_rx_list(struct otus_softc *sc) 1073 { 1074 int error, i; 1075 1076 error = otus_alloc_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT, 1077 OTUS_RXBUFSZ); 1078 if (error != 0) 1079 return (error); 1080 1081 STAILQ_INIT(&sc->sc_rx_active); 1082 STAILQ_INIT(&sc->sc_rx_inactive); 1083 1084 for (i = 0; i < OTUS_RX_LIST_COUNT; i++) 1085 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1086 1087 return (0); 1088 } 1089 1090 static int 1091 otus_alloc_tx_list(struct otus_softc *sc) 1092 { 1093 int error, i; 1094 1095 error = otus_alloc_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT, 1096 OTUS_TXBUFSZ); 1097 if (error != 0) 1098 return (error); 1099 1100 STAILQ_INIT(&sc->sc_tx_inactive); 1101 1102 for (i = 0; i != OTUS_N_XFER; i++) { 1103 STAILQ_INIT(&sc->sc_tx_active[i]); 1104 STAILQ_INIT(&sc->sc_tx_pending[i]); 1105 } 1106 1107 for (i = 0; i < OTUS_TX_LIST_COUNT; i++) { 1108 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1109 } 1110 1111 return (0); 1112 } 1113 1114 static void 1115 otus_free_tx_list(struct otus_softc *sc) 1116 { 1117 int i; 1118 1119 /* prevent further allocations from TX list(s) */ 1120 STAILQ_INIT(&sc->sc_tx_inactive); 1121 1122 for (i = 0; i != OTUS_N_XFER; i++) { 1123 STAILQ_INIT(&sc->sc_tx_active[i]); 1124 STAILQ_INIT(&sc->sc_tx_pending[i]); 1125 } 1126 1127 otus_free_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT); 1128 } 1129 1130 static void 1131 otus_free_rx_list(struct otus_softc *sc) 1132 { 1133 /* prevent further allocations from RX list(s) */ 1134 STAILQ_INIT(&sc->sc_rx_inactive); 1135 STAILQ_INIT(&sc->sc_rx_active); 1136 1137 otus_free_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT); 1138 } 1139 1140 static void 1141 otus_free_list(struct otus_softc *sc, struct otus_data data[], int ndata) 1142 { 1143 int i; 1144 1145 for (i = 0; i < ndata; i++) { 1146 struct otus_data *dp = &data[i]; 1147 1148 if (dp->buf != NULL) { 1149 free(dp->buf, M_USBDEV); 1150 dp->buf = NULL; 1151 } 1152 if (dp->ni != NULL) { 1153 ieee80211_free_node(dp->ni); 1154 dp->ni = NULL; 1155 } 1156 } 1157 } 1158 1159 static struct otus_data * 1160 _otus_getbuf(struct otus_softc *sc) 1161 { 1162 struct otus_data *bf; 1163 1164 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1165 if (bf != NULL) 1166 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1167 else 1168 bf = NULL; 1169 return (bf); 1170 } 1171 1172 static struct otus_data * 1173 otus_getbuf(struct otus_softc *sc) 1174 { 1175 struct otus_data *bf; 1176 1177 OTUS_LOCK_ASSERT(sc); 1178 1179 bf = _otus_getbuf(sc); 1180 return (bf); 1181 } 1182 1183 static void 1184 otus_freebuf(struct otus_softc *sc, struct otus_data *bf) 1185 { 1186 1187 OTUS_LOCK_ASSERT(sc); 1188 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, bf, next); 1189 } 1190 1191 static struct otus_tx_cmd * 1192 _otus_get_txcmd(struct otus_softc *sc) 1193 { 1194 struct otus_tx_cmd *bf; 1195 1196 bf = STAILQ_FIRST(&sc->sc_cmd_inactive); 1197 if (bf != NULL) 1198 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next_cmd); 1199 else 1200 bf = NULL; 1201 return (bf); 1202 } 1203 1204 static struct otus_tx_cmd * 1205 otus_get_txcmd(struct otus_softc *sc) 1206 { 1207 struct otus_tx_cmd *bf; 1208 1209 OTUS_LOCK_ASSERT(sc); 1210 1211 bf = _otus_get_txcmd(sc); 1212 if (bf == NULL) { 1213 device_printf(sc->sc_dev, "%s: no tx cmd buffers\n", 1214 __func__); 1215 } 1216 return (bf); 1217 } 1218 1219 static void 1220 otus_free_txcmd(struct otus_softc *sc, struct otus_tx_cmd *bf) 1221 { 1222 1223 OTUS_LOCK_ASSERT(sc); 1224 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, bf, next_cmd); 1225 } 1226 1227 void 1228 otus_next_scan(void *arg, int pending) 1229 { 1230 #if 0 1231 struct otus_softc *sc = arg; 1232 1233 if (usbd_is_dying(sc->sc_udev)) 1234 return; 1235 1236 usbd_ref_incr(sc->sc_udev); 1237 1238 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1239 ieee80211_next_scan(&sc->sc_ic.ic_if); 1240 1241 usbd_ref_decr(sc->sc_udev); 1242 #endif 1243 } 1244 1245 int 1246 otus_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1247 { 1248 struct otus_vap *uvp = OTUS_VAP(vap); 1249 struct ieee80211com *ic = vap->iv_ic; 1250 struct otus_softc *sc = ic->ic_softc; 1251 struct ieee80211_node *ni; 1252 enum ieee80211_state ostate; 1253 1254 ostate = vap->iv_state; 1255 OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1256 ieee80211_state_name[ostate], 1257 ieee80211_state_name[nstate]); 1258 1259 IEEE80211_UNLOCK(ic); 1260 1261 OTUS_LOCK(sc); 1262 1263 /* XXX TODO: more fleshing out! */ 1264 1265 switch (nstate) { 1266 case IEEE80211_S_RUN: 1267 ni = ieee80211_ref_node(vap->iv_bss); 1268 1269 if (ic->ic_opmode == IEEE80211_M_STA) { 1270 otus_updateslot(sc); 1271 otus_set_bssid(sc, ni->ni_bssid); 1272 1273 /* Start calibration timer. */ 1274 taskqueue_enqueue_timeout(taskqueue_thread, 1275 &sc->calib_to, hz); 1276 } 1277 ieee80211_free_node(ni); 1278 break; 1279 default: 1280 break; 1281 } 1282 1283 /* XXX TODO: calibration? */ 1284 1285 sc->sc_led_newstate(sc); 1286 1287 OTUS_UNLOCK(sc); 1288 IEEE80211_LOCK(ic); 1289 return (uvp->newstate(vap, nstate, arg)); 1290 } 1291 1292 int 1293 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 1294 void *odata, int odatalen) 1295 { 1296 struct otus_tx_cmd *cmd; 1297 struct ar_cmd_hdr *hdr; 1298 int xferlen, error; 1299 1300 OTUS_LOCK_ASSERT(sc); 1301 1302 /* Always bulk-out a multiple of 4 bytes. */ 1303 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 1304 if (xferlen > OTUS_MAX_TXCMDSZ) { 1305 device_printf(sc->sc_dev, "%s: command (0x%02x) size (%d) > %d\n", 1306 __func__, 1307 code, 1308 xferlen, 1309 OTUS_MAX_TXCMDSZ); 1310 return (EIO); 1311 } 1312 1313 cmd = otus_get_txcmd(sc); 1314 if (cmd == NULL) { 1315 device_printf(sc->sc_dev, "%s: failed to get buf\n", 1316 __func__); 1317 return (EIO); 1318 } 1319 1320 hdr = (struct ar_cmd_hdr *)cmd->buf; 1321 hdr->code = code; 1322 hdr->len = ilen; 1323 hdr->token = ++sc->token; /* Don't care about endianness. */ 1324 cmd->token = hdr->token; 1325 /* XXX TODO: check max cmd length? */ 1326 memcpy((uint8_t *)&hdr[1], idata, ilen); 1327 1328 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 1329 "%s: sending command code=0x%02x len=%d token=%d\n", 1330 __func__, code, ilen, hdr->token); 1331 1332 cmd->odata = odata; 1333 cmd->odatalen = odatalen; 1334 cmd->buflen = xferlen; 1335 1336 /* Queue the command to the endpoint */ 1337 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next_cmd); 1338 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_CMD]); 1339 1340 /* Sleep on the command; wait for it to complete */ 1341 error = msleep(cmd, &sc->sc_mtx, PCATCH, "otuscmd", hz); 1342 1343 /* 1344 * At this point we don't own cmd any longer; it'll be 1345 * freed by the cmd bulk path or the RX notification 1346 * path. If the data is made available then it'll be copied 1347 * to the caller. All that is left to do is communicate 1348 * status back to the caller. 1349 */ 1350 if (error != 0) { 1351 device_printf(sc->sc_dev, 1352 "%s: timeout waiting for command 0x%02x reply\n", 1353 __func__, code); 1354 } 1355 return error; 1356 } 1357 1358 void 1359 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 1360 { 1361 1362 OTUS_LOCK_ASSERT(sc); 1363 1364 sc->write_buf[sc->write_idx].reg = htole32(reg); 1365 sc->write_buf[sc->write_idx].val = htole32(val); 1366 1367 if (++sc->write_idx > (AR_MAX_WRITE_IDX-1)) 1368 (void)otus_write_barrier(sc); 1369 } 1370 1371 int 1372 otus_write_barrier(struct otus_softc *sc) 1373 { 1374 int error; 1375 1376 OTUS_LOCK_ASSERT(sc); 1377 1378 if (sc->write_idx == 0) 1379 return 0; /* Nothing to flush. */ 1380 1381 OTUS_DPRINTF(sc, OTUS_DEBUG_REGIO, "%s: called; %d updates\n", 1382 __func__, 1383 sc->write_idx); 1384 1385 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 1386 sizeof (sc->write_buf[0]) * sc->write_idx, NULL, 0); 1387 sc->write_idx = 0; 1388 return error; 1389 } 1390 1391 static struct ieee80211_node * 1392 otus_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1393 { 1394 1395 return malloc(sizeof (struct otus_node), M_80211_NODE, 1396 M_NOWAIT | M_ZERO); 1397 } 1398 1399 #if 0 1400 int 1401 otus_media_change(struct ifnet *ifp) 1402 { 1403 struct otus_softc *sc = ifp->if_softc; 1404 struct ieee80211com *ic = &sc->sc_ic; 1405 uint8_t rate, ridx; 1406 int error; 1407 1408 error = ieee80211_media_change(ifp); 1409 if (error != ENETRESET) 1410 return error; 1411 1412 if (ic->ic_fixed_rate != -1) { 1413 rate = ic->ic_sup_rates[ic->ic_curmode]. 1414 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1415 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 1416 if (otus_rates[ridx].rate == rate) 1417 break; 1418 sc->fixed_ridx = ridx; 1419 } 1420 1421 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1422 error = otus_init(sc); 1423 1424 return error; 1425 } 1426 #endif 1427 1428 int 1429 otus_read_eeprom(struct otus_softc *sc) 1430 { 1431 uint32_t regs[8], reg; 1432 uint8_t *eep; 1433 int i, j, error; 1434 1435 OTUS_LOCK_ASSERT(sc); 1436 1437 /* Read EEPROM by blocks of 32 bytes. */ 1438 eep = (uint8_t *)&sc->eeprom; 1439 reg = AR_EEPROM_OFFSET; 1440 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 1441 for (j = 0; j < 8; j++, reg += 4) 1442 regs[j] = htole32(reg); 1443 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep, 32); 1444 if (error != 0) 1445 break; 1446 eep += 32; 1447 } 1448 return error; 1449 } 1450 1451 void 1452 otus_newassoc(struct ieee80211_node *ni, int isnew) 1453 { 1454 struct ieee80211com *ic = ni->ni_ic; 1455 struct otus_softc *sc = ic->ic_softc; 1456 struct otus_node *on = OTUS_NODE(ni); 1457 1458 OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "new assoc isnew=%d addr=%s\n", 1459 isnew, ether_sprintf(ni->ni_macaddr)); 1460 1461 on->tx_done = 0; 1462 on->tx_err = 0; 1463 on->tx_retries = 0; 1464 } 1465 1466 static void 1467 otus_cmd_handle_response(struct otus_softc *sc, struct ar_cmd_hdr *hdr) 1468 { 1469 struct otus_tx_cmd *cmd; 1470 1471 OTUS_LOCK_ASSERT(sc); 1472 1473 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1474 "%s: received reply code=0x%02x len=%d token=%d\n", 1475 __func__, 1476 hdr->code, hdr->len, hdr->token); 1477 1478 /* 1479 * Walk the list, freeing items that aren't ours, 1480 * stopping when we hit our token. 1481 */ 1482 while ((cmd = STAILQ_FIRST(&sc->sc_cmd_waiting)) != NULL) { 1483 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next_cmd); 1484 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1485 "%s: cmd=%p; hdr.token=%d, cmd.token=%d\n", 1486 __func__, 1487 cmd, 1488 (int) hdr->token, 1489 (int) cmd->token); 1490 if (hdr->token == cmd->token) { 1491 /* Copy answer into caller's supplied buffer. */ 1492 if (cmd->odata != NULL) { 1493 if (hdr->len != cmd->odatalen) { 1494 device_printf(sc->sc_dev, 1495 "%s: code 0x%02x, len=%d, olen=%d\n", 1496 __func__, 1497 (int) hdr->code, 1498 (int) hdr->len, 1499 (int) cmd->odatalen); 1500 } 1501 memcpy(cmd->odata, &hdr[1], 1502 MIN(cmd->odatalen, hdr->len)); 1503 } 1504 wakeup(cmd); 1505 } 1506 1507 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next_cmd); 1508 } 1509 } 1510 1511 void 1512 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1513 { 1514 struct ieee80211com *ic = &sc->sc_ic; 1515 struct ar_cmd_hdr *hdr; 1516 1517 OTUS_LOCK_ASSERT(sc); 1518 1519 if (__predict_false(len < sizeof (*hdr))) { 1520 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1521 "cmd too small %d\n", len); 1522 return; 1523 } 1524 hdr = (struct ar_cmd_hdr *)buf; 1525 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1526 sizeof (*hdr) + hdr->len > 64)) { 1527 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1528 "cmd too large %d\n", hdr->len); 1529 return; 1530 } 1531 1532 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1533 "%s: code=%.02x\n", 1534 __func__, 1535 hdr->code); 1536 1537 /* 1538 * This has to reach into the cmd queue "waiting for 1539 * an RX response" list, grab the head entry and check 1540 * if we need to wake anyone up. 1541 */ 1542 if ((hdr->code & 0xc0) != 0xc0) { 1543 otus_cmd_handle_response(sc, hdr); 1544 return; 1545 } 1546 1547 /* Received unsolicited notification. */ 1548 switch (hdr->code & 0x3f) { 1549 case AR_EVT_BEACON: 1550 break; 1551 case AR_EVT_TX_COMP: 1552 { 1553 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1554 struct ieee80211_node *ni; 1555 1556 ni = ieee80211_find_node(&ic->ic_sta, tx->macaddr); 1557 if (ni == NULL) { 1558 device_printf(sc->sc_dev, 1559 "%s: txcomp on unknown node (%s)\n", 1560 __func__, 1561 ether_sprintf(tx->macaddr)); 1562 break; 1563 } 1564 1565 OTUS_DPRINTF(sc, OTUS_DEBUG_TXCOMP, 1566 "tx completed %s status=%d phy=0x%x\n", 1567 ether_sprintf(tx->macaddr), le16toh(tx->status), 1568 le32toh(tx->phy)); 1569 1570 switch (le16toh(tx->status)) { 1571 case AR_TX_STATUS_COMP: 1572 #if 0 1573 ackfailcnt = 0; 1574 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1575 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 1576 #endif 1577 /* 1578 * We don't get the above; only error notifications. 1579 * Sigh. So, don't worry about this. 1580 */ 1581 break; 1582 case AR_TX_STATUS_RETRY_COMP: 1583 OTUS_NODE(ni)->tx_retries++; 1584 break; 1585 case AR_TX_STATUS_FAILED: 1586 OTUS_NODE(ni)->tx_err++; 1587 break; 1588 } 1589 ieee80211_free_node(ni); 1590 break; 1591 } 1592 case AR_EVT_TBTT: 1593 break; 1594 case AR_EVT_DO_BB_RESET: 1595 /* 1596 * This is "tell driver to reset baseband" from ar9170-fw. 1597 * 1598 * I'm not sure what we should do here, so I'm going to 1599 * fall through; it gets generated when RTSRetryCnt internally 1600 * reaches '5' - I guess the firmware authors thought that 1601 * meant that the BB may have gone deaf or something. 1602 */ 1603 default: 1604 device_printf(sc->sc_dev, 1605 "%s: received notification code=0x%02x len=%d\n", 1606 __func__, 1607 hdr->code, hdr->len); 1608 } 1609 } 1610 1611 void 1612 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len, struct mbufq *rxq) 1613 { 1614 struct ieee80211com *ic = &sc->sc_ic; 1615 struct ieee80211_rx_stats rxs; 1616 #if 0 1617 struct ieee80211_node *ni; 1618 #endif 1619 struct ar_rx_tail *tail; 1620 struct ieee80211_frame *wh; 1621 struct mbuf *m; 1622 uint8_t *plcp; 1623 // int s; 1624 int mlen; 1625 1626 if (__predict_false(len < AR_PLCP_HDR_LEN)) { 1627 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1628 "sub-xfer too short %d\n", len); 1629 return; 1630 } 1631 plcp = buf; 1632 1633 /* All bits in the PLCP header are set to 1 for non-MPDU. */ 1634 if (memcmp(plcp, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1635 otus_cmd_rxeof(sc, plcp + AR_PLCP_HDR_LEN, 1636 len - AR_PLCP_HDR_LEN); 1637 return; 1638 } 1639 1640 /* Received MPDU. */ 1641 if (__predict_false(len < AR_PLCP_HDR_LEN + sizeof (*tail))) { 1642 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "MPDU too short %d\n", len); 1643 counter_u64_add(ic->ic_ierrors, 1); 1644 return; 1645 } 1646 tail = (struct ar_rx_tail *)(plcp + len - sizeof (*tail)); 1647 1648 /* Discard error frames; don't discard BAD_RA (eg monitor mode); let net80211 do that */ 1649 if (__predict_false((tail->error & ~AR_RX_ERROR_BAD_RA) != 0)) { 1650 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "error frame 0x%02x\n", tail->error); 1651 if (tail->error & AR_RX_ERROR_FCS) { 1652 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "bad FCS\n"); 1653 } else if (tail->error & AR_RX_ERROR_MMIC) { 1654 /* Report Michael MIC failures to net80211. */ 1655 #if 0 1656 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyidx); 1657 #endif 1658 device_printf(sc->sc_dev, "%s: MIC failure\n", __func__); 1659 } 1660 counter_u64_add(ic->ic_ierrors, 1); 1661 return; 1662 } 1663 /* Compute MPDU's length. */ 1664 mlen = len - AR_PLCP_HDR_LEN - sizeof (*tail); 1665 /* Make sure there's room for an 802.11 header + FCS. */ 1666 if (__predict_false(mlen < IEEE80211_MIN_LEN)) { 1667 counter_u64_add(ic->ic_ierrors, 1); 1668 return; 1669 } 1670 mlen -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1671 1672 wh = (struct ieee80211_frame *)(plcp + AR_PLCP_HDR_LEN); 1673 1674 /* 1675 * TODO: I see > 2KiB buffers in this path; is it A-MSDU or something? 1676 */ 1677 m = m_get2(mlen, M_NOWAIT, MT_DATA, M_PKTHDR); 1678 if (m == NULL) { 1679 device_printf(sc->sc_dev, "%s: failed m_get2() (mlen=%d)\n", __func__, mlen); 1680 counter_u64_add(ic->ic_ierrors, 1); 1681 return; 1682 } 1683 1684 /* Finalize mbuf. */ 1685 memcpy(mtod(m, uint8_t *), wh, mlen); 1686 m->m_pkthdr.len = m->m_len = mlen; 1687 1688 #if 0 1689 if (__predict_false(sc->sc_drvbpf != NULL)) { 1690 struct otus_rx_radiotap_header *tap = &sc->sc_rxtap; 1691 struct mbuf mb; 1692 1693 tap->wr_flags = 0; 1694 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1695 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1696 tap->wr_antsignal = tail->rssi; 1697 tap->wr_rate = 2; /* In case it can't be found below. */ 1698 switch (tail->status & AR_RX_STATUS_MT_MASK) { 1699 case AR_RX_STATUS_MT_CCK: 1700 switch (plcp[0]) { 1701 case 10: tap->wr_rate = 2; break; 1702 case 20: tap->wr_rate = 4; break; 1703 case 55: tap->wr_rate = 11; break; 1704 case 110: tap->wr_rate = 22; break; 1705 } 1706 if (tail->status & AR_RX_STATUS_SHPREAMBLE) 1707 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1708 break; 1709 case AR_RX_STATUS_MT_OFDM: 1710 switch (plcp[0] & 0xf) { 1711 case 0xb: tap->wr_rate = 12; break; 1712 case 0xf: tap->wr_rate = 18; break; 1713 case 0xa: tap->wr_rate = 24; break; 1714 case 0xe: tap->wr_rate = 36; break; 1715 case 0x9: tap->wr_rate = 48; break; 1716 case 0xd: tap->wr_rate = 72; break; 1717 case 0x8: tap->wr_rate = 96; break; 1718 case 0xc: tap->wr_rate = 108; break; 1719 } 1720 break; 1721 } 1722 mb.m_data = (caddr_t)tap; 1723 mb.m_next = m; 1724 mb.m_nextpkt = NULL; 1725 mb.m_type = 0; 1726 mb.m_flags = 0; 1727 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1728 } 1729 #endif 1730 1731 /* Add RSSI/NF to this mbuf */ 1732 bzero(&rxs, sizeof(rxs)); 1733 rxs.r_flags = IEEE80211_R_NF | IEEE80211_R_RSSI; 1734 rxs.nf = sc->sc_nf[0]; /* XXX chain 0 != combined rssi/nf */ 1735 rxs.rssi = tail->rssi; 1736 /* XXX TODO: add MIMO RSSI/NF as well */ 1737 ieee80211_add_rx_params(m, &rxs); 1738 1739 /* XXX make a method */ 1740 STAILQ_INSERT_TAIL(&rxq->mq_head, m, m_stailqpkt); 1741 1742 #if 0 1743 OTUS_UNLOCK(sc); 1744 ni = ieee80211_find_rxnode(ic, wh); 1745 rxi.rxi_flags = 0; 1746 rxi.rxi_rssi = tail->rssi; 1747 rxi.rxi_tstamp = 0; /* unused */ 1748 ieee80211_input(ifp, m, ni, &rxi); 1749 1750 /* Node is no longer needed. */ 1751 ieee80211_release_node(ic, ni); 1752 OTUS_LOCK(sc); 1753 #endif 1754 } 1755 1756 static void 1757 otus_rxeof(struct usb_xfer *xfer, struct otus_data *data, struct mbufq *rxq) 1758 { 1759 struct otus_softc *sc = usbd_xfer_softc(xfer); 1760 caddr_t buf = data->buf; 1761 struct ar_rx_head *head; 1762 uint16_t hlen; 1763 int len; 1764 1765 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 1766 1767 while (len >= sizeof (*head)) { 1768 head = (struct ar_rx_head *)buf; 1769 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1770 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1771 "tag not valid 0x%x\n", le16toh(head->tag)); 1772 break; 1773 } 1774 hlen = le16toh(head->len); 1775 if (__predict_false(sizeof (*head) + hlen > len)) { 1776 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1777 "xfer too short %d/%d\n", len, hlen); 1778 break; 1779 } 1780 /* Process sub-xfer. */ 1781 otus_sub_rxeof(sc, (uint8_t *)&head[1], hlen, rxq); 1782 1783 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1784 hlen = (sizeof (*head) + hlen + 3) & ~3; 1785 buf += hlen; 1786 len -= hlen; 1787 } 1788 } 1789 1790 static void 1791 otus_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1792 { 1793 struct otus_softc *sc = usbd_xfer_softc(xfer); 1794 struct ieee80211com *ic = &sc->sc_ic; 1795 struct ieee80211_frame *wh; 1796 struct ieee80211_node *ni; 1797 struct mbuf *m; 1798 struct mbufq scrx; 1799 struct otus_data *data; 1800 1801 OTUS_LOCK_ASSERT(sc); 1802 1803 mbufq_init(&scrx, 1024); 1804 1805 #if 0 1806 device_printf(sc->sc_dev, "%s: called; state=%d; error=%d\n", 1807 __func__, 1808 USB_GET_STATE(xfer), 1809 error); 1810 #endif 1811 1812 switch (USB_GET_STATE(xfer)) { 1813 case USB_ST_TRANSFERRED: 1814 data = STAILQ_FIRST(&sc->sc_rx_active); 1815 if (data == NULL) 1816 goto tr_setup; 1817 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1818 otus_rxeof(xfer, data, &scrx); 1819 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1820 /* FALLTHROUGH */ 1821 case USB_ST_SETUP: 1822 tr_setup: 1823 /* 1824 * XXX TODO: what if sc_rx isn't empty, but data 1825 * is empty? Then we leak mbufs. 1826 */ 1827 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1828 if (data == NULL) { 1829 //KASSERT(m == NULL, ("mbuf isn't NULL")); 1830 return; 1831 } 1832 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1833 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1834 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1835 usbd_xfer_max_len(xfer)); 1836 usbd_transfer_submit(xfer); 1837 /* 1838 * To avoid LOR we should unlock our private mutex here to call 1839 * ieee80211_input() because here is at the end of a USB 1840 * callback and safe to unlock. 1841 */ 1842 OTUS_UNLOCK(sc); 1843 while ((m = mbufq_dequeue(&scrx)) != NULL) { 1844 wh = mtod(m, struct ieee80211_frame *); 1845 ni = ieee80211_find_rxnode(ic, 1846 (struct ieee80211_frame_min *)wh); 1847 if (ni != NULL) { 1848 if (ni->ni_flags & IEEE80211_NODE_HT) 1849 m->m_flags |= M_AMPDU; 1850 (void)ieee80211_input_mimo(ni, m, NULL); 1851 ieee80211_free_node(ni); 1852 } else 1853 (void)ieee80211_input_mimo_all(ic, m, NULL); 1854 } 1855 #ifdef IEEE80211_SUPPORT_SUPERG 1856 ieee80211_ff_age_all(ic, 100); 1857 #endif 1858 OTUS_LOCK(sc); 1859 break; 1860 default: 1861 /* needs it to the inactive queue due to a error. */ 1862 data = STAILQ_FIRST(&sc->sc_rx_active); 1863 if (data != NULL) { 1864 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1865 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1866 } 1867 if (error != USB_ERR_CANCELLED) { 1868 usbd_xfer_set_stall(xfer); 1869 counter_u64_add(ic->ic_ierrors, 1); 1870 goto tr_setup; 1871 } 1872 break; 1873 } 1874 } 1875 1876 static void 1877 otus_txeof(struct usb_xfer *xfer, struct otus_data *data) 1878 { 1879 struct otus_softc *sc = usbd_xfer_softc(xfer); 1880 1881 OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, 1882 "%s: called; data=%p\n", __func__, data); 1883 1884 OTUS_LOCK_ASSERT(sc); 1885 1886 if (sc->sc_tx_n_active == 0) { 1887 device_printf(sc->sc_dev, 1888 "%s: completed but tx_active=0\n", 1889 __func__); 1890 } else { 1891 sc->sc_tx_n_active--; 1892 } 1893 1894 if (data->m) { 1895 /* XXX status? */ 1896 /* XXX we get TX status via the RX path.. */ 1897 ieee80211_tx_complete(data->ni, data->m, 0); 1898 data->m = NULL; 1899 data->ni = NULL; 1900 } 1901 } 1902 1903 static void 1904 otus_txcmdeof(struct usb_xfer *xfer, struct otus_tx_cmd *cmd) 1905 { 1906 struct otus_softc *sc = usbd_xfer_softc(xfer); 1907 1908 OTUS_LOCK_ASSERT(sc); 1909 1910 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1911 "%s: called; data=%p; odata=%p\n", 1912 __func__, cmd, cmd->odata); 1913 1914 /* 1915 * Non-response commands still need wakeup so the caller 1916 * knows it was submitted and completed OK; response commands should 1917 * wait until they're ACKed by the firmware with a response. 1918 */ 1919 if (cmd->odata) { 1920 STAILQ_INSERT_TAIL(&sc->sc_cmd_waiting, cmd, next_cmd); 1921 } else { 1922 wakeup(cmd); 1923 otus_free_txcmd(sc, cmd); 1924 } 1925 } 1926 1927 static void 1928 otus_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1929 { 1930 uint8_t which = OTUS_BULK_TX; 1931 struct otus_softc *sc = usbd_xfer_softc(xfer); 1932 struct ieee80211com *ic = &sc->sc_ic; 1933 struct otus_data *data; 1934 1935 OTUS_LOCK_ASSERT(sc); 1936 1937 switch (USB_GET_STATE(xfer)) { 1938 case USB_ST_TRANSFERRED: 1939 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1940 if (data == NULL) 1941 goto tr_setup; 1942 OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, 1943 "%s: transfer done %p\n", __func__, data); 1944 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1945 otus_txeof(xfer, data); 1946 otus_freebuf(sc, data); 1947 /* FALLTHROUGH */ 1948 case USB_ST_SETUP: 1949 tr_setup: 1950 data = STAILQ_FIRST(&sc->sc_tx_pending[which]); 1951 if (data == NULL) { 1952 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 1953 "%s: empty pending queue sc %p\n", __func__, sc); 1954 sc->sc_tx_n_active = 0; 1955 goto finish; 1956 } 1957 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending[which], next); 1958 STAILQ_INSERT_TAIL(&sc->sc_tx_active[which], data, next); 1959 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1960 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 1961 "%s: submitting transfer %p\n", __func__, data); 1962 usbd_transfer_submit(xfer); 1963 sc->sc_tx_n_active++; 1964 break; 1965 default: 1966 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1967 if (data != NULL) { 1968 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1969 otus_txeof(xfer, data); 1970 otus_freebuf(sc, data); 1971 } 1972 counter_u64_add(ic->ic_oerrors, 1); 1973 1974 if (error != USB_ERR_CANCELLED) { 1975 usbd_xfer_set_stall(xfer); 1976 goto tr_setup; 1977 } 1978 break; 1979 } 1980 1981 finish: 1982 #ifdef IEEE80211_SUPPORT_SUPERG 1983 /* 1984 * If the TX active queue drops below a certain 1985 * threshold, ensure we age fast-frames out so they're 1986 * transmitted. 1987 */ 1988 if (sc->sc_tx_n_active < 2) { 1989 /* XXX ew - net80211 should defer this for us! */ 1990 OTUS_UNLOCK(sc); 1991 ieee80211_ff_flush(ic, WME_AC_VO); 1992 ieee80211_ff_flush(ic, WME_AC_VI); 1993 ieee80211_ff_flush(ic, WME_AC_BE); 1994 ieee80211_ff_flush(ic, WME_AC_BK); 1995 OTUS_LOCK(sc); 1996 } 1997 #endif 1998 /* Kick TX */ 1999 otus_tx_start(sc); 2000 } 2001 2002 static void 2003 otus_bulk_cmd_callback(struct usb_xfer *xfer, usb_error_t error) 2004 { 2005 struct otus_softc *sc = usbd_xfer_softc(xfer); 2006 #if 0 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 #endif 2009 struct otus_tx_cmd *cmd; 2010 2011 OTUS_LOCK_ASSERT(sc); 2012 2013 switch (USB_GET_STATE(xfer)) { 2014 case USB_ST_TRANSFERRED: 2015 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2016 if (cmd == NULL) 2017 goto tr_setup; 2018 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 2019 "%s: transfer done %p\n", __func__, cmd); 2020 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); 2021 otus_txcmdeof(xfer, cmd); 2022 /* FALLTHROUGH */ 2023 case USB_ST_SETUP: 2024 tr_setup: 2025 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2026 if (cmd == NULL) { 2027 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 2028 "%s: empty pending queue sc %p\n", __func__, sc); 2029 return; 2030 } 2031 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next_cmd); 2032 STAILQ_INSERT_TAIL(&sc->sc_cmd_active, cmd, next_cmd); 2033 usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); 2034 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 2035 "%s: submitting transfer %p; buf=%p, buflen=%d\n", __func__, cmd, cmd->buf, cmd->buflen); 2036 usbd_transfer_submit(xfer); 2037 break; 2038 default: 2039 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2040 if (cmd != NULL) { 2041 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); 2042 otus_txcmdeof(xfer, cmd); 2043 } 2044 2045 if (error != USB_ERR_CANCELLED) { 2046 usbd_xfer_set_stall(xfer); 2047 goto tr_setup; 2048 } 2049 break; 2050 } 2051 } 2052 2053 /* 2054 * This isn't used by carl9170; it however may be used by the 2055 * initial bootloader. 2056 */ 2057 static void 2058 otus_bulk_irq_callback(struct usb_xfer *xfer, usb_error_t error) 2059 { 2060 struct otus_softc *sc = usbd_xfer_softc(xfer); 2061 int actlen; 2062 int sumlen; 2063 2064 usbd_xfer_status(xfer, &actlen, &sumlen, NULL, NULL); 2065 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, 2066 "%s: called; state=%d\n", __func__, USB_GET_STATE(xfer)); 2067 2068 switch (USB_GET_STATE(xfer)) { 2069 case USB_ST_TRANSFERRED: 2070 /* 2071 * Read usb frame data, if any. 2072 * "actlen" has the total length for all frames 2073 * transferred. 2074 */ 2075 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, 2076 "%s: comp; %d bytes\n", 2077 __func__, 2078 actlen); 2079 #if 0 2080 pc = usbd_xfer_get_frame(xfer, 0); 2081 otus_dump_usb_rx_page(sc, pc, actlen); 2082 #endif 2083 /* XXX fallthrough */ 2084 case USB_ST_SETUP: 2085 /* 2086 * Setup xfer frame lengths/count and data 2087 */ 2088 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: setup\n", __func__); 2089 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 2090 usbd_transfer_submit(xfer); 2091 break; 2092 2093 default: /* Error */ 2094 /* 2095 * Print error message and clear stall 2096 * for example. 2097 */ 2098 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: ERROR?\n", __func__); 2099 break; 2100 } 2101 } 2102 2103 /* 2104 * Map net80211 rate to hw rate for otus MAC/PHY. 2105 */ 2106 static uint8_t 2107 otus_rate_to_hw_rate(struct otus_softc *sc, uint8_t rate) 2108 { 2109 int is_2ghz; 2110 2111 is_2ghz = !! (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_curchan)); 2112 2113 switch (rate) { 2114 /* CCK */ 2115 case 2: 2116 return (0x0); 2117 case 4: 2118 return (0x1); 2119 case 11: 2120 return (0x2); 2121 case 22: 2122 return (0x3); 2123 /* OFDM */ 2124 case 12: 2125 return (0xb); 2126 case 18: 2127 return (0xf); 2128 case 24: 2129 return (0xa); 2130 case 36: 2131 return (0xe); 2132 case 48: 2133 return (0x9); 2134 case 72: 2135 return (0xd); 2136 case 96: 2137 return (0x8); 2138 case 108: 2139 return (0xc); 2140 default: 2141 device_printf(sc->sc_dev, "%s: unknown rate '%d'\n", 2142 __func__, (int) rate); 2143 case 0: 2144 if (is_2ghz) 2145 return (0x0); /* 1MB CCK */ 2146 else 2147 return (0xb); /* 6MB OFDM */ 2148 2149 /* XXX TODO: HT */ 2150 } 2151 } 2152 2153 static int 2154 otus_hw_rate_is_ofdm(struct otus_softc *sc, uint8_t hw_rate) 2155 { 2156 2157 switch (hw_rate) { 2158 case 0x0: 2159 case 0x1: 2160 case 0x2: 2161 case 0x3: 2162 return (0); 2163 default: 2164 return (1); 2165 } 2166 } 2167 2168 2169 static void 2170 otus_tx_update_ratectl(struct otus_softc *sc, struct ieee80211_node *ni) 2171 { 2172 int tx, tx_success, tx_retry; 2173 2174 tx = OTUS_NODE(ni)->tx_done; 2175 tx_success = OTUS_NODE(ni)->tx_done - OTUS_NODE(ni)->tx_err; 2176 tx_retry = OTUS_NODE(ni)->tx_retries; 2177 2178 ieee80211_ratectl_tx_update(ni->ni_vap, ni, &tx, &tx_success, 2179 &tx_retry); 2180 } 2181 2182 /* 2183 * XXX TODO: support tx bpf parameters for configuration! 2184 * 2185 * Relevant pieces: 2186 * 2187 * ac = params->ibp_pri & 3; 2188 * rate = params->ibp_rate0; 2189 * params->ibp_flags & IEEE80211_BPF_NOACK 2190 * params->ibp_flags & IEEE80211_BPF_RTS 2191 * params->ibp_flags & IEEE80211_BPF_CTS 2192 * tx->rts_ntries = params->ibp_try1; 2193 * tx->data_ntries = params->ibp_try0; 2194 */ 2195 static int 2196 otus_tx(struct otus_softc *sc, struct ieee80211_node *ni, struct mbuf *m, 2197 struct otus_data *data, const struct ieee80211_bpf_params *params) 2198 { 2199 struct ieee80211com *ic = &sc->sc_ic; 2200 struct ieee80211vap *vap = ni->ni_vap; 2201 struct ieee80211_frame *wh; 2202 struct ieee80211_key *k; 2203 struct ar_tx_head *head; 2204 uint32_t phyctl; 2205 uint16_t macctl, qos; 2206 uint8_t qid, rate; 2207 int hasqos, xferlen; 2208 2209 wh = mtod(m, struct ieee80211_frame *); 2210 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2211 k = ieee80211_crypto_encap(ni, m); 2212 if (k == NULL) { 2213 device_printf(sc->sc_dev, 2214 "%s: m=%p: ieee80211_crypto_encap returns NULL\n", 2215 __func__, 2216 m); 2217 return (ENOBUFS); 2218 } 2219 wh = mtod(m, struct ieee80211_frame *); 2220 } 2221 2222 /* Calculate transfer length; ensure data buffer is large enough */ 2223 xferlen = sizeof (*head) + m->m_pkthdr.len; 2224 if (xferlen > OTUS_TXBUFSZ) { 2225 device_printf(sc->sc_dev, 2226 "%s: 802.11 TX frame is %d bytes, max %d bytes\n", 2227 __func__, 2228 xferlen, 2229 OTUS_TXBUFSZ); 2230 return (ENOBUFS); 2231 } 2232 2233 hasqos = !! IEEE80211_QOS_HAS_SEQ(wh); 2234 2235 if (hasqos) { 2236 uint8_t tid; 2237 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2238 tid = qos & IEEE80211_QOS_TID; 2239 qid = TID_TO_WME_AC(tid); 2240 } else { 2241 qos = 0; 2242 qid = WME_AC_BE; 2243 } 2244 2245 /* Pickup a rate index. */ 2246 if (params != NULL) { 2247 rate = otus_rate_to_hw_rate(sc, params->ibp_rate0); 2248 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2249 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) { 2250 /* Get lowest rate */ 2251 rate = otus_rate_to_hw_rate(sc, 0); 2252 } else if (m->m_flags & M_EAPOL) { 2253 /* Get lowest rate */ 2254 rate = otus_rate_to_hw_rate(sc, 0); 2255 } else { 2256 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2257 rate = otus_rate_to_hw_rate(sc, ni->ni_txrate); 2258 } 2259 2260 phyctl = 0; 2261 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 2262 2263 /* 2264 * XXX TODO: params for NOACK, ACK, RTS, CTS, etc 2265 */ 2266 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2267 (hasqos && ((qos & IEEE80211_QOS_ACKPOLICY) == 2268 IEEE80211_QOS_ACKPOLICY_NOACK))) 2269 macctl |= AR_TX_MAC_NOACK; 2270 2271 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2272 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= vap->iv_rtsthreshold) 2273 macctl |= AR_TX_MAC_RTS; 2274 else if (ic->ic_flags & IEEE80211_F_USEPROT) { 2275 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2276 macctl |= AR_TX_MAC_CTS; 2277 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2278 macctl |= AR_TX_MAC_RTS; 2279 } 2280 } 2281 2282 phyctl |= AR_TX_PHY_MCS(rate); 2283 if (otus_hw_rate_is_ofdm(sc, rate)) { 2284 phyctl |= AR_TX_PHY_MT_OFDM; 2285 /* Always use all tx antennas for now, just to be safe */ 2286 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2287 } else { /* CCK */ 2288 phyctl |= AR_TX_PHY_MT_CCK; 2289 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2290 } 2291 2292 /* Update net80211 with the current counters */ 2293 otus_tx_update_ratectl(sc, ni); 2294 2295 /* Update rate control stats for frames that are ACK'ed. */ 2296 if (!(macctl & AR_TX_MAC_NOACK)) 2297 OTUS_NODE(ni)->tx_done++; 2298 2299 2300 /* Fill Tx descriptor. */ 2301 head = (struct ar_tx_head *)data->buf; 2302 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 2303 head->macctl = htole16(macctl); 2304 head->phyctl = htole32(phyctl); 2305 2306 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); 2307 2308 data->buflen = xferlen; 2309 data->ni = ni; 2310 data->m = m; 2311 2312 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 2313 "%s: tx: m=%p; data=%p; len=%d mac=0x%04x phy=0x%08x rate=0x%02x, ni_txrate=%d\n", 2314 __func__, m, data, le16toh(head->len), macctl, phyctl, 2315 (int) rate, (int) ni->ni_txrate); 2316 2317 /* Submit transfer */ 2318 STAILQ_INSERT_TAIL(&sc->sc_tx_pending[OTUS_BULK_TX], data, next); 2319 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_TX]); 2320 2321 return 0; 2322 } 2323 2324 int 2325 otus_set_multi(struct otus_softc *sc) 2326 { 2327 uint32_t lo, hi; 2328 struct ieee80211com *ic = &sc->sc_ic; 2329 int r; 2330 2331 if (ic->ic_allmulti > 0 || ic->ic_promisc > 0 || 2332 ic->ic_opmode == IEEE80211_M_MONITOR) { 2333 lo = 0xffffffff; 2334 hi = 0xffffffff; 2335 } else { 2336 struct ieee80211vap *vap; 2337 struct ifnet *ifp; 2338 struct ifmultiaddr *ifma; 2339 2340 lo = hi = 0; 2341 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 2342 ifp = vap->iv_ifp; 2343 if_maddr_rlock(ifp); 2344 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2345 caddr_t dl; 2346 uint32_t val; 2347 2348 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2349 val = LE_READ_4(dl + 4); 2350 /* Get address byte 5 */ 2351 val = val & 0x0000ff00; 2352 val = val >> 8; 2353 2354 /* As per below, shift it >> 2 to get only 6 bits */ 2355 val = val >> 2; 2356 if (val < 32) 2357 lo |= 1 << val; 2358 else 2359 hi |= 1 << (val - 32); 2360 } 2361 if_maddr_runlock(ifp); 2362 } 2363 } 2364 #if 0 2365 /* XXX openbsd code */ 2366 while (enm != NULL) { 2367 bit = enm->enm_addrlo[5] >> 2; 2368 if (bit < 32) 2369 lo |= 1 << bit; 2370 else 2371 hi |= 1 << (bit - 32); 2372 ETHER_NEXT_MULTI(step, enm); 2373 } 2374 #endif 2375 2376 hi |= 1U << 31; /* Make sure the broadcast bit is set. */ 2377 2378 OTUS_LOCK(sc); 2379 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo); 2380 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi); 2381 r = otus_write_barrier(sc); 2382 OTUS_UNLOCK(sc); 2383 return (r); 2384 } 2385 2386 static void 2387 otus_updateedca(struct otus_softc *sc) 2388 { 2389 #define EXP2(val) ((1 << (val)) - 1) 2390 #define AIFS(val) ((val) * 9 + 10) 2391 struct ieee80211com *ic = &sc->sc_ic; 2392 const struct wmeParams *edca; 2393 2394 OTUS_LOCK_ASSERT(sc); 2395 2396 edca = ic->ic_wme.wme_chanParams.cap_wmeParams; 2397 2398 /* Set CWmin/CWmax values. */ 2399 otus_write(sc, AR_MAC_REG_AC0_CW, 2400 EXP2(edca[WME_AC_BE].wmep_logcwmax) << 16 | 2401 EXP2(edca[WME_AC_BE].wmep_logcwmin)); 2402 otus_write(sc, AR_MAC_REG_AC1_CW, 2403 EXP2(edca[WME_AC_BK].wmep_logcwmax) << 16 | 2404 EXP2(edca[WME_AC_BK].wmep_logcwmin)); 2405 otus_write(sc, AR_MAC_REG_AC2_CW, 2406 EXP2(edca[WME_AC_VI].wmep_logcwmax) << 16 | 2407 EXP2(edca[WME_AC_VI].wmep_logcwmin)); 2408 otus_write(sc, AR_MAC_REG_AC3_CW, 2409 EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | 2410 EXP2(edca[WME_AC_VO].wmep_logcwmin)); 2411 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 2412 EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | 2413 EXP2(edca[WME_AC_VO].wmep_logcwmin)); 2414 2415 /* Set AIFSN values. */ 2416 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 2417 AIFS(edca[WME_AC_VI].wmep_aifsn) << 24 | 2418 AIFS(edca[WME_AC_BK].wmep_aifsn) << 12 | 2419 AIFS(edca[WME_AC_BE].wmep_aifsn)); 2420 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 2421 AIFS(edca[WME_AC_VO].wmep_aifsn) << 16 | /* Special TXQ. */ 2422 AIFS(edca[WME_AC_VO].wmep_aifsn) << 4 | 2423 AIFS(edca[WME_AC_VI].wmep_aifsn) >> 8); 2424 2425 /* Set TXOP limit. */ 2426 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 2427 edca[WME_AC_BK].wmep_txopLimit << 16 | 2428 edca[WME_AC_BE].wmep_txopLimit); 2429 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 2430 edca[WME_AC_VO].wmep_txopLimit << 16 | 2431 edca[WME_AC_VI].wmep_txopLimit); 2432 2433 /* XXX ACK policy? */ 2434 2435 (void)otus_write_barrier(sc); 2436 2437 #undef AIFS 2438 #undef EXP2 2439 } 2440 2441 static void 2442 otus_updateslot(struct otus_softc *sc) 2443 { 2444 struct ieee80211com *ic = &sc->sc_ic; 2445 uint32_t slottime; 2446 2447 OTUS_LOCK_ASSERT(sc); 2448 2449 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2450 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 2451 (void)otus_write_barrier(sc); 2452 } 2453 2454 int 2455 otus_init_mac(struct otus_softc *sc) 2456 { 2457 int error; 2458 2459 OTUS_LOCK_ASSERT(sc); 2460 2461 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 2462 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 2463 otus_write(sc, AR_MAC_REG_SNIFFER, 0x2000000); 2464 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 2465 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 2466 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 2467 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 2468 otus_write(sc, AR_MAC_REG_TID_CFACK_CFEND_RATE, 0x19000000); 2469 /* NAV protects ACK only (in TXOP). */ 2470 otus_write(sc, AR_MAC_REG_TXOP_DURATION, 0x201); 2471 /* Set beacon Tx power to 0x7. */ 2472 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 2473 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 2474 otus_write(sc, AR_MAC_REG_AMPDU_FACTOR, 0x10000a); 2475 /* Filter any control frames, BAR is bit 24. */ 2476 // otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0x0500ffff); 2477 // otus_write(sc, AR_MAC_REG_RX_CONTROL, 0x1); 2478 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 2479 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 2480 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 2481 otus_write(sc, AR_MAC_REG_ACK_TPC, 0x4003c1e); 2482 /* Enable LED0 and LED1. */ 2483 otus_write(sc, AR_GPIO_REG_PORT_TYPE, 0x3); 2484 otus_write(sc, AR_GPIO_REG_PORT_DATA, 0x3); 2485 /* Switch MAC to OTUS interface. */ 2486 otus_write(sc, 0x1c3600, 0x3); 2487 otus_write(sc, AR_MAC_REG_AMPDU_RX_THRESH, 0xffff); 2488 otus_write(sc, AR_MAC_REG_MISC_680, 0xf00008); 2489 /* Disable Rx timeout (workaround). */ 2490 otus_write(sc, AR_MAC_REG_RX_TIMEOUT, 0); 2491 2492 /* Set USB Rx stream mode maximum frame number to 2. */ 2493 otus_write(sc, 0x1e1110, 0x4); 2494 /* Set USB Rx stream mode timeout to 10us. */ 2495 otus_write(sc, 0x1e1114, 0x80); 2496 2497 /* Set clock frequency to 88/80MHz. */ 2498 otus_write(sc, AR_PWR_REG_CLOCK_SEL, 0x73); 2499 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 2500 otus_write(sc, AR_MAC_REG_TXRX_MPI, 0x110011); 2501 otus_write(sc, AR_MAC_REG_FCS_SELECT, 0x4); 2502 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 2503 2504 /* Disable HW decryption for now. */ 2505 otus_write(sc, AR_MAC_REG_ENCRYPTION, 0x78); 2506 2507 if ((error = otus_write_barrier(sc)) != 0) 2508 return error; 2509 2510 /* Set default EDCA parameters. */ 2511 otus_updateedca(sc); 2512 2513 return 0; 2514 } 2515 2516 /* 2517 * Return default value for PHY register based on current operating mode. 2518 */ 2519 uint32_t 2520 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 2521 { 2522 int i; 2523 2524 for (i = 0; i < nitems(ar5416_phy_regs); i++) 2525 if (AR_PHY(ar5416_phy_regs[i]) == reg) 2526 return sc->phy_vals[i]; 2527 return 0; /* Register not found. */ 2528 } 2529 2530 /* 2531 * Update PHY's programming based on vendor-specific data stored in EEPROM. 2532 * This is for FEM-type devices only. 2533 */ 2534 int 2535 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 2536 { 2537 const struct ModalEepHeader *eep; 2538 uint32_t tmp, offset; 2539 2540 if (IEEE80211_IS_CHAN_5GHZ(c)) 2541 eep = &sc->eeprom.modalHeader[0]; 2542 else 2543 eep = &sc->eeprom.modalHeader[1]; 2544 2545 /* Offset of chain 2. */ 2546 offset = 2 * 0x1000; 2547 2548 tmp = le32toh(eep->antCtrlCommon); 2549 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 2550 2551 tmp = le32toh(eep->antCtrlChain[0]); 2552 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 2553 2554 tmp = le32toh(eep->antCtrlChain[1]); 2555 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 2556 2557 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 2558 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 2559 tmp &= ~(0x7f << 7); 2560 tmp |= (eep->switchSettling & 0x7f) << 7; 2561 otus_write(sc, AR_PHY_SETTLING, tmp); 2562 } 2563 2564 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 2565 tmp &= ~0xffff; 2566 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 2567 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 2568 2569 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 2570 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 2571 otus_write(sc, AR_PHY_RF_CTL4, tmp); 2572 2573 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 2574 tmp &= ~(0xff << 16); 2575 tmp |= eep->txEndToRxOn << 16; 2576 otus_write(sc, AR_PHY_RF_CTL3, tmp); 2577 2578 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 2579 tmp &= ~(0x7f << 12); 2580 tmp |= (eep->thresh62 & 0x7f) << 12; 2581 otus_write(sc, AR_PHY_CCA, tmp); 2582 2583 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 2584 tmp &= ~(0x3f << 12); 2585 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 2586 otus_write(sc, AR_PHY_RXGAIN, tmp); 2587 2588 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 2589 tmp &= ~(0x3f << 12); 2590 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 2591 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 2592 2593 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 2594 tmp &= ~(0x3f << 18); 2595 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 2596 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2597 tmp &= ~(0xf << 10); 2598 tmp |= (eep->bswMargin[0] & 0xf) << 10; 2599 } 2600 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 2601 2602 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 2603 tmp &= ~(0x3f << 18); 2604 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 2605 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 2606 2607 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 2608 tmp &= ~(0x3f << 5 | 0x1f); 2609 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 2610 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 2611 2612 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 2613 tmp &= ~(0x3f << 5 | 0x1f); 2614 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 2615 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 2616 2617 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 2618 tmp &= ~(0xf << 16); 2619 tmp |= (eep->xpd & 0xf) << 16; 2620 otus_write(sc, AR_PHY_TPCRG1, tmp); 2621 2622 return otus_write_barrier(sc); 2623 } 2624 2625 int 2626 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 2627 { 2628 const uint32_t *vals; 2629 int error, i; 2630 2631 /* Select PHY programming based on band and bandwidth. */ 2632 if (IEEE80211_IS_CHAN_2GHZ(c)) 2633 vals = ar5416_phy_vals_2ghz_20mhz; 2634 else 2635 vals = ar5416_phy_vals_5ghz_20mhz; 2636 for (i = 0; i < nitems(ar5416_phy_regs); i++) 2637 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 2638 sc->phy_vals = vals; 2639 2640 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 2641 if ((error = otus_set_board_values(sc, c)) != 0) 2642 return error; 2643 2644 /* Initial Tx power settings. */ 2645 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 2646 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 2647 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 2648 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 2649 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 2650 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 2651 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 2652 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 2653 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 2654 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 2655 2656 if (IEEE80211_IS_CHAN_2GHZ(c)) 2657 otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5163); 2658 else 2659 otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5143); 2660 2661 return otus_write_barrier(sc); 2662 } 2663 2664 static __inline uint8_t 2665 otus_reverse_bits(uint8_t v) 2666 { 2667 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 2668 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 2669 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 2670 return v; 2671 } 2672 2673 int 2674 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 2675 { 2676 uint8_t chansel, d0, d1; 2677 uint16_t data; 2678 int error; 2679 2680 OTUS_LOCK_ASSERT(sc); 2681 2682 d0 = 0; 2683 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2684 chansel = (c->ic_freq - 4800) / 5; 2685 if (chansel & 1) 2686 d0 |= AR_BANK4_AMODE_REFSEL(2); 2687 else 2688 d0 |= AR_BANK4_AMODE_REFSEL(1); 2689 } else { 2690 d0 |= AR_BANK4_AMODE_REFSEL(2); 2691 if (c->ic_freq == 2484) { /* CH 14 */ 2692 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 2693 chansel = 10 + (c->ic_freq - 2274) / 5; 2694 } else 2695 chansel = 16 + (c->ic_freq - 2272) / 5; 2696 chansel <<= 2; 2697 } 2698 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 2699 d1 = otus_reverse_bits(chansel); 2700 2701 /* Write bits 0-4 of d0 and d1. */ 2702 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 2703 otus_write(sc, AR_PHY(44), data); 2704 /* Write bits 5-7 of d0 and d1. */ 2705 data = (d1 >> 5) << 5 | (d0 >> 5); 2706 otus_write(sc, AR_PHY(58), data); 2707 2708 if ((error = otus_write_barrier(sc)) == 0) 2709 otus_delay_ms(sc, 10); 2710 return error; 2711 } 2712 2713 void 2714 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 2715 { 2716 #define COEFF_SCALE_SHIFT 24 2717 uint32_t exp, man; 2718 2719 /* exponent = 14 - floor(log2(coeff)) */ 2720 for (exp = 31; exp > 0; exp--) 2721 if (coeff & (1 << exp)) 2722 break; 2723 KASSERT(exp != 0, ("exp")); 2724 exp = 14 - (exp - COEFF_SCALE_SHIFT); 2725 2726 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 2727 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 2728 2729 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 2730 *exponent = exp - 16; 2731 #undef COEFF_SCALE_SHIFT 2732 } 2733 2734 static int 2735 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 2736 { 2737 struct ieee80211com *ic = &sc->sc_ic; 2738 struct ar_cmd_frequency cmd; 2739 struct ar_rsp_frequency rsp; 2740 const uint32_t *vals; 2741 uint32_t coeff, exp, man, tmp; 2742 uint8_t code; 2743 int error, chan, i; 2744 2745 error = 0; 2746 chan = ieee80211_chan2ieee(ic, c); 2747 2748 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2749 "setting channel %d (%dMHz)\n", chan, c->ic_freq); 2750 2751 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 2752 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 2753 if ((error = otus_write_barrier(sc)) != 0) 2754 goto finish; 2755 2756 /* Disable BB Heavy Clip. */ 2757 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 2758 if ((error = otus_write_barrier(sc)) != 0) 2759 goto finish; 2760 2761 /* XXX Is that FREQ_START ? */ 2762 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL, 0); 2763 if (error != 0) 2764 goto finish; 2765 2766 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 2767 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 2768 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "band switch\n"); 2769 2770 /* Cold/Warm reset BB/ADDA. */ 2771 otus_write(sc, AR_PWR_REG_RESET, sc->bb_reset ? 0x800 : 0x400); 2772 if ((error = otus_write_barrier(sc)) != 0) 2773 goto finish; 2774 otus_write(sc, AR_PWR_REG_RESET, 0); 2775 if ((error = otus_write_barrier(sc)) != 0) 2776 goto finish; 2777 sc->bb_reset = 0; 2778 2779 if ((error = otus_program_phy(sc, c)) != 0) { 2780 device_printf(sc->sc_dev, 2781 "%s: could not program PHY\n", 2782 __func__); 2783 goto finish; 2784 } 2785 2786 /* Select RF programming based on band. */ 2787 if (IEEE80211_IS_CHAN_5GHZ(c)) 2788 vals = ar5416_banks_vals_5ghz; 2789 else 2790 vals = ar5416_banks_vals_2ghz; 2791 for (i = 0; i < nitems(ar5416_banks_regs); i++) 2792 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 2793 if ((error = otus_write_barrier(sc)) != 0) { 2794 device_printf(sc->sc_dev, 2795 "%s: could not program RF\n", 2796 __func__); 2797 goto finish; 2798 } 2799 code = AR_CMD_RF_INIT; 2800 } else { 2801 code = AR_CMD_FREQUENCY; 2802 } 2803 2804 if ((error = otus_set_rf_bank4(sc, c)) != 0) 2805 goto finish; 2806 2807 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 2808 otus_write(sc, AR_PHY_TURBO, tmp); 2809 if ((error = otus_write_barrier(sc)) != 0) 2810 goto finish; 2811 2812 /* Send firmware command to set channel. */ 2813 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2814 cmd.dynht2040 = htole32(0); 2815 cmd.htena = htole32(1); 2816 /* Set Delta Slope (exponent and mantissa). */ 2817 coeff = (100 << 24) / c->ic_freq; 2818 otus_get_delta_slope(coeff, &exp, &man); 2819 cmd.dsc_exp = htole32(exp); 2820 cmd.dsc_man = htole32(man); 2821 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2822 "ds coeff=%u exp=%u man=%u\n", coeff, exp, man); 2823 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2824 coeff = (9 * coeff) / 10; 2825 otus_get_delta_slope(coeff, &exp, &man); 2826 cmd.dsc_shgi_exp = htole32(exp); 2827 cmd.dsc_shgi_man = htole32(man); 2828 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2829 "ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man); 2830 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2831 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2832 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2833 "%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY"); 2834 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp, sizeof(rsp)); 2835 if (error != 0) 2836 goto finish; 2837 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2838 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2839 "status=0x%x\n", le32toh(rsp.status)); 2840 /* Force cold reset on next channel. */ 2841 sc->bb_reset = 1; 2842 } 2843 #ifdef USB_DEBUG 2844 if (otus_debug & OTUS_DEBUG_RESET) { 2845 device_printf(sc->sc_dev, "calibration status=0x%x\n", 2846 le32toh(rsp.status)); 2847 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2848 /* Sign-extend 9-bit NF values. */ 2849 device_printf(sc->sc_dev, 2850 "noisefloor chain %d=%d\n", i, 2851 (((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); 2852 device_printf(sc->sc_dev, 2853 "noisefloor ext chain %d=%d\n", i, 2854 ((int32_t)le32toh(rsp.nf_ext[i])) >> 23); 2855 } 2856 } 2857 #endif 2858 for (i = 0; i < OTUS_NUM_CHAINS; i++) { 2859 sc->sc_nf[i] = ((((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); 2860 } 2861 sc->sc_curchan = c; 2862 finish: 2863 return (error); 2864 } 2865 2866 #ifdef notyet 2867 int 2868 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2869 struct ieee80211_key *k) 2870 { 2871 struct otus_softc *sc = ic->ic_softc; 2872 struct otus_cmd_key cmd; 2873 2874 /* Defer setting of WEP keys until interface is brought up. */ 2875 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2876 (IFF_UP | IFF_RUNNING)) 2877 return 0; 2878 2879 /* Do it in a process context. */ 2880 cmd.key = *k; 2881 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2882 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2883 return 0; 2884 } 2885 2886 void 2887 otus_set_key_cb(struct otus_softc *sc, void *arg) 2888 { 2889 struct otus_cmd_key *cmd = arg; 2890 struct ieee80211_key *k = &cmd->key; 2891 struct ar_cmd_ekey key; 2892 uint16_t cipher; 2893 int error; 2894 2895 memset(&key, 0, sizeof key); 2896 if (k->k_flags & IEEE80211_KEY_GROUP) { 2897 key.uid = htole16(k->k_id); 2898 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2899 key.macaddr[0] |= 0x80; 2900 } else { 2901 key.uid = htole16(OTUS_UID(cmd->associd)); 2902 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2903 } 2904 key.kix = htole16(0); 2905 /* Map net80211 cipher to hardware. */ 2906 switch (k->k_cipher) { 2907 case IEEE80211_CIPHER_WEP40: 2908 cipher = AR_CIPHER_WEP64; 2909 break; 2910 case IEEE80211_CIPHER_WEP104: 2911 cipher = AR_CIPHER_WEP128; 2912 break; 2913 case IEEE80211_CIPHER_TKIP: 2914 cipher = AR_CIPHER_TKIP; 2915 break; 2916 case IEEE80211_CIPHER_CCMP: 2917 cipher = AR_CIPHER_AES; 2918 break; 2919 default: 2920 return; 2921 } 2922 key.cipher = htole16(cipher); 2923 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 2924 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); 2925 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) 2926 return; 2927 2928 /* TKIP: set Tx/Rx MIC Key. */ 2929 key.kix = htole16(1); 2930 memcpy(key.key, k->k_key + 16, 16); 2931 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); 2932 } 2933 2934 void 2935 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2936 struct ieee80211_key *k) 2937 { 2938 struct otus_softc *sc = ic->ic_softc; 2939 struct otus_cmd_key cmd; 2940 2941 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2942 ic->ic_state != IEEE80211_S_RUN) 2943 return; /* Nothing to do. */ 2944 2945 /* Do it in a process context. */ 2946 cmd.key = *k; 2947 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2948 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 2949 } 2950 2951 void 2952 otus_delete_key_cb(struct otus_softc *sc, void *arg) 2953 { 2954 struct otus_cmd_key *cmd = arg; 2955 struct ieee80211_key *k = &cmd->key; 2956 uint32_t uid; 2957 2958 if (k->k_flags & IEEE80211_KEY_GROUP) 2959 uid = htole32(k->k_id); 2960 else 2961 uid = htole32(OTUS_UID(cmd->associd)); 2962 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL, 0); 2963 } 2964 #endif 2965 2966 /* 2967 * XXX TODO: check if we have to be doing any calibration in the host 2968 * or whether it's purely a firmware thing. 2969 */ 2970 void 2971 otus_calibrate_to(void *arg, int pending) 2972 { 2973 #if 0 2974 struct otus_softc *sc = arg; 2975 2976 device_printf(sc->sc_dev, "%s: called\n", __func__); 2977 struct ieee80211com *ic = &sc->sc_ic; 2978 struct ieee80211_node *ni; 2979 int s; 2980 2981 if (usbd_is_dying(sc->sc_udev)) 2982 return; 2983 2984 usbd_ref_incr(sc->sc_udev); 2985 2986 s = splnet(); 2987 ni = ic->ic_bss; 2988 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 2989 splx(s); 2990 2991 if (!usbd_is_dying(sc->sc_udev)) 2992 timeout_add_sec(&sc->calib_to, 1); 2993 2994 usbd_ref_decr(sc->sc_udev); 2995 #endif 2996 } 2997 2998 int 2999 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 3000 { 3001 3002 OTUS_LOCK_ASSERT(sc); 3003 3004 otus_write(sc, AR_MAC_REG_BSSID_L, 3005 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3006 otus_write(sc, AR_MAC_REG_BSSID_H, 3007 bssid[4] | bssid[5] << 8); 3008 return otus_write_barrier(sc); 3009 } 3010 3011 int 3012 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 3013 { 3014 OTUS_LOCK_ASSERT(sc); 3015 3016 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 3017 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3018 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 3019 addr[4] | addr[5] << 8); 3020 return otus_write_barrier(sc); 3021 } 3022 3023 /* Default single-LED. */ 3024 void 3025 otus_led_newstate_type1(struct otus_softc *sc) 3026 { 3027 /* TBD */ 3028 device_printf(sc->sc_dev, "%s: TODO\n", __func__); 3029 } 3030 3031 /* NETGEAR, dual-LED. */ 3032 void 3033 otus_led_newstate_type2(struct otus_softc *sc) 3034 { 3035 /* TBD */ 3036 device_printf(sc->sc_dev, "%s: TODO\n", __func__); 3037 } 3038 3039 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 3040 void 3041 otus_led_newstate_type3(struct otus_softc *sc) 3042 { 3043 #if 0 3044 struct ieee80211com *ic = &sc->sc_ic; 3045 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3046 3047 uint32_t state = sc->led_state; 3048 3049 OTUS_LOCK_ASSERT(sc); 3050 3051 if (!vap) { 3052 state = 0; /* led off */ 3053 } else if (vap->iv_state == IEEE80211_S_INIT) { 3054 state = 0; /* LED off. */ 3055 } else if (vap->iv_state == IEEE80211_S_RUN) { 3056 /* Associated, LED always on. */ 3057 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 3058 state = AR_LED0_ON; /* 2GHz=>Red. */ 3059 else 3060 state = AR_LED1_ON; /* 5GHz=>Blue. */ 3061 } else { 3062 /* Scanning, blink LED. */ 3063 state ^= AR_LED0_ON | AR_LED1_ON; 3064 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 3065 state &= ~AR_LED1_ON; 3066 else 3067 state &= ~AR_LED0_ON; 3068 } 3069 if (state != sc->led_state) { 3070 otus_write(sc, AR_GPIO_REG_PORT_DATA, state); 3071 if (otus_write_barrier(sc) == 0) 3072 sc->led_state = state; 3073 } 3074 #endif 3075 } 3076 3077 /* 3078 * TODO: 3079 * 3080 * + If in monitor mode, set BSSID to all zeros, else the node BSSID. 3081 * + Handle STA + monitor (eg tcpdump/promisc/radiotap) as well as 3082 * pure monitor mode. 3083 */ 3084 static int 3085 otus_set_operating_mode(struct otus_softc *sc) 3086 { 3087 struct ieee80211com *ic = &sc->sc_ic; 3088 uint32_t rx_ctrl; 3089 uint32_t frm_filt; 3090 uint32_t cam_mode; 3091 uint32_t rx_sniffer; 3092 3093 OTUS_LOCK_ASSERT(sc); 3094 3095 /* XXX TODO: too many magic constants */ 3096 rx_ctrl = 0x1; 3097 /* Filter any control frames, BAR is bit 24. */ 3098 frm_filt = 0x0500ffff; 3099 cam_mode = 0x0f000002; /* XXX STA */ 3100 rx_sniffer = 0x20000000; 3101 3102 switch (ic->ic_opmode) { 3103 case IEEE80211_M_STA: 3104 cam_mode = 0x0f000002; /* XXX STA */ 3105 rx_ctrl = 0x1; 3106 frm_filt = 0x0500ffff; 3107 rx_sniffer = 0x20000000; 3108 break; 3109 case IEEE80211_M_MONITOR: 3110 cam_mode = 0x0f000002; /* XXX STA */ 3111 rx_ctrl = 0x1; 3112 frm_filt = 0xffffffff; 3113 rx_sniffer = 0x20000001; 3114 break; 3115 default: 3116 break; 3117 } 3118 3119 otus_write(sc, AR_MAC_REG_SNIFFER, rx_sniffer); 3120 otus_write(sc, AR_MAC_REG_CAM_MODE, cam_mode); 3121 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, frm_filt); 3122 otus_write(sc, AR_MAC_REG_RX_CONTROL, cam_mode); 3123 3124 (void) otus_write_barrier(sc); 3125 return (0); 3126 } 3127 3128 int 3129 otus_init(struct otus_softc *sc) 3130 { 3131 struct ieee80211com *ic = &sc->sc_ic; 3132 int error; 3133 3134 OTUS_UNLOCK_ASSERT(sc); 3135 3136 OTUS_LOCK(sc); 3137 3138 /* Drain any pending TX frames */ 3139 otus_drain_mbufq(sc); 3140 3141 /* Init MAC */ 3142 if ((error = otus_init_mac(sc)) != 0) { 3143 OTUS_UNLOCK(sc); 3144 device_printf(sc->sc_dev, 3145 "%s: could not initialize MAC\n", __func__); 3146 return error; 3147 } 3148 3149 (void) otus_set_macaddr(sc, ic->ic_macaddr); 3150 (void) otus_set_operating_mode(sc); 3151 3152 sc->bb_reset = 1; /* Force cold reset. */ 3153 3154 if ((error = otus_set_chan(sc, ic->ic_curchan, 0)) != 0) { 3155 OTUS_UNLOCK(sc); 3156 device_printf(sc->sc_dev, 3157 "%s: could not set channel\n", __func__); 3158 return error; 3159 } 3160 3161 /* Start Rx. */ 3162 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0x100); 3163 (void)otus_write_barrier(sc); 3164 3165 sc->sc_running = 1; 3166 3167 OTUS_UNLOCK(sc); 3168 return 0; 3169 } 3170 3171 void 3172 otus_stop(struct otus_softc *sc) 3173 { 3174 #if 0 3175 int s; 3176 #endif 3177 3178 OTUS_UNLOCK_ASSERT(sc); 3179 3180 OTUS_LOCK(sc); 3181 sc->sc_running = 0; 3182 sc->sc_tx_timer = 0; 3183 OTUS_UNLOCK(sc); 3184 3185 taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); 3186 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); 3187 taskqueue_drain(taskqueue_thread, &sc->tx_task); 3188 taskqueue_drain(taskqueue_thread, &sc->wme_update_task); 3189 3190 OTUS_LOCK(sc); 3191 sc->sc_running = 0; 3192 /* Stop Rx. */ 3193 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0); 3194 (void)otus_write_barrier(sc); 3195 3196 /* Drain any pending TX frames */ 3197 otus_drain_mbufq(sc); 3198 3199 OTUS_UNLOCK(sc); 3200 } 3201