1 /* $OpenBSD: if_otus.c,v 1.49 2015/11/24 13:33:18 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros AR9001U chipset. 22 */ 23 24 #include <sys/cdefs.h> 25 #include "opt_wlan.h" 26 27 #include <sys/param.h> 28 #include <sys/endian.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/malloc.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/conf.h> 36 #include <sys/bus.h> 37 #include <sys/rman.h> 38 #include <sys/firmware.h> 39 #include <sys/module.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/if_ether.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_regdomain.h> 60 #include <net80211/ieee80211_radiotap.h> 61 #include <net80211/ieee80211_ratectl.h> 62 #ifdef IEEE80211_SUPPORT_SUPERG 63 #include <net80211/ieee80211_superg.h> 64 #endif 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include "usbdevs.h" 69 70 #define USB_DEBUG_VAR otus_debug 71 #include <dev/usb/usb_debug.h> 72 73 #include "if_otusreg.h" 74 75 static int otus_debug = 0; 76 static SYSCTL_NODE(_hw_usb, OID_AUTO, otus, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 77 "USB otus"); 78 SYSCTL_INT(_hw_usb_otus, OID_AUTO, debug, CTLFLAG_RWTUN, &otus_debug, 0, 79 "Debug level"); 80 #define OTUS_DEBUG_XMIT 0x00000001 81 #define OTUS_DEBUG_RECV 0x00000002 82 #define OTUS_DEBUG_TXDONE 0x00000004 83 #define OTUS_DEBUG_RXDONE 0x00000008 84 #define OTUS_DEBUG_CMD 0x00000010 85 #define OTUS_DEBUG_CMDDONE 0x00000020 86 #define OTUS_DEBUG_RESET 0x00000040 87 #define OTUS_DEBUG_STATE 0x00000080 88 #define OTUS_DEBUG_CMDNOTIFY 0x00000100 89 #define OTUS_DEBUG_REGIO 0x00000200 90 #define OTUS_DEBUG_IRQ 0x00000400 91 #define OTUS_DEBUG_TXCOMP 0x00000800 92 #define OTUS_DEBUG_RX_BUFFER 0x00001000 93 #define OTUS_DEBUG_ANY 0xffffffff 94 95 #define OTUS_DPRINTF(sc, dm, ...) \ 96 do { \ 97 if ((dm == OTUS_DEBUG_ANY) || (dm & otus_debug)) \ 98 device_printf(sc->sc_dev, __VA_ARGS__); \ 99 } while (0) 100 #define OTUS_DEV(v, p) { USB_VPI(v, p, 0) } 101 static const STRUCT_USB_HOST_ID otus_devs[] = { 102 OTUS_DEV(USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512), 103 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275), 104 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N), 105 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170), 106 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612), 107 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2), 108 OTUS_DEV(USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN), 109 OTUS_DEV(USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX), 110 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1), 111 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1), 112 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2), 113 OTUS_DEV(USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2), 114 OTUS_DEV(USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG), 115 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2), 116 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000), 117 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100), 118 OTUS_DEV(USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300), 119 OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494), 120 OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600), 121 OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81), 122 OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82), 123 OTUS_DEV(USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221), 124 OTUS_DEV(USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N), 125 }; 126 127 static device_probe_t otus_match; 128 static device_attach_t otus_attach; 129 static device_detach_t otus_detach; 130 131 static int otus_attachhook(struct otus_softc *); 132 static void otus_getradiocaps(struct ieee80211com *, int, int *, 133 struct ieee80211_channel[]); 134 int otus_load_firmware(struct otus_softc *, const char *, 135 uint32_t); 136 int otus_open_pipes(struct otus_softc *); 137 void otus_close_pipes(struct otus_softc *); 138 139 static int otus_alloc_tx_cmd_list(struct otus_softc *); 140 static void otus_free_tx_cmd_list(struct otus_softc *); 141 142 static int otus_alloc_rx_list(struct otus_softc *); 143 static void otus_free_rx_list(struct otus_softc *); 144 static int otus_alloc_tx_list(struct otus_softc *); 145 static void otus_free_tx_list(struct otus_softc *); 146 static void otus_free_list(struct otus_softc *, struct otus_data [], int); 147 static struct otus_data *_otus_getbuf(struct otus_softc *); 148 static struct otus_data *otus_getbuf(struct otus_softc *); 149 static void otus_freebuf(struct otus_softc *, struct otus_data *); 150 151 static struct otus_tx_cmd *_otus_get_txcmd(struct otus_softc *); 152 static struct otus_tx_cmd *otus_get_txcmd(struct otus_softc *); 153 static void otus_free_txcmd(struct otus_softc *, struct otus_tx_cmd *); 154 155 void otus_next_scan(void *, int); 156 static void otus_tx_task(void *, int pending); 157 void otus_do_async(struct otus_softc *, 158 void (*)(struct otus_softc *, void *), void *, int); 159 int otus_newstate(struct ieee80211vap *, enum ieee80211_state, 160 int); 161 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 162 void *, int); 163 void otus_write(struct otus_softc *, uint32_t, uint32_t); 164 int otus_write_barrier(struct otus_softc *); 165 static struct ieee80211_node *otus_node_alloc(struct ieee80211vap *vap, 166 const uint8_t mac[IEEE80211_ADDR_LEN]); 167 int otus_read_eeprom(struct otus_softc *); 168 void otus_newassoc(struct ieee80211_node *, int); 169 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 170 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int, 171 struct mbufq *); 172 static int otus_tx(struct otus_softc *, struct ieee80211_node *, 173 struct mbuf *, struct otus_data *, 174 const struct ieee80211_bpf_params *); 175 int otus_ioctl(if_t, u_long, caddr_t); 176 int otus_set_multi(struct otus_softc *); 177 static int otus_updateedca(struct ieee80211com *); 178 static void otus_updateedca_locked(struct otus_softc *); 179 static void otus_updateslot(struct otus_softc *); 180 static void otus_set_operating_mode(struct otus_softc *sc); 181 static void otus_set_rx_filter(struct otus_softc *sc); 182 int otus_init_mac(struct otus_softc *); 183 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 184 int otus_set_board_values(struct otus_softc *, 185 struct ieee80211_channel *); 186 int otus_program_phy(struct otus_softc *, 187 struct ieee80211_channel *); 188 int otus_set_rf_bank4(struct otus_softc *, 189 struct ieee80211_channel *); 190 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 191 static int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 192 int); 193 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 194 struct ieee80211_key *); 195 void otus_set_key_cb(struct otus_softc *, void *); 196 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 197 struct ieee80211_key *); 198 void otus_delete_key_cb(struct otus_softc *, void *); 199 void otus_calibrate_to(void *, int); 200 int otus_set_bssid(struct otus_softc *, const uint8_t *); 201 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 202 void otus_led_newstate_type1(struct otus_softc *); 203 void otus_led_newstate_type2(struct otus_softc *); 204 void otus_led_newstate_type3(struct otus_softc *); 205 int otus_init(struct otus_softc *sc); 206 void otus_stop(struct otus_softc *sc); 207 208 static device_method_t otus_methods[] = { 209 DEVMETHOD(device_probe, otus_match), 210 DEVMETHOD(device_attach, otus_attach), 211 DEVMETHOD(device_detach, otus_detach), 212 213 DEVMETHOD_END 214 }; 215 216 static driver_t otus_driver = { 217 .name = "otus", 218 .methods = otus_methods, 219 .size = sizeof(struct otus_softc) 220 }; 221 222 DRIVER_MODULE(otus, uhub, otus_driver, NULL, NULL); 223 MODULE_DEPEND(otus, wlan, 1, 1, 1); 224 MODULE_DEPEND(otus, usb, 1, 1, 1); 225 MODULE_DEPEND(otus, firmware, 1, 1, 1); 226 MODULE_VERSION(otus, 1); 227 228 static usb_callback_t otus_bulk_tx_callback; 229 static usb_callback_t otus_bulk_rx_callback; 230 static usb_callback_t otus_bulk_irq_callback; 231 static usb_callback_t otus_bulk_cmd_callback; 232 233 static const struct usb_config otus_config[OTUS_N_XFER] = { 234 [OTUS_BULK_TX] = { 235 .type = UE_BULK, 236 .endpoint = UE_ADDR_ANY, 237 .direction = UE_DIR_OUT, 238 .bufsize = 0x200, 239 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 240 .callback = otus_bulk_tx_callback, 241 .timeout = 5000, /* ms */ 242 }, 243 [OTUS_BULK_RX] = { 244 .type = UE_BULK, 245 .endpoint = UE_ADDR_ANY, 246 .direction = UE_DIR_IN, 247 .bufsize = OTUS_RXBUFSZ, 248 .flags = { .ext_buffer = 1, .pipe_bof = 1,.short_xfer_ok = 1,}, 249 .callback = otus_bulk_rx_callback, 250 }, 251 [OTUS_BULK_IRQ] = { 252 .type = UE_INTERRUPT, 253 .endpoint = UE_ADDR_ANY, 254 .direction = UE_DIR_IN, 255 .bufsize = OTUS_MAX_CTRLSZ, 256 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 257 .callback = otus_bulk_irq_callback, 258 }, 259 [OTUS_BULK_CMD] = { 260 .type = UE_INTERRUPT, 261 .endpoint = UE_ADDR_ANY, 262 .direction = UE_DIR_OUT, 263 .bufsize = OTUS_MAX_CTRLSZ, 264 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 265 .callback = otus_bulk_cmd_callback, 266 .timeout = 5000, /* ms */ 267 }, 268 }; 269 270 static int 271 otus_match(device_t self) 272 { 273 struct usb_attach_arg *uaa = device_get_ivars(self); 274 275 if (uaa->usb_mode != USB_MODE_HOST || 276 uaa->info.bIfaceIndex != 0 || 277 uaa->info.bConfigIndex != 0) 278 return (ENXIO); 279 280 return (usbd_lookup_id_by_uaa(otus_devs, sizeof(otus_devs), uaa)); 281 } 282 283 static int 284 otus_attach(device_t self) 285 { 286 struct usb_attach_arg *uaa = device_get_ivars(self); 287 struct otus_softc *sc = device_get_softc(self); 288 int error; 289 uint8_t iface_index; 290 291 device_set_usb_desc(self); 292 sc->sc_udev = uaa->device; 293 sc->sc_dev = self; 294 295 mtx_init(&sc->sc_mtx, device_get_nameunit(self), MTX_NETWORK_LOCK, 296 MTX_DEF); 297 298 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->scan_to, 0, otus_next_scan, sc); 299 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->calib_to, 0, otus_calibrate_to, sc); 300 TASK_INIT(&sc->tx_task, 0, otus_tx_task, sc); 301 mbufq_init(&sc->sc_snd, ifqmaxlen); 302 303 iface_index = 0; 304 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 305 otus_config, OTUS_N_XFER, sc, &sc->sc_mtx); 306 if (error) { 307 device_printf(sc->sc_dev, 308 "could not allocate USB transfers, err=%s\n", 309 usbd_errstr(error)); 310 goto fail_usb; 311 } 312 313 if ((error = otus_open_pipes(sc)) != 0) { 314 device_printf(sc->sc_dev, "%s: could not open pipes\n", 315 __func__); 316 goto fail; 317 } 318 319 /* XXX check return status; fail out if appropriate */ 320 if (otus_attachhook(sc) != 0) 321 goto fail; 322 323 return (0); 324 325 fail: 326 otus_close_pipes(sc); 327 fail_usb: 328 mtx_destroy(&sc->sc_mtx); 329 return (ENXIO); 330 } 331 332 static int 333 otus_detach(device_t self) 334 { 335 struct otus_softc *sc = device_get_softc(self); 336 struct ieee80211com *ic = &sc->sc_ic; 337 338 otus_stop(sc); 339 340 usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); 341 342 taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); 343 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); 344 taskqueue_drain(taskqueue_thread, &sc->tx_task); 345 346 otus_close_pipes(sc); 347 #if 0 348 /* Wait for all queued asynchronous commands to complete. */ 349 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 350 351 usbd_ref_wait(sc->sc_udev); 352 #endif 353 354 ieee80211_ifdetach(ic); 355 mtx_destroy(&sc->sc_mtx); 356 return 0; 357 } 358 359 static void 360 otus_delay_ms(struct otus_softc *sc, int ms) 361 { 362 363 DELAY(1000 * ms); 364 } 365 366 static struct ieee80211vap * 367 otus_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 368 enum ieee80211_opmode opmode, int flags, 369 const uint8_t bssid[IEEE80211_ADDR_LEN], 370 const uint8_t mac[IEEE80211_ADDR_LEN]) 371 { 372 struct otus_vap *uvp; 373 struct ieee80211vap *vap; 374 375 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 376 return (NULL); 377 378 uvp = malloc(sizeof(struct otus_vap), M_80211_VAP, M_WAITOK | M_ZERO); 379 vap = &uvp->vap; 380 381 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 382 flags, bssid) != 0) { 383 /* out of memory */ 384 free(uvp, M_80211_VAP); 385 return (NULL); 386 } 387 388 /* override state transition machine */ 389 uvp->newstate = vap->iv_newstate; 390 vap->iv_newstate = otus_newstate; 391 392 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 393 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 394 395 ieee80211_ratectl_init(vap); 396 397 /* complete setup */ 398 ieee80211_vap_attach(vap, ieee80211_media_change, 399 ieee80211_media_status, mac); 400 ic->ic_opmode = opmode; 401 402 return (vap); 403 } 404 405 static void 406 otus_vap_delete(struct ieee80211vap *vap) 407 { 408 struct otus_vap *uvp = OTUS_VAP(vap); 409 410 ieee80211_ratectl_deinit(vap); 411 ieee80211_vap_detach(vap); 412 free(uvp, M_80211_VAP); 413 } 414 415 static void 416 otus_parent(struct ieee80211com *ic) 417 { 418 struct otus_softc *sc = ic->ic_softc; 419 int startall = 0; 420 421 if (ic->ic_nrunning > 0) { 422 if (!sc->sc_running) { 423 otus_init(sc); 424 startall = 1; 425 } else { 426 (void) otus_set_multi(sc); 427 } 428 } else if (sc->sc_running) 429 otus_stop(sc); 430 431 if (startall) 432 ieee80211_start_all(ic); 433 } 434 435 static void 436 otus_drain_mbufq(struct otus_softc *sc) 437 { 438 struct mbuf *m; 439 struct ieee80211_node *ni; 440 441 OTUS_LOCK_ASSERT(sc); 442 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 443 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 444 m->m_pkthdr.rcvif = NULL; 445 ieee80211_free_node(ni); 446 m_freem(m); 447 } 448 } 449 450 static void 451 otus_tx_start(struct otus_softc *sc) 452 { 453 454 taskqueue_enqueue(taskqueue_thread, &sc->tx_task); 455 } 456 457 static int 458 otus_transmit(struct ieee80211com *ic, struct mbuf *m) 459 { 460 struct otus_softc *sc = ic->ic_softc; 461 int error; 462 463 OTUS_LOCK(sc); 464 if (! sc->sc_running) { 465 OTUS_UNLOCK(sc); 466 return (ENXIO); 467 } 468 469 /* XXX TODO: handle fragments */ 470 error = mbufq_enqueue(&sc->sc_snd, m); 471 if (error) { 472 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 473 "%s: mbufq_enqueue failed: %d\n", 474 __func__, 475 error); 476 OTUS_UNLOCK(sc); 477 return (error); 478 } 479 OTUS_UNLOCK(sc); 480 481 /* Kick TX */ 482 otus_tx_start(sc); 483 484 return (0); 485 } 486 487 static void 488 _otus_start(struct otus_softc *sc) 489 { 490 struct ieee80211_node *ni; 491 struct otus_data *bf; 492 struct mbuf *m; 493 494 OTUS_LOCK_ASSERT(sc); 495 496 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 497 bf = otus_getbuf(sc); 498 if (bf == NULL) { 499 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 500 "%s: failed to get buffer\n", __func__); 501 mbufq_prepend(&sc->sc_snd, m); 502 break; 503 } 504 505 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 506 m->m_pkthdr.rcvif = NULL; 507 508 if (otus_tx(sc, ni, m, bf, NULL) != 0) { 509 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 510 "%s: failed to transmit\n", __func__); 511 if_inc_counter(ni->ni_vap->iv_ifp, 512 IFCOUNTER_OERRORS, 1); 513 otus_freebuf(sc, bf); 514 ieee80211_free_node(ni); 515 m_freem(m); 516 break; 517 } 518 } 519 } 520 521 static void 522 otus_tx_task(void *arg, int pending) 523 { 524 struct otus_softc *sc = arg; 525 526 OTUS_LOCK(sc); 527 _otus_start(sc); 528 OTUS_UNLOCK(sc); 529 } 530 531 static int 532 otus_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 533 const struct ieee80211_bpf_params *params) 534 { 535 struct ieee80211com *ic= ni->ni_ic; 536 struct otus_softc *sc = ic->ic_softc; 537 struct otus_data *bf = NULL; 538 int error = 0; 539 540 /* Don't transmit if we're not running */ 541 OTUS_LOCK(sc); 542 if (! sc->sc_running) { 543 error = ENETDOWN; 544 goto error; 545 } 546 547 bf = otus_getbuf(sc); 548 if (bf == NULL) { 549 error = ENOBUFS; 550 goto error; 551 } 552 553 if (otus_tx(sc, ni, m, bf, params) != 0) { 554 error = EIO; 555 goto error; 556 } 557 558 OTUS_UNLOCK(sc); 559 return (0); 560 error: 561 if (bf) 562 otus_freebuf(sc, bf); 563 OTUS_UNLOCK(sc); 564 m_freem(m); 565 return (error); 566 } 567 568 static void 569 otus_update_chw(struct ieee80211com *ic) 570 { 571 572 printf("%s: TODO\n", __func__); 573 } 574 575 static void 576 otus_set_channel(struct ieee80211com *ic) 577 { 578 struct otus_softc *sc = ic->ic_softc; 579 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "%s: set channel: %d\n", 580 __func__, 581 ic->ic_curchan->ic_freq); 582 583 OTUS_LOCK(sc); 584 (void) otus_set_chan(sc, ic->ic_curchan, 0); 585 OTUS_UNLOCK(sc); 586 } 587 588 static int 589 otus_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 590 { 591 592 /* For now, no A-MPDU TX support in the driver */ 593 return (0); 594 } 595 596 static void 597 otus_scan_start(struct ieee80211com *ic) 598 { 599 600 // printf("%s: TODO\n", __func__); 601 } 602 603 static void 604 otus_scan_end(struct ieee80211com *ic) 605 { 606 607 // printf("%s: TODO\n", __func__); 608 } 609 610 static void 611 otus_update_mcast(struct ieee80211com *ic) 612 { 613 struct otus_softc *sc = ic->ic_softc; 614 615 (void) otus_set_multi(sc); 616 } 617 618 static int 619 otus_attachhook(struct otus_softc *sc) 620 { 621 struct ieee80211com *ic = &sc->sc_ic; 622 usb_device_request_t req; 623 uint32_t in, out; 624 int error; 625 626 /* Not locked */ 627 error = otus_load_firmware(sc, "otusfw_init", AR_FW_INIT_ADDR); 628 if (error != 0) { 629 device_printf(sc->sc_dev, "%s: could not load %s firmware\n", 630 __func__, "init"); 631 return (ENXIO); 632 } 633 634 /* XXX not locked? */ 635 otus_delay_ms(sc, 1000); 636 637 /* Not locked */ 638 error = otus_load_firmware(sc, "otusfw_main", AR_FW_MAIN_ADDR); 639 if (error != 0) { 640 device_printf(sc->sc_dev, "%s: could not load %s firmware\n", 641 __func__, "main"); 642 return (ENXIO); 643 } 644 645 OTUS_LOCK(sc); 646 647 /* Tell device that firmware transfer is complete. */ 648 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 649 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 650 USETW(req.wValue, 0); 651 USETW(req.wIndex, 0); 652 USETW(req.wLength, 0); 653 if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, NULL, 654 0, NULL, 250) != 0) { 655 OTUS_UNLOCK(sc); 656 device_printf(sc->sc_dev, 657 "%s: firmware initialization failed\n", 658 __func__); 659 return (ENXIO); 660 } 661 662 /* Send an ECHO command to check that everything is settled. */ 663 in = 0xbadc0ffe; 664 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out, sizeof(out)) != 0) { 665 OTUS_UNLOCK(sc); 666 device_printf(sc->sc_dev, 667 "%s: echo command failed\n", __func__); 668 return (ENXIO); 669 } 670 if (in != out) { 671 OTUS_UNLOCK(sc); 672 device_printf(sc->sc_dev, 673 "%s: echo reply mismatch: 0x%08x!=0x%08x\n", 674 __func__, in, out); 675 return (ENXIO); 676 } 677 678 /* Read entire EEPROM. */ 679 if (otus_read_eeprom(sc) != 0) { 680 OTUS_UNLOCK(sc); 681 device_printf(sc->sc_dev, 682 "%s: could not read EEPROM\n", 683 __func__); 684 return (ENXIO); 685 } 686 687 OTUS_UNLOCK(sc); 688 689 sc->txmask = sc->eeprom.baseEepHeader.txMask; 690 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 691 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 692 IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->eeprom.baseEepHeader.macAddr); 693 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 694 695 if (sc->txmask == 0x5) 696 ic->ic_txstream = 2; 697 else 698 ic->ic_txstream = 1; 699 700 if (sc->rxmask == 0x5) 701 ic->ic_rxstream = 2; 702 else 703 ic->ic_rxstream = 1; 704 705 device_printf(sc->sc_dev, 706 "MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 707 (sc->capflags & AR5416_OPFLAGS_11A) ? 708 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 709 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 710 ether_sprintf(ic->ic_macaddr)); 711 712 ic->ic_softc = sc; 713 ic->ic_name = device_get_nameunit(sc->sc_dev); 714 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 715 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 716 717 /* Set device capabilities. */ 718 ic->ic_caps = 719 IEEE80211_C_STA | /* station mode */ 720 #if 0 721 IEEE80211_C_BGSCAN | /* Background scan. */ 722 #endif 723 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 724 IEEE80211_C_WME | /* WME/QoS */ 725 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 726 IEEE80211_C_FF | /* Atheros fast-frames supported. */ 727 IEEE80211_C_MONITOR | /* Enable monitor mode */ 728 IEEE80211_C_SWAMSDUTX | /* Do software A-MSDU TX */ 729 IEEE80211_C_WPA; /* WPA/RSN. */ 730 731 ic->ic_htcaps = 732 IEEE80211_HTC_HT | 733 #if 0 734 IEEE80211_HTC_AMPDU | 735 #endif 736 IEEE80211_HTC_AMSDU | 737 IEEE80211_HTCAP_MAXAMSDU_3839 | 738 IEEE80211_HTCAP_SMPS_OFF; 739 740 otus_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 741 ic->ic_channels); 742 743 ieee80211_ifattach(ic); 744 ic->ic_raw_xmit = otus_raw_xmit; 745 ic->ic_scan_start = otus_scan_start; 746 ic->ic_scan_end = otus_scan_end; 747 ic->ic_set_channel = otus_set_channel; 748 ic->ic_getradiocaps = otus_getradiocaps; 749 ic->ic_vap_create = otus_vap_create; 750 ic->ic_vap_delete = otus_vap_delete; 751 ic->ic_update_mcast = otus_update_mcast; 752 ic->ic_update_promisc = otus_update_mcast; 753 ic->ic_parent = otus_parent; 754 ic->ic_transmit = otus_transmit; 755 ic->ic_update_chw = otus_update_chw; 756 ic->ic_ampdu_enable = otus_ampdu_enable; 757 ic->ic_wme.wme_update = otus_updateedca; 758 ic->ic_newassoc = otus_newassoc; 759 ic->ic_node_alloc = otus_node_alloc; 760 761 #ifdef notyet 762 ic->ic_set_key = otus_set_key; 763 ic->ic_delete_key = otus_delete_key; 764 #endif 765 766 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 767 sizeof(sc->sc_txtap), OTUS_TX_RADIOTAP_PRESENT, 768 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 769 OTUS_RX_RADIOTAP_PRESENT); 770 771 return (0); 772 } 773 774 static void 775 otus_getradiocaps(struct ieee80211com *ic, 776 int maxchans, int *nchans, struct ieee80211_channel chans[]) 777 { 778 struct otus_softc *sc = ic->ic_softc; 779 uint8_t bands[IEEE80211_MODE_BYTES]; 780 781 /* Set supported .11b and .11g rates. */ 782 memset(bands, 0, sizeof(bands)); 783 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 784 setbit(bands, IEEE80211_MODE_11B); 785 setbit(bands, IEEE80211_MODE_11G); 786 setbit(bands, IEEE80211_MODE_11NG); 787 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 788 ar_chans, 14, bands, 0); 789 } 790 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 791 setbit(bands, IEEE80211_MODE_11A); 792 setbit(bands, IEEE80211_MODE_11NA); 793 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 794 &ar_chans[14], nitems(ar_chans) - 14, bands, 0); 795 } 796 } 797 798 int 799 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 800 { 801 usb_device_request_t req; 802 char *ptr; 803 const struct firmware *fw; 804 int mlen, error, size; 805 806 error = 0; 807 808 /* Read firmware image from the filesystem. */ 809 if ((fw = firmware_get(name)) == NULL) { 810 device_printf(sc->sc_dev, 811 "%s: failed loadfirmware of file %s\n", __func__, name); 812 return (ENXIO); 813 } 814 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 815 req.bRequest = AR_FW_DOWNLOAD; 816 USETW(req.wIndex, 0); 817 818 OTUS_LOCK(sc); 819 820 /* XXX const */ 821 ptr = __DECONST(char *, fw->data); 822 size = fw->datasize; 823 addr >>= 8; 824 while (size > 0) { 825 mlen = MIN(size, 4096); 826 827 USETW(req.wValue, addr); 828 USETW(req.wLength, mlen); 829 if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 830 &req, ptr, 0, NULL, 250) != 0) { 831 error = EIO; 832 break; 833 } 834 addr += mlen >> 8; 835 ptr += mlen; 836 size -= mlen; 837 } 838 839 OTUS_UNLOCK(sc); 840 841 firmware_put(fw, FIRMWARE_UNLOAD); 842 if (error != 0) 843 device_printf(sc->sc_dev, 844 "%s: %s: error=%d\n", __func__, name, error); 845 return error; 846 } 847 848 int 849 otus_open_pipes(struct otus_softc *sc) 850 { 851 #if 0 852 int isize, error; 853 int i; 854 #endif 855 int error; 856 857 OTUS_UNLOCK_ASSERT(sc); 858 859 if ((error = otus_alloc_tx_cmd_list(sc)) != 0) { 860 device_printf(sc->sc_dev, 861 "%s: could not allocate command xfer\n", 862 __func__); 863 goto fail; 864 } 865 866 if ((error = otus_alloc_tx_list(sc)) != 0) { 867 device_printf(sc->sc_dev, "%s: could not allocate Tx xfers\n", 868 __func__); 869 goto fail; 870 } 871 872 if ((error = otus_alloc_rx_list(sc)) != 0) { 873 device_printf(sc->sc_dev, "%s: could not allocate Rx xfers\n", 874 __func__); 875 goto fail; 876 } 877 878 /* Enable RX transfers; needed for initial firmware messages */ 879 OTUS_LOCK(sc); 880 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_RX]); 881 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_IRQ]); 882 OTUS_UNLOCK(sc); 883 return 0; 884 885 fail: otus_close_pipes(sc); 886 return error; 887 } 888 889 void 890 otus_close_pipes(struct otus_softc *sc) 891 { 892 893 OTUS_LOCK(sc); 894 otus_free_tx_cmd_list(sc); 895 otus_free_tx_list(sc); 896 otus_free_rx_list(sc); 897 OTUS_UNLOCK(sc); 898 899 usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); 900 } 901 902 static void 903 otus_free_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], int ndata) 904 { 905 int i; 906 907 /* XXX TODO: someone has to have waken up waiters! */ 908 for (i = 0; i < ndata; i++) { 909 struct otus_tx_cmd *dp = &cmd[i]; 910 911 if (dp->buf != NULL) { 912 free(dp->buf, M_USBDEV); 913 dp->buf = NULL; 914 } 915 } 916 } 917 918 static int 919 otus_alloc_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], 920 int ndata, int maxsz) 921 { 922 int i, error; 923 924 for (i = 0; i < ndata; i++) { 925 struct otus_tx_cmd *dp = &cmd[i]; 926 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT | M_ZERO); 927 dp->odata = NULL; 928 if (dp->buf == NULL) { 929 device_printf(sc->sc_dev, 930 "could not allocate buffer\n"); 931 error = ENOMEM; 932 goto fail; 933 } 934 } 935 936 return (0); 937 fail: 938 otus_free_cmd_list(sc, cmd, ndata); 939 return (error); 940 } 941 942 static int 943 otus_alloc_tx_cmd_list(struct otus_softc *sc) 944 { 945 int error, i; 946 947 error = otus_alloc_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT, 948 OTUS_MAX_TXCMDSZ); 949 if (error != 0) 950 return (error); 951 952 STAILQ_INIT(&sc->sc_cmd_active); 953 STAILQ_INIT(&sc->sc_cmd_inactive); 954 STAILQ_INIT(&sc->sc_cmd_pending); 955 STAILQ_INIT(&sc->sc_cmd_waiting); 956 957 for (i = 0; i < OTUS_CMD_LIST_COUNT; i++) 958 STAILQ_INSERT_HEAD(&sc->sc_cmd_inactive, &sc->sc_cmd[i], 959 next_cmd); 960 961 return (0); 962 } 963 964 static void 965 otus_free_tx_cmd_list(struct otus_softc *sc) 966 { 967 968 /* 969 * XXX TODO: something needs to wake up any pending/sleeping 970 * waiters! 971 */ 972 STAILQ_INIT(&sc->sc_cmd_active); 973 STAILQ_INIT(&sc->sc_cmd_inactive); 974 STAILQ_INIT(&sc->sc_cmd_pending); 975 STAILQ_INIT(&sc->sc_cmd_waiting); 976 977 otus_free_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT); 978 } 979 980 static int 981 otus_alloc_list(struct otus_softc *sc, struct otus_data data[], 982 int ndata, int maxsz) 983 { 984 int i, error; 985 986 for (i = 0; i < ndata; i++) { 987 struct otus_data *dp = &data[i]; 988 dp->sc = sc; 989 dp->m = NULL; 990 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT | M_ZERO); 991 if (dp->buf == NULL) { 992 device_printf(sc->sc_dev, 993 "could not allocate buffer\n"); 994 error = ENOMEM; 995 goto fail; 996 } 997 dp->ni = NULL; 998 } 999 1000 return (0); 1001 fail: 1002 otus_free_list(sc, data, ndata); 1003 return (error); 1004 } 1005 1006 static int 1007 otus_alloc_rx_list(struct otus_softc *sc) 1008 { 1009 int error, i; 1010 1011 error = otus_alloc_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT, 1012 OTUS_RXBUFSZ); 1013 if (error != 0) 1014 return (error); 1015 1016 STAILQ_INIT(&sc->sc_rx_active); 1017 STAILQ_INIT(&sc->sc_rx_inactive); 1018 1019 for (i = 0; i < OTUS_RX_LIST_COUNT; i++) 1020 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1021 1022 return (0); 1023 } 1024 1025 static int 1026 otus_alloc_tx_list(struct otus_softc *sc) 1027 { 1028 int error, i; 1029 1030 error = otus_alloc_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT, 1031 OTUS_TXBUFSZ); 1032 if (error != 0) 1033 return (error); 1034 1035 STAILQ_INIT(&sc->sc_tx_inactive); 1036 1037 for (i = 0; i != OTUS_N_XFER; i++) { 1038 STAILQ_INIT(&sc->sc_tx_active[i]); 1039 STAILQ_INIT(&sc->sc_tx_pending[i]); 1040 } 1041 1042 for (i = 0; i < OTUS_TX_LIST_COUNT; i++) { 1043 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1044 } 1045 1046 return (0); 1047 } 1048 1049 static void 1050 otus_free_tx_list(struct otus_softc *sc) 1051 { 1052 int i; 1053 1054 /* prevent further allocations from TX list(s) */ 1055 STAILQ_INIT(&sc->sc_tx_inactive); 1056 1057 for (i = 0; i != OTUS_N_XFER; i++) { 1058 STAILQ_INIT(&sc->sc_tx_active[i]); 1059 STAILQ_INIT(&sc->sc_tx_pending[i]); 1060 } 1061 1062 otus_free_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT); 1063 } 1064 1065 static void 1066 otus_free_rx_list(struct otus_softc *sc) 1067 { 1068 /* prevent further allocations from RX list(s) */ 1069 STAILQ_INIT(&sc->sc_rx_inactive); 1070 STAILQ_INIT(&sc->sc_rx_active); 1071 1072 otus_free_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT); 1073 } 1074 1075 static void 1076 otus_free_list(struct otus_softc *sc, struct otus_data data[], int ndata) 1077 { 1078 int i; 1079 1080 for (i = 0; i < ndata; i++) { 1081 struct otus_data *dp = &data[i]; 1082 1083 if (dp->buf != NULL) { 1084 free(dp->buf, M_USBDEV); 1085 dp->buf = NULL; 1086 } 1087 if (dp->ni != NULL) { 1088 ieee80211_free_node(dp->ni); 1089 dp->ni = NULL; 1090 } 1091 } 1092 } 1093 1094 static struct otus_data * 1095 _otus_getbuf(struct otus_softc *sc) 1096 { 1097 struct otus_data *bf; 1098 1099 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1100 if (bf != NULL) 1101 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1102 else 1103 bf = NULL; 1104 /* XXX bzero? */ 1105 return (bf); 1106 } 1107 1108 static struct otus_data * 1109 otus_getbuf(struct otus_softc *sc) 1110 { 1111 struct otus_data *bf; 1112 1113 OTUS_LOCK_ASSERT(sc); 1114 1115 bf = _otus_getbuf(sc); 1116 return (bf); 1117 } 1118 1119 static void 1120 otus_freebuf(struct otus_softc *sc, struct otus_data *bf) 1121 { 1122 1123 OTUS_LOCK_ASSERT(sc); 1124 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, bf, next); 1125 } 1126 1127 static struct otus_tx_cmd * 1128 _otus_get_txcmd(struct otus_softc *sc) 1129 { 1130 struct otus_tx_cmd *bf; 1131 1132 bf = STAILQ_FIRST(&sc->sc_cmd_inactive); 1133 if (bf != NULL) 1134 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next_cmd); 1135 else 1136 bf = NULL; 1137 return (bf); 1138 } 1139 1140 static struct otus_tx_cmd * 1141 otus_get_txcmd(struct otus_softc *sc) 1142 { 1143 struct otus_tx_cmd *bf; 1144 1145 OTUS_LOCK_ASSERT(sc); 1146 1147 bf = _otus_get_txcmd(sc); 1148 if (bf == NULL) { 1149 device_printf(sc->sc_dev, "%s: no tx cmd buffers\n", 1150 __func__); 1151 } 1152 return (bf); 1153 } 1154 1155 static void 1156 otus_free_txcmd(struct otus_softc *sc, struct otus_tx_cmd *bf) 1157 { 1158 1159 OTUS_LOCK_ASSERT(sc); 1160 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, bf, next_cmd); 1161 } 1162 1163 void 1164 otus_next_scan(void *arg, int pending) 1165 { 1166 #if 0 1167 struct otus_softc *sc = arg; 1168 1169 if (usbd_is_dying(sc->sc_udev)) 1170 return; 1171 1172 usbd_ref_incr(sc->sc_udev); 1173 1174 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1175 ieee80211_next_scan(&sc->sc_ic.ic_if); 1176 1177 usbd_ref_decr(sc->sc_udev); 1178 #endif 1179 } 1180 1181 int 1182 otus_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1183 { 1184 struct otus_vap *uvp = OTUS_VAP(vap); 1185 struct ieee80211com *ic = vap->iv_ic; 1186 struct otus_softc *sc = ic->ic_softc; 1187 enum ieee80211_state ostate; 1188 1189 ostate = vap->iv_state; 1190 OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1191 ieee80211_state_name[ostate], 1192 ieee80211_state_name[nstate]); 1193 1194 IEEE80211_UNLOCK(ic); 1195 1196 OTUS_LOCK(sc); 1197 1198 /* XXX TODO: more fleshing out! */ 1199 1200 switch (nstate) { 1201 case IEEE80211_S_INIT: 1202 otus_set_operating_mode(sc); 1203 otus_set_rx_filter(sc); 1204 break; 1205 case IEEE80211_S_RUN: 1206 if (ic->ic_opmode == IEEE80211_M_STA) { 1207 otus_updateslot(sc); 1208 otus_set_operating_mode(sc); 1209 otus_set_rx_filter(sc); 1210 1211 /* Start calibration timer. */ 1212 taskqueue_enqueue_timeout(taskqueue_thread, 1213 &sc->calib_to, hz); 1214 } 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 /* XXX TODO: calibration? */ 1221 1222 sc->sc_led_newstate(sc); 1223 1224 OTUS_UNLOCK(sc); 1225 IEEE80211_LOCK(ic); 1226 return (uvp->newstate(vap, nstate, arg)); 1227 } 1228 1229 int 1230 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 1231 void *odata, int odatalen) 1232 { 1233 struct otus_tx_cmd *cmd; 1234 struct ar_cmd_hdr *hdr; 1235 int xferlen, error; 1236 1237 OTUS_LOCK_ASSERT(sc); 1238 1239 /* Always bulk-out a multiple of 4 bytes. */ 1240 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 1241 if (xferlen > OTUS_MAX_TXCMDSZ) { 1242 device_printf(sc->sc_dev, "%s: command (0x%02x) size (%d) > %d\n", 1243 __func__, 1244 code, 1245 xferlen, 1246 OTUS_MAX_TXCMDSZ); 1247 return (EIO); 1248 } 1249 1250 cmd = otus_get_txcmd(sc); 1251 if (cmd == NULL) { 1252 device_printf(sc->sc_dev, "%s: failed to get buf\n", 1253 __func__); 1254 return (EIO); 1255 } 1256 1257 hdr = (struct ar_cmd_hdr *)cmd->buf; 1258 hdr->code = code; 1259 hdr->len = ilen; 1260 hdr->token = ++sc->token; /* Don't care about endianness. */ 1261 cmd->token = hdr->token; 1262 /* XXX TODO: check max cmd length? */ 1263 memcpy((uint8_t *)&hdr[1], idata, ilen); 1264 1265 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 1266 "%s: sending command code=0x%02x len=%d token=%d\n", 1267 __func__, code, ilen, hdr->token); 1268 1269 cmd->odata = odata; 1270 cmd->odatalen = odatalen; 1271 cmd->buflen = xferlen; 1272 1273 /* Queue the command to the endpoint */ 1274 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next_cmd); 1275 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_CMD]); 1276 1277 /* Sleep on the command; wait for it to complete */ 1278 error = msleep(cmd, &sc->sc_mtx, PCATCH, "otuscmd", hz); 1279 1280 /* 1281 * At this point we don't own cmd any longer; it'll be 1282 * freed by the cmd bulk path or the RX notification 1283 * path. If the data is made available then it'll be copied 1284 * to the caller. All that is left to do is communicate 1285 * status back to the caller. 1286 */ 1287 if (error != 0) { 1288 device_printf(sc->sc_dev, 1289 "%s: timeout waiting for command 0x%02x reply\n", 1290 __func__, code); 1291 } 1292 return error; 1293 } 1294 1295 void 1296 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 1297 { 1298 1299 OTUS_LOCK_ASSERT(sc); 1300 1301 sc->write_buf[sc->write_idx].reg = htole32(reg); 1302 sc->write_buf[sc->write_idx].val = htole32(val); 1303 1304 if (++sc->write_idx > (AR_MAX_WRITE_IDX-1)) 1305 (void)otus_write_barrier(sc); 1306 } 1307 1308 int 1309 otus_write_barrier(struct otus_softc *sc) 1310 { 1311 int error; 1312 1313 OTUS_LOCK_ASSERT(sc); 1314 1315 if (sc->write_idx == 0) 1316 return 0; /* Nothing to flush. */ 1317 1318 OTUS_DPRINTF(sc, OTUS_DEBUG_REGIO, "%s: called; %d updates\n", 1319 __func__, 1320 sc->write_idx); 1321 1322 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 1323 sizeof (sc->write_buf[0]) * sc->write_idx, NULL, 0); 1324 sc->write_idx = 0; 1325 return error; 1326 } 1327 1328 static struct ieee80211_node * 1329 otus_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1330 { 1331 1332 return malloc(sizeof (struct otus_node), M_80211_NODE, 1333 M_NOWAIT | M_ZERO); 1334 } 1335 1336 int 1337 otus_read_eeprom(struct otus_softc *sc) 1338 { 1339 uint32_t regs[8], reg; 1340 uint8_t *eep; 1341 int i, j, error; 1342 1343 OTUS_LOCK_ASSERT(sc); 1344 1345 /* Read EEPROM by blocks of 32 bytes. */ 1346 eep = (uint8_t *)&sc->eeprom; 1347 reg = AR_EEPROM_OFFSET; 1348 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 1349 for (j = 0; j < 8; j++, reg += 4) 1350 regs[j] = htole32(reg); 1351 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep, 32); 1352 if (error != 0) 1353 break; 1354 eep += 32; 1355 } 1356 return error; 1357 } 1358 1359 void 1360 otus_newassoc(struct ieee80211_node *ni, int isnew) 1361 { 1362 struct ieee80211com *ic = ni->ni_ic; 1363 struct otus_softc *sc = ic->ic_softc; 1364 struct otus_node *on = OTUS_NODE(ni); 1365 1366 OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "new assoc isnew=%d addr=%s\n", 1367 isnew, ether_sprintf(ni->ni_macaddr)); 1368 1369 on->tx_done = 0; 1370 on->tx_err = 0; 1371 on->tx_retries = 0; 1372 } 1373 1374 static void 1375 otus_cmd_handle_response(struct otus_softc *sc, struct ar_cmd_hdr *hdr) 1376 { 1377 struct otus_tx_cmd *cmd; 1378 1379 OTUS_LOCK_ASSERT(sc); 1380 1381 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1382 "%s: received reply code=0x%02x len=%d token=%d\n", 1383 __func__, 1384 hdr->code, hdr->len, hdr->token); 1385 1386 /* 1387 * Walk the list, freeing items that aren't ours, 1388 * stopping when we hit our token. 1389 */ 1390 while ((cmd = STAILQ_FIRST(&sc->sc_cmd_waiting)) != NULL) { 1391 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next_cmd); 1392 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1393 "%s: cmd=%p; hdr.token=%d, cmd.token=%d\n", 1394 __func__, 1395 cmd, 1396 (int) hdr->token, 1397 (int) cmd->token); 1398 if (hdr->token == cmd->token) { 1399 /* Copy answer into caller's supplied buffer. */ 1400 if (cmd->odata != NULL) { 1401 if (hdr->len != cmd->odatalen) { 1402 device_printf(sc->sc_dev, 1403 "%s: code 0x%02x, len=%d, olen=%d\n", 1404 __func__, 1405 (int) hdr->code, 1406 (int) hdr->len, 1407 (int) cmd->odatalen); 1408 } 1409 memcpy(cmd->odata, &hdr[1], 1410 MIN(cmd->odatalen, hdr->len)); 1411 } 1412 wakeup(cmd); 1413 } 1414 1415 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next_cmd); 1416 } 1417 } 1418 1419 void 1420 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1421 { 1422 struct ieee80211com *ic = &sc->sc_ic; 1423 struct ar_cmd_hdr *hdr; 1424 1425 OTUS_LOCK_ASSERT(sc); 1426 1427 if (__predict_false(len < sizeof (*hdr))) { 1428 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1429 "cmd too small %d\n", len); 1430 return; 1431 } 1432 hdr = (struct ar_cmd_hdr *)buf; 1433 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1434 sizeof (*hdr) + hdr->len > 64)) { 1435 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1436 "cmd too large %d\n", hdr->len); 1437 return; 1438 } 1439 1440 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1441 "%s: code=%.02x\n", 1442 __func__, 1443 hdr->code); 1444 1445 /* 1446 * This has to reach into the cmd queue "waiting for 1447 * an RX response" list, grab the head entry and check 1448 * if we need to wake anyone up. 1449 */ 1450 if ((hdr->code & 0xc0) != 0xc0) { 1451 otus_cmd_handle_response(sc, hdr); 1452 return; 1453 } 1454 1455 /* Received unsolicited notification. */ 1456 switch (hdr->code & 0x3f) { 1457 case AR_EVT_BEACON: 1458 break; 1459 case AR_EVT_TX_COMP: 1460 { 1461 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1462 struct ieee80211_node *ni; 1463 1464 ni = ieee80211_find_node(&ic->ic_sta, tx->macaddr); 1465 if (ni == NULL) { 1466 device_printf(sc->sc_dev, 1467 "%s: txcomp on unknown node (%s)\n", 1468 __func__, 1469 ether_sprintf(tx->macaddr)); 1470 break; 1471 } 1472 1473 OTUS_DPRINTF(sc, OTUS_DEBUG_TXCOMP, 1474 "tx completed %s status=%d phy=0x%x\n", 1475 ether_sprintf(tx->macaddr), le16toh(tx->status), 1476 le32toh(tx->phy)); 1477 1478 switch (le16toh(tx->status)) { 1479 case AR_TX_STATUS_COMP: 1480 #if 0 1481 ackfailcnt = 0; 1482 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1483 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 1484 #endif 1485 /* 1486 * We don't get the above; only error notifications. 1487 * Sigh. So, don't worry about this. 1488 */ 1489 break; 1490 case AR_TX_STATUS_RETRY_COMP: 1491 OTUS_NODE(ni)->tx_retries++; 1492 break; 1493 case AR_TX_STATUS_FAILED: 1494 OTUS_NODE(ni)->tx_err++; 1495 break; 1496 } 1497 ieee80211_free_node(ni); 1498 break; 1499 } 1500 case AR_EVT_TBTT: 1501 break; 1502 case AR_EVT_DO_BB_RESET: 1503 /* 1504 * This is "tell driver to reset baseband" from ar9170-fw. 1505 * 1506 * I'm not sure what we should do here, so I'm going to 1507 * fall through; it gets generated when RTSRetryCnt internally 1508 * reaches '5' - I guess the firmware authors thought that 1509 * meant that the BB may have gone deaf or something. 1510 */ 1511 default: 1512 device_printf(sc->sc_dev, 1513 "%s: received notification code=0x%02x len=%d\n", 1514 __func__, 1515 hdr->code, hdr->len); 1516 } 1517 } 1518 1519 /* 1520 * Handle a single MPDU. 1521 * 1522 * This may be a single MPDU, or it may be a sub-frame from an A-MPDU. 1523 * In the latter case some of the header details need to be adjusted. 1524 */ 1525 void 1526 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len, struct mbufq *rxq) 1527 { 1528 struct ieee80211com *ic = &sc->sc_ic; 1529 struct ieee80211_rx_stats rxs; 1530 #if 0 1531 struct ieee80211_node *ni; 1532 #endif 1533 struct ar_rx_macstatus *mac_status = NULL; 1534 struct ar_rx_phystatus *phy_status = NULL; 1535 struct ieee80211_frame *wh; 1536 struct mbuf *m; 1537 // int s; 1538 1539 if (otus_debug & OTUS_DEBUG_RX_BUFFER) { 1540 device_printf(sc->sc_dev, "%s: %*D\n", 1541 __func__, len, buf, "-"); 1542 } 1543 1544 /* 1545 * Before any data path stuff - check to see if this is a command 1546 * response. 1547 * 1548 * All bits in the PLCP header are set to 1 for non-MPDU. 1549 */ 1550 if ((len >= AR_PLCP_HDR_LEN) && 1551 memcmp(buf, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1552 otus_cmd_rxeof(sc, buf + AR_PLCP_HDR_LEN, 1553 len - AR_PLCP_HDR_LEN); 1554 return; 1555 } 1556 1557 /* 1558 * First step - get the status for the given frame. 1559 * This will tell us whether it's a single MPDU or 1560 * an A-MPDU subframe. 1561 */ 1562 if (len < sizeof(*mac_status)) { 1563 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1564 "%s: sub-xfer too short (no mac_status) (len %d)\n", 1565 __func__, len); 1566 counter_u64_add(ic->ic_ierrors, 1); 1567 return; 1568 } 1569 /* 1570 * Remove the mac_status from the payload length. 1571 * 1572 * Note: cheating, don't reallocate the buffer! 1573 */ 1574 mac_status = (struct ar_rx_macstatus *)(buf + len - sizeof(*mac_status)); 1575 len -= sizeof(*mac_status); 1576 1577 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: mac status=0x%x\n", 1578 __func__, mac_status->status); 1579 1580 /* 1581 * Next - check the MAC status before doing anything else. 1582 * Extract out the PLCP header for single and first frames; 1583 * since there's a single RX path we can shove PLCP headers 1584 * from both into sc->ar_last_rx_plcp[] so it can be reused. 1585 */ 1586 if (((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_SINGLE) || 1587 ((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_FIRST)) { 1588 /* 1589 * Ok, we need to at least have a PLCP header at 1590 * this point. 1591 */ 1592 if (len < AR_PLCP_HDR_LEN) { 1593 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1594 "%s sub-xfer too short (no mac+plcp) (len %d\n)", 1595 __func__, len); 1596 counter_u64_add(ic->ic_ierrors, 1); 1597 return; 1598 } 1599 memcpy(sc->ar_last_rx_plcp, buf, AR_PLCP_HDR_LEN); 1600 1601 /* 1602 * At this point we can just consume the PLCP header. 1603 * The beginning of the frame should thus be data. 1604 */ 1605 buf += AR_PLCP_HDR_LEN; 1606 len -= AR_PLCP_HDR_LEN; 1607 } 1608 1609 /* 1610 * Next - see if we have a PHY status. 1611 * 1612 * The PHY status is at the end of the final A-MPDU subframe 1613 * or a single MPDU frame. 1614 * 1615 * We'll use this to tag frames with noise floor / RSSI 1616 * if they have valid information. 1617 */ 1618 if (((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_SINGLE) || 1619 ((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_LAST)) { 1620 if (len < sizeof(*phy_status)) { 1621 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1622 "%s sub-xfer too short (no phy status) (len %d\n)", 1623 __func__, len); 1624 counter_u64_add(ic->ic_ierrors, 1); 1625 return; 1626 } 1627 /* 1628 * Take a pointer to the phy status and remove the length 1629 * from the end of the buffer. 1630 * 1631 * Note: we're cheating here; don't reallocate the buffer! 1632 */ 1633 phy_status = (struct ar_rx_phystatus *) 1634 (buf + len - sizeof(*phy_status)); 1635 len -= sizeof(*phy_status); 1636 } 1637 1638 /* 1639 * Middle frames just have a MAC status (stripped above.) 1640 * No PHY status, and PLCP is from ar_last_rx_plcp. 1641 */ 1642 1643 /* 1644 * Discard error frames; don't discard BAD_RA (eg monitor mode); 1645 * let net80211 do that 1646 */ 1647 if (__predict_false((mac_status->error & ~AR_RX_ERROR_BAD_RA) != 0)) { 1648 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "error frame 0x%02x\n", mac_status->error); 1649 if (mac_status->error & AR_RX_ERROR_FCS) { 1650 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "bad FCS\n"); 1651 } else if (mac_status->error & AR_RX_ERROR_MMIC) { 1652 /* Report Michael MIC failures to net80211. */ 1653 #if 0 1654 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyidx); 1655 #endif 1656 device_printf(sc->sc_dev, "%s: MIC failure\n", __func__); 1657 } 1658 counter_u64_add(ic->ic_ierrors, 1); 1659 return; 1660 } 1661 1662 /* 1663 * Make sure there's room for an 802.11 header + FCS. 1664 * 1665 * Note: a CTS/ACK is 14 bytes (FC, DUR, RA, FCS). 1666 * Making it IEEE80211_MIN_LEN misses CTS/ACKs. 1667 * 1668 * This won't be tossed at this point; eventually once 1669 * rx radiotap is implemented this will allow for 1670 * CTS/ACK frames. Passing them up to net80211 will 1671 * currently make it angry (too short packets.) 1672 */ 1673 if (len < 2 + 2 + IEEE80211_ADDR_LEN + IEEE80211_CRC_LEN) { 1674 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1675 "%s: too short for 802.11 (len %d)\n", 1676 __func__, len); 1677 counter_u64_add(ic->ic_ierrors, 1); 1678 return; 1679 } 1680 1681 len -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1682 wh = (struct ieee80211_frame *) buf; 1683 1684 /* 1685 * The firmware does seem to spit out a bunch of frames 1686 * with invalid frame control values here. Just toss them 1687 * rather than letting net80211 get angry and log. 1688 */ 1689 if ((wh->i_fc[0] & IEEE80211_FC0_VERSION_MASK) != 1690 IEEE80211_FC0_VERSION_0) { 1691 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1692 "%s: invalid 802.11 fc version (firmware bug?)\n", 1693 __func__); 1694 counter_u64_add(ic->ic_ierrors, 1); 1695 return; 1696 } 1697 1698 m = m_get2(len, M_NOWAIT, MT_DATA, M_PKTHDR); 1699 if (m == NULL) { 1700 device_printf(sc->sc_dev, "%s: failed m_get2() (len=%d)\n", 1701 __func__, len); 1702 counter_u64_add(ic->ic_ierrors, 1); 1703 return; 1704 } 1705 1706 /* Finalize mbuf. */ 1707 memcpy(mtod(m, uint8_t *), wh, len); 1708 m->m_pkthdr.len = m->m_len = len; 1709 1710 /* XXX TODO: add setting rx radiotap fields here */ 1711 1712 /* 1713 * Ok, check the frame length and toss if it's too short 1714 * for net80211. This will toss ACK/CTS. 1715 */ 1716 if (m->m_len < IEEE80211_MIN_LEN) { 1717 /* XXX TODO: add radiotap receive here */ 1718 m_free(m); m = NULL; 1719 return; 1720 } 1721 1722 /* Add RSSI to this mbuf if we have a PHY header */ 1723 bzero(&rxs, sizeof(rxs)); 1724 rxs.r_flags = IEEE80211_R_NF; 1725 rxs.c_nf = sc->sc_nf[0]; /* XXX chain 0 != combined rssi/nf */ 1726 if (phy_status != NULL) { 1727 rxs.r_flags |= IEEE80211_R_RSSI; 1728 rxs.c_rssi = phy_status->rssi; 1729 } 1730 /* XXX TODO: add MIMO RSSI/NF as well */ 1731 if (ieee80211_add_rx_params(m, &rxs) == 0) { 1732 counter_u64_add(ic->ic_ierrors, 1); 1733 return; 1734 } 1735 1736 /* XXX make a method */ 1737 STAILQ_INSERT_TAIL(&rxq->mq_head, m, m_stailqpkt); 1738 1739 #if 0 1740 OTUS_UNLOCK(sc); 1741 ni = ieee80211_find_rxnode(ic, wh); 1742 rxi.rxi_flags = 0; 1743 rxi.rxi_rssi = tail->rssi; 1744 rxi.rxi_tstamp = 0; /* unused */ 1745 ieee80211_input(ifp, m, ni, &rxi); 1746 1747 /* Node is no longer needed. */ 1748 ieee80211_release_node(ic, ni); 1749 OTUS_LOCK(sc); 1750 #endif 1751 } 1752 1753 static void 1754 otus_rxeof(struct usb_xfer *xfer, struct otus_data *data, struct mbufq *rxq) 1755 { 1756 struct otus_softc *sc = usbd_xfer_softc(xfer); 1757 caddr_t buf = data->buf; 1758 struct ar_rx_head *head; 1759 uint16_t hlen; 1760 int len, offset = 0; 1761 1762 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 1763 1764 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1765 "%s: transfer completed; len=%d\n", 1766 __func__, len); 1767 if (otus_debug & OTUS_DEBUG_RX_BUFFER) { 1768 device_printf(sc->sc_dev, "%s: %*D\n", 1769 __func__, len, buf, "-"); 1770 } 1771 1772 while (len >= sizeof (*head)) { 1773 head = (struct ar_rx_head *)buf; 1774 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1775 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1776 "tag not valid 0x%x\n", le16toh(head->tag)); 1777 break; 1778 } 1779 hlen = le16toh(head->len); 1780 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: hlen=%d\n", 1781 __func__, hlen); 1782 if (__predict_false(sizeof (*head) + hlen > len)) { 1783 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1784 "xfer too short %d/%d\n", len, hlen); 1785 break; 1786 } 1787 /* Process sub-xfer. */ 1788 otus_sub_rxeof(sc, (uint8_t *) (((uint8_t *) buf) + 4), hlen, rxq); 1789 1790 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1791 hlen = (sizeof (*head) + hlen + 3) & ~3; 1792 offset += hlen; 1793 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1794 "%s: rounded size is %d, next packet starts at %d\n", 1795 __func__, hlen, offset); 1796 buf += hlen; 1797 len -= hlen; 1798 } 1799 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: done!\n", __func__); 1800 } 1801 1802 static void 1803 otus_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1804 { 1805 struct otus_softc *sc = usbd_xfer_softc(xfer); 1806 struct ieee80211com *ic = &sc->sc_ic; 1807 struct ieee80211_frame *wh; 1808 struct ieee80211_node *ni; 1809 struct mbuf *m; 1810 struct mbufq scrx; 1811 struct otus_data *data; 1812 1813 OTUS_LOCK_ASSERT(sc); 1814 1815 mbufq_init(&scrx, 1024); 1816 1817 #if 0 1818 device_printf(sc->sc_dev, "%s: called; state=%d; error=%d\n", 1819 __func__, 1820 USB_GET_STATE(xfer), 1821 error); 1822 #endif 1823 1824 switch (USB_GET_STATE(xfer)) { 1825 case USB_ST_TRANSFERRED: 1826 data = STAILQ_FIRST(&sc->sc_rx_active); 1827 if (data == NULL) 1828 goto tr_setup; 1829 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1830 otus_rxeof(xfer, data, &scrx); 1831 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1832 /* FALLTHROUGH */ 1833 case USB_ST_SETUP: 1834 tr_setup: 1835 /* 1836 * XXX TODO: what if sc_rx isn't empty, but data 1837 * is empty? Then we leak mbufs. 1838 */ 1839 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1840 if (data == NULL) { 1841 //KASSERT(m == NULL, ("mbuf isn't NULL")); 1842 return; 1843 } 1844 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1845 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1846 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1847 usbd_xfer_max_len(xfer)); 1848 usbd_transfer_submit(xfer); 1849 /* 1850 * To avoid LOR we should unlock our private mutex here to call 1851 * ieee80211_input() because here is at the end of a USB 1852 * callback and safe to unlock. 1853 */ 1854 OTUS_UNLOCK(sc); 1855 while ((m = mbufq_dequeue(&scrx)) != NULL) { 1856 wh = mtod(m, struct ieee80211_frame *); 1857 ni = ieee80211_find_rxnode(ic, 1858 (struct ieee80211_frame_min *)wh); 1859 if (ni != NULL) { 1860 if (ni->ni_flags & IEEE80211_NODE_HT) 1861 m->m_flags |= M_AMPDU; 1862 (void)ieee80211_input_mimo(ni, m); 1863 ieee80211_free_node(ni); 1864 } else 1865 (void)ieee80211_input_mimo_all(ic, m); 1866 } 1867 #ifdef IEEE80211_SUPPORT_SUPERG 1868 ieee80211_ff_age_all(ic, 100); 1869 #endif 1870 OTUS_LOCK(sc); 1871 break; 1872 default: 1873 /* needs it to the inactive queue due to a error. */ 1874 data = STAILQ_FIRST(&sc->sc_rx_active); 1875 if (data != NULL) { 1876 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1877 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1878 } 1879 if (error != USB_ERR_CANCELLED) { 1880 usbd_xfer_set_stall(xfer); 1881 counter_u64_add(ic->ic_ierrors, 1); 1882 goto tr_setup; 1883 } 1884 break; 1885 } 1886 } 1887 1888 static void 1889 otus_txeof(struct usb_xfer *xfer, struct otus_data *data) 1890 { 1891 struct otus_softc *sc = usbd_xfer_softc(xfer); 1892 1893 OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, 1894 "%s: called; data=%p\n", __func__, data); 1895 1896 OTUS_LOCK_ASSERT(sc); 1897 1898 if (sc->sc_tx_n_active == 0) { 1899 device_printf(sc->sc_dev, 1900 "%s: completed but tx_active=0\n", 1901 __func__); 1902 } else { 1903 sc->sc_tx_n_active--; 1904 } 1905 1906 if (data->m) { 1907 /* XXX status? */ 1908 /* XXX we get TX status via the RX path.. */ 1909 ieee80211_tx_complete(data->ni, data->m, 0); 1910 data->m = NULL; 1911 data->ni = NULL; 1912 } 1913 } 1914 1915 static void 1916 otus_txcmdeof(struct usb_xfer *xfer, struct otus_tx_cmd *cmd) 1917 { 1918 struct otus_softc *sc = usbd_xfer_softc(xfer); 1919 1920 OTUS_LOCK_ASSERT(sc); 1921 1922 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1923 "%s: called; data=%p; odata=%p\n", 1924 __func__, cmd, cmd->odata); 1925 1926 /* 1927 * Non-response commands still need wakeup so the caller 1928 * knows it was submitted and completed OK; response commands should 1929 * wait until they're ACKed by the firmware with a response. 1930 */ 1931 if (cmd->odata) { 1932 STAILQ_INSERT_TAIL(&sc->sc_cmd_waiting, cmd, next_cmd); 1933 } else { 1934 wakeup(cmd); 1935 otus_free_txcmd(sc, cmd); 1936 } 1937 } 1938 1939 static void 1940 otus_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1941 { 1942 uint8_t which = OTUS_BULK_TX; 1943 struct otus_softc *sc = usbd_xfer_softc(xfer); 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 struct otus_data *data; 1946 1947 OTUS_LOCK_ASSERT(sc); 1948 1949 switch (USB_GET_STATE(xfer)) { 1950 case USB_ST_TRANSFERRED: 1951 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1952 if (data == NULL) 1953 goto tr_setup; 1954 OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, 1955 "%s: transfer done %p\n", __func__, data); 1956 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1957 otus_txeof(xfer, data); 1958 otus_freebuf(sc, data); 1959 /* FALLTHROUGH */ 1960 case USB_ST_SETUP: 1961 tr_setup: 1962 data = STAILQ_FIRST(&sc->sc_tx_pending[which]); 1963 if (data == NULL) { 1964 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 1965 "%s: empty pending queue sc %p\n", __func__, sc); 1966 sc->sc_tx_n_active = 0; 1967 goto finish; 1968 } 1969 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending[which], next); 1970 STAILQ_INSERT_TAIL(&sc->sc_tx_active[which], data, next); 1971 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1972 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 1973 "%s: submitting transfer %p\n", __func__, data); 1974 usbd_transfer_submit(xfer); 1975 sc->sc_tx_n_active++; 1976 break; 1977 default: 1978 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1979 if (data != NULL) { 1980 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1981 otus_txeof(xfer, data); 1982 otus_freebuf(sc, data); 1983 } 1984 counter_u64_add(ic->ic_oerrors, 1); 1985 1986 if (error != USB_ERR_CANCELLED) { 1987 usbd_xfer_set_stall(xfer); 1988 goto tr_setup; 1989 } 1990 break; 1991 } 1992 1993 finish: 1994 #ifdef IEEE80211_SUPPORT_SUPERG 1995 /* 1996 * If the TX active queue drops below a certain 1997 * threshold, ensure we age fast-frames out so they're 1998 * transmitted. 1999 */ 2000 if (sc->sc_tx_n_active < 2) { 2001 /* XXX ew - net80211 should defer this for us! */ 2002 OTUS_UNLOCK(sc); 2003 ieee80211_ff_flush(ic, WME_AC_VO); 2004 ieee80211_ff_flush(ic, WME_AC_VI); 2005 ieee80211_ff_flush(ic, WME_AC_BE); 2006 ieee80211_ff_flush(ic, WME_AC_BK); 2007 OTUS_LOCK(sc); 2008 } 2009 #endif 2010 /* Kick TX */ 2011 otus_tx_start(sc); 2012 } 2013 2014 static void 2015 otus_bulk_cmd_callback(struct usb_xfer *xfer, usb_error_t error) 2016 { 2017 struct otus_softc *sc = usbd_xfer_softc(xfer); 2018 #if 0 2019 struct ieee80211com *ic = &sc->sc_ic; 2020 #endif 2021 struct otus_tx_cmd *cmd; 2022 2023 OTUS_LOCK_ASSERT(sc); 2024 2025 switch (USB_GET_STATE(xfer)) { 2026 case USB_ST_TRANSFERRED: 2027 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2028 if (cmd == NULL) 2029 goto tr_setup; 2030 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 2031 "%s: transfer done %p\n", __func__, cmd); 2032 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); 2033 otus_txcmdeof(xfer, cmd); 2034 /* FALLTHROUGH */ 2035 case USB_ST_SETUP: 2036 tr_setup: 2037 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2038 if (cmd == NULL) { 2039 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 2040 "%s: empty pending queue sc %p\n", __func__, sc); 2041 return; 2042 } 2043 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next_cmd); 2044 STAILQ_INSERT_TAIL(&sc->sc_cmd_active, cmd, next_cmd); 2045 usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); 2046 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 2047 "%s: submitting transfer %p; buf=%p, buflen=%d\n", __func__, cmd, cmd->buf, cmd->buflen); 2048 usbd_transfer_submit(xfer); 2049 break; 2050 default: 2051 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2052 if (cmd != NULL) { 2053 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); 2054 otus_txcmdeof(xfer, cmd); 2055 } 2056 2057 if (error != USB_ERR_CANCELLED) { 2058 usbd_xfer_set_stall(xfer); 2059 goto tr_setup; 2060 } 2061 break; 2062 } 2063 } 2064 2065 /* 2066 * This isn't used by carl9170; it however may be used by the 2067 * initial bootloader. 2068 */ 2069 static void 2070 otus_bulk_irq_callback(struct usb_xfer *xfer, usb_error_t error) 2071 { 2072 struct otus_softc *sc = usbd_xfer_softc(xfer); 2073 int actlen; 2074 int sumlen; 2075 2076 usbd_xfer_status(xfer, &actlen, &sumlen, NULL, NULL); 2077 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, 2078 "%s: called; state=%d\n", __func__, USB_GET_STATE(xfer)); 2079 2080 switch (USB_GET_STATE(xfer)) { 2081 case USB_ST_TRANSFERRED: 2082 /* 2083 * Read usb frame data, if any. 2084 * "actlen" has the total length for all frames 2085 * transferred. 2086 */ 2087 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, 2088 "%s: comp; %d bytes\n", 2089 __func__, 2090 actlen); 2091 #if 0 2092 pc = usbd_xfer_get_frame(xfer, 0); 2093 otus_dump_usb_rx_page(sc, pc, actlen); 2094 #endif 2095 /* XXX fallthrough */ 2096 case USB_ST_SETUP: 2097 /* 2098 * Setup xfer frame lengths/count and data 2099 */ 2100 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: setup\n", __func__); 2101 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 2102 usbd_transfer_submit(xfer); 2103 break; 2104 2105 default: /* Error */ 2106 /* 2107 * Print error message and clear stall 2108 * for example. 2109 */ 2110 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: ERROR?\n", __func__); 2111 break; 2112 } 2113 } 2114 2115 /* 2116 * Map net80211 rate to hw rate for otus MAC/PHY. 2117 */ 2118 static uint8_t 2119 otus_rate_to_hw_rate(struct otus_softc *sc, uint8_t rate) 2120 { 2121 int is_2ghz; 2122 2123 is_2ghz = !! (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_curchan)); 2124 2125 /* MCS check */ 2126 if (rate & 0x80) { 2127 return rate; 2128 } 2129 2130 switch (rate) { 2131 /* CCK */ 2132 case 2: 2133 return (0x0); 2134 case 4: 2135 return (0x1); 2136 case 11: 2137 return (0x2); 2138 case 22: 2139 return (0x3); 2140 /* OFDM */ 2141 case 12: 2142 return (0xb); 2143 case 18: 2144 return (0xf); 2145 case 24: 2146 return (0xa); 2147 case 36: 2148 return (0xe); 2149 case 48: 2150 return (0x9); 2151 case 72: 2152 return (0xd); 2153 case 96: 2154 return (0x8); 2155 case 108: 2156 return (0xc); 2157 default: 2158 device_printf(sc->sc_dev, "%s: unknown rate '%d'\n", 2159 __func__, (int) rate); 2160 case 0: 2161 if (is_2ghz) 2162 return (0x0); /* 1MB CCK */ 2163 else 2164 return (0xb); /* 6MB OFDM */ 2165 } 2166 } 2167 2168 static int 2169 otus_hw_rate_is_ht(struct otus_softc *sc, uint8_t hw_rate) 2170 { 2171 2172 return !! (hw_rate & 0x80); 2173 } 2174 2175 static int 2176 otus_hw_rate_is_ofdm(struct otus_softc *sc, uint8_t hw_rate) 2177 { 2178 2179 switch (hw_rate) { 2180 case 0x0: 2181 case 0x1: 2182 case 0x2: 2183 case 0x3: 2184 return (0); 2185 default: 2186 return (1); 2187 } 2188 } 2189 2190 static void 2191 otus_tx_update_ratectl(struct otus_softc *sc, struct ieee80211_node *ni) 2192 { 2193 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs; 2194 struct otus_node *on = OTUS_NODE(ni); 2195 2196 txs->flags = IEEE80211_RATECTL_TX_STATS_NODE | 2197 IEEE80211_RATECTL_TX_STATS_RETRIES; 2198 txs->ni = ni; 2199 txs->nframes = on->tx_done; 2200 txs->nsuccess = on->tx_done - on->tx_err; 2201 txs->nretries = on->tx_retries; 2202 2203 ieee80211_ratectl_tx_update(ni->ni_vap, txs); 2204 on->tx_done = on->tx_err = on->tx_retries = 0; 2205 } 2206 2207 /* 2208 * XXX TODO: support tx bpf parameters for configuration! 2209 * 2210 * Relevant pieces: 2211 * 2212 * ac = params->ibp_pri & 3; 2213 * rate = params->ibp_rate0; 2214 * params->ibp_flags & IEEE80211_BPF_NOACK 2215 * params->ibp_flags & IEEE80211_BPF_RTS 2216 * params->ibp_flags & IEEE80211_BPF_CTS 2217 * tx->rts_ntries = params->ibp_try1; 2218 * tx->data_ntries = params->ibp_try0; 2219 */ 2220 static int 2221 otus_tx(struct otus_softc *sc, struct ieee80211_node *ni, struct mbuf *m, 2222 struct otus_data *data, const struct ieee80211_bpf_params *params) 2223 { 2224 const struct ieee80211_txparam *tp = ni->ni_txparms; 2225 struct ieee80211com *ic = &sc->sc_ic; 2226 struct ieee80211vap *vap = ni->ni_vap; 2227 struct ieee80211_frame *wh; 2228 struct ieee80211_key *k; 2229 struct ar_tx_head *head; 2230 uint32_t phyctl; 2231 uint16_t macctl, qos; 2232 uint8_t qid, rate; 2233 int hasqos, xferlen, type, ismcast; 2234 2235 wh = mtod(m, struct ieee80211_frame *); 2236 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2237 k = ieee80211_crypto_encap(ni, m); 2238 if (k == NULL) { 2239 device_printf(sc->sc_dev, 2240 "%s: m=%p: ieee80211_crypto_encap returns NULL\n", 2241 __func__, 2242 m); 2243 return (ENOBUFS); 2244 } 2245 wh = mtod(m, struct ieee80211_frame *); 2246 } 2247 2248 /* Calculate transfer length; ensure data buffer is large enough */ 2249 xferlen = sizeof (*head) + m->m_pkthdr.len; 2250 if (xferlen > OTUS_TXBUFSZ) { 2251 device_printf(sc->sc_dev, 2252 "%s: 802.11 TX frame is %d bytes, max %d bytes\n", 2253 __func__, 2254 xferlen, 2255 OTUS_TXBUFSZ); 2256 return (ENOBUFS); 2257 } 2258 2259 hasqos = !! IEEE80211_QOS_HAS_SEQ(wh); 2260 2261 if (hasqos) { 2262 uint8_t tid; 2263 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2264 tid = qos & IEEE80211_QOS_TID; 2265 qid = TID_TO_WME_AC(tid); 2266 } else { 2267 qos = 0; 2268 qid = WME_AC_BE; 2269 } 2270 2271 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2272 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2273 2274 /* Pickup a rate index. */ 2275 if (params != NULL) 2276 rate = otus_rate_to_hw_rate(sc, params->ibp_rate0); 2277 else if (!!(m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2278 rate = otus_rate_to_hw_rate(sc, tp->mgmtrate); 2279 else if (ismcast) 2280 rate = otus_rate_to_hw_rate(sc, tp->mcastrate); 2281 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2282 rate = otus_rate_to_hw_rate(sc, tp->ucastrate); 2283 else { 2284 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2285 rate = otus_rate_to_hw_rate(sc, ni->ni_txrate); 2286 } 2287 2288 phyctl = 0; 2289 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 2290 2291 /* 2292 * XXX TODO: params for NOACK, ACK, RTS, CTS, etc 2293 */ 2294 if (ismcast || 2295 (hasqos && ((qos & IEEE80211_QOS_ACKPOLICY) == 2296 IEEE80211_QOS_ACKPOLICY_NOACK))) 2297 macctl |= AR_TX_MAC_NOACK; 2298 2299 if (!ismcast) { 2300 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= vap->iv_rtsthreshold) 2301 macctl |= AR_TX_MAC_RTS; 2302 else if (otus_hw_rate_is_ht(sc, rate)) { 2303 if (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) 2304 macctl |= AR_TX_MAC_RTS; 2305 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 2306 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2307 macctl |= AR_TX_MAC_CTS; 2308 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2309 macctl |= AR_TX_MAC_RTS; 2310 } 2311 } 2312 2313 phyctl |= AR_TX_PHY_MCS(rate & 0x7f); /* Note: MCS rates are 0x80 and above */ 2314 if (otus_hw_rate_is_ht(sc, rate)) { 2315 phyctl |= AR_TX_PHY_MT_HT; 2316 /* Always use all tx antennas for now, just to be safe */ 2317 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2318 2319 /* Heavy clip */ 2320 phyctl |= (rate & 0x7) << AR_TX_PHY_TX_HEAVY_CLIP_SHIFT; 2321 } else if (otus_hw_rate_is_ofdm(sc, rate)) { 2322 phyctl |= AR_TX_PHY_MT_OFDM; 2323 /* Always use all tx antennas for now, just to be safe */ 2324 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2325 } else { /* CCK */ 2326 phyctl |= AR_TX_PHY_MT_CCK; 2327 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2328 } 2329 2330 /* Update net80211 with the current counters */ 2331 otus_tx_update_ratectl(sc, ni); 2332 2333 /* Update rate control stats for frames that are ACK'ed. */ 2334 if (!(macctl & AR_TX_MAC_NOACK)) 2335 OTUS_NODE(ni)->tx_done++; 2336 2337 /* Fill Tx descriptor. */ 2338 head = (struct ar_tx_head *)data->buf; 2339 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 2340 head->macctl = htole16(macctl); 2341 head->phyctl = htole32(phyctl); 2342 2343 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); 2344 2345 data->buflen = xferlen; 2346 data->ni = ni; 2347 data->m = m; 2348 2349 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 2350 "%s: tx: m=%p; data=%p; len=%d mac=0x%04x phy=0x%08x rate=0x%02x, ni_txrate=%d\n", 2351 __func__, m, data, le16toh(head->len), macctl, phyctl, 2352 (int) rate, (int) ni->ni_txrate); 2353 2354 /* Submit transfer */ 2355 STAILQ_INSERT_TAIL(&sc->sc_tx_pending[OTUS_BULK_TX], data, next); 2356 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_TX]); 2357 2358 return 0; 2359 } 2360 2361 static u_int 2362 otus_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2363 { 2364 uint32_t val, *hashes = arg; 2365 2366 val = le32dec(LLADDR(sdl) + 4); 2367 /* Get address byte 5 */ 2368 val = val & 0x0000ff00; 2369 val = val >> 8; 2370 2371 /* As per below, shift it >> 2 to get only 6 bits */ 2372 val = val >> 2; 2373 if (val < 32) 2374 hashes[0] |= 1 << val; 2375 else 2376 hashes[1] |= 1 << (val - 32); 2377 2378 return (1); 2379 } 2380 2381 int 2382 otus_set_multi(struct otus_softc *sc) 2383 { 2384 struct ieee80211com *ic = &sc->sc_ic; 2385 uint32_t hashes[2]; 2386 int r; 2387 2388 if (ic->ic_allmulti > 0 || ic->ic_promisc > 0 || 2389 ic->ic_opmode == IEEE80211_M_MONITOR) { 2390 hashes[0] = 0xffffffff; 2391 hashes[1] = 0xffffffff; 2392 } else { 2393 struct ieee80211vap *vap; 2394 2395 hashes[0] = hashes[1] = 0; 2396 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) 2397 if_foreach_llmaddr(vap->iv_ifp, otus_hash_maddr, 2398 hashes); 2399 } 2400 #if 0 2401 /* XXX openbsd code */ 2402 while (enm != NULL) { 2403 bit = enm->enm_addrlo[5] >> 2; 2404 if (bit < 32) 2405 hashes[0] |= 1 << bit; 2406 else 2407 hashes[1] |= 1 << (bit - 32); 2408 ETHER_NEXT_MULTI(step, enm); 2409 } 2410 #endif 2411 2412 hashes[1] |= 1U << 31; /* Make sure the broadcast bit is set. */ 2413 2414 OTUS_LOCK(sc); 2415 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, hashes[0]); 2416 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hashes[1]); 2417 r = otus_write_barrier(sc); 2418 /* XXX operating mode? filter? */ 2419 OTUS_UNLOCK(sc); 2420 return (r); 2421 } 2422 2423 static int 2424 otus_updateedca(struct ieee80211com *ic) 2425 { 2426 struct otus_softc *sc = ic->ic_softc; 2427 2428 OTUS_LOCK(sc); 2429 /* 2430 * XXX TODO: take temporary copy of EDCA information 2431 * when scheduling this so we have a more time-correct view 2432 * of things. 2433 * XXX TODO: this can be done on the net80211 level 2434 */ 2435 otus_updateedca_locked(sc); 2436 OTUS_UNLOCK(sc); 2437 return (0); 2438 } 2439 2440 static void 2441 otus_updateedca_locked(struct otus_softc *sc) 2442 { 2443 #define EXP2(val) ((1 << (val)) - 1) 2444 #define AIFS(val) ((val) * 9 + 10) 2445 struct chanAccParams chp; 2446 struct ieee80211com *ic = &sc->sc_ic; 2447 const struct wmeParams *edca; 2448 2449 ieee80211_wme_ic_getparams(ic, &chp); 2450 2451 OTUS_LOCK_ASSERT(sc); 2452 2453 edca = chp.cap_wmeParams; 2454 2455 /* Set CWmin/CWmax values. */ 2456 otus_write(sc, AR_MAC_REG_AC0_CW, 2457 EXP2(edca[WME_AC_BE].wmep_logcwmax) << 16 | 2458 EXP2(edca[WME_AC_BE].wmep_logcwmin)); 2459 otus_write(sc, AR_MAC_REG_AC1_CW, 2460 EXP2(edca[WME_AC_BK].wmep_logcwmax) << 16 | 2461 EXP2(edca[WME_AC_BK].wmep_logcwmin)); 2462 otus_write(sc, AR_MAC_REG_AC2_CW, 2463 EXP2(edca[WME_AC_VI].wmep_logcwmax) << 16 | 2464 EXP2(edca[WME_AC_VI].wmep_logcwmin)); 2465 otus_write(sc, AR_MAC_REG_AC3_CW, 2466 EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | 2467 EXP2(edca[WME_AC_VO].wmep_logcwmin)); 2468 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 2469 EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | 2470 EXP2(edca[WME_AC_VO].wmep_logcwmin)); 2471 2472 /* Set AIFSN values. */ 2473 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 2474 AIFS(edca[WME_AC_VI].wmep_aifsn) << 24 | 2475 AIFS(edca[WME_AC_BK].wmep_aifsn) << 12 | 2476 AIFS(edca[WME_AC_BE].wmep_aifsn)); 2477 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 2478 AIFS(edca[WME_AC_VO].wmep_aifsn) << 16 | /* Special TXQ. */ 2479 AIFS(edca[WME_AC_VO].wmep_aifsn) << 4 | 2480 AIFS(edca[WME_AC_VI].wmep_aifsn) >> 8); 2481 2482 /* Set TXOP limit. */ 2483 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 2484 edca[WME_AC_BK].wmep_txopLimit << 16 | 2485 edca[WME_AC_BE].wmep_txopLimit); 2486 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 2487 edca[WME_AC_VO].wmep_txopLimit << 16 | 2488 edca[WME_AC_VI].wmep_txopLimit); 2489 2490 /* XXX ACK policy? */ 2491 2492 (void)otus_write_barrier(sc); 2493 2494 #undef AIFS 2495 #undef EXP2 2496 } 2497 2498 static void 2499 otus_updateslot(struct otus_softc *sc) 2500 { 2501 struct ieee80211com *ic = &sc->sc_ic; 2502 uint32_t slottime; 2503 2504 OTUS_LOCK_ASSERT(sc); 2505 2506 slottime = IEEE80211_GET_SLOTTIME(ic); 2507 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 2508 (void)otus_write_barrier(sc); 2509 } 2510 2511 /* 2512 * Things to do based on 2GHz or 5GHz: 2513 * 2514 * + slottime 2515 * + dyn_sifs_ack 2516 * + rts_cts_rate 2517 * + slot time 2518 * + mac_rates 2519 * + mac_tpc 2520 * 2521 * And in the transmit path 2522 * + tpc: carl9170_tx_rate_tpc_chains 2523 * + carl9170_tx_physet() 2524 * + disable short premable tx 2525 */ 2526 2527 int 2528 otus_init_mac(struct otus_softc *sc) 2529 { 2530 int error; 2531 2532 OTUS_LOCK_ASSERT(sc); 2533 2534 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 2535 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 2536 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 2537 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 2538 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 2539 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 2540 otus_write(sc, AR_MAC_REG_TID_CFACK_CFEND_RATE, 0x19000000); 2541 /* NAV protects ACK only (in TXOP). */ 2542 otus_write(sc, AR_MAC_REG_TXOP_DURATION, 0x201); 2543 /* Set beacon Tx power to 0x7. */ 2544 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 2545 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 2546 otus_write(sc, AR_MAC_REG_AMPDU_FACTOR, 0x10000a); 2547 2548 otus_set_rx_filter(sc); 2549 2550 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 2551 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 2552 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 2553 otus_write(sc, AR_MAC_REG_ACK_TPC, 0x4003c1e); 2554 2555 /* Enable LED0 and LED1. */ 2556 otus_write(sc, AR_GPIO_REG_PORT_TYPE, 0x3); 2557 otus_write(sc, AR_GPIO_REG_PORT_DATA, 0x3); 2558 /* Switch MAC to OTUS interface. */ 2559 otus_write(sc, 0x1c3600, 0x3); 2560 otus_write(sc, AR_MAC_REG_AMPDU_RX_THRESH, 0xffff); 2561 otus_write(sc, AR_MAC_REG_MISC_680, 0xf00008); 2562 /* Disable Rx timeout (workaround). */ 2563 otus_write(sc, AR_MAC_REG_RX_TIMEOUT, 0); 2564 2565 /* Set USB Rx stream mode maximum frame number to 2. */ 2566 otus_write(sc, 0x1e1110, 0x4); 2567 /* Set USB Rx stream mode timeout to 10us. */ 2568 otus_write(sc, 0x1e1114, 0x80); 2569 2570 /* Set clock frequency to 88/80MHz. */ 2571 otus_write(sc, AR_PWR_REG_CLOCK_SEL, 0x73); 2572 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 2573 otus_write(sc, AR_MAC_REG_TXRX_MPI, 0x110011); 2574 otus_write(sc, AR_MAC_REG_FCS_SELECT, 0x4); 2575 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 2576 2577 /* Disable HW decryption for now. */ 2578 otus_write(sc, AR_MAC_REG_ENCRYPTION, 0x78); 2579 2580 if ((error = otus_write_barrier(sc)) != 0) 2581 return error; 2582 2583 /* Set default EDCA parameters. */ 2584 otus_updateedca_locked(sc); 2585 2586 return 0; 2587 } 2588 2589 /* 2590 * Return default value for PHY register based on current operating mode. 2591 */ 2592 uint32_t 2593 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 2594 { 2595 int i; 2596 2597 for (i = 0; i < nitems(ar5416_phy_regs); i++) 2598 if (AR_PHY(ar5416_phy_regs[i]) == reg) 2599 return sc->phy_vals[i]; 2600 return 0; /* Register not found. */ 2601 } 2602 2603 /* 2604 * Update PHY's programming based on vendor-specific data stored in EEPROM. 2605 * This is for FEM-type devices only. 2606 */ 2607 int 2608 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 2609 { 2610 const struct ModalEepHeader *eep; 2611 uint32_t tmp, offset; 2612 2613 if (IEEE80211_IS_CHAN_5GHZ(c)) 2614 eep = &sc->eeprom.modalHeader[0]; 2615 else 2616 eep = &sc->eeprom.modalHeader[1]; 2617 2618 /* Offset of chain 2. */ 2619 offset = 2 * 0x1000; 2620 2621 tmp = le32toh(eep->antCtrlCommon); 2622 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 2623 2624 tmp = le32toh(eep->antCtrlChain[0]); 2625 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 2626 2627 tmp = le32toh(eep->antCtrlChain[1]); 2628 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 2629 2630 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 2631 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 2632 tmp &= ~(0x7f << 7); 2633 tmp |= (eep->switchSettling & 0x7f) << 7; 2634 otus_write(sc, AR_PHY_SETTLING, tmp); 2635 } 2636 2637 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 2638 tmp &= ~0xffff; 2639 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 2640 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 2641 2642 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 2643 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 2644 otus_write(sc, AR_PHY_RF_CTL4, tmp); 2645 2646 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 2647 tmp &= ~(0xff << 16); 2648 tmp |= eep->txEndToRxOn << 16; 2649 otus_write(sc, AR_PHY_RF_CTL3, tmp); 2650 2651 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 2652 tmp &= ~(0x7f << 12); 2653 tmp |= (eep->thresh62 & 0x7f) << 12; 2654 otus_write(sc, AR_PHY_CCA, tmp); 2655 2656 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 2657 tmp &= ~(0x3f << 12); 2658 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 2659 otus_write(sc, AR_PHY_RXGAIN, tmp); 2660 2661 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 2662 tmp &= ~(0x3f << 12); 2663 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 2664 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 2665 2666 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 2667 tmp &= ~(0x3f << 18); 2668 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 2669 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2670 tmp &= ~(0xf << 10); 2671 tmp |= (eep->bswMargin[0] & 0xf) << 10; 2672 } 2673 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 2674 2675 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 2676 tmp &= ~(0x3f << 18); 2677 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 2678 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 2679 2680 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 2681 tmp &= ~(0x3f << 5 | 0x1f); 2682 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 2683 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 2684 2685 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 2686 tmp &= ~(0x3f << 5 | 0x1f); 2687 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 2688 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 2689 2690 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 2691 tmp &= ~(0xf << 16); 2692 tmp |= (eep->xpd & 0xf) << 16; 2693 otus_write(sc, AR_PHY_TPCRG1, tmp); 2694 2695 return otus_write_barrier(sc); 2696 } 2697 2698 int 2699 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 2700 { 2701 const uint32_t *vals; 2702 int error, i; 2703 2704 /* Select PHY programming based on band and bandwidth. */ 2705 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2706 if (IEEE80211_IS_CHAN_HT40(c)) 2707 vals = ar5416_phy_vals_2ghz_40mhz; 2708 else 2709 vals = ar5416_phy_vals_2ghz_20mhz; 2710 } else { 2711 if (IEEE80211_IS_CHAN_HT40(c)) 2712 vals = ar5416_phy_vals_5ghz_40mhz; 2713 else 2714 vals = ar5416_phy_vals_5ghz_20mhz; 2715 } 2716 for (i = 0; i < nitems(ar5416_phy_regs); i++) 2717 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 2718 sc->phy_vals = vals; 2719 2720 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 2721 if ((error = otus_set_board_values(sc, c)) != 0) 2722 return error; 2723 2724 /* Initial Tx power settings. */ 2725 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 2726 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 2727 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 2728 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 2729 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 2730 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 2731 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 2732 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 2733 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 2734 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 2735 2736 if (IEEE80211_IS_CHAN_2GHZ(c)) 2737 otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5163); 2738 else 2739 otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5143); 2740 2741 return otus_write_barrier(sc); 2742 } 2743 2744 static __inline uint8_t 2745 otus_reverse_bits(uint8_t v) 2746 { 2747 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 2748 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 2749 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 2750 return v; 2751 } 2752 2753 int 2754 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 2755 { 2756 uint8_t chansel, d0, d1; 2757 uint16_t data; 2758 int error; 2759 2760 OTUS_LOCK_ASSERT(sc); 2761 2762 d0 = 0; 2763 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2764 chansel = (c->ic_freq - 4800) / 5; 2765 if (chansel & 1) 2766 d0 |= AR_BANK4_AMODE_REFSEL(2); 2767 else 2768 d0 |= AR_BANK4_AMODE_REFSEL(1); 2769 } else { 2770 d0 |= AR_BANK4_AMODE_REFSEL(2); 2771 if (c->ic_freq == 2484) { /* CH 14 */ 2772 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 2773 chansel = 10 + (c->ic_freq - 2274) / 5; 2774 } else 2775 chansel = 16 + (c->ic_freq - 2272) / 5; 2776 chansel <<= 2; 2777 } 2778 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 2779 d1 = otus_reverse_bits(chansel); 2780 2781 /* Write bits 0-4 of d0 and d1. */ 2782 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 2783 otus_write(sc, AR_PHY(44), data); 2784 /* Write bits 5-7 of d0 and d1. */ 2785 data = (d1 >> 5) << 5 | (d0 >> 5); 2786 otus_write(sc, AR_PHY(58), data); 2787 2788 if ((error = otus_write_barrier(sc)) == 0) 2789 otus_delay_ms(sc, 10); 2790 return error; 2791 } 2792 2793 void 2794 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 2795 { 2796 #define COEFF_SCALE_SHIFT 24 2797 uint32_t exp, man; 2798 2799 /* exponent = 14 - floor(log2(coeff)) */ 2800 for (exp = 31; exp > 0; exp--) 2801 if (coeff & (1 << exp)) 2802 break; 2803 KASSERT(exp != 0, ("exp")); 2804 exp = 14 - (exp - COEFF_SCALE_SHIFT); 2805 2806 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 2807 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 2808 2809 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 2810 *exponent = exp - 16; 2811 #undef COEFF_SCALE_SHIFT 2812 } 2813 2814 static int 2815 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 2816 { 2817 struct ieee80211com *ic = &sc->sc_ic; 2818 struct ar_cmd_frequency cmd; 2819 struct ar_rsp_frequency rsp; 2820 const uint32_t *vals; 2821 uint32_t coeff, exp, man, tmp; 2822 uint8_t code; 2823 int error, chan, i; 2824 2825 error = 0; 2826 chan = ieee80211_chan2ieee(ic, c); 2827 2828 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2829 "setting channel %d (%dMHz)\n", chan, c->ic_freq); 2830 2831 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 2832 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 2833 if ((error = otus_write_barrier(sc)) != 0) 2834 goto finish; 2835 2836 /* Disable BB Heavy Clip. */ 2837 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 2838 if ((error = otus_write_barrier(sc)) != 0) 2839 goto finish; 2840 2841 /* XXX Is that FREQ_START ? */ 2842 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL, 0); 2843 if (error != 0) 2844 goto finish; 2845 2846 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 2847 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 2848 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "band switch\n"); 2849 2850 /* Cold/Warm reset BB/ADDA. */ 2851 otus_write(sc, AR_PWR_REG_RESET, sc->bb_reset ? 0x800 : 0x400); 2852 if ((error = otus_write_barrier(sc)) != 0) 2853 goto finish; 2854 otus_write(sc, AR_PWR_REG_RESET, 0); 2855 if ((error = otus_write_barrier(sc)) != 0) 2856 goto finish; 2857 sc->bb_reset = 0; 2858 2859 if ((error = otus_program_phy(sc, c)) != 0) { 2860 device_printf(sc->sc_dev, 2861 "%s: could not program PHY\n", 2862 __func__); 2863 goto finish; 2864 } 2865 2866 /* Select RF programming based on band. */ 2867 if (IEEE80211_IS_CHAN_5GHZ(c)) 2868 vals = ar5416_banks_vals_5ghz; 2869 else 2870 vals = ar5416_banks_vals_2ghz; 2871 for (i = 0; i < nitems(ar5416_banks_regs); i++) 2872 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 2873 if ((error = otus_write_barrier(sc)) != 0) { 2874 device_printf(sc->sc_dev, 2875 "%s: could not program RF\n", 2876 __func__); 2877 goto finish; 2878 } 2879 code = AR_CMD_RF_INIT; 2880 } else { 2881 code = AR_CMD_FREQUENCY; 2882 } 2883 2884 if ((error = otus_set_rf_bank4(sc, c)) != 0) 2885 goto finish; 2886 2887 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 2888 otus_write(sc, AR_PHY_TURBO, tmp); 2889 if ((error = otus_write_barrier(sc)) != 0) 2890 goto finish; 2891 2892 /* Send firmware command to set channel. */ 2893 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2894 cmd.dynht2040 = htole32(0); 2895 cmd.htena = htole32(1); 2896 /* Set Delta Slope (exponent and mantissa). */ 2897 coeff = (100 << 24) / c->ic_freq; 2898 otus_get_delta_slope(coeff, &exp, &man); 2899 cmd.dsc_exp = htole32(exp); 2900 cmd.dsc_man = htole32(man); 2901 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2902 "ds coeff=%u exp=%u man=%u\n", coeff, exp, man); 2903 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2904 coeff = (9 * coeff) / 10; 2905 otus_get_delta_slope(coeff, &exp, &man); 2906 cmd.dsc_shgi_exp = htole32(exp); 2907 cmd.dsc_shgi_man = htole32(man); 2908 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2909 "ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man); 2910 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2911 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2912 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2913 "%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY"); 2914 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp, sizeof(rsp)); 2915 if (error != 0) 2916 goto finish; 2917 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2918 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2919 "status=0x%x\n", le32toh(rsp.status)); 2920 /* Force cold reset on next channel. */ 2921 sc->bb_reset = 1; 2922 } 2923 #ifdef USB_DEBUG 2924 if (otus_debug & OTUS_DEBUG_RESET) { 2925 device_printf(sc->sc_dev, "calibration status=0x%x\n", 2926 le32toh(rsp.status)); 2927 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2928 /* Sign-extend 9-bit NF values. */ 2929 device_printf(sc->sc_dev, 2930 "noisefloor chain %d=%d\n", i, 2931 (((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); 2932 device_printf(sc->sc_dev, 2933 "noisefloor ext chain %d=%d\n", i, 2934 ((int32_t)le32toh(rsp.nf_ext[i])) >> 23); 2935 } 2936 } 2937 #endif 2938 for (i = 0; i < OTUS_NUM_CHAINS; i++) { 2939 sc->sc_nf[i] = ((((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); 2940 } 2941 sc->sc_curchan = c; 2942 finish: 2943 return (error); 2944 } 2945 2946 #ifdef notyet 2947 int 2948 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2949 struct ieee80211_key *k) 2950 { 2951 struct otus_softc *sc = ic->ic_softc; 2952 struct otus_cmd_key cmd; 2953 2954 /* Defer setting of WEP keys until interface is brought up. */ 2955 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2956 (IFF_UP | IFF_RUNNING)) 2957 return 0; 2958 2959 /* Do it in a process context. */ 2960 cmd.key = *k; 2961 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2962 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2963 return 0; 2964 } 2965 2966 void 2967 otus_set_key_cb(struct otus_softc *sc, void *arg) 2968 { 2969 struct otus_cmd_key *cmd = arg; 2970 struct ieee80211_key *k = &cmd->key; 2971 struct ar_cmd_ekey key; 2972 uint16_t cipher; 2973 int error; 2974 2975 memset(&key, 0, sizeof key); 2976 if (k->k_flags & IEEE80211_KEY_GROUP) { 2977 key.uid = htole16(k->k_id); 2978 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2979 key.macaddr[0] |= 0x80; 2980 } else { 2981 key.uid = htole16(OTUS_UID(cmd->associd)); 2982 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2983 } 2984 key.kix = htole16(0); 2985 /* Map net80211 cipher to hardware. */ 2986 switch (k->k_cipher) { 2987 case IEEE80211_CIPHER_WEP40: 2988 cipher = AR_CIPHER_WEP64; 2989 break; 2990 case IEEE80211_CIPHER_WEP104: 2991 cipher = AR_CIPHER_WEP128; 2992 break; 2993 case IEEE80211_CIPHER_TKIP: 2994 cipher = AR_CIPHER_TKIP; 2995 break; 2996 case IEEE80211_CIPHER_CCMP: 2997 cipher = AR_CIPHER_AES; 2998 break; 2999 default: 3000 return; 3001 } 3002 key.cipher = htole16(cipher); 3003 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 3004 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); 3005 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) 3006 return; 3007 3008 /* TKIP: set Tx/Rx MIC Key. */ 3009 key.kix = htole16(1); 3010 memcpy(key.key, k->k_key + 16, 16); 3011 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); 3012 } 3013 3014 void 3015 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3016 struct ieee80211_key *k) 3017 { 3018 struct otus_softc *sc = ic->ic_softc; 3019 struct otus_cmd_key cmd; 3020 3021 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 3022 ic->ic_state != IEEE80211_S_RUN) 3023 return; /* Nothing to do. */ 3024 3025 /* Do it in a process context. */ 3026 cmd.key = *k; 3027 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 3028 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 3029 } 3030 3031 void 3032 otus_delete_key_cb(struct otus_softc *sc, void *arg) 3033 { 3034 struct otus_cmd_key *cmd = arg; 3035 struct ieee80211_key *k = &cmd->key; 3036 uint32_t uid; 3037 3038 if (k->k_flags & IEEE80211_KEY_GROUP) 3039 uid = htole32(k->k_id); 3040 else 3041 uid = htole32(OTUS_UID(cmd->associd)); 3042 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL, 0); 3043 } 3044 #endif 3045 3046 /* 3047 * XXX TODO: check if we have to be doing any calibration in the host 3048 * or whether it's purely a firmware thing. 3049 */ 3050 void 3051 otus_calibrate_to(void *arg, int pending) 3052 { 3053 #if 0 3054 struct otus_softc *sc = arg; 3055 3056 device_printf(sc->sc_dev, "%s: called\n", __func__); 3057 struct ieee80211com *ic = &sc->sc_ic; 3058 struct ieee80211_node *ni; 3059 3060 if (usbd_is_dying(sc->sc_udev)) 3061 return; 3062 3063 usbd_ref_incr(sc->sc_udev); 3064 3065 ni = ic->ic_bss; 3066 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 3067 3068 if (!usbd_is_dying(sc->sc_udev)) 3069 timeout_add_sec(&sc->calib_to, 1); 3070 3071 usbd_ref_decr(sc->sc_udev); 3072 #endif 3073 } 3074 3075 int 3076 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 3077 { 3078 3079 OTUS_LOCK_ASSERT(sc); 3080 3081 otus_write(sc, AR_MAC_REG_BSSID_L, 3082 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3083 otus_write(sc, AR_MAC_REG_BSSID_H, 3084 bssid[4] | bssid[5] << 8); 3085 return otus_write_barrier(sc); 3086 } 3087 3088 int 3089 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 3090 { 3091 OTUS_LOCK_ASSERT(sc); 3092 3093 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 3094 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3095 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 3096 addr[4] | addr[5] << 8); 3097 return otus_write_barrier(sc); 3098 } 3099 3100 /* Default single-LED. */ 3101 void 3102 otus_led_newstate_type1(struct otus_softc *sc) 3103 { 3104 /* TBD */ 3105 device_printf(sc->sc_dev, "%s: TODO\n", __func__); 3106 } 3107 3108 /* NETGEAR, dual-LED. */ 3109 void 3110 otus_led_newstate_type2(struct otus_softc *sc) 3111 { 3112 /* TBD */ 3113 device_printf(sc->sc_dev, "%s: TODO\n", __func__); 3114 } 3115 3116 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 3117 void 3118 otus_led_newstate_type3(struct otus_softc *sc) 3119 { 3120 #if 0 3121 struct ieee80211com *ic = &sc->sc_ic; 3122 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3123 3124 uint32_t state = sc->led_state; 3125 3126 OTUS_LOCK_ASSERT(sc); 3127 3128 if (!vap) { 3129 state = 0; /* led off */ 3130 } else if (vap->iv_state == IEEE80211_S_INIT) { 3131 state = 0; /* LED off. */ 3132 } else if (vap->iv_state == IEEE80211_S_RUN) { 3133 /* Associated, LED always on. */ 3134 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 3135 state = AR_LED0_ON; /* 2GHz=>Red. */ 3136 else 3137 state = AR_LED1_ON; /* 5GHz=>Blue. */ 3138 } else { 3139 /* Scanning, blink LED. */ 3140 state ^= AR_LED0_ON | AR_LED1_ON; 3141 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 3142 state &= ~AR_LED1_ON; 3143 else 3144 state &= ~AR_LED0_ON; 3145 } 3146 if (state != sc->led_state) { 3147 otus_write(sc, AR_GPIO_REG_PORT_DATA, state); 3148 if (otus_write_barrier(sc) == 0) 3149 sc->led_state = state; 3150 } 3151 #endif 3152 } 3153 3154 static uint8_t zero_macaddr[IEEE80211_ADDR_LEN] = { 0,0,0,0,0,0 }; 3155 3156 /* 3157 * Set up operating mode, MAC/BSS address and RX filter. 3158 */ 3159 static void 3160 otus_set_operating_mode(struct otus_softc *sc) 3161 { 3162 struct ieee80211com *ic = &sc->sc_ic; 3163 struct ieee80211vap *vap; 3164 uint32_t cam_mode = AR_MAC_CAM_DEFAULTS; 3165 uint32_t rx_ctrl = AR_MAC_RX_CTRL_DEAGG | AR_MAC_RX_CTRL_SHORT_FILTER; 3166 uint32_t sniffer = AR_MAC_SNIFFER_DEFAULTS; 3167 uint32_t enc_mode = 0x78; /* XXX */ 3168 const uint8_t *macaddr; 3169 uint8_t bssid[IEEE80211_ADDR_LEN]; 3170 struct ieee80211_node *ni; 3171 3172 OTUS_LOCK_ASSERT(sc); 3173 3174 /* 3175 * If we're in sniffer mode or we don't have a MAC 3176 * address assigned, ensure it gets reset to all-zero. 3177 */ 3178 IEEE80211_ADDR_COPY(bssid, zero_macaddr); 3179 vap = TAILQ_FIRST(&ic->ic_vaps); 3180 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 3181 3182 switch (ic->ic_opmode) { 3183 case IEEE80211_M_STA: 3184 if (vap) { 3185 ni = ieee80211_ref_node(vap->iv_bss); 3186 IEEE80211_ADDR_COPY(bssid, ni->ni_bssid); 3187 ieee80211_free_node(ni); 3188 } 3189 cam_mode |= AR_MAC_CAM_STA; 3190 rx_ctrl |= AR_MAC_RX_CTRL_PASS_TO_HOST; 3191 break; 3192 case IEEE80211_M_MONITOR: 3193 /* 3194 * Note: monitor mode ends up causing the MAC to 3195 * generate ACK frames for everything it sees. 3196 * So don't do that; instead just put it in STA mode 3197 * and disable RX filters. 3198 */ 3199 default: 3200 cam_mode |= AR_MAC_CAM_STA; 3201 rx_ctrl |= AR_MAC_RX_CTRL_PASS_TO_HOST; 3202 break; 3203 } 3204 3205 /* 3206 * TODO: if/when we do hardware encryption, ensure it's 3207 * disabled if the NIC is in monitor mode. 3208 */ 3209 otus_write(sc, AR_MAC_REG_SNIFFER, sniffer); 3210 otus_write(sc, AR_MAC_REG_CAM_MODE, cam_mode); 3211 otus_write(sc, AR_MAC_REG_ENCRYPTION, enc_mode); 3212 otus_write(sc, AR_MAC_REG_RX_CONTROL, rx_ctrl); 3213 otus_set_macaddr(sc, macaddr); 3214 otus_set_bssid(sc, bssid); 3215 /* XXX barrier? */ 3216 } 3217 3218 static void 3219 otus_set_rx_filter(struct otus_softc *sc) 3220 { 3221 // struct ieee80211com *ic = &sc->sc_ic; 3222 3223 OTUS_LOCK_ASSERT(sc); 3224 3225 #if 0 3226 if (ic->ic_allmulti > 0 || ic->ic_promisc > 0 || 3227 ic->ic_opmode == IEEE80211_M_MONITOR) { 3228 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0xff00ffff); 3229 } else { 3230 #endif 3231 /* Filter any control frames, BAR is bit 24. */ 3232 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0x0500ffff); 3233 #if 0 3234 } 3235 #endif 3236 } 3237 3238 int 3239 otus_init(struct otus_softc *sc) 3240 { 3241 struct ieee80211com *ic = &sc->sc_ic; 3242 int error; 3243 3244 OTUS_UNLOCK_ASSERT(sc); 3245 3246 OTUS_LOCK(sc); 3247 3248 /* Drain any pending TX frames */ 3249 otus_drain_mbufq(sc); 3250 3251 /* Init MAC */ 3252 if ((error = otus_init_mac(sc)) != 0) { 3253 OTUS_UNLOCK(sc); 3254 device_printf(sc->sc_dev, 3255 "%s: could not initialize MAC\n", __func__); 3256 return error; 3257 } 3258 3259 otus_set_operating_mode(sc); 3260 otus_set_rx_filter(sc); 3261 (void) otus_set_operating_mode(sc); 3262 3263 sc->bb_reset = 1; /* Force cold reset. */ 3264 3265 if ((error = otus_set_chan(sc, ic->ic_curchan, 0)) != 0) { 3266 OTUS_UNLOCK(sc); 3267 device_printf(sc->sc_dev, 3268 "%s: could not set channel\n", __func__); 3269 return error; 3270 } 3271 3272 /* Start Rx. */ 3273 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0x100); 3274 (void)otus_write_barrier(sc); 3275 3276 sc->sc_running = 1; 3277 3278 OTUS_UNLOCK(sc); 3279 return 0; 3280 } 3281 3282 void 3283 otus_stop(struct otus_softc *sc) 3284 { 3285 #if 0 3286 int s; 3287 #endif 3288 3289 OTUS_UNLOCK_ASSERT(sc); 3290 3291 OTUS_LOCK(sc); 3292 sc->sc_running = 0; 3293 sc->sc_tx_timer = 0; 3294 OTUS_UNLOCK(sc); 3295 3296 taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); 3297 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); 3298 taskqueue_drain(taskqueue_thread, &sc->tx_task); 3299 3300 OTUS_LOCK(sc); 3301 sc->sc_running = 0; 3302 /* Stop Rx. */ 3303 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0); 3304 (void)otus_write_barrier(sc); 3305 3306 /* Drain any pending TX frames */ 3307 otus_drain_mbufq(sc); 3308 3309 OTUS_UNLOCK(sc); 3310 } 3311