1 /* $OpenBSD: if_otus.c,v 1.49 2015/11/24 13:33:18 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros AR9001U chipset. 22 */ 23 24 #include <sys/cdefs.h> 25 #include "opt_wlan.h" 26 27 #include <sys/param.h> 28 #include <sys/endian.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/malloc.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/conf.h> 36 #include <sys/bus.h> 37 #include <sys/rman.h> 38 #include <sys/firmware.h> 39 #include <sys/module.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/if_ether.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_regdomain.h> 60 #include <net80211/ieee80211_radiotap.h> 61 #include <net80211/ieee80211_ratectl.h> 62 #ifdef IEEE80211_SUPPORT_SUPERG 63 #include <net80211/ieee80211_superg.h> 64 #endif 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include "usbdevs.h" 69 70 #define USB_DEBUG_VAR otus_debug 71 #include <dev/usb/usb_debug.h> 72 73 #include "if_otusreg.h" 74 75 static int otus_debug = 0; 76 static SYSCTL_NODE(_hw_usb, OID_AUTO, otus, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 77 "USB otus"); 78 SYSCTL_INT(_hw_usb_otus, OID_AUTO, debug, CTLFLAG_RWTUN, &otus_debug, 0, 79 "Debug level"); 80 #define OTUS_DEBUG_XMIT 0x00000001 81 #define OTUS_DEBUG_RECV 0x00000002 82 #define OTUS_DEBUG_TXDONE 0x00000004 83 #define OTUS_DEBUG_RXDONE 0x00000008 84 #define OTUS_DEBUG_CMD 0x00000010 85 #define OTUS_DEBUG_CMDDONE 0x00000020 86 #define OTUS_DEBUG_RESET 0x00000040 87 #define OTUS_DEBUG_STATE 0x00000080 88 #define OTUS_DEBUG_CMDNOTIFY 0x00000100 89 #define OTUS_DEBUG_REGIO 0x00000200 90 #define OTUS_DEBUG_IRQ 0x00000400 91 #define OTUS_DEBUG_TXCOMP 0x00000800 92 #define OTUS_DEBUG_RX_BUFFER 0x00001000 93 #define OTUS_DEBUG_ANY 0xffffffff 94 95 #define OTUS_DPRINTF(sc, dm, ...) \ 96 do { \ 97 if ((dm == OTUS_DEBUG_ANY) || (dm & otus_debug)) \ 98 device_printf(sc->sc_dev, __VA_ARGS__); \ 99 } while (0) 100 #define OTUS_DEV(v, p) { USB_VPI(v, p, 0) } 101 static const STRUCT_USB_HOST_ID otus_devs[] = { 102 OTUS_DEV(USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512), 103 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275), 104 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N), 105 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170), 106 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612), 107 OTUS_DEV(USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2), 108 OTUS_DEV(USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN), 109 OTUS_DEV(USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX), 110 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1), 111 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1), 112 OTUS_DEV(USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2), 113 OTUS_DEV(USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2), 114 OTUS_DEV(USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG), 115 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2), 116 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000), 117 OTUS_DEV(USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100), 118 OTUS_DEV(USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300), 119 OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494), 120 OTUS_DEV(USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600), 121 OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81), 122 OTUS_DEV(USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82), 123 OTUS_DEV(USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221), 124 OTUS_DEV(USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N), 125 }; 126 127 static device_probe_t otus_match; 128 static device_attach_t otus_attach; 129 static device_detach_t otus_detach; 130 131 static int otus_attachhook(struct otus_softc *); 132 static void otus_getradiocaps(struct ieee80211com *, int, int *, 133 struct ieee80211_channel[]); 134 int otus_load_firmware(struct otus_softc *, const char *, 135 uint32_t); 136 int otus_open_pipes(struct otus_softc *); 137 void otus_close_pipes(struct otus_softc *); 138 139 static int otus_alloc_tx_cmd_list(struct otus_softc *); 140 static void otus_free_tx_cmd_list(struct otus_softc *); 141 142 static int otus_alloc_rx_list(struct otus_softc *); 143 static void otus_free_rx_list(struct otus_softc *); 144 static int otus_alloc_tx_list(struct otus_softc *); 145 static void otus_free_tx_list(struct otus_softc *); 146 static void otus_free_list(struct otus_softc *, struct otus_data [], int); 147 static struct otus_data *_otus_getbuf(struct otus_softc *); 148 static struct otus_data *otus_getbuf(struct otus_softc *); 149 static void otus_freebuf(struct otus_softc *, struct otus_data *); 150 151 static struct otus_tx_cmd *_otus_get_txcmd(struct otus_softc *); 152 static struct otus_tx_cmd *otus_get_txcmd(struct otus_softc *); 153 static void otus_free_txcmd(struct otus_softc *, struct otus_tx_cmd *); 154 155 void otus_next_scan(void *, int); 156 static void otus_tx_task(void *, int pending); 157 void otus_do_async(struct otus_softc *, 158 void (*)(struct otus_softc *, void *), void *, int); 159 int otus_newstate(struct ieee80211vap *, enum ieee80211_state, 160 int); 161 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 162 void *, int); 163 void otus_write(struct otus_softc *, uint32_t, uint32_t); 164 int otus_write_barrier(struct otus_softc *); 165 static struct ieee80211_node *otus_node_alloc(struct ieee80211vap *vap, 166 const uint8_t mac[IEEE80211_ADDR_LEN]); 167 int otus_read_eeprom(struct otus_softc *); 168 void otus_newassoc(struct ieee80211_node *, int); 169 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 170 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int, 171 struct mbufq *); 172 static int otus_tx(struct otus_softc *, struct ieee80211_node *, 173 struct mbuf *, struct otus_data *, 174 const struct ieee80211_bpf_params *); 175 int otus_ioctl(if_t, u_long, caddr_t); 176 int otus_set_multi(struct otus_softc *); 177 static int otus_updateedca(struct ieee80211com *); 178 static void otus_updateedca_locked(struct otus_softc *); 179 static void otus_updateslot(struct otus_softc *); 180 static void otus_set_operating_mode(struct otus_softc *sc); 181 static void otus_set_rx_filter(struct otus_softc *sc); 182 int otus_init_mac(struct otus_softc *); 183 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 184 int otus_set_board_values(struct otus_softc *, 185 struct ieee80211_channel *); 186 int otus_program_phy(struct otus_softc *, 187 struct ieee80211_channel *); 188 int otus_set_rf_bank4(struct otus_softc *, 189 struct ieee80211_channel *); 190 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 191 static int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 192 int); 193 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 194 struct ieee80211_key *); 195 void otus_set_key_cb(struct otus_softc *, void *); 196 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 197 struct ieee80211_key *); 198 void otus_delete_key_cb(struct otus_softc *, void *); 199 void otus_calibrate_to(void *, int); 200 int otus_set_bssid(struct otus_softc *, const uint8_t *); 201 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 202 void otus_led_newstate_type1(struct otus_softc *); 203 void otus_led_newstate_type2(struct otus_softc *); 204 void otus_led_newstate_type3(struct otus_softc *); 205 int otus_init(struct otus_softc *sc); 206 void otus_stop(struct otus_softc *sc); 207 208 static device_method_t otus_methods[] = { 209 DEVMETHOD(device_probe, otus_match), 210 DEVMETHOD(device_attach, otus_attach), 211 DEVMETHOD(device_detach, otus_detach), 212 213 DEVMETHOD_END 214 }; 215 216 static driver_t otus_driver = { 217 .name = "otus", 218 .methods = otus_methods, 219 .size = sizeof(struct otus_softc) 220 }; 221 222 DRIVER_MODULE(otus, uhub, otus_driver, NULL, NULL); 223 MODULE_DEPEND(otus, wlan, 1, 1, 1); 224 MODULE_DEPEND(otus, usb, 1, 1, 1); 225 MODULE_DEPEND(otus, firmware, 1, 1, 1); 226 MODULE_VERSION(otus, 1); 227 228 static usb_callback_t otus_bulk_tx_callback; 229 static usb_callback_t otus_bulk_rx_callback; 230 static usb_callback_t otus_bulk_irq_callback; 231 static usb_callback_t otus_bulk_cmd_callback; 232 233 static const struct usb_config otus_config[OTUS_N_XFER] = { 234 [OTUS_BULK_TX] = { 235 .type = UE_BULK, 236 .endpoint = UE_ADDR_ANY, 237 .direction = UE_DIR_OUT, 238 .bufsize = 0x200, 239 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 240 .callback = otus_bulk_tx_callback, 241 .timeout = 5000, /* ms */ 242 }, 243 [OTUS_BULK_RX] = { 244 .type = UE_BULK, 245 .endpoint = UE_ADDR_ANY, 246 .direction = UE_DIR_IN, 247 .bufsize = OTUS_RXBUFSZ, 248 .flags = { .ext_buffer = 1, .pipe_bof = 1,.short_xfer_ok = 1,}, 249 .callback = otus_bulk_rx_callback, 250 }, 251 [OTUS_BULK_IRQ] = { 252 .type = UE_INTERRUPT, 253 .endpoint = UE_ADDR_ANY, 254 .direction = UE_DIR_IN, 255 .bufsize = OTUS_MAX_CTRLSZ, 256 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 257 .callback = otus_bulk_irq_callback, 258 }, 259 [OTUS_BULK_CMD] = { 260 .type = UE_INTERRUPT, 261 .endpoint = UE_ADDR_ANY, 262 .direction = UE_DIR_OUT, 263 .bufsize = OTUS_MAX_CTRLSZ, 264 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 265 .callback = otus_bulk_cmd_callback, 266 .timeout = 5000, /* ms */ 267 }, 268 }; 269 270 static int 271 otus_match(device_t self) 272 { 273 struct usb_attach_arg *uaa = device_get_ivars(self); 274 275 if (uaa->usb_mode != USB_MODE_HOST || 276 uaa->info.bIfaceIndex != 0 || 277 uaa->info.bConfigIndex != 0) 278 return (ENXIO); 279 280 return (usbd_lookup_id_by_uaa(otus_devs, sizeof(otus_devs), uaa)); 281 } 282 283 static int 284 otus_attach(device_t self) 285 { 286 struct usb_attach_arg *uaa = device_get_ivars(self); 287 struct otus_softc *sc = device_get_softc(self); 288 int error; 289 uint8_t iface_index; 290 291 device_set_usb_desc(self); 292 sc->sc_udev = uaa->device; 293 sc->sc_dev = self; 294 295 mtx_init(&sc->sc_mtx, device_get_nameunit(self), MTX_NETWORK_LOCK, 296 MTX_DEF); 297 298 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->scan_to, 0, otus_next_scan, sc); 299 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->calib_to, 0, otus_calibrate_to, sc); 300 TASK_INIT(&sc->tx_task, 0, otus_tx_task, sc); 301 mbufq_init(&sc->sc_snd, ifqmaxlen); 302 303 iface_index = 0; 304 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 305 otus_config, OTUS_N_XFER, sc, &sc->sc_mtx); 306 if (error) { 307 device_printf(sc->sc_dev, 308 "could not allocate USB transfers, err=%s\n", 309 usbd_errstr(error)); 310 goto fail_usb; 311 } 312 313 if ((error = otus_open_pipes(sc)) != 0) { 314 device_printf(sc->sc_dev, "%s: could not open pipes\n", 315 __func__); 316 goto fail; 317 } 318 319 /* XXX check return status; fail out if appropriate */ 320 if (otus_attachhook(sc) != 0) 321 goto fail; 322 323 return (0); 324 325 fail: 326 otus_close_pipes(sc); 327 fail_usb: 328 mtx_destroy(&sc->sc_mtx); 329 return (ENXIO); 330 } 331 332 static int 333 otus_detach(device_t self) 334 { 335 struct otus_softc *sc = device_get_softc(self); 336 struct ieee80211com *ic = &sc->sc_ic; 337 338 otus_stop(sc); 339 340 usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); 341 342 taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); 343 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); 344 taskqueue_drain(taskqueue_thread, &sc->tx_task); 345 346 otus_close_pipes(sc); 347 #if 0 348 /* Wait for all queued asynchronous commands to complete. */ 349 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 350 351 usbd_ref_wait(sc->sc_udev); 352 #endif 353 354 ieee80211_ifdetach(ic); 355 mtx_destroy(&sc->sc_mtx); 356 return 0; 357 } 358 359 static void 360 otus_delay_ms(struct otus_softc *sc, int ms) 361 { 362 363 DELAY(1000 * ms); 364 } 365 366 static struct ieee80211vap * 367 otus_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 368 enum ieee80211_opmode opmode, int flags, 369 const uint8_t bssid[IEEE80211_ADDR_LEN], 370 const uint8_t mac[IEEE80211_ADDR_LEN]) 371 { 372 struct otus_vap *uvp; 373 struct ieee80211vap *vap; 374 375 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 376 return (NULL); 377 378 uvp = malloc(sizeof(struct otus_vap), M_80211_VAP, M_WAITOK | M_ZERO); 379 vap = &uvp->vap; 380 381 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 382 flags, bssid) != 0) { 383 /* out of memory */ 384 free(uvp, M_80211_VAP); 385 return (NULL); 386 } 387 388 /* override state transition machine */ 389 uvp->newstate = vap->iv_newstate; 390 vap->iv_newstate = otus_newstate; 391 392 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 393 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 394 395 ieee80211_ratectl_init(vap); 396 397 /* complete setup */ 398 ieee80211_vap_attach(vap, ieee80211_media_change, 399 ieee80211_media_status, mac); 400 ic->ic_opmode = opmode; 401 402 return (vap); 403 } 404 405 static void 406 otus_vap_delete(struct ieee80211vap *vap) 407 { 408 struct otus_vap *uvp = OTUS_VAP(vap); 409 410 ieee80211_ratectl_deinit(vap); 411 ieee80211_vap_detach(vap); 412 free(uvp, M_80211_VAP); 413 } 414 415 static void 416 otus_parent(struct ieee80211com *ic) 417 { 418 struct otus_softc *sc = ic->ic_softc; 419 int startall = 0; 420 421 if (ic->ic_nrunning > 0) { 422 if (!sc->sc_running) { 423 otus_init(sc); 424 startall = 1; 425 } else { 426 (void) otus_set_multi(sc); 427 } 428 } else if (sc->sc_running) 429 otus_stop(sc); 430 431 if (startall) 432 ieee80211_start_all(ic); 433 } 434 435 static void 436 otus_drain_mbufq(struct otus_softc *sc) 437 { 438 struct mbuf *m; 439 struct ieee80211_node *ni; 440 441 OTUS_LOCK_ASSERT(sc); 442 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 443 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 444 m->m_pkthdr.rcvif = NULL; 445 ieee80211_free_node(ni); 446 m_freem(m); 447 } 448 } 449 450 static void 451 otus_tx_start(struct otus_softc *sc) 452 { 453 454 taskqueue_enqueue(taskqueue_thread, &sc->tx_task); 455 } 456 457 static int 458 otus_transmit(struct ieee80211com *ic, struct mbuf *m) 459 { 460 struct otus_softc *sc = ic->ic_softc; 461 int error; 462 463 OTUS_LOCK(sc); 464 if (! sc->sc_running) { 465 OTUS_UNLOCK(sc); 466 return (ENXIO); 467 } 468 469 /* XXX TODO: handle fragments */ 470 error = mbufq_enqueue(&sc->sc_snd, m); 471 if (error) { 472 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 473 "%s: mbufq_enqueue failed: %d\n", 474 __func__, 475 error); 476 OTUS_UNLOCK(sc); 477 return (error); 478 } 479 OTUS_UNLOCK(sc); 480 481 /* Kick TX */ 482 otus_tx_start(sc); 483 484 return (0); 485 } 486 487 static void 488 _otus_start(struct otus_softc *sc) 489 { 490 struct ieee80211_node *ni; 491 struct otus_data *bf; 492 struct mbuf *m; 493 494 OTUS_LOCK_ASSERT(sc); 495 496 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 497 bf = otus_getbuf(sc); 498 if (bf == NULL) { 499 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 500 "%s: failed to get buffer\n", __func__); 501 mbufq_prepend(&sc->sc_snd, m); 502 break; 503 } 504 505 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 506 m->m_pkthdr.rcvif = NULL; 507 508 if (otus_tx(sc, ni, m, bf, NULL) != 0) { 509 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 510 "%s: failed to transmit\n", __func__); 511 if_inc_counter(ni->ni_vap->iv_ifp, 512 IFCOUNTER_OERRORS, 1); 513 otus_freebuf(sc, bf); 514 ieee80211_free_node(ni); 515 m_freem(m); 516 break; 517 } 518 } 519 } 520 521 static void 522 otus_tx_task(void *arg, int pending) 523 { 524 struct otus_softc *sc = arg; 525 526 OTUS_LOCK(sc); 527 _otus_start(sc); 528 OTUS_UNLOCK(sc); 529 } 530 531 static int 532 otus_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 533 const struct ieee80211_bpf_params *params) 534 { 535 struct ieee80211com *ic= ni->ni_ic; 536 struct otus_softc *sc = ic->ic_softc; 537 struct otus_data *bf = NULL; 538 int error = 0; 539 540 /* Don't transmit if we're not running */ 541 OTUS_LOCK(sc); 542 if (! sc->sc_running) { 543 error = ENETDOWN; 544 goto error; 545 } 546 547 bf = otus_getbuf(sc); 548 if (bf == NULL) { 549 error = ENOBUFS; 550 goto error; 551 } 552 553 if (otus_tx(sc, ni, m, bf, params) != 0) { 554 error = EIO; 555 goto error; 556 } 557 558 OTUS_UNLOCK(sc); 559 return (0); 560 error: 561 if (bf) 562 otus_freebuf(sc, bf); 563 OTUS_UNLOCK(sc); 564 m_freem(m); 565 return (error); 566 } 567 568 static void 569 otus_update_chw(struct ieee80211com *ic) 570 { 571 572 printf("%s: TODO\n", __func__); 573 } 574 575 static void 576 otus_set_channel(struct ieee80211com *ic) 577 { 578 struct otus_softc *sc = ic->ic_softc; 579 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "%s: set channel: %d\n", 580 __func__, 581 ic->ic_curchan->ic_freq); 582 583 OTUS_LOCK(sc); 584 (void) otus_set_chan(sc, ic->ic_curchan, 0); 585 OTUS_UNLOCK(sc); 586 } 587 588 static int 589 otus_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 590 { 591 592 /* For now, no A-MPDU TX support in the driver */ 593 return (0); 594 } 595 596 static void 597 otus_scan_start(struct ieee80211com *ic) 598 { 599 600 // printf("%s: TODO\n", __func__); 601 } 602 603 static void 604 otus_scan_end(struct ieee80211com *ic) 605 { 606 607 // printf("%s: TODO\n", __func__); 608 } 609 610 static void 611 otus_update_mcast(struct ieee80211com *ic) 612 { 613 struct otus_softc *sc = ic->ic_softc; 614 615 (void) otus_set_multi(sc); 616 } 617 618 static int 619 otus_attachhook(struct otus_softc *sc) 620 { 621 struct ieee80211com *ic = &sc->sc_ic; 622 usb_device_request_t req; 623 uint32_t in, out; 624 int error; 625 626 /* Not locked */ 627 error = otus_load_firmware(sc, "otusfw_init", AR_FW_INIT_ADDR); 628 if (error != 0) { 629 device_printf(sc->sc_dev, "%s: could not load %s firmware\n", 630 __func__, "init"); 631 return (ENXIO); 632 } 633 634 /* XXX not locked? */ 635 otus_delay_ms(sc, 1000); 636 637 /* Not locked */ 638 error = otus_load_firmware(sc, "otusfw_main", AR_FW_MAIN_ADDR); 639 if (error != 0) { 640 device_printf(sc->sc_dev, "%s: could not load %s firmware\n", 641 __func__, "main"); 642 return (ENXIO); 643 } 644 645 OTUS_LOCK(sc); 646 647 /* Tell device that firmware transfer is complete. */ 648 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 649 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 650 USETW(req.wValue, 0); 651 USETW(req.wIndex, 0); 652 USETW(req.wLength, 0); 653 if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, NULL, 654 0, NULL, 250) != 0) { 655 OTUS_UNLOCK(sc); 656 device_printf(sc->sc_dev, 657 "%s: firmware initialization failed\n", 658 __func__); 659 return (ENXIO); 660 } 661 662 /* Send an ECHO command to check that everything is settled. */ 663 in = 0xbadc0ffe; 664 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out, sizeof(out)) != 0) { 665 OTUS_UNLOCK(sc); 666 device_printf(sc->sc_dev, 667 "%s: echo command failed\n", __func__); 668 return (ENXIO); 669 } 670 if (in != out) { 671 OTUS_UNLOCK(sc); 672 device_printf(sc->sc_dev, 673 "%s: echo reply mismatch: 0x%08x!=0x%08x\n", 674 __func__, in, out); 675 return (ENXIO); 676 } 677 678 /* Read entire EEPROM. */ 679 if (otus_read_eeprom(sc) != 0) { 680 OTUS_UNLOCK(sc); 681 device_printf(sc->sc_dev, 682 "%s: could not read EEPROM\n", 683 __func__); 684 return (ENXIO); 685 } 686 687 OTUS_UNLOCK(sc); 688 689 sc->txmask = sc->eeprom.baseEepHeader.txMask; 690 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 691 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 692 IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->eeprom.baseEepHeader.macAddr); 693 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 694 695 if (sc->txmask == 0x5) 696 ic->ic_txstream = 2; 697 else 698 ic->ic_txstream = 1; 699 700 if (sc->rxmask == 0x5) 701 ic->ic_rxstream = 2; 702 else 703 ic->ic_rxstream = 1; 704 705 device_printf(sc->sc_dev, 706 "MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 707 (sc->capflags & AR5416_OPFLAGS_11A) ? 708 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 709 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 710 ether_sprintf(ic->ic_macaddr)); 711 712 ic->ic_softc = sc; 713 ic->ic_name = device_get_nameunit(sc->sc_dev); 714 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 715 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 716 717 /* Set device capabilities. */ 718 ic->ic_caps = 719 IEEE80211_C_STA | /* station mode */ 720 #if 0 721 IEEE80211_C_BGSCAN | /* Background scan. */ 722 #endif 723 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 724 IEEE80211_C_WME | /* WME/QoS */ 725 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 726 IEEE80211_C_FF | /* Atheros fast-frames supported. */ 727 IEEE80211_C_MONITOR | /* Enable monitor mode */ 728 IEEE80211_C_SWAMSDUTX | /* Do software A-MSDU TX */ 729 IEEE80211_C_WPA; /* WPA/RSN. */ 730 731 /* 732 * Although A-MPDU RX is fine, A-MPDU TX apparently has some 733 * hardware bugs. Looking at Linux carl9170, it has a work-around 734 * that forces all frames into the AC_BE queue regardless of 735 * the actual QoS queue. 736 */ 737 ic->ic_htcaps = 738 IEEE80211_HTC_HT | 739 #if 0 740 IEEE80211_HTC_AMPDU | 741 #endif 742 IEEE80211_HTC_AMSDU | 743 IEEE80211_HTCAP_MAXAMSDU_3839 | 744 IEEE80211_HTCAP_SMPS_OFF; 745 746 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD; 747 748 otus_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 749 ic->ic_channels); 750 751 ieee80211_ifattach(ic); 752 ic->ic_raw_xmit = otus_raw_xmit; 753 ic->ic_scan_start = otus_scan_start; 754 ic->ic_scan_end = otus_scan_end; 755 ic->ic_set_channel = otus_set_channel; 756 ic->ic_getradiocaps = otus_getradiocaps; 757 ic->ic_vap_create = otus_vap_create; 758 ic->ic_vap_delete = otus_vap_delete; 759 ic->ic_update_mcast = otus_update_mcast; 760 ic->ic_update_promisc = otus_update_mcast; 761 ic->ic_parent = otus_parent; 762 ic->ic_transmit = otus_transmit; 763 ic->ic_update_chw = otus_update_chw; 764 ic->ic_ampdu_enable = otus_ampdu_enable; 765 ic->ic_wme.wme_update = otus_updateedca; 766 ic->ic_newassoc = otus_newassoc; 767 ic->ic_node_alloc = otus_node_alloc; 768 769 #ifdef notyet 770 ic->ic_set_key = otus_set_key; 771 ic->ic_delete_key = otus_delete_key; 772 #endif 773 774 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 775 sizeof(sc->sc_txtap), OTUS_TX_RADIOTAP_PRESENT, 776 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 777 OTUS_RX_RADIOTAP_PRESENT); 778 779 return (0); 780 } 781 782 static void 783 otus_getradiocaps(struct ieee80211com *ic, 784 int maxchans, int *nchans, struct ieee80211_channel chans[]) 785 { 786 struct otus_softc *sc = ic->ic_softc; 787 uint8_t bands[IEEE80211_MODE_BYTES]; 788 789 /* Set supported .11b and .11g rates. */ 790 memset(bands, 0, sizeof(bands)); 791 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 792 setbit(bands, IEEE80211_MODE_11B); 793 setbit(bands, IEEE80211_MODE_11G); 794 setbit(bands, IEEE80211_MODE_11NG); 795 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 796 ar_chans, 14, bands, 0); 797 } 798 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 799 setbit(bands, IEEE80211_MODE_11A); 800 setbit(bands, IEEE80211_MODE_11NA); 801 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 802 &ar_chans[14], nitems(ar_chans) - 14, bands, 0); 803 } 804 } 805 806 int 807 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 808 { 809 usb_device_request_t req; 810 char *ptr; 811 const struct firmware *fw; 812 int mlen, error, size; 813 814 error = 0; 815 816 /* Read firmware image from the filesystem. */ 817 if ((fw = firmware_get(name)) == NULL) { 818 device_printf(sc->sc_dev, 819 "%s: failed loadfirmware of file %s\n", __func__, name); 820 return (ENXIO); 821 } 822 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 823 req.bRequest = AR_FW_DOWNLOAD; 824 USETW(req.wIndex, 0); 825 826 OTUS_LOCK(sc); 827 828 /* XXX const */ 829 ptr = __DECONST(char *, fw->data); 830 size = fw->datasize; 831 addr >>= 8; 832 while (size > 0) { 833 mlen = MIN(size, 4096); 834 835 USETW(req.wValue, addr); 836 USETW(req.wLength, mlen); 837 if (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 838 &req, ptr, 0, NULL, 250) != 0) { 839 error = EIO; 840 break; 841 } 842 addr += mlen >> 8; 843 ptr += mlen; 844 size -= mlen; 845 } 846 847 OTUS_UNLOCK(sc); 848 849 firmware_put(fw, FIRMWARE_UNLOAD); 850 if (error != 0) 851 device_printf(sc->sc_dev, 852 "%s: %s: error=%d\n", __func__, name, error); 853 return error; 854 } 855 856 int 857 otus_open_pipes(struct otus_softc *sc) 858 { 859 #if 0 860 int isize, error; 861 int i; 862 #endif 863 int error; 864 865 OTUS_UNLOCK_ASSERT(sc); 866 867 if ((error = otus_alloc_tx_cmd_list(sc)) != 0) { 868 device_printf(sc->sc_dev, 869 "%s: could not allocate command xfer\n", 870 __func__); 871 goto fail; 872 } 873 874 if ((error = otus_alloc_tx_list(sc)) != 0) { 875 device_printf(sc->sc_dev, "%s: could not allocate Tx xfers\n", 876 __func__); 877 goto fail; 878 } 879 880 if ((error = otus_alloc_rx_list(sc)) != 0) { 881 device_printf(sc->sc_dev, "%s: could not allocate Rx xfers\n", 882 __func__); 883 goto fail; 884 } 885 886 /* Enable RX transfers; needed for initial firmware messages */ 887 OTUS_LOCK(sc); 888 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_RX]); 889 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_IRQ]); 890 OTUS_UNLOCK(sc); 891 return 0; 892 893 fail: otus_close_pipes(sc); 894 return error; 895 } 896 897 void 898 otus_close_pipes(struct otus_softc *sc) 899 { 900 901 OTUS_LOCK(sc); 902 otus_free_tx_cmd_list(sc); 903 otus_free_tx_list(sc); 904 otus_free_rx_list(sc); 905 OTUS_UNLOCK(sc); 906 907 usbd_transfer_unsetup(sc->sc_xfer, OTUS_N_XFER); 908 } 909 910 static void 911 otus_free_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], int ndata) 912 { 913 int i; 914 915 /* XXX TODO: someone has to have waken up waiters! */ 916 for (i = 0; i < ndata; i++) { 917 struct otus_tx_cmd *dp = &cmd[i]; 918 919 if (dp->buf != NULL) { 920 free(dp->buf, M_USBDEV); 921 dp->buf = NULL; 922 } 923 } 924 } 925 926 static int 927 otus_alloc_cmd_list(struct otus_softc *sc, struct otus_tx_cmd cmd[], 928 int ndata, int maxsz) 929 { 930 int i, error; 931 932 for (i = 0; i < ndata; i++) { 933 struct otus_tx_cmd *dp = &cmd[i]; 934 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT | M_ZERO); 935 dp->odata = NULL; 936 if (dp->buf == NULL) { 937 device_printf(sc->sc_dev, 938 "could not allocate buffer\n"); 939 error = ENOMEM; 940 goto fail; 941 } 942 } 943 944 return (0); 945 fail: 946 otus_free_cmd_list(sc, cmd, ndata); 947 return (error); 948 } 949 950 static int 951 otus_alloc_tx_cmd_list(struct otus_softc *sc) 952 { 953 int error, i; 954 955 error = otus_alloc_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT, 956 OTUS_MAX_TXCMDSZ); 957 if (error != 0) 958 return (error); 959 960 STAILQ_INIT(&sc->sc_cmd_active); 961 STAILQ_INIT(&sc->sc_cmd_inactive); 962 STAILQ_INIT(&sc->sc_cmd_pending); 963 STAILQ_INIT(&sc->sc_cmd_waiting); 964 965 for (i = 0; i < OTUS_CMD_LIST_COUNT; i++) 966 STAILQ_INSERT_HEAD(&sc->sc_cmd_inactive, &sc->sc_cmd[i], 967 next_cmd); 968 969 return (0); 970 } 971 972 static void 973 otus_free_tx_cmd_list(struct otus_softc *sc) 974 { 975 976 /* 977 * XXX TODO: something needs to wake up any pending/sleeping 978 * waiters! 979 */ 980 STAILQ_INIT(&sc->sc_cmd_active); 981 STAILQ_INIT(&sc->sc_cmd_inactive); 982 STAILQ_INIT(&sc->sc_cmd_pending); 983 STAILQ_INIT(&sc->sc_cmd_waiting); 984 985 otus_free_cmd_list(sc, sc->sc_cmd, OTUS_CMD_LIST_COUNT); 986 } 987 988 static int 989 otus_alloc_list(struct otus_softc *sc, struct otus_data data[], 990 int ndata, int maxsz) 991 { 992 int i, error; 993 994 for (i = 0; i < ndata; i++) { 995 struct otus_data *dp = &data[i]; 996 dp->sc = sc; 997 dp->m = NULL; 998 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT | M_ZERO); 999 if (dp->buf == NULL) { 1000 device_printf(sc->sc_dev, 1001 "could not allocate buffer\n"); 1002 error = ENOMEM; 1003 goto fail; 1004 } 1005 dp->ni = NULL; 1006 } 1007 1008 return (0); 1009 fail: 1010 otus_free_list(sc, data, ndata); 1011 return (error); 1012 } 1013 1014 static int 1015 otus_alloc_rx_list(struct otus_softc *sc) 1016 { 1017 int error, i; 1018 1019 error = otus_alloc_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT, 1020 OTUS_RXBUFSZ); 1021 if (error != 0) 1022 return (error); 1023 1024 STAILQ_INIT(&sc->sc_rx_active); 1025 STAILQ_INIT(&sc->sc_rx_inactive); 1026 1027 for (i = 0; i < OTUS_RX_LIST_COUNT; i++) 1028 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1029 1030 return (0); 1031 } 1032 1033 static int 1034 otus_alloc_tx_list(struct otus_softc *sc) 1035 { 1036 int error, i; 1037 1038 error = otus_alloc_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT, 1039 OTUS_TXBUFSZ); 1040 if (error != 0) 1041 return (error); 1042 1043 STAILQ_INIT(&sc->sc_tx_inactive); 1044 1045 for (i = 0; i != OTUS_N_XFER; i++) { 1046 STAILQ_INIT(&sc->sc_tx_active[i]); 1047 STAILQ_INIT(&sc->sc_tx_pending[i]); 1048 } 1049 1050 for (i = 0; i < OTUS_TX_LIST_COUNT; i++) { 1051 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1052 } 1053 1054 return (0); 1055 } 1056 1057 static void 1058 otus_free_tx_list(struct otus_softc *sc) 1059 { 1060 int i; 1061 1062 /* prevent further allocations from TX list(s) */ 1063 STAILQ_INIT(&sc->sc_tx_inactive); 1064 1065 for (i = 0; i != OTUS_N_XFER; i++) { 1066 STAILQ_INIT(&sc->sc_tx_active[i]); 1067 STAILQ_INIT(&sc->sc_tx_pending[i]); 1068 } 1069 1070 otus_free_list(sc, sc->sc_tx, OTUS_TX_LIST_COUNT); 1071 } 1072 1073 static void 1074 otus_free_rx_list(struct otus_softc *sc) 1075 { 1076 /* prevent further allocations from RX list(s) */ 1077 STAILQ_INIT(&sc->sc_rx_inactive); 1078 STAILQ_INIT(&sc->sc_rx_active); 1079 1080 otus_free_list(sc, sc->sc_rx, OTUS_RX_LIST_COUNT); 1081 } 1082 1083 static void 1084 otus_free_list(struct otus_softc *sc, struct otus_data data[], int ndata) 1085 { 1086 int i; 1087 1088 for (i = 0; i < ndata; i++) { 1089 struct otus_data *dp = &data[i]; 1090 1091 if (dp->buf != NULL) { 1092 free(dp->buf, M_USBDEV); 1093 dp->buf = NULL; 1094 } 1095 if (dp->ni != NULL) { 1096 ieee80211_free_node(dp->ni); 1097 dp->ni = NULL; 1098 } 1099 } 1100 } 1101 1102 static struct otus_data * 1103 _otus_getbuf(struct otus_softc *sc) 1104 { 1105 struct otus_data *bf; 1106 1107 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1108 if (bf != NULL) 1109 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1110 else 1111 bf = NULL; 1112 /* XXX bzero? */ 1113 return (bf); 1114 } 1115 1116 static struct otus_data * 1117 otus_getbuf(struct otus_softc *sc) 1118 { 1119 struct otus_data *bf; 1120 1121 OTUS_LOCK_ASSERT(sc); 1122 1123 bf = _otus_getbuf(sc); 1124 return (bf); 1125 } 1126 1127 static void 1128 otus_freebuf(struct otus_softc *sc, struct otus_data *bf) 1129 { 1130 1131 OTUS_LOCK_ASSERT(sc); 1132 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, bf, next); 1133 } 1134 1135 static struct otus_tx_cmd * 1136 _otus_get_txcmd(struct otus_softc *sc) 1137 { 1138 struct otus_tx_cmd *bf; 1139 1140 bf = STAILQ_FIRST(&sc->sc_cmd_inactive); 1141 if (bf != NULL) 1142 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next_cmd); 1143 else 1144 bf = NULL; 1145 return (bf); 1146 } 1147 1148 static struct otus_tx_cmd * 1149 otus_get_txcmd(struct otus_softc *sc) 1150 { 1151 struct otus_tx_cmd *bf; 1152 1153 OTUS_LOCK_ASSERT(sc); 1154 1155 bf = _otus_get_txcmd(sc); 1156 if (bf == NULL) { 1157 device_printf(sc->sc_dev, "%s: no tx cmd buffers\n", 1158 __func__); 1159 } 1160 return (bf); 1161 } 1162 1163 static void 1164 otus_free_txcmd(struct otus_softc *sc, struct otus_tx_cmd *bf) 1165 { 1166 1167 OTUS_LOCK_ASSERT(sc); 1168 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, bf, next_cmd); 1169 } 1170 1171 void 1172 otus_next_scan(void *arg, int pending) 1173 { 1174 #if 0 1175 struct otus_softc *sc = arg; 1176 1177 if (usbd_is_dying(sc->sc_udev)) 1178 return; 1179 1180 usbd_ref_incr(sc->sc_udev); 1181 1182 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1183 ieee80211_next_scan(&sc->sc_ic.ic_if); 1184 1185 usbd_ref_decr(sc->sc_udev); 1186 #endif 1187 } 1188 1189 int 1190 otus_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1191 { 1192 struct otus_vap *uvp = OTUS_VAP(vap); 1193 struct ieee80211com *ic = vap->iv_ic; 1194 struct otus_softc *sc = ic->ic_softc; 1195 enum ieee80211_state ostate; 1196 1197 ostate = vap->iv_state; 1198 OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1199 ieee80211_state_name[ostate], 1200 ieee80211_state_name[nstate]); 1201 1202 IEEE80211_UNLOCK(ic); 1203 1204 OTUS_LOCK(sc); 1205 1206 /* XXX TODO: more fleshing out! */ 1207 1208 switch (nstate) { 1209 case IEEE80211_S_INIT: 1210 otus_set_operating_mode(sc); 1211 otus_set_rx_filter(sc); 1212 break; 1213 case IEEE80211_S_RUN: 1214 if (ic->ic_opmode == IEEE80211_M_STA) { 1215 otus_updateslot(sc); 1216 otus_set_operating_mode(sc); 1217 otus_set_rx_filter(sc); 1218 1219 /* Start calibration timer. */ 1220 taskqueue_enqueue_timeout(taskqueue_thread, 1221 &sc->calib_to, hz); 1222 } 1223 break; 1224 default: 1225 break; 1226 } 1227 1228 /* XXX TODO: calibration? */ 1229 1230 sc->sc_led_newstate(sc); 1231 1232 OTUS_UNLOCK(sc); 1233 IEEE80211_LOCK(ic); 1234 return (uvp->newstate(vap, nstate, arg)); 1235 } 1236 1237 int 1238 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 1239 void *odata, int odatalen) 1240 { 1241 struct otus_tx_cmd *cmd; 1242 struct ar_cmd_hdr *hdr; 1243 int xferlen, error; 1244 1245 OTUS_LOCK_ASSERT(sc); 1246 1247 /* Always bulk-out a multiple of 4 bytes. */ 1248 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 1249 if (xferlen > OTUS_MAX_TXCMDSZ) { 1250 device_printf(sc->sc_dev, "%s: command (0x%02x) size (%d) > %d\n", 1251 __func__, 1252 code, 1253 xferlen, 1254 OTUS_MAX_TXCMDSZ); 1255 return (EIO); 1256 } 1257 1258 cmd = otus_get_txcmd(sc); 1259 if (cmd == NULL) { 1260 device_printf(sc->sc_dev, "%s: failed to get buf\n", 1261 __func__); 1262 return (EIO); 1263 } 1264 1265 hdr = (struct ar_cmd_hdr *)cmd->buf; 1266 hdr->code = code; 1267 hdr->len = ilen; 1268 hdr->token = ++sc->token; /* Don't care about endianness. */ 1269 cmd->token = hdr->token; 1270 /* XXX TODO: check max cmd length? */ 1271 memcpy((uint8_t *)&hdr[1], idata, ilen); 1272 1273 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 1274 "%s: sending command code=0x%02x len=%d token=%d\n", 1275 __func__, code, ilen, hdr->token); 1276 1277 cmd->odata = odata; 1278 cmd->odatalen = odatalen; 1279 cmd->buflen = xferlen; 1280 1281 /* Queue the command to the endpoint */ 1282 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next_cmd); 1283 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_CMD]); 1284 1285 /* Sleep on the command; wait for it to complete */ 1286 error = msleep(cmd, &sc->sc_mtx, PCATCH, "otuscmd", hz); 1287 1288 /* 1289 * At this point we don't own cmd any longer; it'll be 1290 * freed by the cmd bulk path or the RX notification 1291 * path. If the data is made available then it'll be copied 1292 * to the caller. All that is left to do is communicate 1293 * status back to the caller. 1294 */ 1295 if (error != 0) { 1296 device_printf(sc->sc_dev, 1297 "%s: timeout waiting for command 0x%02x reply\n", 1298 __func__, code); 1299 } 1300 return error; 1301 } 1302 1303 void 1304 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 1305 { 1306 1307 OTUS_LOCK_ASSERT(sc); 1308 1309 sc->write_buf[sc->write_idx].reg = htole32(reg); 1310 sc->write_buf[sc->write_idx].val = htole32(val); 1311 1312 if (++sc->write_idx > (AR_MAX_WRITE_IDX-1)) 1313 (void)otus_write_barrier(sc); 1314 } 1315 1316 int 1317 otus_write_barrier(struct otus_softc *sc) 1318 { 1319 int error; 1320 1321 OTUS_LOCK_ASSERT(sc); 1322 1323 if (sc->write_idx == 0) 1324 return 0; /* Nothing to flush. */ 1325 1326 OTUS_DPRINTF(sc, OTUS_DEBUG_REGIO, "%s: called; %d updates\n", 1327 __func__, 1328 sc->write_idx); 1329 1330 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 1331 sizeof (sc->write_buf[0]) * sc->write_idx, NULL, 0); 1332 sc->write_idx = 0; 1333 return error; 1334 } 1335 1336 static struct ieee80211_node * 1337 otus_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1338 { 1339 1340 return malloc(sizeof (struct otus_node), M_80211_NODE, 1341 M_NOWAIT | M_ZERO); 1342 } 1343 1344 int 1345 otus_read_eeprom(struct otus_softc *sc) 1346 { 1347 uint32_t regs[8], reg; 1348 uint8_t *eep; 1349 int i, j, error; 1350 1351 OTUS_LOCK_ASSERT(sc); 1352 1353 /* Read EEPROM by blocks of 32 bytes. */ 1354 eep = (uint8_t *)&sc->eeprom; 1355 reg = AR_EEPROM_OFFSET; 1356 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 1357 for (j = 0; j < 8; j++, reg += 4) 1358 regs[j] = htole32(reg); 1359 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep, 32); 1360 if (error != 0) 1361 break; 1362 eep += 32; 1363 } 1364 return error; 1365 } 1366 1367 void 1368 otus_newassoc(struct ieee80211_node *ni, int isnew) 1369 { 1370 struct ieee80211com *ic = ni->ni_ic; 1371 struct otus_softc *sc = ic->ic_softc; 1372 struct otus_node *on = OTUS_NODE(ni); 1373 1374 OTUS_DPRINTF(sc, OTUS_DEBUG_STATE, "new assoc isnew=%d addr=%s\n", 1375 isnew, ether_sprintf(ni->ni_macaddr)); 1376 1377 on->tx_done = 0; 1378 on->tx_err = 0; 1379 on->tx_retries = 0; 1380 } 1381 1382 static void 1383 otus_cmd_handle_response(struct otus_softc *sc, struct ar_cmd_hdr *hdr) 1384 { 1385 struct otus_tx_cmd *cmd; 1386 1387 OTUS_LOCK_ASSERT(sc); 1388 1389 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1390 "%s: received reply code=0x%02x len=%d token=%d\n", 1391 __func__, 1392 hdr->code, hdr->len, hdr->token); 1393 1394 /* 1395 * Walk the list, freeing items that aren't ours, 1396 * stopping when we hit our token. 1397 */ 1398 while ((cmd = STAILQ_FIRST(&sc->sc_cmd_waiting)) != NULL) { 1399 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next_cmd); 1400 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1401 "%s: cmd=%p; hdr.token=%d, cmd.token=%d\n", 1402 __func__, 1403 cmd, 1404 (int) hdr->token, 1405 (int) cmd->token); 1406 if (hdr->token == cmd->token) { 1407 /* Copy answer into caller's supplied buffer. */ 1408 if (cmd->odata != NULL) { 1409 if (hdr->len != cmd->odatalen) { 1410 device_printf(sc->sc_dev, 1411 "%s: code 0x%02x, len=%d, olen=%d\n", 1412 __func__, 1413 (int) hdr->code, 1414 (int) hdr->len, 1415 (int) cmd->odatalen); 1416 } 1417 memcpy(cmd->odata, &hdr[1], 1418 MIN(cmd->odatalen, hdr->len)); 1419 } 1420 wakeup(cmd); 1421 } 1422 1423 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next_cmd); 1424 } 1425 } 1426 1427 void 1428 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1429 { 1430 struct ieee80211com *ic = &sc->sc_ic; 1431 struct ar_cmd_hdr *hdr; 1432 1433 OTUS_LOCK_ASSERT(sc); 1434 1435 if (__predict_false(len < sizeof (*hdr))) { 1436 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1437 "cmd too small %d\n", len); 1438 return; 1439 } 1440 hdr = (struct ar_cmd_hdr *)buf; 1441 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1442 sizeof (*hdr) + hdr->len > 64)) { 1443 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1444 "cmd too large %d\n", hdr->len); 1445 return; 1446 } 1447 1448 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1449 "%s: code=%.02x\n", 1450 __func__, 1451 hdr->code); 1452 1453 /* 1454 * This has to reach into the cmd queue "waiting for 1455 * an RX response" list, grab the head entry and check 1456 * if we need to wake anyone up. 1457 */ 1458 if ((hdr->code & 0xc0) != 0xc0) { 1459 otus_cmd_handle_response(sc, hdr); 1460 return; 1461 } 1462 1463 /* Received unsolicited notification. */ 1464 switch (hdr->code & 0x3f) { 1465 case AR_EVT_BEACON: 1466 break; 1467 case AR_EVT_TX_COMP: 1468 { 1469 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1470 struct ieee80211_node *ni; 1471 1472 ni = ieee80211_find_node(&ic->ic_sta, tx->macaddr); 1473 if (ni == NULL) { 1474 device_printf(sc->sc_dev, 1475 "%s: txcomp on unknown node (%s)\n", 1476 __func__, 1477 ether_sprintf(tx->macaddr)); 1478 break; 1479 } 1480 1481 OTUS_DPRINTF(sc, OTUS_DEBUG_TXCOMP, 1482 "tx completed %s status=%d phy=0x%x\n", 1483 ether_sprintf(tx->macaddr), le16toh(tx->status), 1484 le32toh(tx->phy)); 1485 1486 switch (le16toh(tx->status)) { 1487 case AR_TX_STATUS_COMP: 1488 #if 0 1489 ackfailcnt = 0; 1490 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1491 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 1492 #endif 1493 /* 1494 * We don't get the above; only error notifications. 1495 * Sigh. So, don't worry about this. 1496 */ 1497 break; 1498 case AR_TX_STATUS_RETRY_COMP: 1499 OTUS_NODE(ni)->tx_retries++; 1500 break; 1501 case AR_TX_STATUS_FAILED: 1502 OTUS_NODE(ni)->tx_err++; 1503 break; 1504 } 1505 ieee80211_free_node(ni); 1506 break; 1507 } 1508 case AR_EVT_TBTT: 1509 break; 1510 case AR_EVT_DO_BB_RESET: 1511 /* 1512 * This is "tell driver to reset baseband" from ar9170-fw. 1513 * 1514 * I'm not sure what we should do here, so I'm going to 1515 * fall through; it gets generated when RTSRetryCnt internally 1516 * reaches '5' - I guess the firmware authors thought that 1517 * meant that the BB may have gone deaf or something. 1518 */ 1519 default: 1520 device_printf(sc->sc_dev, 1521 "%s: received notification code=0x%02x len=%d\n", 1522 __func__, 1523 hdr->code, hdr->len); 1524 } 1525 } 1526 1527 /* 1528 * Handle a single MPDU. 1529 * 1530 * This may be a single MPDU, or it may be a sub-frame from an A-MPDU. 1531 * In the latter case some of the header details need to be adjusted. 1532 */ 1533 void 1534 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len, struct mbufq *rxq) 1535 { 1536 struct ieee80211com *ic = &sc->sc_ic; 1537 struct ieee80211_rx_stats rxs; 1538 #if 0 1539 struct ieee80211_node *ni; 1540 #endif 1541 struct ar_rx_macstatus *mac_status = NULL; 1542 struct ar_rx_phystatus *phy_status = NULL; 1543 struct ieee80211_frame *wh; 1544 struct mbuf *m; 1545 // int s; 1546 1547 if (otus_debug & OTUS_DEBUG_RX_BUFFER) { 1548 device_printf(sc->sc_dev, "%s: %*D\n", 1549 __func__, len, buf, "-"); 1550 } 1551 1552 /* 1553 * Before any data path stuff - check to see if this is a command 1554 * response. 1555 * 1556 * All bits in the PLCP header are set to 1 for non-MPDU. 1557 */ 1558 if ((len >= AR_PLCP_HDR_LEN) && 1559 memcmp(buf, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1560 otus_cmd_rxeof(sc, buf + AR_PLCP_HDR_LEN, 1561 len - AR_PLCP_HDR_LEN); 1562 return; 1563 } 1564 1565 /* 1566 * First step - get the status for the given frame. 1567 * This will tell us whether it's a single MPDU or 1568 * an A-MPDU subframe. 1569 */ 1570 if (len < sizeof(*mac_status)) { 1571 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1572 "%s: sub-xfer too short (no mac_status) (len %d)\n", 1573 __func__, len); 1574 counter_u64_add(ic->ic_ierrors, 1); 1575 return; 1576 } 1577 /* 1578 * Remove the mac_status from the payload length. 1579 * 1580 * Note: cheating, don't reallocate the buffer! 1581 */ 1582 mac_status = (struct ar_rx_macstatus *)(buf + len - sizeof(*mac_status)); 1583 len -= sizeof(*mac_status); 1584 1585 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: mac status=0x%x\n", 1586 __func__, mac_status->status); 1587 1588 /* 1589 * Next - check the MAC status before doing anything else. 1590 * Extract out the PLCP header for single and first frames; 1591 * since there's a single RX path we can shove PLCP headers 1592 * from both into sc->ar_last_rx_plcp[] so it can be reused. 1593 */ 1594 if (((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_SINGLE) || 1595 ((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_FIRST)) { 1596 /* 1597 * Ok, we need to at least have a PLCP header at 1598 * this point. 1599 */ 1600 if (len < AR_PLCP_HDR_LEN) { 1601 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1602 "%s sub-xfer too short (no mac+plcp) (len %d\n)", 1603 __func__, len); 1604 counter_u64_add(ic->ic_ierrors, 1); 1605 return; 1606 } 1607 memcpy(sc->ar_last_rx_plcp, buf, AR_PLCP_HDR_LEN); 1608 1609 /* 1610 * At this point we can just consume the PLCP header. 1611 * The beginning of the frame should thus be data. 1612 */ 1613 buf += AR_PLCP_HDR_LEN; 1614 len -= AR_PLCP_HDR_LEN; 1615 } 1616 1617 /* 1618 * Next - see if we have a PHY status. 1619 * 1620 * The PHY status is at the end of the final A-MPDU subframe 1621 * or a single MPDU frame. 1622 * 1623 * We'll use this to tag frames with noise floor / RSSI 1624 * if they have valid information. 1625 */ 1626 if (((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_SINGLE) || 1627 ((mac_status->status & AR_RX_STATUS_MPDU_MASK) == AR_RX_STATUS_MPDU_LAST)) { 1628 if (len < sizeof(*phy_status)) { 1629 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1630 "%s sub-xfer too short (no phy status) (len %d\n)", 1631 __func__, len); 1632 counter_u64_add(ic->ic_ierrors, 1); 1633 return; 1634 } 1635 /* 1636 * Take a pointer to the phy status and remove the length 1637 * from the end of the buffer. 1638 * 1639 * Note: we're cheating here; don't reallocate the buffer! 1640 */ 1641 phy_status = (struct ar_rx_phystatus *) 1642 (buf + len - sizeof(*phy_status)); 1643 len -= sizeof(*phy_status); 1644 } 1645 1646 /* 1647 * Middle frames just have a MAC status (stripped above.) 1648 * No PHY status, and PLCP is from ar_last_rx_plcp. 1649 */ 1650 1651 /* 1652 * Discard error frames; don't discard BAD_RA (eg monitor mode); 1653 * let net80211 do that 1654 */ 1655 if (__predict_false((mac_status->error & ~AR_RX_ERROR_BAD_RA) != 0)) { 1656 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "error frame 0x%02x\n", mac_status->error); 1657 if (mac_status->error & AR_RX_ERROR_FCS) { 1658 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "bad FCS\n"); 1659 } else if (mac_status->error & AR_RX_ERROR_MMIC) { 1660 /* Report Michael MIC failures to net80211. */ 1661 #if 0 1662 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyidx); 1663 #endif 1664 device_printf(sc->sc_dev, "%s: MIC failure\n", __func__); 1665 } 1666 counter_u64_add(ic->ic_ierrors, 1); 1667 return; 1668 } 1669 1670 /* 1671 * Make sure there's room for an 802.11 header + FCS. 1672 * 1673 * Note: a CTS/ACK is 14 bytes (FC, DUR, RA, FCS). 1674 * Making it IEEE80211_MIN_LEN misses CTS/ACKs. 1675 * 1676 * This won't be tossed at this point; eventually once 1677 * rx radiotap is implemented this will allow for 1678 * CTS/ACK frames. Passing them up to net80211 will 1679 * currently make it angry (too short packets.) 1680 */ 1681 if (len < 2 + 2 + IEEE80211_ADDR_LEN + IEEE80211_CRC_LEN) { 1682 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1683 "%s: too short for 802.11 (len %d)\n", 1684 __func__, len); 1685 counter_u64_add(ic->ic_ierrors, 1); 1686 return; 1687 } 1688 1689 len -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1690 wh = (struct ieee80211_frame *) buf; 1691 1692 /* 1693 * The firmware does seem to spit out a bunch of frames 1694 * with invalid frame control values here. Just toss them 1695 * rather than letting net80211 get angry and log. 1696 */ 1697 if (!IEEE80211_IS_FC0_CHECK_VER(wh, IEEE80211_FC0_VERSION_0)) { 1698 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1699 "%s: invalid 802.11 fc version (firmware bug?)\n", 1700 __func__); 1701 counter_u64_add(ic->ic_ierrors, 1); 1702 return; 1703 } 1704 1705 m = m_get2(len, M_NOWAIT, MT_DATA, M_PKTHDR); 1706 if (m == NULL) { 1707 device_printf(sc->sc_dev, "%s: failed m_get2() (len=%d)\n", 1708 __func__, len); 1709 counter_u64_add(ic->ic_ierrors, 1); 1710 return; 1711 } 1712 1713 /* Finalize mbuf. */ 1714 memcpy(mtod(m, uint8_t *), wh, len); 1715 m->m_pkthdr.len = m->m_len = len; 1716 1717 /* XXX TODO: add setting rx radiotap fields here */ 1718 1719 /* 1720 * Ok, check the frame length and toss if it's too short 1721 * for net80211. This will toss ACK/CTS. 1722 */ 1723 if (m->m_len < IEEE80211_MIN_LEN) { 1724 /* XXX TODO: add radiotap receive here */ 1725 m_free(m); m = NULL; 1726 return; 1727 } 1728 1729 /* Add RSSI to this mbuf if we have a PHY header */ 1730 bzero(&rxs, sizeof(rxs)); 1731 rxs.r_flags = IEEE80211_R_NF; 1732 rxs.c_nf = sc->sc_nf[0]; /* XXX chain 0 != combined rssi/nf */ 1733 if (phy_status != NULL) { 1734 rxs.r_flags |= IEEE80211_R_RSSI; 1735 rxs.c_rssi = phy_status->rssi; 1736 } 1737 /* XXX TODO: add MIMO RSSI/NF as well */ 1738 if (ieee80211_add_rx_params(m, &rxs) == 0) { 1739 counter_u64_add(ic->ic_ierrors, 1); 1740 return; 1741 } 1742 1743 /* XXX make a method */ 1744 STAILQ_INSERT_TAIL(&rxq->mq_head, m, m_stailqpkt); 1745 1746 #if 0 1747 OTUS_UNLOCK(sc); 1748 ni = ieee80211_find_rxnode(ic, wh); 1749 rxi.rxi_flags = 0; 1750 rxi.rxi_rssi = tail->rssi; 1751 rxi.rxi_tstamp = 0; /* unused */ 1752 ieee80211_input(ifp, m, ni, &rxi); 1753 1754 /* Node is no longer needed. */ 1755 ieee80211_release_node(ic, ni); 1756 OTUS_LOCK(sc); 1757 #endif 1758 } 1759 1760 static void 1761 otus_rxeof(struct usb_xfer *xfer, struct otus_data *data, struct mbufq *rxq) 1762 { 1763 struct otus_softc *sc = usbd_xfer_softc(xfer); 1764 caddr_t buf = data->buf; 1765 struct ar_rx_head *head; 1766 uint16_t hlen; 1767 int len, offset = 0; 1768 1769 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 1770 1771 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1772 "%s: transfer completed; len=%d\n", 1773 __func__, len); 1774 if (otus_debug & OTUS_DEBUG_RX_BUFFER) { 1775 device_printf(sc->sc_dev, "%s: %*D\n", 1776 __func__, len, buf, "-"); 1777 } 1778 1779 while (len >= sizeof (*head)) { 1780 head = (struct ar_rx_head *)buf; 1781 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1782 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1783 "tag not valid 0x%x\n", le16toh(head->tag)); 1784 break; 1785 } 1786 hlen = le16toh(head->len); 1787 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: hlen=%d\n", 1788 __func__, hlen); 1789 if (__predict_false(sizeof (*head) + hlen > len)) { 1790 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1791 "xfer too short %d/%d\n", len, hlen); 1792 break; 1793 } 1794 /* Process sub-xfer. */ 1795 otus_sub_rxeof(sc, (uint8_t *) (((uint8_t *) buf) + 4), hlen, rxq); 1796 1797 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1798 hlen = (sizeof (*head) + hlen + 3) & ~3; 1799 offset += hlen; 1800 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, 1801 "%s: rounded size is %d, next packet starts at %d\n", 1802 __func__, hlen, offset); 1803 buf += hlen; 1804 len -= hlen; 1805 } 1806 OTUS_DPRINTF(sc, OTUS_DEBUG_RXDONE, "%s: done!\n", __func__); 1807 } 1808 1809 static void 1810 otus_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1811 { 1812 struct otus_softc *sc = usbd_xfer_softc(xfer); 1813 struct ieee80211com *ic = &sc->sc_ic; 1814 struct ieee80211_frame *wh; 1815 struct ieee80211_node *ni; 1816 struct mbuf *m; 1817 struct mbufq scrx; 1818 struct otus_data *data; 1819 1820 OTUS_LOCK_ASSERT(sc); 1821 1822 mbufq_init(&scrx, 1024); 1823 1824 #if 0 1825 device_printf(sc->sc_dev, "%s: called; state=%d; error=%d\n", 1826 __func__, 1827 USB_GET_STATE(xfer), 1828 error); 1829 #endif 1830 1831 switch (USB_GET_STATE(xfer)) { 1832 case USB_ST_TRANSFERRED: 1833 data = STAILQ_FIRST(&sc->sc_rx_active); 1834 if (data == NULL) 1835 goto tr_setup; 1836 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1837 otus_rxeof(xfer, data, &scrx); 1838 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1839 /* FALLTHROUGH */ 1840 case USB_ST_SETUP: 1841 tr_setup: 1842 /* 1843 * XXX TODO: what if sc_rx isn't empty, but data 1844 * is empty? Then we leak mbufs. 1845 */ 1846 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1847 if (data == NULL) { 1848 //KASSERT(m == NULL, ("mbuf isn't NULL")); 1849 return; 1850 } 1851 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1852 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1853 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1854 usbd_xfer_max_len(xfer)); 1855 usbd_transfer_submit(xfer); 1856 /* 1857 * To avoid LOR we should unlock our private mutex here to call 1858 * ieee80211_input() because here is at the end of a USB 1859 * callback and safe to unlock. 1860 */ 1861 OTUS_UNLOCK(sc); 1862 while ((m = mbufq_dequeue(&scrx)) != NULL) { 1863 wh = mtod(m, struct ieee80211_frame *); 1864 ni = ieee80211_find_rxnode(ic, 1865 (struct ieee80211_frame_min *)wh); 1866 if (ni != NULL) { 1867 if (ni->ni_flags & IEEE80211_NODE_HT) 1868 m->m_flags |= M_AMPDU; 1869 (void)ieee80211_input_mimo(ni, m); 1870 ieee80211_free_node(ni); 1871 } else 1872 (void)ieee80211_input_mimo_all(ic, m); 1873 } 1874 #ifdef IEEE80211_SUPPORT_SUPERG 1875 ieee80211_ff_age_all(ic, 100); 1876 #endif 1877 OTUS_LOCK(sc); 1878 break; 1879 default: 1880 /* needs it to the inactive queue due to a error. */ 1881 data = STAILQ_FIRST(&sc->sc_rx_active); 1882 if (data != NULL) { 1883 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1884 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1885 } 1886 if (error != USB_ERR_CANCELLED) { 1887 usbd_xfer_set_stall(xfer); 1888 counter_u64_add(ic->ic_ierrors, 1); 1889 goto tr_setup; 1890 } 1891 break; 1892 } 1893 } 1894 1895 static void 1896 otus_txeof(struct usb_xfer *xfer, struct otus_data *data) 1897 { 1898 struct otus_softc *sc = usbd_xfer_softc(xfer); 1899 1900 OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, 1901 "%s: called; data=%p\n", __func__, data); 1902 1903 OTUS_LOCK_ASSERT(sc); 1904 1905 if (sc->sc_tx_n_active == 0) { 1906 device_printf(sc->sc_dev, 1907 "%s: completed but tx_active=0\n", 1908 __func__); 1909 } else { 1910 sc->sc_tx_n_active--; 1911 } 1912 1913 if (data->m) { 1914 /* XXX status? */ 1915 /* XXX we get TX status via the RX path.. */ 1916 ieee80211_tx_complete(data->ni, data->m, 0); 1917 data->m = NULL; 1918 data->ni = NULL; 1919 } 1920 } 1921 1922 static void 1923 otus_txcmdeof(struct usb_xfer *xfer, struct otus_tx_cmd *cmd) 1924 { 1925 struct otus_softc *sc = usbd_xfer_softc(xfer); 1926 1927 OTUS_LOCK_ASSERT(sc); 1928 1929 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 1930 "%s: called; data=%p; odata=%p\n", 1931 __func__, cmd, cmd->odata); 1932 1933 /* 1934 * Non-response commands still need wakeup so the caller 1935 * knows it was submitted and completed OK; response commands should 1936 * wait until they're ACKed by the firmware with a response. 1937 */ 1938 if (cmd->odata) { 1939 STAILQ_INSERT_TAIL(&sc->sc_cmd_waiting, cmd, next_cmd); 1940 } else { 1941 wakeup(cmd); 1942 otus_free_txcmd(sc, cmd); 1943 } 1944 } 1945 1946 static void 1947 otus_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1948 { 1949 uint8_t which = OTUS_BULK_TX; 1950 struct otus_softc *sc = usbd_xfer_softc(xfer); 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 struct otus_data *data; 1953 1954 OTUS_LOCK_ASSERT(sc); 1955 1956 switch (USB_GET_STATE(xfer)) { 1957 case USB_ST_TRANSFERRED: 1958 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1959 if (data == NULL) 1960 goto tr_setup; 1961 OTUS_DPRINTF(sc, OTUS_DEBUG_TXDONE, 1962 "%s: transfer done %p\n", __func__, data); 1963 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1964 otus_txeof(xfer, data); 1965 otus_freebuf(sc, data); 1966 /* FALLTHROUGH */ 1967 case USB_ST_SETUP: 1968 tr_setup: 1969 data = STAILQ_FIRST(&sc->sc_tx_pending[which]); 1970 if (data == NULL) { 1971 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 1972 "%s: empty pending queue sc %p\n", __func__, sc); 1973 sc->sc_tx_n_active = 0; 1974 goto finish; 1975 } 1976 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending[which], next); 1977 STAILQ_INSERT_TAIL(&sc->sc_tx_active[which], data, next); 1978 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1979 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 1980 "%s: submitting transfer %p\n", __func__, data); 1981 usbd_transfer_submit(xfer); 1982 sc->sc_tx_n_active++; 1983 break; 1984 default: 1985 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1986 if (data != NULL) { 1987 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1988 otus_txeof(xfer, data); 1989 otus_freebuf(sc, data); 1990 } 1991 counter_u64_add(ic->ic_oerrors, 1); 1992 1993 if (error != USB_ERR_CANCELLED) { 1994 usbd_xfer_set_stall(xfer); 1995 goto tr_setup; 1996 } 1997 break; 1998 } 1999 2000 finish: 2001 #ifdef IEEE80211_SUPPORT_SUPERG 2002 /* 2003 * If the TX active queue drops below a certain 2004 * threshold, ensure we age fast-frames out so they're 2005 * transmitted. 2006 */ 2007 if (sc->sc_tx_n_active < 2) { 2008 /* XXX ew - net80211 should defer this for us! */ 2009 OTUS_UNLOCK(sc); 2010 ieee80211_ff_flush(ic, WME_AC_VO); 2011 ieee80211_ff_flush(ic, WME_AC_VI); 2012 ieee80211_ff_flush(ic, WME_AC_BE); 2013 ieee80211_ff_flush(ic, WME_AC_BK); 2014 OTUS_LOCK(sc); 2015 } 2016 #endif 2017 /* Kick TX */ 2018 otus_tx_start(sc); 2019 } 2020 2021 static void 2022 otus_bulk_cmd_callback(struct usb_xfer *xfer, usb_error_t error) 2023 { 2024 struct otus_softc *sc = usbd_xfer_softc(xfer); 2025 #if 0 2026 struct ieee80211com *ic = &sc->sc_ic; 2027 #endif 2028 struct otus_tx_cmd *cmd; 2029 2030 OTUS_LOCK_ASSERT(sc); 2031 2032 switch (USB_GET_STATE(xfer)) { 2033 case USB_ST_TRANSFERRED: 2034 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2035 if (cmd == NULL) 2036 goto tr_setup; 2037 OTUS_DPRINTF(sc, OTUS_DEBUG_CMDDONE, 2038 "%s: transfer done %p\n", __func__, cmd); 2039 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); 2040 otus_txcmdeof(xfer, cmd); 2041 /* FALLTHROUGH */ 2042 case USB_ST_SETUP: 2043 tr_setup: 2044 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2045 if (cmd == NULL) { 2046 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 2047 "%s: empty pending queue sc %p\n", __func__, sc); 2048 return; 2049 } 2050 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next_cmd); 2051 STAILQ_INSERT_TAIL(&sc->sc_cmd_active, cmd, next_cmd); 2052 usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); 2053 OTUS_DPRINTF(sc, OTUS_DEBUG_CMD, 2054 "%s: submitting transfer %p; buf=%p, buflen=%d\n", __func__, cmd, cmd->buf, cmd->buflen); 2055 usbd_transfer_submit(xfer); 2056 break; 2057 default: 2058 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2059 if (cmd != NULL) { 2060 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next_cmd); 2061 otus_txcmdeof(xfer, cmd); 2062 } 2063 2064 if (error != USB_ERR_CANCELLED) { 2065 usbd_xfer_set_stall(xfer); 2066 goto tr_setup; 2067 } 2068 break; 2069 } 2070 } 2071 2072 /* 2073 * This isn't used by carl9170; it however may be used by the 2074 * initial bootloader. 2075 */ 2076 static void 2077 otus_bulk_irq_callback(struct usb_xfer *xfer, usb_error_t error) 2078 { 2079 struct otus_softc *sc = usbd_xfer_softc(xfer); 2080 int actlen; 2081 int sumlen; 2082 2083 usbd_xfer_status(xfer, &actlen, &sumlen, NULL, NULL); 2084 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, 2085 "%s: called; state=%d\n", __func__, USB_GET_STATE(xfer)); 2086 2087 switch (USB_GET_STATE(xfer)) { 2088 case USB_ST_TRANSFERRED: 2089 /* 2090 * Read usb frame data, if any. 2091 * "actlen" has the total length for all frames 2092 * transferred. 2093 */ 2094 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, 2095 "%s: comp; %d bytes\n", 2096 __func__, 2097 actlen); 2098 #if 0 2099 pc = usbd_xfer_get_frame(xfer, 0); 2100 otus_dump_usb_rx_page(sc, pc, actlen); 2101 #endif 2102 /* XXX fallthrough */ 2103 case USB_ST_SETUP: 2104 /* 2105 * Setup xfer frame lengths/count and data 2106 */ 2107 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: setup\n", __func__); 2108 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 2109 usbd_transfer_submit(xfer); 2110 break; 2111 2112 default: /* Error */ 2113 /* 2114 * Print error message and clear stall 2115 * for example. 2116 */ 2117 OTUS_DPRINTF(sc, OTUS_DEBUG_IRQ, "%s: ERROR?\n", __func__); 2118 break; 2119 } 2120 } 2121 2122 /* 2123 * Map net80211 rate to hw rate for otus MAC/PHY. 2124 */ 2125 static uint8_t 2126 otus_rate_to_hw_rate(struct otus_softc *sc, uint8_t rate) 2127 { 2128 int is_2ghz; 2129 2130 is_2ghz = !! (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_curchan)); 2131 2132 /* MCS check */ 2133 if (rate & 0x80) { 2134 return rate; 2135 } 2136 2137 switch (rate) { 2138 /* CCK */ 2139 case 2: 2140 return (0x0); 2141 case 4: 2142 return (0x1); 2143 case 11: 2144 return (0x2); 2145 case 22: 2146 return (0x3); 2147 /* OFDM */ 2148 case 12: 2149 return (0xb); 2150 case 18: 2151 return (0xf); 2152 case 24: 2153 return (0xa); 2154 case 36: 2155 return (0xe); 2156 case 48: 2157 return (0x9); 2158 case 72: 2159 return (0xd); 2160 case 96: 2161 return (0x8); 2162 case 108: 2163 return (0xc); 2164 default: 2165 device_printf(sc->sc_dev, "%s: unknown rate '%d'\n", 2166 __func__, (int) rate); 2167 case 0: 2168 if (is_2ghz) 2169 return (0x0); /* 1MB CCK */ 2170 else 2171 return (0xb); /* 6MB OFDM */ 2172 } 2173 } 2174 2175 static int 2176 otus_hw_rate_is_ht(struct otus_softc *sc, uint8_t hw_rate) 2177 { 2178 2179 return !! (hw_rate & 0x80); 2180 } 2181 2182 static int 2183 otus_hw_rate_is_ofdm(struct otus_softc *sc, uint8_t hw_rate) 2184 { 2185 2186 switch (hw_rate) { 2187 case 0x0: 2188 case 0x1: 2189 case 0x2: 2190 case 0x3: 2191 return (0); 2192 default: 2193 return (1); 2194 } 2195 } 2196 2197 static void 2198 otus_tx_update_ratectl(struct otus_softc *sc, struct ieee80211_node *ni) 2199 { 2200 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs; 2201 struct otus_node *on = OTUS_NODE(ni); 2202 2203 txs->flags = IEEE80211_RATECTL_TX_STATS_NODE | 2204 IEEE80211_RATECTL_TX_STATS_RETRIES; 2205 txs->ni = ni; 2206 txs->nframes = on->tx_done; 2207 txs->nsuccess = on->tx_done - on->tx_err; 2208 txs->nretries = on->tx_retries; 2209 2210 ieee80211_ratectl_tx_update(ni->ni_vap, txs); 2211 on->tx_done = on->tx_err = on->tx_retries = 0; 2212 } 2213 2214 /* 2215 * XXX TODO: support tx bpf parameters for configuration! 2216 * 2217 * Relevant pieces: 2218 * 2219 * ac = params->ibp_pri & 3; 2220 * rate = params->ibp_rate0; 2221 * params->ibp_flags & IEEE80211_BPF_NOACK 2222 * params->ibp_flags & IEEE80211_BPF_RTS 2223 * params->ibp_flags & IEEE80211_BPF_CTS 2224 * tx->rts_ntries = params->ibp_try1; 2225 * tx->data_ntries = params->ibp_try0; 2226 */ 2227 static int 2228 otus_tx(struct otus_softc *sc, struct ieee80211_node *ni, struct mbuf *m, 2229 struct otus_data *data, const struct ieee80211_bpf_params *params) 2230 { 2231 const struct ieee80211_txparam *tp = ni->ni_txparms; 2232 struct ieee80211com *ic = &sc->sc_ic; 2233 struct ieee80211vap *vap = ni->ni_vap; 2234 struct ieee80211_frame *wh; 2235 struct ieee80211_key *k; 2236 struct ar_tx_head *head; 2237 uint32_t phyctl; 2238 uint16_t macctl, qos; 2239 uint8_t qid, rate; 2240 int hasqos, xferlen, type, ismcast; 2241 2242 wh = mtod(m, struct ieee80211_frame *); 2243 2244 ieee80211_output_seqno_assign(ni, -1, m); 2245 2246 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2247 k = ieee80211_crypto_encap(ni, m); 2248 if (k == NULL) { 2249 device_printf(sc->sc_dev, 2250 "%s: m=%p: ieee80211_crypto_encap returns NULL\n", 2251 __func__, 2252 m); 2253 return (ENOBUFS); 2254 } 2255 wh = mtod(m, struct ieee80211_frame *); 2256 } 2257 2258 /* Calculate transfer length; ensure data buffer is large enough */ 2259 xferlen = sizeof (*head) + m->m_pkthdr.len; 2260 if (xferlen > OTUS_TXBUFSZ) { 2261 device_printf(sc->sc_dev, 2262 "%s: 802.11 TX frame is %d bytes, max %d bytes\n", 2263 __func__, 2264 xferlen, 2265 OTUS_TXBUFSZ); 2266 return (ENOBUFS); 2267 } 2268 2269 hasqos = !! IEEE80211_QOS_HAS_SEQ(wh); 2270 2271 if (hasqos) { 2272 uint8_t tid; 2273 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2274 tid = qos & IEEE80211_QOS_TID; 2275 qid = TID_TO_WME_AC(tid); 2276 } else { 2277 qos = 0; 2278 qid = WME_AC_BE; 2279 } 2280 2281 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2282 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2283 2284 /* Pickup a rate index. */ 2285 if (params != NULL) 2286 rate = otus_rate_to_hw_rate(sc, params->ibp_rate0); 2287 else if (!!(m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2288 rate = otus_rate_to_hw_rate(sc, tp->mgmtrate); 2289 else if (ismcast) 2290 rate = otus_rate_to_hw_rate(sc, tp->mcastrate); 2291 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2292 rate = otus_rate_to_hw_rate(sc, tp->ucastrate); 2293 else { 2294 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2295 rate = otus_rate_to_hw_rate(sc, 2296 ieee80211_node_get_txrate_dot11rate(ni)); 2297 } 2298 2299 phyctl = 0; 2300 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 2301 2302 /* 2303 * XXX TODO: params for NOACK, ACK, RTS, CTS, etc 2304 */ 2305 if (ismcast || 2306 (hasqos && ((qos & IEEE80211_QOS_ACKPOLICY) == 2307 IEEE80211_QOS_ACKPOLICY_NOACK))) 2308 macctl |= AR_TX_MAC_NOACK; 2309 2310 if (!ismcast) { 2311 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= vap->iv_rtsthreshold) 2312 macctl |= AR_TX_MAC_RTS; 2313 else if (otus_hw_rate_is_ht(sc, rate)) { 2314 if (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) 2315 macctl |= AR_TX_MAC_RTS; 2316 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 2317 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2318 macctl |= AR_TX_MAC_CTS; 2319 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2320 macctl |= AR_TX_MAC_RTS; 2321 } 2322 } 2323 2324 phyctl |= AR_TX_PHY_MCS(rate & 0x7f); /* Note: MCS rates are 0x80 and above */ 2325 if (otus_hw_rate_is_ht(sc, rate)) { 2326 phyctl |= AR_TX_PHY_MT_HT; 2327 /* Always use all tx antennas for now, just to be safe */ 2328 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2329 2330 /* Heavy clip */ 2331 phyctl |= (rate & 0x7) << AR_TX_PHY_TX_HEAVY_CLIP_SHIFT; 2332 } else if (otus_hw_rate_is_ofdm(sc, rate)) { 2333 phyctl |= AR_TX_PHY_MT_OFDM; 2334 /* Always use all tx antennas for now, just to be safe */ 2335 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2336 } else { /* CCK */ 2337 phyctl |= AR_TX_PHY_MT_CCK; 2338 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 2339 } 2340 2341 /* Update net80211 with the current counters */ 2342 otus_tx_update_ratectl(sc, ni); 2343 2344 /* Update rate control stats for frames that are ACK'ed. */ 2345 if (!(macctl & AR_TX_MAC_NOACK)) 2346 OTUS_NODE(ni)->tx_done++; 2347 2348 /* Fill Tx descriptor. */ 2349 head = (struct ar_tx_head *)data->buf; 2350 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 2351 head->macctl = htole16(macctl); 2352 head->phyctl = htole32(phyctl); 2353 2354 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); 2355 2356 data->buflen = xferlen; 2357 data->ni = ni; 2358 data->m = m; 2359 2360 OTUS_DPRINTF(sc, OTUS_DEBUG_XMIT, 2361 "%s: tx: m=%p; data=%p; len=%d mac=0x%04x phy=0x%08x " 2362 "rate=0x%02x, dot11rate=%d\n", 2363 __func__, m, data, le16toh(head->len), macctl, phyctl, 2364 (int) rate, 2365 (int) ieee80211_node_get_txrate_dot11rate(ni)); 2366 2367 /* Submit transfer */ 2368 STAILQ_INSERT_TAIL(&sc->sc_tx_pending[OTUS_BULK_TX], data, next); 2369 usbd_transfer_start(sc->sc_xfer[OTUS_BULK_TX]); 2370 2371 return 0; 2372 } 2373 2374 static u_int 2375 otus_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2376 { 2377 uint32_t val, *hashes = arg; 2378 2379 val = le32dec(LLADDR(sdl) + 4); 2380 /* Get address byte 5 */ 2381 val = val & 0x0000ff00; 2382 val = val >> 8; 2383 2384 /* As per below, shift it >> 2 to get only 6 bits */ 2385 val = val >> 2; 2386 if (val < 32) 2387 hashes[0] |= 1 << val; 2388 else 2389 hashes[1] |= 1 << (val - 32); 2390 2391 return (1); 2392 } 2393 2394 int 2395 otus_set_multi(struct otus_softc *sc) 2396 { 2397 struct ieee80211com *ic = &sc->sc_ic; 2398 uint32_t hashes[2]; 2399 int r; 2400 2401 if (ic->ic_allmulti > 0 || ic->ic_promisc > 0 || 2402 ic->ic_opmode == IEEE80211_M_MONITOR) { 2403 hashes[0] = 0xffffffff; 2404 hashes[1] = 0xffffffff; 2405 } else { 2406 struct ieee80211vap *vap; 2407 2408 hashes[0] = hashes[1] = 0; 2409 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) 2410 if_foreach_llmaddr(vap->iv_ifp, otus_hash_maddr, 2411 hashes); 2412 } 2413 #if 0 2414 /* XXX openbsd code */ 2415 while (enm != NULL) { 2416 bit = enm->enm_addrlo[5] >> 2; 2417 if (bit < 32) 2418 hashes[0] |= 1 << bit; 2419 else 2420 hashes[1] |= 1 << (bit - 32); 2421 ETHER_NEXT_MULTI(step, enm); 2422 } 2423 #endif 2424 2425 hashes[1] |= 1U << 31; /* Make sure the broadcast bit is set. */ 2426 2427 OTUS_LOCK(sc); 2428 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, hashes[0]); 2429 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hashes[1]); 2430 r = otus_write_barrier(sc); 2431 /* XXX operating mode? filter? */ 2432 OTUS_UNLOCK(sc); 2433 return (r); 2434 } 2435 2436 static int 2437 otus_updateedca(struct ieee80211com *ic) 2438 { 2439 struct otus_softc *sc = ic->ic_softc; 2440 2441 OTUS_LOCK(sc); 2442 /* 2443 * XXX TODO: take temporary copy of EDCA information 2444 * when scheduling this so we have a more time-correct view 2445 * of things. 2446 * XXX TODO: this can be done on the net80211 level 2447 */ 2448 otus_updateedca_locked(sc); 2449 OTUS_UNLOCK(sc); 2450 return (0); 2451 } 2452 2453 static void 2454 otus_updateedca_locked(struct otus_softc *sc) 2455 { 2456 #define EXP2(val) ((1 << (val)) - 1) 2457 #define AIFS(val) ((val) * 9 + 10) 2458 struct chanAccParams chp; 2459 struct ieee80211com *ic = &sc->sc_ic; 2460 const struct wmeParams *edca; 2461 2462 ieee80211_wme_ic_getparams(ic, &chp); 2463 2464 OTUS_LOCK_ASSERT(sc); 2465 2466 edca = chp.cap_wmeParams; 2467 2468 /* Set CWmin/CWmax values. */ 2469 otus_write(sc, AR_MAC_REG_AC0_CW, 2470 EXP2(edca[WME_AC_BE].wmep_logcwmax) << 16 | 2471 EXP2(edca[WME_AC_BE].wmep_logcwmin)); 2472 otus_write(sc, AR_MAC_REG_AC1_CW, 2473 EXP2(edca[WME_AC_BK].wmep_logcwmax) << 16 | 2474 EXP2(edca[WME_AC_BK].wmep_logcwmin)); 2475 otus_write(sc, AR_MAC_REG_AC2_CW, 2476 EXP2(edca[WME_AC_VI].wmep_logcwmax) << 16 | 2477 EXP2(edca[WME_AC_VI].wmep_logcwmin)); 2478 otus_write(sc, AR_MAC_REG_AC3_CW, 2479 EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | 2480 EXP2(edca[WME_AC_VO].wmep_logcwmin)); 2481 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 2482 EXP2(edca[WME_AC_VO].wmep_logcwmax) << 16 | 2483 EXP2(edca[WME_AC_VO].wmep_logcwmin)); 2484 2485 /* Set AIFSN values. */ 2486 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 2487 AIFS(edca[WME_AC_VI].wmep_aifsn) << 24 | 2488 AIFS(edca[WME_AC_BK].wmep_aifsn) << 12 | 2489 AIFS(edca[WME_AC_BE].wmep_aifsn)); 2490 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 2491 AIFS(edca[WME_AC_VO].wmep_aifsn) << 16 | /* Special TXQ. */ 2492 AIFS(edca[WME_AC_VO].wmep_aifsn) << 4 | 2493 AIFS(edca[WME_AC_VI].wmep_aifsn) >> 8); 2494 2495 /* Set TXOP limit. */ 2496 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 2497 edca[WME_AC_BK].wmep_txopLimit << 16 | 2498 edca[WME_AC_BE].wmep_txopLimit); 2499 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 2500 edca[WME_AC_VO].wmep_txopLimit << 16 | 2501 edca[WME_AC_VI].wmep_txopLimit); 2502 2503 /* XXX ACK policy? */ 2504 2505 (void)otus_write_barrier(sc); 2506 2507 #undef AIFS 2508 #undef EXP2 2509 } 2510 2511 static void 2512 otus_updateslot(struct otus_softc *sc) 2513 { 2514 struct ieee80211com *ic = &sc->sc_ic; 2515 uint32_t slottime; 2516 2517 OTUS_LOCK_ASSERT(sc); 2518 2519 slottime = IEEE80211_GET_SLOTTIME(ic); 2520 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 2521 (void)otus_write_barrier(sc); 2522 } 2523 2524 /* 2525 * Things to do based on 2GHz or 5GHz: 2526 * 2527 * + slottime 2528 * + dyn_sifs_ack 2529 * + rts_cts_rate 2530 * + slot time 2531 * + mac_rates 2532 * + mac_tpc 2533 * 2534 * And in the transmit path 2535 * + tpc: carl9170_tx_rate_tpc_chains 2536 * + carl9170_tx_physet() 2537 * + disable short premable tx 2538 */ 2539 2540 int 2541 otus_init_mac(struct otus_softc *sc) 2542 { 2543 int error; 2544 2545 OTUS_LOCK_ASSERT(sc); 2546 2547 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 2548 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 2549 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 2550 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 2551 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 2552 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 2553 otus_write(sc, AR_MAC_REG_TID_CFACK_CFEND_RATE, 0x19000000); 2554 /* NAV protects ACK only (in TXOP). */ 2555 otus_write(sc, AR_MAC_REG_TXOP_DURATION, 0x201); 2556 /* Set beacon Tx power to 0x7. */ 2557 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 2558 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 2559 otus_write(sc, AR_MAC_REG_AMPDU_FACTOR, 0x10000a); 2560 2561 otus_set_rx_filter(sc); 2562 2563 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 2564 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 2565 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 2566 otus_write(sc, AR_MAC_REG_ACK_TPC, 0x4003c1e); 2567 2568 /* Enable LED0 and LED1. */ 2569 otus_write(sc, AR_GPIO_REG_PORT_TYPE, 0x3); 2570 otus_write(sc, AR_GPIO_REG_PORT_DATA, 0x3); 2571 /* Switch MAC to OTUS interface. */ 2572 otus_write(sc, 0x1c3600, 0x3); 2573 otus_write(sc, AR_MAC_REG_AMPDU_RX_THRESH, 0xffff); 2574 otus_write(sc, AR_MAC_REG_MISC_680, 0xf00008); 2575 /* Disable Rx timeout (workaround). */ 2576 otus_write(sc, AR_MAC_REG_RX_TIMEOUT, 0); 2577 2578 /* Set USB Rx stream mode maximum frame number to 2. */ 2579 otus_write(sc, 0x1e1110, 0x4); 2580 /* Set USB Rx stream mode timeout to 10us. */ 2581 otus_write(sc, 0x1e1114, 0x80); 2582 2583 /* Set clock frequency to 88/80MHz. */ 2584 otus_write(sc, AR_PWR_REG_CLOCK_SEL, 0x73); 2585 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 2586 otus_write(sc, AR_MAC_REG_TXRX_MPI, 0x110011); 2587 otus_write(sc, AR_MAC_REG_FCS_SELECT, 0x4); 2588 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 2589 2590 /* Disable HW decryption for now. */ 2591 otus_write(sc, AR_MAC_REG_ENCRYPTION, 0x78); 2592 2593 if ((error = otus_write_barrier(sc)) != 0) 2594 return error; 2595 2596 /* Set default EDCA parameters. */ 2597 otus_updateedca_locked(sc); 2598 2599 return 0; 2600 } 2601 2602 /* 2603 * Return default value for PHY register based on current operating mode. 2604 */ 2605 uint32_t 2606 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 2607 { 2608 int i; 2609 2610 for (i = 0; i < nitems(ar5416_phy_regs); i++) 2611 if (AR_PHY(ar5416_phy_regs[i]) == reg) 2612 return sc->phy_vals[i]; 2613 return 0; /* Register not found. */ 2614 } 2615 2616 /* 2617 * Update PHY's programming based on vendor-specific data stored in EEPROM. 2618 * This is for FEM-type devices only. 2619 */ 2620 int 2621 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 2622 { 2623 const struct ModalEepHeader *eep; 2624 uint32_t tmp, offset; 2625 2626 if (IEEE80211_IS_CHAN_5GHZ(c)) 2627 eep = &sc->eeprom.modalHeader[0]; 2628 else 2629 eep = &sc->eeprom.modalHeader[1]; 2630 2631 /* Offset of chain 2. */ 2632 offset = 2 * 0x1000; 2633 2634 tmp = le32toh(eep->antCtrlCommon); 2635 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 2636 2637 tmp = le32toh(eep->antCtrlChain[0]); 2638 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 2639 2640 tmp = le32toh(eep->antCtrlChain[1]); 2641 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 2642 2643 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 2644 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 2645 tmp &= ~(0x7f << 7); 2646 tmp |= (eep->switchSettling & 0x7f) << 7; 2647 otus_write(sc, AR_PHY_SETTLING, tmp); 2648 } 2649 2650 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 2651 tmp &= ~0xffff; 2652 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 2653 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 2654 2655 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 2656 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 2657 otus_write(sc, AR_PHY_RF_CTL4, tmp); 2658 2659 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 2660 tmp &= ~(0xff << 16); 2661 tmp |= eep->txEndToRxOn << 16; 2662 otus_write(sc, AR_PHY_RF_CTL3, tmp); 2663 2664 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 2665 tmp &= ~(0x7f << 12); 2666 tmp |= (eep->thresh62 & 0x7f) << 12; 2667 otus_write(sc, AR_PHY_CCA, tmp); 2668 2669 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 2670 tmp &= ~(0x3f << 12); 2671 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 2672 otus_write(sc, AR_PHY_RXGAIN, tmp); 2673 2674 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 2675 tmp &= ~(0x3f << 12); 2676 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 2677 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 2678 2679 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 2680 tmp &= ~(0x3f << 18); 2681 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 2682 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2683 tmp &= ~(0xf << 10); 2684 tmp |= (eep->bswMargin[0] & 0xf) << 10; 2685 } 2686 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 2687 2688 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 2689 tmp &= ~(0x3f << 18); 2690 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 2691 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 2692 2693 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 2694 tmp &= ~(0x3f << 5 | 0x1f); 2695 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 2696 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 2697 2698 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 2699 tmp &= ~(0x3f << 5 | 0x1f); 2700 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 2701 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 2702 2703 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 2704 tmp &= ~(0xf << 16); 2705 tmp |= (eep->xpd & 0xf) << 16; 2706 otus_write(sc, AR_PHY_TPCRG1, tmp); 2707 2708 return otus_write_barrier(sc); 2709 } 2710 2711 int 2712 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 2713 { 2714 const uint32_t *vals; 2715 int error, i; 2716 2717 /* Select PHY programming based on band and bandwidth. */ 2718 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2719 if (IEEE80211_IS_CHAN_HT40(c)) 2720 vals = ar5416_phy_vals_2ghz_40mhz; 2721 else 2722 vals = ar5416_phy_vals_2ghz_20mhz; 2723 } else { 2724 if (IEEE80211_IS_CHAN_HT40(c)) 2725 vals = ar5416_phy_vals_5ghz_40mhz; 2726 else 2727 vals = ar5416_phy_vals_5ghz_20mhz; 2728 } 2729 for (i = 0; i < nitems(ar5416_phy_regs); i++) 2730 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 2731 sc->phy_vals = vals; 2732 2733 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 2734 if ((error = otus_set_board_values(sc, c)) != 0) 2735 return error; 2736 2737 /* Initial Tx power settings. */ 2738 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 2739 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 2740 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 2741 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 2742 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 2743 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 2744 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 2745 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 2746 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 2747 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 2748 2749 if (IEEE80211_IS_CHAN_2GHZ(c)) 2750 otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5163); 2751 else 2752 otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5143); 2753 2754 return otus_write_barrier(sc); 2755 } 2756 2757 static __inline uint8_t 2758 otus_reverse_bits(uint8_t v) 2759 { 2760 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 2761 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 2762 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 2763 return v; 2764 } 2765 2766 int 2767 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 2768 { 2769 uint8_t chansel, d0, d1; 2770 uint16_t data; 2771 int error; 2772 2773 OTUS_LOCK_ASSERT(sc); 2774 2775 d0 = 0; 2776 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2777 chansel = (c->ic_freq - 4800) / 5; 2778 if (chansel & 1) 2779 d0 |= AR_BANK4_AMODE_REFSEL(2); 2780 else 2781 d0 |= AR_BANK4_AMODE_REFSEL(1); 2782 } else { 2783 d0 |= AR_BANK4_AMODE_REFSEL(2); 2784 if (c->ic_freq == 2484) { /* CH 14 */ 2785 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 2786 chansel = 10 + (c->ic_freq - 2274) / 5; 2787 } else 2788 chansel = 16 + (c->ic_freq - 2272) / 5; 2789 chansel <<= 2; 2790 } 2791 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 2792 d1 = otus_reverse_bits(chansel); 2793 2794 /* Write bits 0-4 of d0 and d1. */ 2795 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 2796 otus_write(sc, AR_PHY(44), data); 2797 /* Write bits 5-7 of d0 and d1. */ 2798 data = (d1 >> 5) << 5 | (d0 >> 5); 2799 otus_write(sc, AR_PHY(58), data); 2800 2801 if ((error = otus_write_barrier(sc)) == 0) 2802 otus_delay_ms(sc, 10); 2803 return error; 2804 } 2805 2806 void 2807 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 2808 { 2809 #define COEFF_SCALE_SHIFT 24 2810 uint32_t exp, man; 2811 2812 /* exponent = 14 - floor(log2(coeff)) */ 2813 for (exp = 31; exp > 0; exp--) 2814 if (coeff & (1 << exp)) 2815 break; 2816 KASSERT(exp != 0, ("exp")); 2817 exp = 14 - (exp - COEFF_SCALE_SHIFT); 2818 2819 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 2820 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 2821 2822 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 2823 *exponent = exp - 16; 2824 #undef COEFF_SCALE_SHIFT 2825 } 2826 2827 static int 2828 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 2829 { 2830 struct ieee80211com *ic = &sc->sc_ic; 2831 struct ar_cmd_frequency cmd; 2832 struct ar_rsp_frequency rsp; 2833 const uint32_t *vals; 2834 uint32_t coeff, exp, man, tmp; 2835 uint8_t code; 2836 int error, chan, i; 2837 2838 error = 0; 2839 chan = ieee80211_chan2ieee(ic, c); 2840 2841 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2842 "setting channel %d (%dMHz)\n", chan, c->ic_freq); 2843 2844 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 2845 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 2846 if ((error = otus_write_barrier(sc)) != 0) 2847 goto finish; 2848 2849 /* Disable BB Heavy Clip. */ 2850 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 2851 if ((error = otus_write_barrier(sc)) != 0) 2852 goto finish; 2853 2854 /* XXX Is that FREQ_START ? */ 2855 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL, 0); 2856 if (error != 0) 2857 goto finish; 2858 2859 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 2860 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 2861 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, "band switch\n"); 2862 2863 /* Cold/Warm reset BB/ADDA. */ 2864 otus_write(sc, AR_PWR_REG_RESET, sc->bb_reset ? 0x800 : 0x400); 2865 if ((error = otus_write_barrier(sc)) != 0) 2866 goto finish; 2867 otus_write(sc, AR_PWR_REG_RESET, 0); 2868 if ((error = otus_write_barrier(sc)) != 0) 2869 goto finish; 2870 sc->bb_reset = 0; 2871 2872 if ((error = otus_program_phy(sc, c)) != 0) { 2873 device_printf(sc->sc_dev, 2874 "%s: could not program PHY\n", 2875 __func__); 2876 goto finish; 2877 } 2878 2879 /* Select RF programming based on band. */ 2880 if (IEEE80211_IS_CHAN_5GHZ(c)) 2881 vals = ar5416_banks_vals_5ghz; 2882 else 2883 vals = ar5416_banks_vals_2ghz; 2884 for (i = 0; i < nitems(ar5416_banks_regs); i++) 2885 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 2886 if ((error = otus_write_barrier(sc)) != 0) { 2887 device_printf(sc->sc_dev, 2888 "%s: could not program RF\n", 2889 __func__); 2890 goto finish; 2891 } 2892 code = AR_CMD_RF_INIT; 2893 } else { 2894 code = AR_CMD_FREQUENCY; 2895 } 2896 2897 if ((error = otus_set_rf_bank4(sc, c)) != 0) 2898 goto finish; 2899 2900 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 2901 otus_write(sc, AR_PHY_TURBO, tmp); 2902 if ((error = otus_write_barrier(sc)) != 0) 2903 goto finish; 2904 2905 /* Send firmware command to set channel. */ 2906 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2907 cmd.dynht2040 = htole32(0); 2908 cmd.htena = htole32(1); 2909 /* Set Delta Slope (exponent and mantissa). */ 2910 coeff = (100 << 24) / c->ic_freq; 2911 otus_get_delta_slope(coeff, &exp, &man); 2912 cmd.dsc_exp = htole32(exp); 2913 cmd.dsc_man = htole32(man); 2914 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2915 "ds coeff=%u exp=%u man=%u\n", coeff, exp, man); 2916 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2917 coeff = (9 * coeff) / 10; 2918 otus_get_delta_slope(coeff, &exp, &man); 2919 cmd.dsc_shgi_exp = htole32(exp); 2920 cmd.dsc_shgi_man = htole32(man); 2921 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2922 "ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man); 2923 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2924 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2925 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2926 "%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY"); 2927 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp, sizeof(rsp)); 2928 if (error != 0) 2929 goto finish; 2930 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2931 OTUS_DPRINTF(sc, OTUS_DEBUG_RESET, 2932 "status=0x%x\n", le32toh(rsp.status)); 2933 /* Force cold reset on next channel. */ 2934 sc->bb_reset = 1; 2935 } 2936 #ifdef USB_DEBUG 2937 if (otus_debug & OTUS_DEBUG_RESET) { 2938 device_printf(sc->sc_dev, "calibration status=0x%x\n", 2939 le32toh(rsp.status)); 2940 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2941 /* Sign-extend 9-bit NF values. */ 2942 device_printf(sc->sc_dev, 2943 "noisefloor chain %d=%d\n", i, 2944 (((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); 2945 device_printf(sc->sc_dev, 2946 "noisefloor ext chain %d=%d\n", i, 2947 ((int32_t)le32toh(rsp.nf_ext[i])) >> 23); 2948 } 2949 } 2950 #endif 2951 for (i = 0; i < OTUS_NUM_CHAINS; i++) { 2952 sc->sc_nf[i] = ((((int32_t)le32toh(rsp.nf[i])) << 4) >> 23); 2953 } 2954 sc->sc_curchan = c; 2955 finish: 2956 return (error); 2957 } 2958 2959 #ifdef notyet 2960 int 2961 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2962 struct ieee80211_key *k) 2963 { 2964 struct otus_softc *sc = ic->ic_softc; 2965 struct otus_cmd_key cmd; 2966 2967 /* Defer setting of WEP keys until interface is brought up. */ 2968 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2969 (IFF_UP | IFF_RUNNING)) 2970 return 0; 2971 2972 /* Do it in a process context. */ 2973 cmd.key = *k; 2974 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2975 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2976 return 0; 2977 } 2978 2979 void 2980 otus_set_key_cb(struct otus_softc *sc, void *arg) 2981 { 2982 struct otus_cmd_key *cmd = arg; 2983 struct ieee80211_key *k = &cmd->key; 2984 struct ar_cmd_ekey key; 2985 uint16_t cipher; 2986 int error; 2987 2988 memset(&key, 0, sizeof key); 2989 if (k->k_flags & IEEE80211_KEY_GROUP) { 2990 key.uid = htole16(k->k_id); 2991 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2992 key.macaddr[0] |= 0x80; 2993 } else { 2994 key.uid = htole16(OTUS_UID(cmd->associd)); 2995 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2996 } 2997 key.kix = htole16(0); 2998 /* Map net80211 cipher to hardware. */ 2999 switch (k->k_cipher) { 3000 case IEEE80211_CIPHER_WEP40: 3001 cipher = AR_CIPHER_WEP64; 3002 break; 3003 case IEEE80211_CIPHER_WEP104: 3004 cipher = AR_CIPHER_WEP128; 3005 break; 3006 case IEEE80211_CIPHER_TKIP: 3007 cipher = AR_CIPHER_TKIP; 3008 break; 3009 case IEEE80211_CIPHER_CCMP: 3010 cipher = AR_CIPHER_AES; 3011 break; 3012 default: 3013 return; 3014 } 3015 key.cipher = htole16(cipher); 3016 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 3017 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); 3018 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) 3019 return; 3020 3021 /* TKIP: set Tx/Rx MIC Key. */ 3022 key.kix = htole16(1); 3023 memcpy(key.key, k->k_key + 16, 16); 3024 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL, 0); 3025 } 3026 3027 void 3028 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3029 struct ieee80211_key *k) 3030 { 3031 struct otus_softc *sc = ic->ic_softc; 3032 struct otus_cmd_key cmd; 3033 3034 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 3035 ic->ic_state != IEEE80211_S_RUN) 3036 return; /* Nothing to do. */ 3037 3038 /* Do it in a process context. */ 3039 cmd.key = *k; 3040 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 3041 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 3042 } 3043 3044 void 3045 otus_delete_key_cb(struct otus_softc *sc, void *arg) 3046 { 3047 struct otus_cmd_key *cmd = arg; 3048 struct ieee80211_key *k = &cmd->key; 3049 uint32_t uid; 3050 3051 if (k->k_flags & IEEE80211_KEY_GROUP) 3052 uid = htole32(k->k_id); 3053 else 3054 uid = htole32(OTUS_UID(cmd->associd)); 3055 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL, 0); 3056 } 3057 #endif 3058 3059 /* 3060 * XXX TODO: check if we have to be doing any calibration in the host 3061 * or whether it's purely a firmware thing. 3062 */ 3063 void 3064 otus_calibrate_to(void *arg, int pending) 3065 { 3066 #if 0 3067 struct otus_softc *sc = arg; 3068 3069 device_printf(sc->sc_dev, "%s: called\n", __func__); 3070 struct ieee80211com *ic = &sc->sc_ic; 3071 struct ieee80211_node *ni; 3072 3073 if (usbd_is_dying(sc->sc_udev)) 3074 return; 3075 3076 usbd_ref_incr(sc->sc_udev); 3077 3078 ni = ic->ic_bss; 3079 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 3080 3081 if (!usbd_is_dying(sc->sc_udev)) 3082 timeout_add_sec(&sc->calib_to, 1); 3083 3084 usbd_ref_decr(sc->sc_udev); 3085 #endif 3086 } 3087 3088 int 3089 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 3090 { 3091 3092 OTUS_LOCK_ASSERT(sc); 3093 3094 otus_write(sc, AR_MAC_REG_BSSID_L, 3095 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3096 otus_write(sc, AR_MAC_REG_BSSID_H, 3097 bssid[4] | bssid[5] << 8); 3098 return otus_write_barrier(sc); 3099 } 3100 3101 int 3102 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 3103 { 3104 OTUS_LOCK_ASSERT(sc); 3105 3106 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 3107 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3108 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 3109 addr[4] | addr[5] << 8); 3110 return otus_write_barrier(sc); 3111 } 3112 3113 /* Default single-LED. */ 3114 void 3115 otus_led_newstate_type1(struct otus_softc *sc) 3116 { 3117 /* TBD */ 3118 device_printf(sc->sc_dev, "%s: TODO\n", __func__); 3119 } 3120 3121 /* NETGEAR, dual-LED. */ 3122 void 3123 otus_led_newstate_type2(struct otus_softc *sc) 3124 { 3125 /* TBD */ 3126 device_printf(sc->sc_dev, "%s: TODO\n", __func__); 3127 } 3128 3129 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 3130 void 3131 otus_led_newstate_type3(struct otus_softc *sc) 3132 { 3133 #if 0 3134 struct ieee80211com *ic = &sc->sc_ic; 3135 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3136 3137 uint32_t state = sc->led_state; 3138 3139 OTUS_LOCK_ASSERT(sc); 3140 3141 if (!vap) { 3142 state = 0; /* led off */ 3143 } else if (vap->iv_state == IEEE80211_S_INIT) { 3144 state = 0; /* LED off. */ 3145 } else if (vap->iv_state == IEEE80211_S_RUN) { 3146 /* Associated, LED always on. */ 3147 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 3148 state = AR_LED0_ON; /* 2GHz=>Red. */ 3149 else 3150 state = AR_LED1_ON; /* 5GHz=>Blue. */ 3151 } else { 3152 /* Scanning, blink LED. */ 3153 state ^= AR_LED0_ON | AR_LED1_ON; 3154 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 3155 state &= ~AR_LED1_ON; 3156 else 3157 state &= ~AR_LED0_ON; 3158 } 3159 if (state != sc->led_state) { 3160 otus_write(sc, AR_GPIO_REG_PORT_DATA, state); 3161 if (otus_write_barrier(sc) == 0) 3162 sc->led_state = state; 3163 } 3164 #endif 3165 } 3166 3167 static uint8_t zero_macaddr[IEEE80211_ADDR_LEN] = { 0,0,0,0,0,0 }; 3168 3169 /* 3170 * Set up operating mode, MAC/BSS address and RX filter. 3171 */ 3172 static void 3173 otus_set_operating_mode(struct otus_softc *sc) 3174 { 3175 struct ieee80211com *ic = &sc->sc_ic; 3176 struct ieee80211vap *vap; 3177 uint32_t cam_mode = AR_MAC_CAM_DEFAULTS; 3178 uint32_t rx_ctrl = AR_MAC_RX_CTRL_DEAGG | AR_MAC_RX_CTRL_SHORT_FILTER; 3179 uint32_t sniffer = AR_MAC_SNIFFER_DEFAULTS; 3180 uint32_t enc_mode = 0x78; /* XXX */ 3181 const uint8_t *macaddr; 3182 uint8_t bssid[IEEE80211_ADDR_LEN]; 3183 struct ieee80211_node *ni; 3184 3185 OTUS_LOCK_ASSERT(sc); 3186 3187 /* 3188 * If we're in sniffer mode or we don't have a MAC 3189 * address assigned, ensure it gets reset to all-zero. 3190 */ 3191 IEEE80211_ADDR_COPY(bssid, zero_macaddr); 3192 vap = TAILQ_FIRST(&ic->ic_vaps); 3193 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 3194 3195 switch (ic->ic_opmode) { 3196 case IEEE80211_M_STA: 3197 if (vap) { 3198 ni = ieee80211_ref_node(vap->iv_bss); 3199 IEEE80211_ADDR_COPY(bssid, ni->ni_bssid); 3200 ieee80211_free_node(ni); 3201 } 3202 cam_mode |= AR_MAC_CAM_STA; 3203 rx_ctrl |= AR_MAC_RX_CTRL_PASS_TO_HOST; 3204 break; 3205 case IEEE80211_M_MONITOR: 3206 /* 3207 * Note: monitor mode ends up causing the MAC to 3208 * generate ACK frames for everything it sees. 3209 * So don't do that; instead just put it in STA mode 3210 * and disable RX filters. 3211 */ 3212 default: 3213 cam_mode |= AR_MAC_CAM_STA; 3214 rx_ctrl |= AR_MAC_RX_CTRL_PASS_TO_HOST; 3215 break; 3216 } 3217 3218 /* 3219 * TODO: if/when we do hardware encryption, ensure it's 3220 * disabled if the NIC is in monitor mode. 3221 */ 3222 otus_write(sc, AR_MAC_REG_SNIFFER, sniffer); 3223 otus_write(sc, AR_MAC_REG_CAM_MODE, cam_mode); 3224 otus_write(sc, AR_MAC_REG_ENCRYPTION, enc_mode); 3225 otus_write(sc, AR_MAC_REG_RX_CONTROL, rx_ctrl); 3226 otus_set_macaddr(sc, macaddr); 3227 otus_set_bssid(sc, bssid); 3228 /* XXX barrier? */ 3229 } 3230 3231 static void 3232 otus_set_rx_filter(struct otus_softc *sc) 3233 { 3234 // struct ieee80211com *ic = &sc->sc_ic; 3235 3236 OTUS_LOCK_ASSERT(sc); 3237 3238 #if 0 3239 if (ic->ic_allmulti > 0 || ic->ic_promisc > 0 || 3240 ic->ic_opmode == IEEE80211_M_MONITOR) { 3241 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0xff00ffff); 3242 } else { 3243 #endif 3244 /* Filter any control frames, BAR is bit 24. */ 3245 otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0x0500ffff); 3246 #if 0 3247 } 3248 #endif 3249 } 3250 3251 int 3252 otus_init(struct otus_softc *sc) 3253 { 3254 struct ieee80211com *ic = &sc->sc_ic; 3255 int error; 3256 3257 OTUS_UNLOCK_ASSERT(sc); 3258 3259 OTUS_LOCK(sc); 3260 3261 /* Drain any pending TX frames */ 3262 otus_drain_mbufq(sc); 3263 3264 /* Init MAC */ 3265 if ((error = otus_init_mac(sc)) != 0) { 3266 OTUS_UNLOCK(sc); 3267 device_printf(sc->sc_dev, 3268 "%s: could not initialize MAC\n", __func__); 3269 return error; 3270 } 3271 3272 otus_set_operating_mode(sc); 3273 otus_set_rx_filter(sc); 3274 (void) otus_set_operating_mode(sc); 3275 3276 sc->bb_reset = 1; /* Force cold reset. */ 3277 3278 if ((error = otus_set_chan(sc, ic->ic_curchan, 0)) != 0) { 3279 OTUS_UNLOCK(sc); 3280 device_printf(sc->sc_dev, 3281 "%s: could not set channel\n", __func__); 3282 return error; 3283 } 3284 3285 /* Start Rx. */ 3286 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0x100); 3287 (void)otus_write_barrier(sc); 3288 3289 sc->sc_running = 1; 3290 3291 OTUS_UNLOCK(sc); 3292 return 0; 3293 } 3294 3295 void 3296 otus_stop(struct otus_softc *sc) 3297 { 3298 #if 0 3299 int s; 3300 #endif 3301 3302 OTUS_UNLOCK_ASSERT(sc); 3303 3304 OTUS_LOCK(sc); 3305 sc->sc_running = 0; 3306 sc->sc_tx_timer = 0; 3307 OTUS_UNLOCK(sc); 3308 3309 taskqueue_drain_timeout(taskqueue_thread, &sc->scan_to); 3310 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_to); 3311 taskqueue_drain(taskqueue_thread, &sc->tx_task); 3312 3313 OTUS_LOCK(sc); 3314 sc->sc_running = 0; 3315 /* Stop Rx. */ 3316 otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0); 3317 (void)otus_write_barrier(sc); 3318 3319 /* Drain any pending TX frames */ 3320 otus_drain_mbufq(sc); 3321 3322 OTUS_UNLOCK(sc); 3323 } 3324