1*ef270ab1SKenneth D. Merry /*- 2*ef270ab1SKenneth D. Merry * Copyright (c) 2017 Broadcom. All rights reserved. 3*ef270ab1SKenneth D. Merry * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4*ef270ab1SKenneth D. Merry * 5*ef270ab1SKenneth D. Merry * Redistribution and use in source and binary forms, with or without 6*ef270ab1SKenneth D. Merry * modification, are permitted provided that the following conditions are met: 7*ef270ab1SKenneth D. Merry * 8*ef270ab1SKenneth D. Merry * 1. Redistributions of source code must retain the above copyright notice, 9*ef270ab1SKenneth D. Merry * this list of conditions and the following disclaimer. 10*ef270ab1SKenneth D. Merry * 11*ef270ab1SKenneth D. Merry * 2. Redistributions in binary form must reproduce the above copyright notice, 12*ef270ab1SKenneth D. Merry * this list of conditions and the following disclaimer in the documentation 13*ef270ab1SKenneth D. Merry * and/or other materials provided with the distribution. 14*ef270ab1SKenneth D. Merry * 15*ef270ab1SKenneth D. Merry * 3. Neither the name of the copyright holder nor the names of its contributors 16*ef270ab1SKenneth D. Merry * may be used to endorse or promote products derived from this software 17*ef270ab1SKenneth D. Merry * without specific prior written permission. 18*ef270ab1SKenneth D. Merry * 19*ef270ab1SKenneth D. Merry * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20*ef270ab1SKenneth D. Merry * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*ef270ab1SKenneth D. Merry * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22*ef270ab1SKenneth D. Merry * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23*ef270ab1SKenneth D. Merry * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24*ef270ab1SKenneth D. Merry * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25*ef270ab1SKenneth D. Merry * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26*ef270ab1SKenneth D. Merry * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27*ef270ab1SKenneth D. Merry * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28*ef270ab1SKenneth D. Merry * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29*ef270ab1SKenneth D. Merry * POSSIBILITY OF SUCH DAMAGE. 30*ef270ab1SKenneth D. Merry * 31*ef270ab1SKenneth D. Merry * $FreeBSD$ 32*ef270ab1SKenneth D. Merry */ 33*ef270ab1SKenneth D. Merry 34*ef270ab1SKenneth D. Merry /** 35*ef270ab1SKenneth D. Merry * @file 36*ef270ab1SKenneth D. Merry * OCS bsd driver common include file 37*ef270ab1SKenneth D. Merry */ 38*ef270ab1SKenneth D. Merry 39*ef270ab1SKenneth D. Merry 40*ef270ab1SKenneth D. Merry #if !defined(__OCS_H__) 41*ef270ab1SKenneth D. Merry #define __OCS_H__ 42*ef270ab1SKenneth D. Merry 43*ef270ab1SKenneth D. Merry #include "ocs_os.h" 44*ef270ab1SKenneth D. Merry #include "ocs_utils.h" 45*ef270ab1SKenneth D. Merry 46*ef270ab1SKenneth D. Merry #include "ocs_hw.h" 47*ef270ab1SKenneth D. Merry #include "ocs_scsi.h" 48*ef270ab1SKenneth D. Merry #include "ocs_io.h" 49*ef270ab1SKenneth D. Merry 50*ef270ab1SKenneth D. Merry #include "version.h" 51*ef270ab1SKenneth D. Merry 52*ef270ab1SKenneth D. Merry #define DRV_NAME "ocs_fc" 53*ef270ab1SKenneth D. Merry #define DRV_VERSION \ 54*ef270ab1SKenneth D. Merry STR_BE_MAJOR "." STR_BE_MINOR "." STR_BE_BUILD "." STR_BE_BRANCH 55*ef270ab1SKenneth D. Merry 56*ef270ab1SKenneth D. Merry /** 57*ef270ab1SKenneth D. Merry * @brief Interrupt context 58*ef270ab1SKenneth D. Merry */ 59*ef270ab1SKenneth D. Merry typedef struct ocs_intr_ctx_s { 60*ef270ab1SKenneth D. Merry uint32_t vec; /** Zero based interrupt vector */ 61*ef270ab1SKenneth D. Merry void *softc; /** software context for interrupt */ 62*ef270ab1SKenneth D. Merry char name[64]; /** label for this context */ 63*ef270ab1SKenneth D. Merry } ocs_intr_ctx_t; 64*ef270ab1SKenneth D. Merry 65*ef270ab1SKenneth D. Merry typedef struct ocs_fcport_s { 66*ef270ab1SKenneth D. Merry struct cam_sim *sim; 67*ef270ab1SKenneth D. Merry struct cam_path *path; 68*ef270ab1SKenneth D. Merry uint32_t role; 69*ef270ab1SKenneth D. Merry 70*ef270ab1SKenneth D. Merry ocs_tgt_resource_t targ_rsrc_wildcard; 71*ef270ab1SKenneth D. Merry ocs_tgt_resource_t targ_rsrc[OCS_MAX_LUN]; 72*ef270ab1SKenneth D. Merry ocs_vport_spec_t *vport; 73*ef270ab1SKenneth D. Merry } ocs_fcport; 74*ef270ab1SKenneth D. Merry 75*ef270ab1SKenneth D. Merry #define FCPORT(ocs, chan) (&((ocs_fcport *)(ocs)->fcports)[(chan)]) 76*ef270ab1SKenneth D. Merry 77*ef270ab1SKenneth D. Merry /** 78*ef270ab1SKenneth D. Merry * @brief Driver's context 79*ef270ab1SKenneth D. Merry */ 80*ef270ab1SKenneth D. Merry 81*ef270ab1SKenneth D. Merry struct ocs_softc { 82*ef270ab1SKenneth D. Merry 83*ef270ab1SKenneth D. Merry device_t dev; 84*ef270ab1SKenneth D. Merry struct cdev *cdev; 85*ef270ab1SKenneth D. Merry 86*ef270ab1SKenneth D. Merry ocs_pci_reg_t reg[PCI_MAX_BAR]; 87*ef270ab1SKenneth D. Merry 88*ef270ab1SKenneth D. Merry uint32_t instance_index; 89*ef270ab1SKenneth D. Merry const char *desc; 90*ef270ab1SKenneth D. Merry 91*ef270ab1SKenneth D. Merry uint32_t irqid; 92*ef270ab1SKenneth D. Merry struct resource *irq; 93*ef270ab1SKenneth D. Merry void *tag; 94*ef270ab1SKenneth D. Merry 95*ef270ab1SKenneth D. Merry ocs_intr_ctx_t intr_ctx; 96*ef270ab1SKenneth D. Merry uint32_t n_vec; 97*ef270ab1SKenneth D. Merry 98*ef270ab1SKenneth D. Merry bus_dma_tag_t dmat; /** Parent DMA tag */ 99*ef270ab1SKenneth D. Merry bus_dma_tag_t buf_dmat;/** IO buffer DMA tag */ 100*ef270ab1SKenneth D. Merry char display_name[OCS_DISPLAY_NAME_LENGTH]; 101*ef270ab1SKenneth D. Merry uint16_t pci_vendor; 102*ef270ab1SKenneth D. Merry uint16_t pci_device; 103*ef270ab1SKenneth D. Merry uint16_t pci_subsystem_vendor; 104*ef270ab1SKenneth D. Merry uint16_t pci_subsystem_device; 105*ef270ab1SKenneth D. Merry char businfo[16]; 106*ef270ab1SKenneth D. Merry const char *driver_version; 107*ef270ab1SKenneth D. Merry const char *fw_version; 108*ef270ab1SKenneth D. Merry const char *model; 109*ef270ab1SKenneth D. Merry 110*ef270ab1SKenneth D. Merry ocs_hw_t hw; 111*ef270ab1SKenneth D. Merry 112*ef270ab1SKenneth D. Merry ocs_rlock_t lock; /**< device wide lock */ 113*ef270ab1SKenneth D. Merry 114*ef270ab1SKenneth D. Merry ocs_xport_e ocs_xport; 115*ef270ab1SKenneth D. Merry ocs_xport_t *xport; /**< pointer to transport object */ 116*ef270ab1SKenneth D. Merry ocs_domain_t *domain; 117*ef270ab1SKenneth D. Merry ocs_list_t domain_list; 118*ef270ab1SKenneth D. Merry uint32_t domain_instance_count; 119*ef270ab1SKenneth D. Merry void (*domain_list_empty_cb)(ocs_t *ocs, void *arg); 120*ef270ab1SKenneth D. Merry void *domain_list_empty_cb_arg; 121*ef270ab1SKenneth D. Merry 122*ef270ab1SKenneth D. Merry uint8_t enable_ini; 123*ef270ab1SKenneth D. Merry uint8_t enable_tgt; 124*ef270ab1SKenneth D. Merry uint8_t fc_type; 125*ef270ab1SKenneth D. Merry int ctrlmask; 126*ef270ab1SKenneth D. Merry uint8_t explicit_buffer_list; 127*ef270ab1SKenneth D. Merry uint8_t external_loopback; 128*ef270ab1SKenneth D. Merry uint8_t skip_hw_teardown; 129*ef270ab1SKenneth D. Merry int speed; 130*ef270ab1SKenneth D. Merry int topology; 131*ef270ab1SKenneth D. Merry int ethernet_license; 132*ef270ab1SKenneth D. Merry int num_scsi_ios; 133*ef270ab1SKenneth D. Merry uint8_t enable_hlm; 134*ef270ab1SKenneth D. Merry uint32_t hlm_group_size; 135*ef270ab1SKenneth D. Merry uint32_t max_isr_time_msec; /*>> Maximum ISR time */ 136*ef270ab1SKenneth D. Merry uint32_t auto_xfer_rdy_size; /*>> Max sized write to use auto xfer rdy*/ 137*ef270ab1SKenneth D. Merry uint8_t esoc; 138*ef270ab1SKenneth D. Merry int logmask; 139*ef270ab1SKenneth D. Merry char *hw_war_version; 140*ef270ab1SKenneth D. Merry uint32_t num_vports; 141*ef270ab1SKenneth D. Merry uint32_t target_io_timer_sec; 142*ef270ab1SKenneth D. Merry uint32_t hw_bounce; 143*ef270ab1SKenneth D. Merry uint8_t rq_threads; 144*ef270ab1SKenneth D. Merry uint8_t rq_selection_policy; 145*ef270ab1SKenneth D. Merry uint8_t rr_quanta; 146*ef270ab1SKenneth D. Merry char *filter_def; 147*ef270ab1SKenneth D. Merry uint32_t max_remote_nodes; 148*ef270ab1SKenneth D. Merry 149*ef270ab1SKenneth D. Merry /* 150*ef270ab1SKenneth D. Merry * tgt_rscn_delay - delay in kicking off RSCN processing 151*ef270ab1SKenneth D. Merry * (nameserver queries) after receiving an RSCN on the target. 152*ef270ab1SKenneth D. Merry * This prevents thrashing of nameserver requests due to a huge burst of 153*ef270ab1SKenneth D. Merry * RSCNs received in a short period of time. 154*ef270ab1SKenneth D. Merry * Note: this is only valid when target RSCN handling is enabled -- see 155*ef270ab1SKenneth D. Merry * ctrlmask. 156*ef270ab1SKenneth D. Merry */ 157*ef270ab1SKenneth D. Merry time_t tgt_rscn_delay_msec; /*>> minimum target RSCN delay */ 158*ef270ab1SKenneth D. Merry 159*ef270ab1SKenneth D. Merry /* 160*ef270ab1SKenneth D. Merry * tgt_rscn_period - determines maximum frequency when processing 161*ef270ab1SKenneth D. Merry * back-to-back RSCNs; e.g. if this value is 30, there will never be 162*ef270ab1SKenneth D. Merry * any more than 1 RSCN handling per 30s window. This prevents 163*ef270ab1SKenneth D. Merry * initiators on a faulty link generating many RSCN from causing the 164*ef270ab1SKenneth D. Merry * target to continually query the nameserver. 165*ef270ab1SKenneth D. Merry * Note: This is only valid when target RSCN handling is enabled 166*ef270ab1SKenneth D. Merry */ 167*ef270ab1SKenneth D. Merry time_t tgt_rscn_period_msec; /*>> minimum target RSCN period */ 168*ef270ab1SKenneth D. Merry 169*ef270ab1SKenneth D. Merry uint32_t enable_task_set_full; 170*ef270ab1SKenneth D. Merry uint32_t io_in_use; 171*ef270ab1SKenneth D. Merry uint32_t io_high_watermark; /**< used to send task set full */ 172*ef270ab1SKenneth D. Merry struct mtx sim_lock; 173*ef270ab1SKenneth D. Merry uint32_t config_tgt:1, /**< Configured to support target mode */ 174*ef270ab1SKenneth D. Merry config_ini:1; /**< Configured to support initiator mode */ 175*ef270ab1SKenneth D. Merry 176*ef270ab1SKenneth D. Merry 177*ef270ab1SKenneth D. Merry uint32_t nodedb_mask; /**< Node debugging mask */ 178*ef270ab1SKenneth D. Merry 179*ef270ab1SKenneth D. Merry char modeldesc[64]; 180*ef270ab1SKenneth D. Merry char serialnum[64]; 181*ef270ab1SKenneth D. Merry char fwrev[64]; 182*ef270ab1SKenneth D. Merry char sli_intf[9]; 183*ef270ab1SKenneth D. Merry 184*ef270ab1SKenneth D. Merry ocs_ramlog_t *ramlog; 185*ef270ab1SKenneth D. Merry ocs_textbuf_t ddump_saved; 186*ef270ab1SKenneth D. Merry 187*ef270ab1SKenneth D. Merry ocs_mgmt_functions_t *mgmt_functions; 188*ef270ab1SKenneth D. Merry ocs_mgmt_functions_t *tgt_mgmt_functions; 189*ef270ab1SKenneth D. Merry ocs_mgmt_functions_t *ini_mgmt_functions; 190*ef270ab1SKenneth D. Merry 191*ef270ab1SKenneth D. Merry ocs_err_injection_e err_injection; 192*ef270ab1SKenneth D. Merry uint32_t cmd_err_inject; 193*ef270ab1SKenneth D. Merry time_t delay_value_msec; 194*ef270ab1SKenneth D. Merry 195*ef270ab1SKenneth D. Merry bool attached; 196*ef270ab1SKenneth D. Merry struct mtx dbg_lock; 197*ef270ab1SKenneth D. Merry 198*ef270ab1SKenneth D. Merry struct cam_devq *devq; 199*ef270ab1SKenneth D. Merry ocs_fcport *fcports; 200*ef270ab1SKenneth D. Merry 201*ef270ab1SKenneth D. Merry void* tgt_ocs; 202*ef270ab1SKenneth D. Merry }; 203*ef270ab1SKenneth D. Merry 204*ef270ab1SKenneth D. Merry static inline void 205*ef270ab1SKenneth D. Merry ocs_device_lock_init(ocs_t *ocs) 206*ef270ab1SKenneth D. Merry { 207*ef270ab1SKenneth D. Merry ocs_rlock_init(ocs, &ocs->lock, "ocsdevicelock"); 208*ef270ab1SKenneth D. Merry } 209*ef270ab1SKenneth D. Merry 210*ef270ab1SKenneth D. Merry static inline int32_t 211*ef270ab1SKenneth D. Merry ocs_device_lock_try(ocs_t *ocs) 212*ef270ab1SKenneth D. Merry { 213*ef270ab1SKenneth D. Merry return ocs_rlock_try(&ocs->lock); 214*ef270ab1SKenneth D. Merry } 215*ef270ab1SKenneth D. Merry 216*ef270ab1SKenneth D. Merry static inline void 217*ef270ab1SKenneth D. Merry ocs_device_lock(ocs_t *ocs) 218*ef270ab1SKenneth D. Merry { 219*ef270ab1SKenneth D. Merry ocs_rlock_acquire(&ocs->lock); 220*ef270ab1SKenneth D. Merry } 221*ef270ab1SKenneth D. Merry 222*ef270ab1SKenneth D. Merry static inline void 223*ef270ab1SKenneth D. Merry ocs_device_unlock(ocs_t *ocs) 224*ef270ab1SKenneth D. Merry { 225*ef270ab1SKenneth D. Merry ocs_rlock_release(&ocs->lock); 226*ef270ab1SKenneth D. Merry } 227*ef270ab1SKenneth D. Merry 228*ef270ab1SKenneth D. Merry static inline void 229*ef270ab1SKenneth D. Merry ocs_device_lock_free(ocs_t *ocs) 230*ef270ab1SKenneth D. Merry { 231*ef270ab1SKenneth D. Merry ocs_rlock_free(&ocs->lock); 232*ef270ab1SKenneth D. Merry } 233*ef270ab1SKenneth D. Merry 234*ef270ab1SKenneth D. Merry extern int32_t ocs_device_detach(ocs_t *ocs); 235*ef270ab1SKenneth D. Merry 236*ef270ab1SKenneth D. Merry extern int32_t ocs_device_attach(ocs_t *ocs); 237*ef270ab1SKenneth D. Merry 238*ef270ab1SKenneth D. Merry #define ocs_is_initiator_enabled() (ocs->enable_ini) 239*ef270ab1SKenneth D. Merry #define ocs_is_target_enabled() (ocs->enable_tgt) 240*ef270ab1SKenneth D. Merry 241*ef270ab1SKenneth D. Merry #include "ocs_xport.h" 242*ef270ab1SKenneth D. Merry #include "ocs_domain.h" 243*ef270ab1SKenneth D. Merry #include "ocs_sport.h" 244*ef270ab1SKenneth D. Merry #include "ocs_node.h" 245*ef270ab1SKenneth D. Merry #include "ocs_unsol.h" 246*ef270ab1SKenneth D. Merry #include "ocs_scsi.h" 247*ef270ab1SKenneth D. Merry #include "ocs_ioctl.h" 248*ef270ab1SKenneth D. Merry 249*ef270ab1SKenneth D. Merry static inline ocs_io_t * 250*ef270ab1SKenneth D. Merry ocs_io_alloc(ocs_t *ocs) 251*ef270ab1SKenneth D. Merry { 252*ef270ab1SKenneth D. Merry return ocs_io_pool_io_alloc(ocs->xport->io_pool); 253*ef270ab1SKenneth D. Merry } 254*ef270ab1SKenneth D. Merry 255*ef270ab1SKenneth D. Merry static inline void 256*ef270ab1SKenneth D. Merry ocs_io_free(ocs_t *ocs, ocs_io_t *io) 257*ef270ab1SKenneth D. Merry { 258*ef270ab1SKenneth D. Merry ocs_io_pool_io_free(ocs->xport->io_pool, io); 259*ef270ab1SKenneth D. Merry } 260*ef270ab1SKenneth D. Merry 261*ef270ab1SKenneth D. Merry #endif /* __OCS_H__ */ 262