1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include "oce_if.h" 44 extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE]; 45 46 /** 47 * @brief Reset (firmware) common function 48 * @param sc software handle to the device 49 * @returns 0 on success, ETIMEDOUT on failure 50 */ 51 int 52 oce_reset_fun(POCE_SOFTC sc) 53 { 54 struct oce_mbx *mbx; 55 struct oce_bmbx *mb; 56 struct ioctl_common_function_reset *fwcmd; 57 int rc = 0; 58 59 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) { 60 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 61 mbx = &mb->mbx; 62 bzero(mbx, sizeof(struct oce_mbx)); 63 64 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload; 65 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 66 MBX_SUBSYSTEM_COMMON, 67 OPCODE_COMMON_FUNCTION_RESET, 68 10, /* MBX_TIMEOUT_SEC */ 69 sizeof(struct 70 ioctl_common_function_reset), 71 OCE_MBX_VER_V0); 72 73 mbx->u0.s.embedded = 1; 74 mbx->payload_length = 75 sizeof(struct ioctl_common_function_reset); 76 77 rc = oce_mbox_dispatch(sc, 2); 78 } 79 80 return rc; 81 } 82 83 84 /** 85 * @brief This funtions tells firmware we are 86 * done with commands. 87 * @param sc software handle to the device 88 * @returns 0 on success, ETIMEDOUT on failure 89 */ 90 int 91 oce_fw_clean(POCE_SOFTC sc) 92 { 93 struct oce_bmbx *mbx; 94 uint8_t *ptr; 95 int ret = 0; 96 97 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 98 ptr = (uint8_t *) &mbx->mbx; 99 100 /* Endian Signature */ 101 *ptr++ = 0xff; 102 *ptr++ = 0xaa; 103 *ptr++ = 0xbb; 104 *ptr++ = 0xff; 105 *ptr++ = 0xff; 106 *ptr++ = 0xcc; 107 *ptr++ = 0xdd; 108 *ptr = 0xff; 109 110 ret = oce_mbox_dispatch(sc, 2); 111 112 return ret; 113 } 114 115 116 /** 117 * @brief Mailbox wait 118 * @param sc software handle to the device 119 * @param tmo_sec timeout in seconds 120 */ 121 static int 122 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec) 123 { 124 tmo_sec *= 10000; 125 pd_mpu_mbox_db_t mbox_db; 126 127 for (;;) { 128 if (tmo_sec != 0) { 129 if (--tmo_sec == 0) 130 break; 131 } 132 133 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB); 134 135 if (mbox_db.bits.ready) 136 return 0; 137 138 DELAY(100); 139 } 140 141 device_printf(sc->dev, "Mailbox timed out\n"); 142 143 return ETIMEDOUT; 144 } 145 146 147 /** 148 * @brief Mailbox dispatch 149 * @param sc software handle to the device 150 * @param tmo_sec timeout in seconds 151 */ 152 int 153 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec) 154 { 155 pd_mpu_mbox_db_t mbox_db; 156 uint32_t pa; 157 int rc; 158 159 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE); 160 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34); 161 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t)); 162 mbox_db.bits.ready = 0; 163 mbox_db.bits.hi = 1; 164 mbox_db.bits.address = pa; 165 166 rc = oce_mbox_wait(sc, tmo_sec); 167 if (rc == 0) { 168 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 169 170 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff; 171 mbox_db.bits.ready = 0; 172 mbox_db.bits.hi = 0; 173 mbox_db.bits.address = pa; 174 175 rc = oce_mbox_wait(sc, tmo_sec); 176 177 if (rc == 0) { 178 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 179 180 rc = oce_mbox_wait(sc, tmo_sec); 181 182 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE); 183 } 184 } 185 186 return rc; 187 } 188 189 190 191 /** 192 * @brief Mailbox common request header initialization 193 * @param hdr mailbox header 194 * @param dom domain 195 * @param port port 196 * @param subsys subsystem 197 * @param opcode opcode 198 * @param timeout timeout 199 * @param pyld_len payload length 200 */ 201 void 202 mbx_common_req_hdr_init(struct mbx_hdr *hdr, 203 uint8_t dom, uint8_t port, 204 uint8_t subsys, uint8_t opcode, 205 uint32_t timeout, uint32_t pyld_len, 206 uint8_t version) 207 { 208 hdr->u0.req.opcode = opcode; 209 hdr->u0.req.subsystem = subsys; 210 hdr->u0.req.port_number = port; 211 hdr->u0.req.domain = dom; 212 213 hdr->u0.req.timeout = timeout; 214 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr); 215 hdr->u0.req.version = version; 216 } 217 218 219 220 /** 221 * @brief Function to initialize the hw with host endian information 222 * @param sc software handle to the device 223 * @returns 0 on success, ETIMEDOUT on failure 224 */ 225 int 226 oce_mbox_init(POCE_SOFTC sc) 227 { 228 struct oce_bmbx *mbx; 229 uint8_t *ptr; 230 int ret = 0; 231 232 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) { 233 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 234 ptr = (uint8_t *) &mbx->mbx; 235 236 /* Endian Signature */ 237 *ptr++ = 0xff; 238 *ptr++ = 0x12; 239 *ptr++ = 0x34; 240 *ptr++ = 0xff; 241 *ptr++ = 0xff; 242 *ptr++ = 0x56; 243 *ptr++ = 0x78; 244 *ptr = 0xff; 245 246 ret = oce_mbox_dispatch(sc, 0); 247 } 248 249 return ret; 250 } 251 252 253 /** 254 * @brief Function to get the firmware version 255 * @param sc software handle to the device 256 * @returns 0 on success, EIO on failure 257 */ 258 int 259 oce_get_fw_version(POCE_SOFTC sc) 260 { 261 struct oce_mbx mbx; 262 struct mbx_get_common_fw_version *fwcmd; 263 int ret = 0; 264 265 bzero(&mbx, sizeof(struct oce_mbx)); 266 267 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload; 268 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 269 MBX_SUBSYSTEM_COMMON, 270 OPCODE_COMMON_GET_FW_VERSION, 271 MBX_TIMEOUT_SEC, 272 sizeof(struct mbx_get_common_fw_version), 273 OCE_MBX_VER_V0); 274 275 mbx.u0.s.embedded = 1; 276 mbx.payload_length = sizeof(struct mbx_get_common_fw_version); 277 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 278 279 ret = oce_mbox_post(sc, &mbx, NULL); 280 if (!ret) 281 ret = fwcmd->hdr.u0.rsp.status; 282 if (ret) { 283 device_printf(sc->dev, 284 "%s failed - cmd status: %d addi status: %d\n", 285 __FUNCTION__, ret, 286 fwcmd->hdr.u0.rsp.additional_status); 287 goto error; 288 } 289 290 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32); 291 error: 292 return ret; 293 } 294 295 296 /** 297 * @brief Firmware will send gracious notifications during 298 * attach only after sending first mcc commnad. We 299 * use MCC queue only for getting async and mailbox 300 * for sending cmds. So to get gracious notifications 301 * atleast send one dummy command on mcc. 302 */ 303 int 304 oce_first_mcc_cmd(POCE_SOFTC sc) 305 { 306 struct oce_mbx *mbx; 307 struct oce_mq *mq = sc->mq; 308 struct mbx_get_common_fw_version *fwcmd; 309 uint32_t reg_value; 310 311 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx); 312 bzero(mbx, sizeof(struct oce_mbx)); 313 314 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload; 315 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 316 MBX_SUBSYSTEM_COMMON, 317 OPCODE_COMMON_GET_FW_VERSION, 318 MBX_TIMEOUT_SEC, 319 sizeof(struct mbx_get_common_fw_version), 320 OCE_MBX_VER_V0); 321 mbx->u0.s.embedded = 1; 322 mbx->payload_length = sizeof(struct mbx_get_common_fw_version); 323 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map, 324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 325 RING_PUT(mq->ring, 1); 326 reg_value = (1 << 16) | mq->mq_id; 327 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value); 328 329 return 0; 330 } 331 332 /** 333 * @brief Function to post a MBX to the mbox 334 * @param sc software handle to the device 335 * @param mbx pointer to the MBX to send 336 * @param mbxctx pointer to the mbx context structure 337 * @returns 0 on success, error on failure 338 */ 339 int 340 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx) 341 { 342 struct oce_mbx *mb_mbx = NULL; 343 struct oce_mq_cqe *mb_cqe = NULL; 344 struct oce_bmbx *mb = NULL; 345 int rc = 0; 346 uint32_t tmo = 0; 347 uint32_t cstatus = 0; 348 uint32_t xstatus = 0; 349 350 LOCK(&sc->bmbx_lock); 351 352 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 353 mb_mbx = &mb->mbx; 354 355 /* get the tmo */ 356 tmo = mbx->tag[0]; 357 mbx->tag[0] = 0; 358 359 /* copy mbx into mbox */ 360 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx)); 361 362 /* now dispatch */ 363 rc = oce_mbox_dispatch(sc, tmo); 364 if (rc == 0) { 365 /* 366 * the command completed successfully. Now get the 367 * completion queue entry 368 */ 369 mb_cqe = &mb->cqe; 370 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe)); 371 372 /* copy mbox mbx back */ 373 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx)); 374 375 /* pick up the mailbox status */ 376 cstatus = mb_cqe->u0.s.completion_status; 377 xstatus = mb_cqe->u0.s.extended_status; 378 379 /* 380 * store the mbx context in the cqe tag section so that 381 * the upper layer handling the cqe can associate the mbx 382 * with the response 383 */ 384 if (cstatus == 0 && mbxctx) { 385 /* save context */ 386 mbxctx->mbx = mb_mbx; 387 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag, 388 sizeof(struct oce_mbx_ctx *)); 389 } 390 } 391 392 UNLOCK(&sc->bmbx_lock); 393 394 return rc; 395 } 396 397 /** 398 * @brief Function to read the mac address associated with an interface 399 * @param sc software handle to the device 400 * @param if_id interface id to read the address from 401 * @param perm set to 1 if reading the factory mac address. 402 * In this case if_id is ignored 403 * @param type type of the mac address, whether network or storage 404 * @param[out] mac [OUTPUT] pointer to a buffer containing the 405 * mac address when the command succeeds. 406 * @returns 0 on success, EIO on failure 407 */ 408 int 409 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, 410 uint8_t perm, uint8_t type, struct mac_address_format *mac) 411 { 412 struct oce_mbx mbx; 413 struct mbx_query_common_iface_mac *fwcmd; 414 int ret = 0; 415 416 bzero(&mbx, sizeof(struct oce_mbx)); 417 418 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload; 419 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 420 MBX_SUBSYSTEM_COMMON, 421 OPCODE_COMMON_QUERY_IFACE_MAC, 422 MBX_TIMEOUT_SEC, 423 sizeof(struct mbx_query_common_iface_mac), 424 OCE_MBX_VER_V0); 425 426 fwcmd->params.req.permanent = perm; 427 if (!perm) 428 fwcmd->params.req.if_id = (uint16_t) if_id; 429 else 430 fwcmd->params.req.if_id = 0; 431 432 fwcmd->params.req.type = type; 433 434 mbx.u0.s.embedded = 1; 435 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac); 436 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 437 438 ret = oce_mbox_post(sc, &mbx, NULL); 439 if (!ret) 440 ret = fwcmd->hdr.u0.rsp.status; 441 if (ret) { 442 device_printf(sc->dev, 443 "%s failed - cmd status: %d addi status: %d\n", 444 __FUNCTION__, ret, 445 fwcmd->hdr.u0.rsp.additional_status); 446 goto error; 447 } 448 449 /* copy the mac addres in the output parameter */ 450 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct; 451 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0], 452 mac->size_of_struct); 453 error: 454 return ret; 455 } 456 457 /** 458 * @brief Function to query the fw attributes from the hw 459 * @param sc software handle to the device 460 * @returns 0 on success, EIO on failure 461 */ 462 int 463 oce_get_fw_config(POCE_SOFTC sc) 464 { 465 struct oce_mbx mbx; 466 struct mbx_common_query_fw_config *fwcmd; 467 int ret = 0; 468 469 bzero(&mbx, sizeof(struct oce_mbx)); 470 471 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload; 472 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 473 MBX_SUBSYSTEM_COMMON, 474 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, 475 MBX_TIMEOUT_SEC, 476 sizeof(struct mbx_common_query_fw_config), 477 OCE_MBX_VER_V0); 478 479 mbx.u0.s.embedded = 1; 480 mbx.payload_length = sizeof(struct mbx_common_query_fw_config); 481 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 482 483 ret = oce_mbox_post(sc, &mbx, NULL); 484 if (!ret) 485 ret = fwcmd->hdr.u0.rsp.status; 486 if (ret) { 487 device_printf(sc->dev, 488 "%s failed - cmd status: %d addi status: %d\n", 489 __FUNCTION__, ret, 490 fwcmd->hdr.u0.rsp.additional_status); 491 goto error; 492 } 493 494 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config)); 495 496 sc->config_number = HOST_32(fwcmd->params.rsp.config_number); 497 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision); 498 sc->port_id = HOST_32(fwcmd->params.rsp.port_id); 499 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode); 500 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) == 501 (ULP_NIC_MODE | ULP_RDMA_MODE)) { 502 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED; 503 } 504 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps); 505 506 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) { 507 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot); 508 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot); 509 } else { 510 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot); 511 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot); 512 } 513 514 error: 515 return ret; 516 517 } 518 519 /** 520 * 521 * @brief function to create a device interface 522 * @param sc software handle to the device 523 * @param cap_flags capability flags 524 * @param en_flags enable capability flags 525 * @param vlan_tag optional vlan tag to associate with the if 526 * @param mac_addr pointer to a buffer containing the mac address 527 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the 528 interface created 529 * @returns 0 on success, EIO on failure 530 */ 531 int 532 oce_if_create(POCE_SOFTC sc, 533 uint32_t cap_flags, 534 uint32_t en_flags, 535 uint16_t vlan_tag, 536 uint8_t *mac_addr, 537 uint32_t *if_id) 538 { 539 struct oce_mbx mbx; 540 struct mbx_create_common_iface *fwcmd; 541 int rc = 0; 542 543 bzero(&mbx, sizeof(struct oce_mbx)); 544 545 fwcmd = (struct mbx_create_common_iface *)&mbx.payload; 546 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 547 MBX_SUBSYSTEM_COMMON, 548 OPCODE_COMMON_CREATE_IFACE, 549 MBX_TIMEOUT_SEC, 550 sizeof(struct mbx_create_common_iface), 551 OCE_MBX_VER_V0); 552 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr)); 553 554 fwcmd->params.req.version = 0; 555 fwcmd->params.req.cap_flags = LE_32(cap_flags); 556 fwcmd->params.req.enable_flags = LE_32(en_flags); 557 if (mac_addr != NULL) { 558 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6); 559 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag); 560 fwcmd->params.req.mac_invalid = 0; 561 } else { 562 fwcmd->params.req.mac_invalid = 1; 563 } 564 565 mbx.u0.s.embedded = 1; 566 mbx.payload_length = sizeof(struct mbx_create_common_iface); 567 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ); 568 569 rc = oce_mbox_post(sc, &mbx, NULL); 570 if (!rc) 571 rc = fwcmd->hdr.u0.rsp.status; 572 if (rc) { 573 device_printf(sc->dev, 574 "%s failed - cmd status: %d addi status: %d\n", 575 __FUNCTION__, rc, 576 fwcmd->hdr.u0.rsp.additional_status); 577 goto error; 578 } 579 580 *if_id = HOST_32(fwcmd->params.rsp.if_id); 581 582 if (mac_addr != NULL) 583 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id); 584 error: 585 return rc; 586 } 587 588 /** 589 * @brief Function to delete an interface 590 * @param sc software handle to the device 591 * @param if_id ID of the interface to delete 592 * @returns 0 on success, EIO on failure 593 */ 594 int 595 oce_if_del(POCE_SOFTC sc, uint32_t if_id) 596 { 597 struct oce_mbx mbx; 598 struct mbx_destroy_common_iface *fwcmd; 599 int rc = 0; 600 601 bzero(&mbx, sizeof(struct oce_mbx)); 602 603 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload; 604 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 605 MBX_SUBSYSTEM_COMMON, 606 OPCODE_COMMON_DESTROY_IFACE, 607 MBX_TIMEOUT_SEC, 608 sizeof(struct mbx_destroy_common_iface), 609 OCE_MBX_VER_V0); 610 611 fwcmd->params.req.if_id = if_id; 612 613 mbx.u0.s.embedded = 1; 614 mbx.payload_length = sizeof(struct mbx_destroy_common_iface); 615 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 616 617 rc = oce_mbox_post(sc, &mbx, NULL); 618 if (!rc) 619 rc = fwcmd->hdr.u0.rsp.status; 620 if (rc) 621 device_printf(sc->dev, 622 "%s failed - cmd status: %d addi status: %d\n", 623 __FUNCTION__, rc, 624 fwcmd->hdr.u0.rsp.additional_status); 625 return rc; 626 } 627 628 /** 629 * @brief Function to send the mbx command to configure vlan 630 * @param sc software handle to the device 631 * @param if_id interface identifier index 632 * @param vtag_arr array of vlan tags 633 * @param vtag_cnt number of elements in array 634 * @param untagged boolean TRUE/FLASE 635 * @param enable_promisc flag to enable/disable VLAN promiscuous mode 636 * @returns 0 on success, EIO on failure 637 */ 638 int 639 oce_config_vlan(POCE_SOFTC sc, 640 uint32_t if_id, 641 struct normal_vlan *vtag_arr, 642 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc) 643 { 644 struct oce_mbx mbx; 645 struct mbx_common_config_vlan *fwcmd; 646 int rc = 0; 647 648 if (sc->vlans_added > sc->max_vlans) 649 goto vlan_promisc; 650 651 bzero(&mbx, sizeof(struct oce_mbx)); 652 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload; 653 654 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 655 MBX_SUBSYSTEM_COMMON, 656 OPCODE_COMMON_CONFIG_IFACE_VLAN, 657 MBX_TIMEOUT_SEC, 658 sizeof(struct mbx_common_config_vlan), 659 OCE_MBX_VER_V0); 660 661 fwcmd->params.req.if_id = (uint8_t) if_id; 662 fwcmd->params.req.promisc = (uint8_t) enable_promisc; 663 fwcmd->params.req.untagged = (uint8_t) untagged; 664 fwcmd->params.req.num_vlans = vtag_cnt; 665 666 if (!enable_promisc) { 667 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans, 668 vtag_cnt * sizeof(struct normal_vlan)); 669 } 670 mbx.u0.s.embedded = 1; 671 mbx.payload_length = sizeof(struct mbx_common_config_vlan); 672 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length)); 673 674 rc = oce_mbox_post(sc, &mbx, NULL); 675 if (!rc) 676 rc = fwcmd->hdr.u0.rsp.status; 677 if (rc) 678 device_printf(sc->dev, 679 "%s failed - cmd status: %d addi status: %d\n", 680 __FUNCTION__, rc, 681 fwcmd->hdr.u0.rsp.additional_status); 682 683 goto done; 684 685 vlan_promisc: 686 /* Enable Vlan Promis */ 687 oce_rxf_set_promiscuous(sc, (1 << 1)); 688 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n"); 689 done: 690 return rc; 691 692 } 693 694 /** 695 * @brief Function to set flow control capability in the hardware 696 * @param sc software handle to the device 697 * @param flow_control flow control flags to set 698 * @returns 0 on success, EIO on failure 699 */ 700 int 701 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control) 702 { 703 struct oce_mbx mbx; 704 struct mbx_common_get_set_flow_control *fwcmd = 705 (struct mbx_common_get_set_flow_control *)&mbx.payload; 706 int rc; 707 708 bzero(&mbx, sizeof(struct oce_mbx)); 709 710 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 711 MBX_SUBSYSTEM_COMMON, 712 OPCODE_COMMON_SET_FLOW_CONTROL, 713 MBX_TIMEOUT_SEC, 714 sizeof(struct mbx_common_get_set_flow_control), 715 OCE_MBX_VER_V0); 716 717 if (flow_control & OCE_FC_TX) 718 fwcmd->tx_flow_control = 1; 719 720 if (flow_control & OCE_FC_RX) 721 fwcmd->rx_flow_control = 1; 722 723 mbx.u0.s.embedded = 1; 724 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control); 725 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 726 727 rc = oce_mbox_post(sc, &mbx, NULL); 728 if (!rc) 729 rc = fwcmd->hdr.u0.rsp.status; 730 if (rc) 731 device_printf(sc->dev, 732 "%s failed - cmd status: %d addi status: %d\n", 733 __FUNCTION__, rc, 734 fwcmd->hdr.u0.rsp.additional_status); 735 return rc; 736 } 737 738 /** 739 * @brief Initialize the RSS CPU indirection table 740 * 741 * The table is used to choose the queue to place the incomming packets. 742 * Incomming packets are hashed. The lowest bits in the hash result 743 * are used as the index into the CPU indirection table. 744 * Each entry in the table contains the RSS CPU-ID returned by the NIC 745 * create. Based on the CPU ID, the receive completion is routed to 746 * the corresponding RSS CQs. (Non-RSS packets are always completed 747 * on the default (0) CQ). 748 * 749 * @param sc software handle to the device 750 * @param *fwcmd pointer to the rss mbox command 751 * @returns none 752 */ 753 static int 754 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) 755 { 756 int i = 0, j = 0, rc = 0; 757 uint8_t *tbl = fwcmd->params.req.cputable; 758 struct oce_rq *rq = NULL; 759 760 761 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) { 762 for_all_rss_queues(sc, rq, i) { 763 if ((j + i) >= INDIRECTION_TABLE_ENTRIES) 764 break; 765 tbl[j + i] = rq->rss_cpuid; 766 } 767 } 768 if (i == 0) { 769 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n"); 770 rc = ENXIO; 771 772 } 773 774 /* fill log2 value indicating the size of the CPU table */ 775 if (rc == 0) 776 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES)); 777 778 return rc; 779 } 780 781 /** 782 * @brief Function to set flow control capability in the hardware 783 * @param sc software handle to the device 784 * @param if_id interface id to read the address from 785 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise 786 * @returns 0 on success, EIO on failure 787 */ 788 int 789 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss) 790 { 791 int rc; 792 struct oce_mbx mbx; 793 struct mbx_config_nic_rss *fwcmd = 794 (struct mbx_config_nic_rss *)&mbx.payload; 795 int version; 796 797 bzero(&mbx, sizeof(struct oce_mbx)); 798 799 if (IS_XE201(sc) || IS_SH(sc)) { 800 version = OCE_MBX_VER_V1; 801 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 | 802 RSS_ENABLE_UDP_IPV6; 803 } else 804 version = OCE_MBX_VER_V0; 805 806 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 807 MBX_SUBSYSTEM_NIC, 808 NIC_CONFIG_RSS, 809 MBX_TIMEOUT_SEC, 810 sizeof(struct mbx_config_nic_rss), 811 version); 812 if (enable_rss) 813 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 | 814 RSS_ENABLE_TCP_IPV4 | 815 RSS_ENABLE_IPV6 | 816 RSS_ENABLE_TCP_IPV6); 817 818 if(!sc->enable_hwlro) 819 fwcmd->params.req.flush = OCE_FLUSH; 820 else 821 fwcmd->params.req.flush = 0; 822 823 fwcmd->params.req.if_id = LE_32(if_id); 824 825 srandom(arc4random()); /* random entropy seed */ 826 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash)); 827 828 rc = oce_rss_itbl_init(sc, fwcmd); 829 if (rc == 0) { 830 mbx.u0.s.embedded = 1; 831 mbx.payload_length = sizeof(struct mbx_config_nic_rss); 832 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 833 834 rc = oce_mbox_post(sc, &mbx, NULL); 835 if (!rc) 836 rc = fwcmd->hdr.u0.rsp.status; 837 if (rc) 838 device_printf(sc->dev, 839 "%s failed - cmd status: %d addi status: %d\n", 840 __FUNCTION__, rc, 841 fwcmd->hdr.u0.rsp.additional_status); 842 } 843 return rc; 844 } 845 846 /** 847 * @brief RXF function to enable/disable device promiscuous mode 848 * @param sc software handle to the device 849 * @param enable enable/disable flag 850 * @returns 0 on success, EIO on failure 851 * @note 852 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer. 853 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead. 854 */ 855 int 856 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable) 857 { 858 struct mbx_set_common_iface_rx_filter *fwcmd; 859 int sz = sizeof(struct mbx_set_common_iface_rx_filter); 860 iface_rx_filter_ctx_t *req; 861 OCE_DMA_MEM sgl; 862 int rc; 863 864 /* allocate mbx payload's dma scatter/gather memory */ 865 rc = oce_dma_alloc(sc, sz, &sgl, 0); 866 if (rc) 867 return rc; 868 869 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter); 870 871 req = &fwcmd->params.req; 872 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS | 873 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 874 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */ 875 if (enable & 0x01) 876 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS; 877 878 if (enable & 0x02) 879 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 880 881 req->if_id = sc->if_id; 882 883 rc = oce_set_common_iface_rx_filter(sc, &sgl); 884 oce_dma_free(sc, &sgl); 885 886 return rc; 887 } 888 889 890 /** 891 * @brief Function modify and select rx filter options 892 * @param sc software handle to the device 893 * @param sgl scatter/gather request/response 894 * @returns 0 on success, error code on failure 895 */ 896 int 897 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl) 898 { 899 struct oce_mbx mbx; 900 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter); 901 struct mbx_set_common_iface_rx_filter *fwcmd; 902 int rc; 903 904 bzero(&mbx, sizeof(struct oce_mbx)); 905 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter); 906 907 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 908 MBX_SUBSYSTEM_COMMON, 909 OPCODE_COMMON_SET_IFACE_RX_FILTER, 910 MBX_TIMEOUT_SEC, 911 mbx_sz, 912 OCE_MBX_VER_V0); 913 914 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE); 915 mbx.u0.s.embedded = 0; 916 mbx.u0.s.sge_count = 1; 917 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr); 918 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr); 919 mbx.payload.u0.u1.sgl[0].length = mbx_sz; 920 mbx.payload_length = mbx_sz; 921 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 922 923 rc = oce_mbox_post(sc, &mbx, NULL); 924 if (!rc) 925 rc = fwcmd->hdr.u0.rsp.status; 926 if (rc) 927 device_printf(sc->dev, 928 "%s failed - cmd status: %d addi status: %d\n", 929 __FUNCTION__, rc, 930 fwcmd->hdr.u0.rsp.additional_status); 931 return rc; 932 } 933 934 /** 935 * @brief Function to query the link status from the hardware 936 * @param sc software handle to the device 937 * @param[out] link pointer to the structure returning link attributes 938 * @returns 0 on success, EIO on failure 939 */ 940 int 941 oce_get_link_status(POCE_SOFTC sc, struct link_status *link) 942 { 943 struct oce_mbx mbx; 944 struct mbx_query_common_link_config *fwcmd; 945 int rc = 0, version; 946 947 bzero(&mbx, sizeof(struct oce_mbx)); 948 949 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1); 950 951 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload; 952 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 953 MBX_SUBSYSTEM_COMMON, 954 OPCODE_COMMON_QUERY_LINK_CONFIG, 955 MBX_TIMEOUT_SEC, 956 sizeof(struct mbx_query_common_link_config), 957 version); 958 959 mbx.u0.s.embedded = 1; 960 mbx.payload_length = sizeof(struct mbx_query_common_link_config); 961 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 962 963 rc = oce_mbox_post(sc, &mbx, NULL); 964 965 if (!rc) 966 rc = fwcmd->hdr.u0.rsp.status; 967 if (rc) { 968 device_printf(sc->dev, 969 "%s failed - cmd status: %d addi status: %d\n", 970 __FUNCTION__, rc, 971 fwcmd->hdr.u0.rsp.additional_status); 972 goto error; 973 } 974 /* interpret response */ 975 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed); 976 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed; 977 link->logical_link_status = fwcmd->params.rsp.logical_link_status; 978 error: 979 return rc; 980 } 981 982 983 /** 984 * @brief Function to get NIC statistics 985 * @param sc software handle to the device 986 * @param *stats pointer to where to store statistics 987 * @param reset_stats resets statistics of set 988 * @returns 0 on success, EIO on failure 989 * @note command depricated in Lancer 990 */ 991 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \ 992 int \ 993 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \ 994 { \ 995 struct oce_mbx mbx; \ 996 struct mbx_get_nic_stats_v##version *fwcmd; \ 997 int rc = 0; \ 998 \ 999 bzero(&mbx, sizeof(struct oce_mbx)); \ 1000 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \ 1001 bzero(fwcmd, sizeof(*fwcmd)); \ 1002 \ 1003 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \ 1004 MBX_SUBSYSTEM_NIC, \ 1005 NIC_GET_STATS, \ 1006 MBX_TIMEOUT_SEC, \ 1007 sizeof(*fwcmd), \ 1008 OCE_MBX_VER_V##version); \ 1009 \ 1010 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \ 1011 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \ 1012 \ 1013 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \ 1014 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \ 1015 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \ 1016 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \ 1017 mbx.payload_length = sizeof(*fwcmd); \ 1018 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \ 1019 \ 1020 rc = oce_mbox_post(sc, &mbx, NULL); \ 1021 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \ 1022 if (!rc) \ 1023 rc = fwcmd->hdr.u0.rsp.status; \ 1024 if (rc) \ 1025 device_printf(sc->dev, \ 1026 "%s failed - cmd status: %d addi status: %d\n", \ 1027 __FUNCTION__, rc, \ 1028 fwcmd->hdr.u0.rsp.additional_status); \ 1029 return rc; \ 1030 } 1031 1032 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0); 1033 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1); 1034 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2); 1035 1036 1037 /** 1038 * @brief Function to get pport (physical port) statistics 1039 * @param sc software handle to the device 1040 * @param *stats pointer to where to store statistics 1041 * @param reset_stats resets statistics of set 1042 * @returns 0 on success, EIO on failure 1043 */ 1044 int 1045 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1046 uint32_t reset_stats) 1047 { 1048 struct oce_mbx mbx; 1049 struct mbx_get_pport_stats *fwcmd; 1050 int rc = 0; 1051 1052 bzero(&mbx, sizeof(struct oce_mbx)); 1053 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats); 1054 bzero(fwcmd, sizeof(struct mbx_get_pport_stats)); 1055 1056 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1057 MBX_SUBSYSTEM_NIC, 1058 NIC_GET_PPORT_STATS, 1059 MBX_TIMEOUT_SEC, 1060 sizeof(struct mbx_get_pport_stats), 1061 OCE_MBX_VER_V0); 1062 1063 fwcmd->params.req.reset_stats = reset_stats; 1064 fwcmd->params.req.port_number = sc->port_id; 1065 1066 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1067 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1068 1069 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1070 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1071 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1072 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats); 1073 1074 mbx.payload_length = sizeof(struct mbx_get_pport_stats); 1075 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1076 1077 rc = oce_mbox_post(sc, &mbx, NULL); 1078 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1079 1080 if (!rc) 1081 rc = fwcmd->hdr.u0.rsp.status; 1082 if (rc) 1083 device_printf(sc->dev, 1084 "%s failed - cmd status: %d addi status: %d\n", 1085 __FUNCTION__, rc, 1086 fwcmd->hdr.u0.rsp.additional_status); 1087 return rc; 1088 } 1089 1090 1091 /** 1092 * @brief Function to get vport (virtual port) statistics 1093 * @param sc software handle to the device 1094 * @param *stats pointer to where to store statistics 1095 * @param reset_stats resets statistics of set 1096 * @returns 0 on success, EIO on failure 1097 */ 1098 int 1099 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1100 uint32_t req_size, uint32_t reset_stats) 1101 { 1102 struct oce_mbx mbx; 1103 struct mbx_get_vport_stats *fwcmd; 1104 int rc = 0; 1105 1106 bzero(&mbx, sizeof(struct oce_mbx)); 1107 1108 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats); 1109 bzero(fwcmd, sizeof(struct mbx_get_vport_stats)); 1110 1111 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1112 MBX_SUBSYSTEM_NIC, 1113 NIC_GET_VPORT_STATS, 1114 MBX_TIMEOUT_SEC, 1115 sizeof(struct mbx_get_vport_stats), 1116 OCE_MBX_VER_V0); 1117 1118 fwcmd->params.req.reset_stats = reset_stats; 1119 fwcmd->params.req.vport_number = sc->if_id; 1120 1121 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1122 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1123 1124 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1125 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1126 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1127 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats); 1128 1129 mbx.payload_length = sizeof(struct mbx_get_vport_stats); 1130 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1131 1132 rc = oce_mbox_post(sc, &mbx, NULL); 1133 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1134 1135 if (!rc) 1136 rc = fwcmd->hdr.u0.rsp.status; 1137 if (rc) 1138 device_printf(sc->dev, 1139 "%s failed - cmd status: %d addi status: %d\n", 1140 __FUNCTION__, rc, 1141 fwcmd->hdr.u0.rsp.additional_status); 1142 return rc; 1143 } 1144 1145 1146 /** 1147 * @brief Function to update the muticast filter with 1148 * values in dma_mem 1149 * @param sc software handle to the device 1150 * @param dma_mem pointer to dma memory region 1151 * @returns 0 on success, EIO on failure 1152 */ 1153 int 1154 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem) 1155 { 1156 struct oce_mbx mbx; 1157 struct oce_mq_sge *sgl; 1158 struct mbx_set_common_iface_multicast *req = NULL; 1159 int rc = 0; 1160 1161 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast); 1162 mbx_common_req_hdr_init(&req->hdr, 0, 0, 1163 MBX_SUBSYSTEM_COMMON, 1164 OPCODE_COMMON_SET_IFACE_MULTICAST, 1165 MBX_TIMEOUT_SEC, 1166 sizeof(struct mbx_set_common_iface_multicast), 1167 OCE_MBX_VER_V0); 1168 1169 bzero(&mbx, sizeof(struct oce_mbx)); 1170 1171 mbx.u0.s.embedded = 0; /*Non embeded*/ 1172 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast); 1173 mbx.u0.s.sge_count = 1; 1174 sgl = &mbx.payload.u0.u1.sgl[0]; 1175 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr)); 1176 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF); 1177 sgl->length = htole32(mbx.payload_length); 1178 1179 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1180 1181 rc = oce_mbox_post(sc, &mbx, NULL); 1182 if (!rc) 1183 rc = req->hdr.u0.rsp.status; 1184 if (rc) 1185 device_printf(sc->dev, 1186 "%s failed - cmd status: %d addi status: %d\n", 1187 __FUNCTION__, rc, 1188 req->hdr.u0.rsp.additional_status); 1189 return rc; 1190 } 1191 1192 1193 /** 1194 * @brief Function to send passthrough Ioctls 1195 * @param sc software handle to the device 1196 * @param dma_mem pointer to dma memory region 1197 * @param req_size size of dma_mem 1198 * @returns 0 on success, EIO on failure 1199 */ 1200 int 1201 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size) 1202 { 1203 struct oce_mbx mbx; 1204 struct oce_mq_sge *sgl; 1205 int rc = 0; 1206 1207 bzero(&mbx, sizeof(struct oce_mbx)); 1208 1209 mbx.u0.s.embedded = 0; /*Non embeded*/ 1210 mbx.payload_length = req_size; 1211 mbx.u0.s.sge_count = 1; 1212 sgl = &mbx.payload.u0.u1.sgl[0]; 1213 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr)); 1214 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF); 1215 sgl->length = htole32(req_size); 1216 1217 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1218 1219 rc = oce_mbox_post(sc, &mbx, NULL); 1220 return rc; 1221 } 1222 1223 1224 int 1225 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1226 uint32_t if_id, uint32_t *pmac_id) 1227 { 1228 struct oce_mbx mbx; 1229 struct mbx_add_common_iface_mac *fwcmd; 1230 int rc = 0; 1231 1232 bzero(&mbx, sizeof(struct oce_mbx)); 1233 1234 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload; 1235 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1236 MBX_SUBSYSTEM_COMMON, 1237 OPCODE_COMMON_ADD_IFACE_MAC, 1238 MBX_TIMEOUT_SEC, 1239 sizeof(struct mbx_add_common_iface_mac), 1240 OCE_MBX_VER_V0); 1241 1242 fwcmd->params.req.if_id = (uint16_t) if_id; 1243 bcopy(mac_addr, fwcmd->params.req.mac_address, 6); 1244 1245 mbx.u0.s.embedded = 1; 1246 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac); 1247 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1248 rc = oce_mbox_post(sc, &mbx, NULL); 1249 if (!rc) 1250 rc = fwcmd->hdr.u0.rsp.status; 1251 if (rc) { 1252 device_printf(sc->dev, 1253 "%s failed - cmd status: %d addi status: %d\n", 1254 __FUNCTION__, rc, 1255 fwcmd->hdr.u0.rsp.additional_status); 1256 goto error; 1257 } 1258 *pmac_id = fwcmd->params.rsp.pmac_id; 1259 error: 1260 return rc; 1261 } 1262 1263 1264 int 1265 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id) 1266 { 1267 struct oce_mbx mbx; 1268 struct mbx_del_common_iface_mac *fwcmd; 1269 int rc = 0; 1270 1271 bzero(&mbx, sizeof(struct oce_mbx)); 1272 1273 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload; 1274 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1275 MBX_SUBSYSTEM_COMMON, 1276 OPCODE_COMMON_DEL_IFACE_MAC, 1277 MBX_TIMEOUT_SEC, 1278 sizeof(struct mbx_del_common_iface_mac), 1279 OCE_MBX_VER_V0); 1280 1281 fwcmd->params.req.if_id = (uint16_t)if_id; 1282 fwcmd->params.req.pmac_id = pmac_id; 1283 1284 mbx.u0.s.embedded = 1; 1285 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac); 1286 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1287 1288 rc = oce_mbox_post(sc, &mbx, NULL); 1289 if (!rc) 1290 rc = fwcmd->hdr.u0.rsp.status; 1291 if (rc) 1292 device_printf(sc->dev, 1293 "%s failed - cmd status: %d addi status: %d\n", 1294 __FUNCTION__, rc, 1295 fwcmd->hdr.u0.rsp.additional_status); 1296 return rc; 1297 } 1298 1299 1300 1301 int 1302 oce_mbox_check_native_mode(POCE_SOFTC sc) 1303 { 1304 struct oce_mbx mbx; 1305 struct mbx_common_set_function_cap *fwcmd; 1306 int rc = 0; 1307 1308 bzero(&mbx, sizeof(struct oce_mbx)); 1309 1310 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload; 1311 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1312 MBX_SUBSYSTEM_COMMON, 1313 OPCODE_COMMON_SET_FUNCTIONAL_CAPS, 1314 MBX_TIMEOUT_SEC, 1315 sizeof(struct mbx_common_set_function_cap), 1316 OCE_MBX_VER_V0); 1317 1318 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS | 1319 CAP_BE3_NATIVE_ERX_API; 1320 1321 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API; 1322 1323 mbx.u0.s.embedded = 1; 1324 mbx.payload_length = sizeof(struct mbx_common_set_function_cap); 1325 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1326 1327 rc = oce_mbox_post(sc, &mbx, NULL); 1328 if (!rc) 1329 rc = fwcmd->hdr.u0.rsp.status; 1330 if (rc) { 1331 device_printf(sc->dev, 1332 "%s failed - cmd status: %d addi status: %d\n", 1333 __FUNCTION__, rc, 1334 fwcmd->hdr.u0.rsp.additional_status); 1335 goto error; 1336 } 1337 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags) 1338 & CAP_BE3_NATIVE_ERX_API; 1339 1340 error: 1341 return 0; 1342 } 1343 1344 1345 1346 int 1347 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1348 uint8_t loopback_type, uint8_t enable) 1349 { 1350 struct oce_mbx mbx; 1351 struct mbx_lowlevel_set_loopback_mode *fwcmd; 1352 int rc = 0; 1353 1354 1355 bzero(&mbx, sizeof(struct oce_mbx)); 1356 1357 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload; 1358 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1359 MBX_SUBSYSTEM_LOWLEVEL, 1360 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, 1361 MBX_TIMEOUT_SEC, 1362 sizeof(struct mbx_lowlevel_set_loopback_mode), 1363 OCE_MBX_VER_V0); 1364 1365 fwcmd->params.req.src_port = port_num; 1366 fwcmd->params.req.dest_port = port_num; 1367 fwcmd->params.req.loopback_type = loopback_type; 1368 fwcmd->params.req.loopback_state = enable; 1369 1370 mbx.u0.s.embedded = 1; 1371 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode); 1372 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1373 1374 rc = oce_mbox_post(sc, &mbx, NULL); 1375 if (!rc) 1376 rc = fwcmd->hdr.u0.rsp.status; 1377 if (rc) 1378 device_printf(sc->dev, 1379 "%s failed - cmd status: %d addi status: %d\n", 1380 __FUNCTION__, rc, 1381 fwcmd->hdr.u0.rsp.additional_status); 1382 1383 return rc; 1384 1385 } 1386 1387 int 1388 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1389 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1390 uint64_t pattern) 1391 { 1392 1393 struct oce_mbx mbx; 1394 struct mbx_lowlevel_test_loopback_mode *fwcmd; 1395 int rc = 0; 1396 1397 1398 bzero(&mbx, sizeof(struct oce_mbx)); 1399 1400 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload; 1401 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1402 MBX_SUBSYSTEM_LOWLEVEL, 1403 OPCODE_LOWLEVEL_TEST_LOOPBACK, 1404 MBX_TIMEOUT_SEC, 1405 sizeof(struct mbx_lowlevel_test_loopback_mode), 1406 OCE_MBX_VER_V0); 1407 1408 fwcmd->params.req.pattern = pattern; 1409 fwcmd->params.req.src_port = port_num; 1410 fwcmd->params.req.dest_port = port_num; 1411 fwcmd->params.req.pkt_size = pkt_size; 1412 fwcmd->params.req.num_pkts = num_pkts; 1413 fwcmd->params.req.loopback_type = loopback_type; 1414 1415 mbx.u0.s.embedded = 1; 1416 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode); 1417 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1418 1419 rc = oce_mbox_post(sc, &mbx, NULL); 1420 if (!rc) 1421 rc = fwcmd->hdr.u0.rsp.status; 1422 if (rc) 1423 device_printf(sc->dev, 1424 "%s failed - cmd status: %d addi status: %d\n", 1425 __FUNCTION__, rc, 1426 fwcmd->hdr.u0.rsp.additional_status); 1427 1428 return rc; 1429 } 1430 1431 int 1432 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1433 POCE_DMA_MEM pdma_mem, uint32_t num_bytes) 1434 { 1435 1436 struct oce_mbx mbx; 1437 struct oce_mq_sge *sgl = NULL; 1438 struct mbx_common_read_write_flashrom *fwcmd = NULL; 1439 int rc = 0, payload_len = 0; 1440 1441 bzero(&mbx, sizeof(struct oce_mbx)); 1442 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom); 1443 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024; 1444 1445 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1446 MBX_SUBSYSTEM_COMMON, 1447 OPCODE_COMMON_WRITE_FLASHROM, 1448 LONG_TIMEOUT, 1449 payload_len, 1450 OCE_MBX_VER_V0); 1451 1452 fwcmd->flash_op_type = LE_32(optype); 1453 fwcmd->flash_op_code = LE_32(opcode); 1454 fwcmd->data_buffer_size = LE_32(num_bytes); 1455 1456 mbx.u0.s.embedded = 0; /*Non embeded*/ 1457 mbx.payload_length = payload_len; 1458 mbx.u0.s.sge_count = 1; 1459 1460 sgl = &mbx.payload.u0.u1.sgl[0]; 1461 sgl->pa_hi = upper_32_bits(pdma_mem->paddr); 1462 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF; 1463 sgl->length = payload_len; 1464 1465 /* post the command */ 1466 rc = oce_mbox_post(sc, &mbx, NULL); 1467 if (!rc) 1468 rc = fwcmd->hdr.u0.rsp.status; 1469 if (rc) 1470 device_printf(sc->dev, 1471 "%s failed - cmd status: %d addi status: %d\n", 1472 __FUNCTION__, rc, 1473 fwcmd->hdr.u0.rsp.additional_status); 1474 1475 return rc; 1476 1477 } 1478 1479 int 1480 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1481 uint32_t offset, uint32_t optype) 1482 { 1483 1484 int rc = 0, payload_len = 0; 1485 struct oce_mbx mbx; 1486 struct mbx_common_read_write_flashrom *fwcmd; 1487 1488 bzero(&mbx, sizeof(struct oce_mbx)); 1489 1490 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload; 1491 1492 /* Firmware requires extra 4 bytes with this ioctl. Since there 1493 is enough room in the mbx payload it should be good enough 1494 Reference: Bug 14853 1495 */ 1496 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4; 1497 1498 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1499 MBX_SUBSYSTEM_COMMON, 1500 OPCODE_COMMON_READ_FLASHROM, 1501 MBX_TIMEOUT_SEC, 1502 payload_len, 1503 OCE_MBX_VER_V0); 1504 1505 fwcmd->flash_op_type = optype; 1506 fwcmd->flash_op_code = FLASHROM_OPER_REPORT; 1507 fwcmd->data_offset = offset; 1508 fwcmd->data_buffer_size = 0x4; 1509 1510 mbx.u0.s.embedded = 1; 1511 mbx.payload_length = payload_len; 1512 1513 /* post the command */ 1514 rc = oce_mbox_post(sc, &mbx, NULL); 1515 if (!rc) 1516 rc = fwcmd->hdr.u0.rsp.status; 1517 if (rc) { 1518 device_printf(sc->dev, 1519 "%s failed - cmd status: %d addi status: %d\n", 1520 __FUNCTION__, rc, 1521 fwcmd->hdr.u0.rsp.additional_status); 1522 goto error; 1523 } 1524 bcopy(fwcmd->data_buffer, flash_crc, 4); 1525 error: 1526 return rc; 1527 } 1528 1529 int 1530 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info) 1531 { 1532 1533 struct oce_mbx mbx; 1534 struct mbx_common_phy_info *fwcmd; 1535 int rc = 0; 1536 1537 bzero(&mbx, sizeof(struct oce_mbx)); 1538 1539 fwcmd = (struct mbx_common_phy_info *)&mbx.payload; 1540 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1541 MBX_SUBSYSTEM_COMMON, 1542 OPCODE_COMMON_GET_PHY_CONFIG, 1543 MBX_TIMEOUT_SEC, 1544 sizeof(struct mbx_common_phy_info), 1545 OCE_MBX_VER_V0); 1546 1547 mbx.u0.s.embedded = 1; 1548 mbx.payload_length = sizeof(struct mbx_common_phy_info); 1549 1550 /* now post the command */ 1551 rc = oce_mbox_post(sc, &mbx, NULL); 1552 if (!rc) 1553 rc = fwcmd->hdr.u0.rsp.status; 1554 if (rc) { 1555 device_printf(sc->dev, 1556 "%s failed - cmd status: %d addi status: %d\n", 1557 __FUNCTION__, rc, 1558 fwcmd->hdr.u0.rsp.additional_status); 1559 goto error; 1560 } 1561 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type); 1562 phy_info->interface_type = 1563 HOST_16(fwcmd->params.rsp.phy_info.interface_type); 1564 phy_info->auto_speeds_supported = 1565 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported); 1566 phy_info->fixed_speeds_supported = 1567 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported); 1568 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params); 1569 error: 1570 return rc; 1571 1572 } 1573 1574 1575 int 1576 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1577 uint32_t data_offset, POCE_DMA_MEM pdma_mem, 1578 uint32_t *written_data, uint32_t *additional_status) 1579 { 1580 1581 struct oce_mbx mbx; 1582 struct mbx_lancer_common_write_object *fwcmd = NULL; 1583 int rc = 0, payload_len = 0; 1584 1585 bzero(&mbx, sizeof(struct oce_mbx)); 1586 payload_len = sizeof(struct mbx_lancer_common_write_object); 1587 1588 mbx.u0.s.embedded = 1;/* Embedded */ 1589 mbx.payload_length = payload_len; 1590 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload; 1591 1592 /* initialize the ioctl header */ 1593 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0, 1594 MBX_SUBSYSTEM_COMMON, 1595 OPCODE_COMMON_WRITE_OBJECT, 1596 LONG_TIMEOUT, 1597 payload_len, 1598 OCE_MBX_VER_V0); 1599 1600 fwcmd->params.req.write_length = data_size; 1601 if (data_size == 0) 1602 fwcmd->params.req.eof = 1; 1603 else 1604 fwcmd->params.req.eof = 0; 1605 1606 strcpy(fwcmd->params.req.object_name, "/prg"); 1607 fwcmd->params.req.descriptor_count = 1; 1608 fwcmd->params.req.write_offset = data_offset; 1609 fwcmd->params.req.buffer_length = data_size; 1610 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF; 1611 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr); 1612 1613 /* post the command */ 1614 rc = oce_mbox_post(sc, &mbx, NULL); 1615 if (!rc) 1616 rc = fwcmd->params.rsp.status; 1617 if (rc) { 1618 device_printf(sc->dev, 1619 "%s failed - cmd status: %d addi status: %d\n", 1620 __FUNCTION__, rc, 1621 fwcmd->params.rsp.additional_status); 1622 goto error; 1623 } 1624 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length); 1625 *additional_status = fwcmd->params.rsp.additional_status; 1626 error: 1627 return rc; 1628 1629 } 1630 1631 1632 1633 int 1634 oce_mbox_create_rq(struct oce_rq *rq) 1635 { 1636 1637 struct oce_mbx mbx; 1638 struct mbx_create_nic_rq *fwcmd; 1639 POCE_SOFTC sc = rq->parent; 1640 int rc, num_pages = 0; 1641 1642 if (rq->qstate == QCREATED) 1643 return 0; 1644 1645 bzero(&mbx, sizeof(struct oce_mbx)); 1646 1647 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload; 1648 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1649 MBX_SUBSYSTEM_NIC, 1650 NIC_CREATE_RQ, MBX_TIMEOUT_SEC, 1651 sizeof(struct mbx_create_nic_rq), 1652 OCE_MBX_VER_V0); 1653 1654 /* oce_page_list will also prepare pages */ 1655 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 1656 1657 if (IS_XE201(sc)) { 1658 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 1659 fwcmd->params.req.page_size = 1; 1660 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1; 1661 } else 1662 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size); 1663 fwcmd->params.req.num_pages = num_pages; 1664 fwcmd->params.req.cq_id = rq->cq->cq_id; 1665 fwcmd->params.req.if_id = sc->if_id; 1666 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 1667 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue; 1668 1669 mbx.u0.s.embedded = 1; 1670 mbx.payload_length = sizeof(struct mbx_create_nic_rq); 1671 1672 rc = oce_mbox_post(sc, &mbx, NULL); 1673 if (!rc) 1674 rc = fwcmd->hdr.u0.rsp.status; 1675 if (rc) { 1676 device_printf(sc->dev, 1677 "%s failed - cmd status: %d addi status: %d\n", 1678 __FUNCTION__, rc, 1679 fwcmd->hdr.u0.rsp.additional_status); 1680 goto error; 1681 } 1682 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 1683 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 1684 error: 1685 return rc; 1686 1687 } 1688 1689 1690 1691 int 1692 oce_mbox_create_wq(struct oce_wq *wq) 1693 { 1694 struct oce_mbx mbx; 1695 struct mbx_create_nic_wq *fwcmd; 1696 POCE_SOFTC sc = wq->parent; 1697 int rc = 0, version, num_pages; 1698 1699 bzero(&mbx, sizeof(struct oce_mbx)); 1700 1701 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload; 1702 if (IS_XE201(sc)) 1703 version = OCE_MBX_VER_V1; 1704 else if(IS_BE(sc)) 1705 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2) 1706 : (version = OCE_MBX_VER_V0); 1707 else 1708 version = OCE_MBX_VER_V2; 1709 1710 if (version > OCE_MBX_VER_V0) 1711 fwcmd->params.req.if_id = sc->if_id; 1712 1713 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1714 MBX_SUBSYSTEM_NIC, 1715 NIC_CREATE_WQ, MBX_TIMEOUT_SEC, 1716 sizeof(struct mbx_create_nic_wq), 1717 version); 1718 1719 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]); 1720 1721 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type; 1722 fwcmd->params.req.num_pages = num_pages; 1723 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1; 1724 fwcmd->params.req.cq_id = wq->cq->cq_id; 1725 fwcmd->params.req.ulp_num = 1; 1726 1727 mbx.u0.s.embedded = 1; 1728 mbx.payload_length = sizeof(struct mbx_create_nic_wq); 1729 1730 rc = oce_mbox_post(sc, &mbx, NULL); 1731 if (!rc) 1732 rc = fwcmd->hdr.u0.rsp.status; 1733 if (rc) { 1734 device_printf(sc->dev, 1735 "%s failed - cmd status: %d addi status: %d\n", 1736 __FUNCTION__, rc, 1737 fwcmd->hdr.u0.rsp.additional_status); 1738 goto error; 1739 } 1740 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id); 1741 if (version == OCE_MBX_VER_V2) 1742 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset); 1743 else 1744 wq->db_offset = PD_TXULP_DB; 1745 error: 1746 return rc; 1747 1748 } 1749 1750 1751 1752 int 1753 oce_mbox_create_eq(struct oce_eq *eq) 1754 { 1755 struct oce_mbx mbx; 1756 struct mbx_create_common_eq *fwcmd; 1757 POCE_SOFTC sc = eq->parent; 1758 int rc = 0; 1759 uint32_t num_pages; 1760 1761 bzero(&mbx, sizeof(struct oce_mbx)); 1762 1763 fwcmd = (struct mbx_create_common_eq *)&mbx.payload; 1764 1765 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1766 MBX_SUBSYSTEM_COMMON, 1767 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC, 1768 sizeof(struct mbx_create_common_eq), 1769 OCE_MBX_VER_V0); 1770 1771 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]); 1772 fwcmd->params.req.ctx.num_pages = num_pages; 1773 fwcmd->params.req.ctx.valid = 1; 1774 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1; 1775 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256); 1776 fwcmd->params.req.ctx.armed = 0; 1777 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd; 1778 1779 1780 mbx.u0.s.embedded = 1; 1781 mbx.payload_length = sizeof(struct mbx_create_common_eq); 1782 1783 rc = oce_mbox_post(sc, &mbx, NULL); 1784 if (!rc) 1785 rc = fwcmd->hdr.u0.rsp.status; 1786 if (rc) { 1787 device_printf(sc->dev, 1788 "%s failed - cmd status: %d addi status: %d\n", 1789 __FUNCTION__, rc, 1790 fwcmd->hdr.u0.rsp.additional_status); 1791 goto error; 1792 } 1793 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id); 1794 error: 1795 return rc; 1796 } 1797 1798 1799 1800 int 1801 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable) 1802 { 1803 struct oce_mbx mbx; 1804 struct mbx_create_common_cq *fwcmd; 1805 POCE_SOFTC sc = cq->parent; 1806 uint8_t version; 1807 oce_cq_ctx_t *ctx; 1808 uint32_t num_pages, page_size; 1809 int rc = 0; 1810 1811 1812 bzero(&mbx, sizeof(struct oce_mbx)); 1813 1814 fwcmd = (struct mbx_create_common_cq *)&mbx.payload; 1815 1816 if (IS_XE201(sc)) 1817 version = OCE_MBX_VER_V2; 1818 else 1819 version = OCE_MBX_VER_V0; 1820 1821 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1822 MBX_SUBSYSTEM_COMMON, 1823 OPCODE_COMMON_CREATE_CQ, 1824 MBX_TIMEOUT_SEC, 1825 sizeof(struct mbx_create_common_cq), 1826 version); 1827 1828 ctx = &fwcmd->params.req.cq_ctx; 1829 1830 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]); 1831 page_size = 1; /* 1 for 4K */ 1832 1833 if (version == OCE_MBX_VER_V2) { 1834 ctx->v2.num_pages = LE_16(num_pages); 1835 ctx->v2.page_size = page_size; 1836 ctx->v2.eventable = is_eventable; 1837 ctx->v2.valid = 1; 1838 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1839 ctx->v2.nodelay = cq->cq_cfg.nodelay; 1840 ctx->v2.coalesce_wm = ncoalesce; 1841 ctx->v2.armed = 0; 1842 ctx->v2.eq_id = cq->eq->eq_id; 1843 if (ctx->v2.count == 3) { 1844 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1) 1845 ctx->v2.cqe_count = (4*1024)-1; 1846 else 1847 ctx->v2.cqe_count = cq->cq_cfg.q_len; 1848 } 1849 } else { 1850 ctx->v0.num_pages = LE_16(num_pages); 1851 ctx->v0.eventable = is_eventable; 1852 ctx->v0.valid = 1; 1853 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1854 ctx->v0.nodelay = cq->cq_cfg.nodelay; 1855 ctx->v0.coalesce_wm = ncoalesce; 1856 ctx->v0.armed = 0; 1857 ctx->v0.eq_id = cq->eq->eq_id; 1858 } 1859 1860 mbx.u0.s.embedded = 1; 1861 mbx.payload_length = sizeof(struct mbx_create_common_cq); 1862 1863 rc = oce_mbox_post(sc, &mbx, NULL); 1864 if (!rc) 1865 rc = fwcmd->hdr.u0.rsp.status; 1866 if (rc) { 1867 device_printf(sc->dev, 1868 "%s failed - cmd status: %d addi status: %d\n", 1869 __FUNCTION__, rc, 1870 fwcmd->hdr.u0.rsp.additional_status); 1871 goto error; 1872 } 1873 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id); 1874 error: 1875 return rc; 1876 1877 } 1878 1879 int 1880 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num) 1881 { 1882 int rc = 0; 1883 struct oce_mbx mbx; 1884 struct mbx_read_common_transrecv_data *fwcmd; 1885 struct oce_mq_sge *sgl; 1886 OCE_DMA_MEM dma; 1887 1888 /* Allocate DMA mem*/ 1889 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data), 1890 &dma, 0)) 1891 return ENOMEM; 1892 1893 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data); 1894 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data)); 1895 1896 bzero(&mbx, sizeof(struct oce_mbx)); 1897 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1898 MBX_SUBSYSTEM_COMMON, 1899 OPCODE_COMMON_READ_TRANSRECEIVER_DATA, 1900 MBX_TIMEOUT_SEC, 1901 sizeof(struct mbx_read_common_transrecv_data), 1902 OCE_MBX_VER_V0); 1903 1904 /* fill rest of mbx */ 1905 mbx.u0.s.embedded = 0; 1906 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data); 1907 mbx.u0.s.sge_count = 1; 1908 sgl = &mbx.payload.u0.u1.sgl[0]; 1909 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 1910 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 1911 sgl->length = htole32(mbx.payload_length); 1912 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1913 1914 fwcmd->params.req.port = LE_32(sc->port_id); 1915 fwcmd->params.req.page_num = LE_32(page_num); 1916 1917 /* command post */ 1918 rc = oce_mbox_post(sc, &mbx, NULL); 1919 if (!rc) 1920 rc = fwcmd->hdr.u0.rsp.status; 1921 if (rc) { 1922 device_printf(sc->dev, 1923 "%s failed - cmd status: %d addi status: %d\n", 1924 __FUNCTION__, rc, 1925 fwcmd->hdr.u0.rsp.additional_status); 1926 goto error; 1927 } 1928 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0) 1929 { 1930 bcopy((char *)fwcmd->params.rsp.page_data, 1931 (char *)&sfp_vpd_dump_buffer[0], 1932 TRANSCEIVER_A0_SIZE); 1933 } 1934 1935 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2) 1936 { 1937 bcopy((char *)fwcmd->params.rsp.page_data, 1938 (char *)&sfp_vpd_dump_buffer[32], 1939 TRANSCEIVER_A2_SIZE); 1940 } 1941 error: 1942 oce_dma_free(sc, &dma); 1943 return rc; 1944 } 1945 1946 void 1947 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1948 int num) 1949 { 1950 struct oce_mbx mbx; 1951 struct mbx_modify_common_eq_delay *fwcmd; 1952 int rc = 0; 1953 int i = 0; 1954 1955 bzero(&mbx, sizeof(struct oce_mbx)); 1956 1957 /* Initialize MODIFY_EQ_DELAY ioctl header */ 1958 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload; 1959 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1960 MBX_SUBSYSTEM_COMMON, 1961 OPCODE_COMMON_MODIFY_EQ_DELAY, 1962 MBX_TIMEOUT_SEC, 1963 sizeof(struct mbx_modify_common_eq_delay), 1964 OCE_MBX_VER_V0); 1965 /* fill rest of mbx */ 1966 mbx.u0.s.embedded = 1; 1967 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay); 1968 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1969 1970 fwcmd->params.req.num_eq = num; 1971 for (i = 0; i < num; i++) { 1972 fwcmd->params.req.delay[i].eq_id = 1973 htole32(set_eqd[i].eq_id); 1974 fwcmd->params.req.delay[i].phase = 0; 1975 fwcmd->params.req.delay[i].dm = 1976 htole32(set_eqd[i].delay_multiplier); 1977 } 1978 1979 1980 /* command post */ 1981 rc = oce_mbox_post(sc, &mbx, NULL); 1982 1983 if (!rc) 1984 rc = fwcmd->hdr.u0.rsp.status; 1985 if (rc) 1986 device_printf(sc->dev, 1987 "%s failed - cmd status: %d addi status: %d\n", 1988 __FUNCTION__, rc, 1989 fwcmd->hdr.u0.rsp.additional_status); 1990 } 1991 1992 int 1993 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss) 1994 { 1995 struct oce_mbx mbx; 1996 struct mbx_common_get_profile_config *fwcmd; 1997 int rc = 0; 1998 int version = 0; 1999 struct oce_mq_sge *sgl; 2000 OCE_DMA_MEM dma; 2001 uint32_t desc_count = 0; 2002 struct oce_nic_resc_desc *nic_desc = NULL; 2003 int i; 2004 boolean_t nic_desc_valid = FALSE; 2005 2006 if (IS_BE2(sc)) 2007 return -1; 2008 2009 /* Allocate DMA mem*/ 2010 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config), 2011 &dma, 0)) 2012 return ENOMEM; 2013 2014 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2015 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config); 2016 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config)); 2017 2018 if (!IS_XE201(sc)) 2019 version = OCE_MBX_VER_V1; 2020 else 2021 version = OCE_MBX_VER_V0; 2022 2023 bzero(&mbx, sizeof(struct oce_mbx)); 2024 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2025 MBX_SUBSYSTEM_COMMON, 2026 OPCODE_COMMON_GET_PROFILE_CONFIG, 2027 MBX_TIMEOUT_SEC, 2028 sizeof(struct mbx_common_get_profile_config), 2029 version); 2030 /* fill rest of mbx */ 2031 mbx.u0.s.embedded = 0; 2032 mbx.payload_length = sizeof(struct mbx_common_get_profile_config); 2033 mbx.u0.s.sge_count = 1; 2034 sgl = &mbx.payload.u0.u1.sgl[0]; 2035 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2036 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2037 sgl->length = htole32(mbx.payload_length); 2038 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2039 2040 fwcmd->params.req.type = ACTIVE_PROFILE; 2041 2042 /* command post */ 2043 rc = oce_mbox_post(sc, &mbx, NULL); 2044 if (!rc) 2045 rc = fwcmd->hdr.u0.rsp.status; 2046 if (rc) { 2047 device_printf(sc->dev, 2048 "%s failed - cmd status: %d addi status: %d\n", 2049 __FUNCTION__, rc, 2050 fwcmd->hdr.u0.rsp.additional_status); 2051 goto error; 2052 } 2053 2054 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2055 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2056 for (i = 0; i < desc_count; i++) { 2057 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2058 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2059 nic_desc_valid = TRUE; 2060 break; 2061 } 2062 nic_desc = (struct oce_nic_resc_desc *) \ 2063 ((char *)nic_desc + nic_desc->desc_len); 2064 } 2065 if (!nic_desc_valid) { 2066 rc = -1; 2067 goto error; 2068 } 2069 else { 2070 sc->max_vlans = HOST_16(nic_desc->vlan_count); 2071 sc->nwqs = HOST_16(nic_desc->txq_count); 2072 if (sc->nwqs) 2073 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2074 else 2075 sc->nwqs = OCE_MAX_WQ; 2076 2077 sc->nrssqs = HOST_16(nic_desc->rssq_count); 2078 if (sc->nrssqs) 2079 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2080 else 2081 sc->nrssqs = max_rss; 2082 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2083 2084 } 2085 error: 2086 oce_dma_free(sc, &dma); 2087 return rc; 2088 2089 } 2090 2091 int 2092 oce_get_func_config(POCE_SOFTC sc) 2093 { 2094 struct oce_mbx mbx; 2095 struct mbx_common_get_func_config *fwcmd; 2096 int rc = 0; 2097 int version = 0; 2098 struct oce_mq_sge *sgl; 2099 OCE_DMA_MEM dma; 2100 uint32_t desc_count = 0; 2101 struct oce_nic_resc_desc *nic_desc = NULL; 2102 int i; 2103 boolean_t nic_desc_valid = FALSE; 2104 uint32_t max_rss = 0; 2105 2106 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native)) 2107 max_rss = OCE_LEGACY_MODE_RSS; 2108 else 2109 max_rss = OCE_MAX_RSS; 2110 2111 /* Allocate DMA mem*/ 2112 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config), 2113 &dma, 0)) 2114 return ENOMEM; 2115 2116 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2117 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config); 2118 bzero(fwcmd, sizeof(struct mbx_common_get_func_config)); 2119 2120 if (IS_SH(sc)) 2121 version = OCE_MBX_VER_V1; 2122 else 2123 version = OCE_MBX_VER_V0; 2124 2125 bzero(&mbx, sizeof(struct oce_mbx)); 2126 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2127 MBX_SUBSYSTEM_COMMON, 2128 OPCODE_COMMON_GET_FUNCTION_CONFIG, 2129 MBX_TIMEOUT_SEC, 2130 sizeof(struct mbx_common_get_func_config), 2131 version); 2132 /* fill rest of mbx */ 2133 mbx.u0.s.embedded = 0; 2134 mbx.payload_length = sizeof(struct mbx_common_get_func_config); 2135 mbx.u0.s.sge_count = 1; 2136 sgl = &mbx.payload.u0.u1.sgl[0]; 2137 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2138 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2139 sgl->length = htole32(mbx.payload_length); 2140 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2141 2142 /* command post */ 2143 rc = oce_mbox_post(sc, &mbx, NULL); 2144 if (!rc) 2145 rc = fwcmd->hdr.u0.rsp.status; 2146 if (rc) { 2147 device_printf(sc->dev, 2148 "%s failed - cmd status: %d addi status: %d\n", 2149 __FUNCTION__, rc, 2150 fwcmd->hdr.u0.rsp.additional_status); 2151 goto error; 2152 } 2153 2154 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2155 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2156 for (i = 0; i < desc_count; i++) { 2157 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2158 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2159 nic_desc_valid = TRUE; 2160 break; 2161 } 2162 nic_desc = (struct oce_nic_resc_desc *) \ 2163 ((char *)nic_desc + nic_desc->desc_len); 2164 } 2165 if (!nic_desc_valid) { 2166 rc = -1; 2167 goto error; 2168 } 2169 else { 2170 sc->max_vlans = nic_desc->vlan_count; 2171 sc->nwqs = HOST_32(nic_desc->txq_count); 2172 if (sc->nwqs) 2173 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2174 else 2175 sc->nwqs = OCE_MAX_WQ; 2176 2177 sc->nrssqs = HOST_32(nic_desc->rssq_count); 2178 if (sc->nrssqs) 2179 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2180 else 2181 sc->nrssqs = max_rss; 2182 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2183 } 2184 error: 2185 oce_dma_free(sc, &dma); 2186 return rc; 2187 2188 } 2189 2190 /* hw lro functions */ 2191 2192 int 2193 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags) 2194 { 2195 struct oce_mbx mbx; 2196 struct mbx_nic_query_lro_capabilities *fwcmd; 2197 int rc = 0; 2198 2199 bzero(&mbx, sizeof(struct oce_mbx)); 2200 2201 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload; 2202 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2203 MBX_SUBSYSTEM_NIC, 2204 0x20,MBX_TIMEOUT_SEC, 2205 sizeof(struct mbx_nic_query_lro_capabilities), 2206 OCE_MBX_VER_V0); 2207 2208 mbx.u0.s.embedded = 1; 2209 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities); 2210 2211 rc = oce_mbox_post(sc, &mbx, NULL); 2212 if (!rc) 2213 rc = fwcmd->hdr.u0.rsp.status; 2214 if (rc) { 2215 device_printf(sc->dev, 2216 "%s failed - cmd status: %d addi status: %d\n", 2217 __FUNCTION__, rc, 2218 fwcmd->hdr.u0.rsp.additional_status); 2219 2220 return rc; 2221 } 2222 if(lro_flags) 2223 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags); 2224 2225 if(lro_rq_cnt) 2226 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt); 2227 2228 return rc; 2229 } 2230 2231 int 2232 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable) 2233 { 2234 struct oce_mbx mbx; 2235 struct mbx_nic_set_iface_lro_config *fwcmd; 2236 int rc = 0; 2237 2238 bzero(&mbx, sizeof(struct oce_mbx)); 2239 2240 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload; 2241 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2242 MBX_SUBSYSTEM_NIC, 2243 0x26,MBX_TIMEOUT_SEC, 2244 sizeof(struct mbx_nic_set_iface_lro_config), 2245 OCE_MBX_VER_V0); 2246 2247 mbx.u0.s.embedded = 1; 2248 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config); 2249 2250 fwcmd->params.req.iface_id = sc->if_id; 2251 fwcmd->params.req.lro_flags = 0; 2252 2253 if(enable) { 2254 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE; 2255 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6; 2256 2257 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */ 2258 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */ 2259 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */ 2260 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */ 2261 } 2262 2263 rc = oce_mbox_post(sc, &mbx, NULL); 2264 if (!rc) 2265 rc = fwcmd->hdr.u0.rsp.status; 2266 if (rc) { 2267 device_printf(sc->dev, 2268 "%s failed - cmd status: %d addi status: %d\n", 2269 __FUNCTION__, rc, 2270 fwcmd->hdr.u0.rsp.additional_status); 2271 2272 return rc; 2273 } 2274 return rc; 2275 } 2276 2277 int 2278 oce_mbox_create_rq_v2(struct oce_rq *rq) 2279 { 2280 struct oce_mbx mbx; 2281 struct mbx_create_nic_rq_v2 *fwcmd; 2282 POCE_SOFTC sc = rq->parent; 2283 int rc = 0, num_pages = 0; 2284 2285 if (rq->qstate == QCREATED) 2286 return 0; 2287 2288 bzero(&mbx, sizeof(struct oce_mbx)); 2289 2290 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload; 2291 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2292 MBX_SUBSYSTEM_NIC, 2293 0x08, MBX_TIMEOUT_SEC, 2294 sizeof(struct mbx_create_nic_rq_v2), 2295 OCE_MBX_VER_V2); 2296 2297 /* oce_page_list will also prepare pages */ 2298 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 2299 2300 fwcmd->params.req.cq_id = rq->cq->cq_id; 2301 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 2302 fwcmd->params.req.num_pages = num_pages; 2303 2304 fwcmd->params.req.if_id = sc->if_id; 2305 2306 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 2307 fwcmd->params.req.page_size = 1; 2308 if(rq->cfg.is_rss_queue) { 2309 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO); 2310 }else { 2311 device_printf(sc->dev, 2312 "non rss lro queue should not be created \n"); 2313 goto error; 2314 } 2315 mbx.u0.s.embedded = 1; 2316 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2); 2317 2318 rc = oce_mbox_post(sc, &mbx, NULL); 2319 if (!rc) 2320 rc = fwcmd->hdr.u0.rsp.status; 2321 if (rc) { 2322 device_printf(sc->dev, 2323 "%s failed - cmd status: %d addi status: %d\n", 2324 __FUNCTION__, rc, 2325 fwcmd->hdr.u0.rsp.additional_status); 2326 goto error; 2327 } 2328 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 2329 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 2330 2331 error: 2332 return rc; 2333 } 2334 2335