1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include "oce_if.h" 44 45 int 46 oce_wait_ready(POCE_SOFTC sc) 47 { 48 #define SLIPORT_READY_TIMEOUT 30000 49 uint32_t sliport_status, i; 50 51 if (!IS_XE201(sc)) 52 return (-1); 53 54 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 55 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET); 56 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 57 return 0; 58 59 if (sliport_status & SLIPORT_STATUS_ERR_MASK && 60 !(sliport_status & SLIPORT_STATUS_RN_MASK)) { 61 device_printf(sc->dev, "Error detected in the card\n"); 62 return EIO; 63 } 64 65 DELAY(1000); 66 } 67 68 device_printf(sc->dev, "Firmware wait timed out\n"); 69 70 return (-1); 71 } 72 73 /** 74 * @brief Reset (firmware) common function 75 * @param sc software handle to the device 76 * @returns 0 on success, ETIMEDOUT on failure 77 */ 78 int 79 oce_reset_fun(POCE_SOFTC sc) 80 { 81 struct oce_mbx *mbx; 82 struct oce_bmbx *mb; 83 struct ioctl_common_function_reset *fwcmd; 84 int rc = 0; 85 86 if (IS_XE201(sc)) { 87 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET, 88 SLI_PORT_CONTROL_IP_MASK); 89 90 rc = oce_wait_ready(sc); 91 if (rc) { 92 device_printf(sc->dev, "Firmware reset Failed\n"); 93 } 94 95 return rc; 96 } 97 98 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 99 mbx = &mb->mbx; 100 bzero(mbx, sizeof(struct oce_mbx)); 101 102 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload; 103 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 104 MBX_SUBSYSTEM_COMMON, 105 OPCODE_COMMON_FUNCTION_RESET, 106 10, /* MBX_TIMEOUT_SEC */ 107 sizeof(struct 108 ioctl_common_function_reset), 109 OCE_MBX_VER_V0); 110 111 mbx->u0.s.embedded = 1; 112 mbx->payload_length = 113 sizeof(struct ioctl_common_function_reset); 114 115 rc = oce_mbox_dispatch(sc, 2); 116 117 return rc; 118 } 119 120 /** 121 * @brief This functions tells firmware we are 122 * done with commands. 123 * @param sc software handle to the device 124 * @returns 0 on success, ETIMEDOUT on failure 125 */ 126 int 127 oce_fw_clean(POCE_SOFTC sc) 128 { 129 struct oce_bmbx *mbx; 130 uint8_t *ptr; 131 int ret = 0; 132 133 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 134 ptr = (uint8_t *) &mbx->mbx; 135 136 /* Endian Signature */ 137 *ptr++ = 0xff; 138 *ptr++ = 0xaa; 139 *ptr++ = 0xbb; 140 *ptr++ = 0xff; 141 *ptr++ = 0xff; 142 *ptr++ = 0xcc; 143 *ptr++ = 0xdd; 144 *ptr = 0xff; 145 146 ret = oce_mbox_dispatch(sc, 2); 147 148 return ret; 149 } 150 151 /** 152 * @brief Mailbox wait 153 * @param sc software handle to the device 154 * @param tmo_sec timeout in seconds 155 */ 156 static int 157 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec) 158 { 159 tmo_sec *= 10000; 160 pd_mpu_mbox_db_t mbox_db; 161 162 for (;;) { 163 if (tmo_sec != 0) { 164 if (--tmo_sec == 0) 165 break; 166 } 167 168 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB); 169 170 if (mbox_db.bits.ready) 171 return 0; 172 173 DELAY(100); 174 } 175 176 device_printf(sc->dev, "Mailbox timed out\n"); 177 178 return ETIMEDOUT; 179 } 180 181 /** 182 * @brief Mailbox dispatch 183 * @param sc software handle to the device 184 * @param tmo_sec timeout in seconds 185 */ 186 int 187 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec) 188 { 189 pd_mpu_mbox_db_t mbox_db; 190 uint32_t pa; 191 int rc; 192 193 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE); 194 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34); 195 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t)); 196 mbox_db.bits.ready = 0; 197 mbox_db.bits.hi = 1; 198 mbox_db.bits.address = pa; 199 200 rc = oce_mbox_wait(sc, tmo_sec); 201 if (rc == 0) { 202 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 203 204 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff; 205 mbox_db.bits.ready = 0; 206 mbox_db.bits.hi = 0; 207 mbox_db.bits.address = pa; 208 209 rc = oce_mbox_wait(sc, tmo_sec); 210 211 if (rc == 0) { 212 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 213 214 rc = oce_mbox_wait(sc, tmo_sec); 215 216 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE); 217 } 218 } 219 220 return rc; 221 } 222 223 /** 224 * @brief Mailbox common request header initialization 225 * @param hdr mailbox header 226 * @param dom domain 227 * @param port port 228 * @param subsys subsystem 229 * @param opcode opcode 230 * @param timeout timeout 231 * @param pyld_len payload length 232 */ 233 void 234 mbx_common_req_hdr_init(struct mbx_hdr *hdr, 235 uint8_t dom, uint8_t port, 236 uint8_t subsys, uint8_t opcode, 237 uint32_t timeout, uint32_t pyld_len, 238 uint8_t version) 239 { 240 hdr->u0.req.opcode = opcode; 241 hdr->u0.req.subsystem = subsys; 242 hdr->u0.req.port_number = port; 243 hdr->u0.req.domain = dom; 244 245 hdr->u0.req.timeout = timeout; 246 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr); 247 hdr->u0.req.version = version; 248 } 249 250 /** 251 * @brief Function to initialize the hw with host endian information 252 * @param sc software handle to the device 253 * @returns 0 on success, ETIMEDOUT on failure 254 */ 255 int 256 oce_mbox_init(POCE_SOFTC sc) 257 { 258 struct oce_bmbx *mbx; 259 uint8_t *ptr; 260 int ret = 0; 261 262 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) { 263 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 264 ptr = (uint8_t *) &mbx->mbx; 265 266 /* Endian Signature */ 267 *ptr++ = 0xff; 268 *ptr++ = 0x12; 269 *ptr++ = 0x34; 270 *ptr++ = 0xff; 271 *ptr++ = 0xff; 272 *ptr++ = 0x56; 273 *ptr++ = 0x78; 274 *ptr = 0xff; 275 276 ret = oce_mbox_dispatch(sc, 0); 277 } 278 279 return ret; 280 } 281 282 /** 283 * @brief Function to get the firmware version 284 * @param sc software handle to the device 285 * @returns 0 on success, EIO on failure 286 */ 287 int 288 oce_get_fw_version(POCE_SOFTC sc) 289 { 290 struct oce_mbx mbx; 291 struct mbx_get_common_fw_version *fwcmd; 292 int ret = 0; 293 294 bzero(&mbx, sizeof(struct oce_mbx)); 295 296 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload; 297 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 298 MBX_SUBSYSTEM_COMMON, 299 OPCODE_COMMON_GET_FW_VERSION, 300 MBX_TIMEOUT_SEC, 301 sizeof(struct mbx_get_common_fw_version), 302 OCE_MBX_VER_V0); 303 304 mbx.u0.s.embedded = 1; 305 mbx.payload_length = sizeof(struct mbx_get_common_fw_version); 306 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 307 308 ret = oce_mbox_post(sc, &mbx, NULL); 309 if (!ret) 310 ret = fwcmd->hdr.u0.rsp.status; 311 if (ret) { 312 device_printf(sc->dev, 313 "%s failed - cmd status: %d addi status: %d\n", 314 __FUNCTION__, ret, 315 fwcmd->hdr.u0.rsp.additional_status); 316 goto error; 317 } 318 319 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32); 320 error: 321 return ret; 322 } 323 324 /** 325 * @brief Firmware will send gracious notifications during 326 * attach only after sending first mcc commnad. We 327 * use MCC queue only for getting async and mailbox 328 * for sending cmds. So to get gracious notifications 329 * atleast send one dummy command on mcc. 330 */ 331 int 332 oce_first_mcc_cmd(POCE_SOFTC sc) 333 { 334 struct oce_mbx *mbx; 335 struct oce_mq *mq = sc->mq; 336 struct mbx_get_common_fw_version *fwcmd; 337 uint32_t reg_value; 338 339 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx); 340 bzero(mbx, sizeof(struct oce_mbx)); 341 342 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload; 343 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 344 MBX_SUBSYSTEM_COMMON, 345 OPCODE_COMMON_GET_FW_VERSION, 346 MBX_TIMEOUT_SEC, 347 sizeof(struct mbx_get_common_fw_version), 348 OCE_MBX_VER_V0); 349 mbx->u0.s.embedded = 1; 350 mbx->payload_length = sizeof(struct mbx_get_common_fw_version); 351 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map, 352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 353 RING_PUT(mq->ring, 1); 354 reg_value = (1 << 16) | mq->mq_id; 355 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value); 356 357 return 0; 358 } 359 360 /** 361 * @brief Function to post a MBX to the mbox 362 * @param sc software handle to the device 363 * @param mbx pointer to the MBX to send 364 * @param mbxctx pointer to the mbx context structure 365 * @returns 0 on success, error on failure 366 */ 367 int 368 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx) 369 { 370 struct oce_mbx *mb_mbx = NULL; 371 struct oce_mq_cqe *mb_cqe = NULL; 372 struct oce_bmbx *mb = NULL; 373 int rc = 0; 374 uint32_t tmo = 0; 375 uint32_t cstatus = 0; 376 uint32_t xstatus = 0; 377 378 LOCK(&sc->bmbx_lock); 379 380 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 381 mb_mbx = &mb->mbx; 382 383 /* get the tmo */ 384 tmo = mbx->tag[0]; 385 mbx->tag[0] = 0; 386 387 /* copy mbx into mbox */ 388 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx)); 389 390 /* now dispatch */ 391 rc = oce_mbox_dispatch(sc, tmo); 392 if (rc == 0) { 393 /* 394 * the command completed successfully. Now get the 395 * completion queue entry 396 */ 397 mb_cqe = &mb->cqe; 398 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe)); 399 400 /* copy mbox mbx back */ 401 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx)); 402 403 /* pick up the mailbox status */ 404 cstatus = mb_cqe->u0.s.completion_status; 405 xstatus = mb_cqe->u0.s.extended_status; 406 407 /* 408 * store the mbx context in the cqe tag section so that 409 * the upper layer handling the cqe can associate the mbx 410 * with the response 411 */ 412 if (cstatus == 0 && mbxctx) { 413 /* save context */ 414 mbxctx->mbx = mb_mbx; 415 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag, 416 sizeof(struct oce_mbx_ctx *)); 417 } 418 } 419 420 UNLOCK(&sc->bmbx_lock); 421 422 return rc; 423 } 424 425 /** 426 * @brief Function to read the mac address associated with an interface 427 * @param sc software handle to the device 428 * @param if_id interface id to read the address from 429 * @param perm set to 1 if reading the factory mac address. 430 * In this case if_id is ignored 431 * @param type type of the mac address, whether network or storage 432 * @param[out] mac [OUTPUT] pointer to a buffer containing the 433 * mac address when the command succeeds. 434 * @returns 0 on success, EIO on failure 435 */ 436 int 437 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, 438 uint8_t perm, uint8_t type, struct mac_address_format *mac) 439 { 440 struct oce_mbx mbx; 441 struct mbx_query_common_iface_mac *fwcmd; 442 int ret = 0; 443 444 bzero(&mbx, sizeof(struct oce_mbx)); 445 446 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload; 447 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 448 MBX_SUBSYSTEM_COMMON, 449 OPCODE_COMMON_QUERY_IFACE_MAC, 450 MBX_TIMEOUT_SEC, 451 sizeof(struct mbx_query_common_iface_mac), 452 OCE_MBX_VER_V0); 453 454 fwcmd->params.req.permanent = perm; 455 if (!perm) 456 fwcmd->params.req.if_id = (uint16_t) if_id; 457 else 458 fwcmd->params.req.if_id = 0; 459 460 fwcmd->params.req.type = type; 461 462 mbx.u0.s.embedded = 1; 463 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac); 464 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 465 466 ret = oce_mbox_post(sc, &mbx, NULL); 467 if (!ret) 468 ret = fwcmd->hdr.u0.rsp.status; 469 if (ret) { 470 device_printf(sc->dev, 471 "%s failed - cmd status: %d addi status: %d\n", 472 __FUNCTION__, ret, 473 fwcmd->hdr.u0.rsp.additional_status); 474 goto error; 475 } 476 477 /* copy the mac addres in the output parameter */ 478 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct; 479 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0], 480 mac->size_of_struct); 481 error: 482 return ret; 483 } 484 485 /** 486 * @brief Function to query the fw attributes from the hw 487 * @param sc software handle to the device 488 * @returns 0 on success, EIO on failure 489 */ 490 int 491 oce_get_fw_config(POCE_SOFTC sc) 492 { 493 struct oce_mbx mbx; 494 struct mbx_common_query_fw_config *fwcmd; 495 int ret = 0; 496 497 bzero(&mbx, sizeof(struct oce_mbx)); 498 499 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload; 500 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 501 MBX_SUBSYSTEM_COMMON, 502 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, 503 MBX_TIMEOUT_SEC, 504 sizeof(struct mbx_common_query_fw_config), 505 OCE_MBX_VER_V0); 506 507 mbx.u0.s.embedded = 1; 508 mbx.payload_length = sizeof(struct mbx_common_query_fw_config); 509 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 510 511 ret = oce_mbox_post(sc, &mbx, NULL); 512 if (!ret) 513 ret = fwcmd->hdr.u0.rsp.status; 514 if (ret) { 515 device_printf(sc->dev, 516 "%s failed - cmd status: %d addi status: %d\n", 517 __FUNCTION__, ret, 518 fwcmd->hdr.u0.rsp.additional_status); 519 goto error; 520 } 521 522 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config)); 523 524 sc->config_number = HOST_32(fwcmd->params.rsp.config_number); 525 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision); 526 sc->port_id = HOST_32(fwcmd->params.rsp.port_id); 527 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode); 528 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) == 529 (ULP_NIC_MODE | ULP_RDMA_MODE)) { 530 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED; 531 } 532 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps); 533 534 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) { 535 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot); 536 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot); 537 } else { 538 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot); 539 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot); 540 } 541 542 error: 543 return ret; 544 545 } 546 547 /** 548 * 549 * @brief function to create a device interface 550 * @param sc software handle to the device 551 * @param cap_flags capability flags 552 * @param en_flags enable capability flags 553 * @param vlan_tag optional vlan tag to associate with the if 554 * @param mac_addr pointer to a buffer containing the mac address 555 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the 556 interface created 557 * @returns 0 on success, EIO on failure 558 */ 559 int 560 oce_if_create(POCE_SOFTC sc, 561 uint32_t cap_flags, 562 uint32_t en_flags, 563 uint16_t vlan_tag, 564 uint8_t *mac_addr, 565 uint32_t *if_id) 566 { 567 struct oce_mbx mbx; 568 struct mbx_create_common_iface *fwcmd; 569 int rc = 0; 570 571 bzero(&mbx, sizeof(struct oce_mbx)); 572 573 fwcmd = (struct mbx_create_common_iface *)&mbx.payload; 574 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 575 MBX_SUBSYSTEM_COMMON, 576 OPCODE_COMMON_CREATE_IFACE, 577 MBX_TIMEOUT_SEC, 578 sizeof(struct mbx_create_common_iface), 579 OCE_MBX_VER_V0); 580 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr)); 581 582 fwcmd->params.req.version = 0; 583 fwcmd->params.req.cap_flags = LE_32(cap_flags); 584 fwcmd->params.req.enable_flags = LE_32(en_flags); 585 if (mac_addr != NULL) { 586 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6); 587 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag); 588 fwcmd->params.req.mac_invalid = 0; 589 } else { 590 fwcmd->params.req.mac_invalid = 1; 591 } 592 593 mbx.u0.s.embedded = 1; 594 mbx.payload_length = sizeof(struct mbx_create_common_iface); 595 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ); 596 597 rc = oce_mbox_post(sc, &mbx, NULL); 598 if (!rc) 599 rc = fwcmd->hdr.u0.rsp.status; 600 if (rc) { 601 device_printf(sc->dev, 602 "%s failed - cmd status: %d addi status: %d\n", 603 __FUNCTION__, rc, 604 fwcmd->hdr.u0.rsp.additional_status); 605 goto error; 606 } 607 608 *if_id = HOST_32(fwcmd->params.rsp.if_id); 609 610 if (mac_addr != NULL) 611 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id); 612 error: 613 return rc; 614 } 615 616 /** 617 * @brief Function to delete an interface 618 * @param sc software handle to the device 619 * @param if_id ID of the interface to delete 620 * @returns 0 on success, EIO on failure 621 */ 622 int 623 oce_if_del(POCE_SOFTC sc, uint32_t if_id) 624 { 625 struct oce_mbx mbx; 626 struct mbx_destroy_common_iface *fwcmd; 627 int rc = 0; 628 629 bzero(&mbx, sizeof(struct oce_mbx)); 630 631 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload; 632 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 633 MBX_SUBSYSTEM_COMMON, 634 OPCODE_COMMON_DESTROY_IFACE, 635 MBX_TIMEOUT_SEC, 636 sizeof(struct mbx_destroy_common_iface), 637 OCE_MBX_VER_V0); 638 639 fwcmd->params.req.if_id = if_id; 640 641 mbx.u0.s.embedded = 1; 642 mbx.payload_length = sizeof(struct mbx_destroy_common_iface); 643 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 644 645 rc = oce_mbox_post(sc, &mbx, NULL); 646 if (!rc) 647 rc = fwcmd->hdr.u0.rsp.status; 648 if (rc) 649 device_printf(sc->dev, 650 "%s failed - cmd status: %d addi status: %d\n", 651 __FUNCTION__, rc, 652 fwcmd->hdr.u0.rsp.additional_status); 653 return rc; 654 } 655 656 /** 657 * @brief Function to send the mbx command to configure vlan 658 * @param sc software handle to the device 659 * @param if_id interface identifier index 660 * @param vtag_arr array of vlan tags 661 * @param vtag_cnt number of elements in array 662 * @param untagged boolean TRUE/FLASE 663 * @param enable_promisc flag to enable/disable VLAN promiscuous mode 664 * @returns 0 on success, EIO on failure 665 */ 666 int 667 oce_config_vlan(POCE_SOFTC sc, 668 uint32_t if_id, 669 struct normal_vlan *vtag_arr, 670 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc) 671 { 672 struct oce_mbx mbx; 673 struct mbx_common_config_vlan *fwcmd; 674 int rc = 0; 675 676 if (sc->vlans_added > sc->max_vlans) 677 goto vlan_promisc; 678 679 bzero(&mbx, sizeof(struct oce_mbx)); 680 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload; 681 682 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 683 MBX_SUBSYSTEM_COMMON, 684 OPCODE_COMMON_CONFIG_IFACE_VLAN, 685 MBX_TIMEOUT_SEC, 686 sizeof(struct mbx_common_config_vlan), 687 OCE_MBX_VER_V0); 688 689 fwcmd->params.req.if_id = (uint8_t) if_id; 690 fwcmd->params.req.promisc = (uint8_t) enable_promisc; 691 fwcmd->params.req.untagged = (uint8_t) untagged; 692 fwcmd->params.req.num_vlans = vtag_cnt; 693 694 if (!enable_promisc) { 695 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans, 696 vtag_cnt * sizeof(struct normal_vlan)); 697 } 698 mbx.u0.s.embedded = 1; 699 mbx.payload_length = sizeof(struct mbx_common_config_vlan); 700 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length)); 701 702 rc = oce_mbox_post(sc, &mbx, NULL); 703 if (!rc) 704 rc = fwcmd->hdr.u0.rsp.status; 705 if (rc) 706 device_printf(sc->dev, 707 "%s failed - cmd status: %d addi status: %d\n", 708 __FUNCTION__, rc, 709 fwcmd->hdr.u0.rsp.additional_status); 710 711 goto done; 712 713 vlan_promisc: 714 /* Enable Vlan Promis */ 715 oce_rxf_set_promiscuous(sc, (1 << 1)); 716 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n"); 717 done: 718 return rc; 719 720 } 721 722 /** 723 * @brief Function to set flow control capability in the hardware 724 * @param sc software handle to the device 725 * @param flow_control flow control flags to set 726 * @returns 0 on success, EIO on failure 727 */ 728 int 729 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control) 730 { 731 struct oce_mbx mbx; 732 struct mbx_common_get_set_flow_control *fwcmd = 733 (struct mbx_common_get_set_flow_control *)&mbx.payload; 734 int rc; 735 736 bzero(&mbx, sizeof(struct oce_mbx)); 737 738 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 739 MBX_SUBSYSTEM_COMMON, 740 OPCODE_COMMON_SET_FLOW_CONTROL, 741 MBX_TIMEOUT_SEC, 742 sizeof(struct mbx_common_get_set_flow_control), 743 OCE_MBX_VER_V0); 744 745 if (flow_control & OCE_FC_TX) 746 fwcmd->tx_flow_control = 1; 747 748 if (flow_control & OCE_FC_RX) 749 fwcmd->rx_flow_control = 1; 750 751 mbx.u0.s.embedded = 1; 752 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control); 753 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 754 755 rc = oce_mbox_post(sc, &mbx, NULL); 756 if (!rc) 757 rc = fwcmd->hdr.u0.rsp.status; 758 if (rc) 759 device_printf(sc->dev, 760 "%s failed - cmd status: %d addi status: %d\n", 761 __FUNCTION__, rc, 762 fwcmd->hdr.u0.rsp.additional_status); 763 return rc; 764 } 765 766 /** 767 * @brief Initialize the RSS CPU indirection table 768 * 769 * The table is used to choose the queue to place the incomming packets. 770 * Incomming packets are hashed. The lowest bits in the hash result 771 * are used as the index into the CPU indirection table. 772 * Each entry in the table contains the RSS CPU-ID returned by the NIC 773 * create. Based on the CPU ID, the receive completion is routed to 774 * the corresponding RSS CQs. (Non-RSS packets are always completed 775 * on the default (0) CQ). 776 * 777 * @param sc software handle to the device 778 * @param *fwcmd pointer to the rss mbox command 779 * @returns none 780 */ 781 static int 782 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) 783 { 784 int i = 0, j = 0, rc = 0; 785 uint8_t *tbl = fwcmd->params.req.cputable; 786 struct oce_rq *rq = NULL; 787 788 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) { 789 for_all_rss_queues(sc, rq, i) { 790 if ((j + i) >= INDIRECTION_TABLE_ENTRIES) 791 break; 792 tbl[j + i] = rq->rss_cpuid; 793 } 794 } 795 if (i == 0) { 796 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n"); 797 rc = ENXIO; 798 799 } 800 801 /* fill log2 value indicating the size of the CPU table */ 802 if (rc == 0) 803 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES)); 804 805 return rc; 806 } 807 808 /** 809 * @brief Function to set flow control capability in the hardware 810 * @param sc software handle to the device 811 * @param if_id interface id to read the address from 812 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise 813 * @returns 0 on success, EIO on failure 814 */ 815 int 816 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss) 817 { 818 int rc; 819 struct oce_mbx mbx; 820 struct mbx_config_nic_rss *fwcmd = 821 (struct mbx_config_nic_rss *)&mbx.payload; 822 int version; 823 824 bzero(&mbx, sizeof(struct oce_mbx)); 825 826 if (IS_XE201(sc) || IS_SH(sc)) { 827 version = OCE_MBX_VER_V1; 828 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 | 829 RSS_ENABLE_UDP_IPV6; 830 } else 831 version = OCE_MBX_VER_V0; 832 833 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 834 MBX_SUBSYSTEM_NIC, 835 NIC_CONFIG_RSS, 836 MBX_TIMEOUT_SEC, 837 sizeof(struct mbx_config_nic_rss), 838 version); 839 if (enable_rss) 840 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 | 841 RSS_ENABLE_TCP_IPV4 | 842 RSS_ENABLE_IPV6 | 843 RSS_ENABLE_TCP_IPV6); 844 845 if(!sc->enable_hwlro) 846 fwcmd->params.req.flush = OCE_FLUSH; 847 else 848 fwcmd->params.req.flush = 0; 849 850 fwcmd->params.req.if_id = LE_32(if_id); 851 852 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash)); 853 854 rc = oce_rss_itbl_init(sc, fwcmd); 855 if (rc == 0) { 856 mbx.u0.s.embedded = 1; 857 mbx.payload_length = sizeof(struct mbx_config_nic_rss); 858 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 859 860 rc = oce_mbox_post(sc, &mbx, NULL); 861 if (!rc) 862 rc = fwcmd->hdr.u0.rsp.status; 863 if (rc) 864 device_printf(sc->dev, 865 "%s failed - cmd status: %d addi status: %d\n", 866 __FUNCTION__, rc, 867 fwcmd->hdr.u0.rsp.additional_status); 868 } 869 return rc; 870 } 871 872 /** 873 * @brief RXF function to enable/disable device promiscuous mode 874 * @param sc software handle to the device 875 * @param enable enable/disable flag 876 * @returns 0 on success, EIO on failure 877 * @note 878 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer. 879 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead. 880 */ 881 int 882 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable) 883 { 884 struct mbx_set_common_iface_rx_filter *fwcmd; 885 int sz = sizeof(struct mbx_set_common_iface_rx_filter); 886 iface_rx_filter_ctx_t *req; 887 OCE_DMA_MEM sgl; 888 int rc; 889 890 /* allocate mbx payload's dma scatter/gather memory */ 891 rc = oce_dma_alloc(sc, sz, &sgl, 0); 892 if (rc) 893 return rc; 894 895 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter); 896 897 req = &fwcmd->params.req; 898 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS | 899 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 900 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */ 901 if (enable & 0x01) 902 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS; 903 904 if (enable & 0x02) 905 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 906 907 req->if_id = sc->if_id; 908 909 rc = oce_set_common_iface_rx_filter(sc, &sgl); 910 oce_dma_free(sc, &sgl); 911 912 return rc; 913 } 914 915 /** 916 * @brief Function modify and select rx filter options 917 * @param sc software handle to the device 918 * @param sgl scatter/gather request/response 919 * @returns 0 on success, error code on failure 920 */ 921 int 922 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl) 923 { 924 struct oce_mbx mbx; 925 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter); 926 struct mbx_set_common_iface_rx_filter *fwcmd; 927 int rc; 928 929 bzero(&mbx, sizeof(struct oce_mbx)); 930 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter); 931 932 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 933 MBX_SUBSYSTEM_COMMON, 934 OPCODE_COMMON_SET_IFACE_RX_FILTER, 935 MBX_TIMEOUT_SEC, 936 mbx_sz, 937 OCE_MBX_VER_V0); 938 939 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE); 940 mbx.u0.s.embedded = 0; 941 mbx.u0.s.sge_count = 1; 942 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr); 943 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr); 944 mbx.payload.u0.u1.sgl[0].length = mbx_sz; 945 mbx.payload_length = mbx_sz; 946 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 947 948 rc = oce_mbox_post(sc, &mbx, NULL); 949 if (!rc) 950 rc = fwcmd->hdr.u0.rsp.status; 951 if (rc) 952 device_printf(sc->dev, 953 "%s failed - cmd status: %d addi status: %d\n", 954 __FUNCTION__, rc, 955 fwcmd->hdr.u0.rsp.additional_status); 956 return rc; 957 } 958 959 /** 960 * @brief Function to query the link status from the hardware 961 * @param sc software handle to the device 962 * @param[out] link pointer to the structure returning link attributes 963 * @returns 0 on success, EIO on failure 964 */ 965 int 966 oce_get_link_status(POCE_SOFTC sc, struct link_status *link) 967 { 968 struct oce_mbx mbx; 969 struct mbx_query_common_link_config *fwcmd; 970 int rc = 0, version; 971 972 bzero(&mbx, sizeof(struct oce_mbx)); 973 974 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1); 975 976 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload; 977 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 978 MBX_SUBSYSTEM_COMMON, 979 OPCODE_COMMON_QUERY_LINK_CONFIG, 980 MBX_TIMEOUT_SEC, 981 sizeof(struct mbx_query_common_link_config), 982 version); 983 984 mbx.u0.s.embedded = 1; 985 mbx.payload_length = sizeof(struct mbx_query_common_link_config); 986 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 987 988 rc = oce_mbox_post(sc, &mbx, NULL); 989 990 if (!rc) 991 rc = fwcmd->hdr.u0.rsp.status; 992 if (rc) { 993 device_printf(sc->dev, 994 "%s failed - cmd status: %d addi status: %d\n", 995 __FUNCTION__, rc, 996 fwcmd->hdr.u0.rsp.additional_status); 997 goto error; 998 } 999 /* interpret response */ 1000 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed); 1001 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed; 1002 link->logical_link_status = fwcmd->params.rsp.logical_link_status; 1003 error: 1004 return rc; 1005 } 1006 1007 /** 1008 * @brief Function to get NIC statistics 1009 * @param sc software handle to the device 1010 * @param *stats pointer to where to store statistics 1011 * @param reset_stats resets statistics of set 1012 * @returns 0 on success, EIO on failure 1013 * @note command depricated in Lancer 1014 */ 1015 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \ 1016 int \ 1017 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \ 1018 { \ 1019 struct oce_mbx mbx; \ 1020 struct mbx_get_nic_stats_v##version *fwcmd; \ 1021 int rc = 0; \ 1022 \ 1023 bzero(&mbx, sizeof(struct oce_mbx)); \ 1024 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \ 1025 bzero(fwcmd, sizeof(*fwcmd)); \ 1026 \ 1027 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \ 1028 MBX_SUBSYSTEM_NIC, \ 1029 NIC_GET_STATS, \ 1030 MBX_TIMEOUT_SEC, \ 1031 sizeof(*fwcmd), \ 1032 OCE_MBX_VER_V##version); \ 1033 \ 1034 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \ 1035 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \ 1036 \ 1037 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \ 1038 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \ 1039 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \ 1040 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \ 1041 mbx.payload_length = sizeof(*fwcmd); \ 1042 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \ 1043 \ 1044 rc = oce_mbox_post(sc, &mbx, NULL); \ 1045 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \ 1046 if (!rc) \ 1047 rc = fwcmd->hdr.u0.rsp.status; \ 1048 if (rc) \ 1049 device_printf(sc->dev, \ 1050 "%s failed - cmd status: %d addi status: %d\n", \ 1051 __FUNCTION__, rc, \ 1052 fwcmd->hdr.u0.rsp.additional_status); \ 1053 return rc; \ 1054 } 1055 1056 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0); 1057 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1); 1058 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2); 1059 1060 /** 1061 * @brief Function to get pport (physical port) statistics 1062 * @param sc software handle to the device 1063 * @param *stats pointer to where to store statistics 1064 * @param reset_stats resets statistics of set 1065 * @returns 0 on success, EIO on failure 1066 */ 1067 int 1068 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1069 uint32_t reset_stats) 1070 { 1071 struct oce_mbx mbx; 1072 struct mbx_get_pport_stats *fwcmd; 1073 int rc = 0; 1074 1075 bzero(&mbx, sizeof(struct oce_mbx)); 1076 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats); 1077 bzero(fwcmd, sizeof(struct mbx_get_pport_stats)); 1078 1079 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1080 MBX_SUBSYSTEM_NIC, 1081 NIC_GET_PPORT_STATS, 1082 MBX_TIMEOUT_SEC, 1083 sizeof(struct mbx_get_pport_stats), 1084 OCE_MBX_VER_V0); 1085 1086 fwcmd->params.req.reset_stats = reset_stats; 1087 fwcmd->params.req.port_number = sc->port_id; 1088 1089 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1090 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1091 1092 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1093 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1094 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1095 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats); 1096 1097 mbx.payload_length = sizeof(struct mbx_get_pport_stats); 1098 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1099 1100 rc = oce_mbox_post(sc, &mbx, NULL); 1101 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1102 1103 if (!rc) 1104 rc = fwcmd->hdr.u0.rsp.status; 1105 if (rc) 1106 device_printf(sc->dev, 1107 "%s failed - cmd status: %d addi status: %d\n", 1108 __FUNCTION__, rc, 1109 fwcmd->hdr.u0.rsp.additional_status); 1110 return rc; 1111 } 1112 1113 /** 1114 * @brief Function to get vport (virtual port) statistics 1115 * @param sc software handle to the device 1116 * @param *stats pointer to where to store statistics 1117 * @param reset_stats resets statistics of set 1118 * @returns 0 on success, EIO on failure 1119 */ 1120 int 1121 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1122 uint32_t req_size, uint32_t reset_stats) 1123 { 1124 struct oce_mbx mbx; 1125 struct mbx_get_vport_stats *fwcmd; 1126 int rc = 0; 1127 1128 bzero(&mbx, sizeof(struct oce_mbx)); 1129 1130 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats); 1131 bzero(fwcmd, sizeof(struct mbx_get_vport_stats)); 1132 1133 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1134 MBX_SUBSYSTEM_NIC, 1135 NIC_GET_VPORT_STATS, 1136 MBX_TIMEOUT_SEC, 1137 sizeof(struct mbx_get_vport_stats), 1138 OCE_MBX_VER_V0); 1139 1140 fwcmd->params.req.reset_stats = reset_stats; 1141 fwcmd->params.req.vport_number = sc->if_id; 1142 1143 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1144 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1145 1146 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1147 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1148 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1149 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats); 1150 1151 mbx.payload_length = sizeof(struct mbx_get_vport_stats); 1152 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1153 1154 rc = oce_mbox_post(sc, &mbx, NULL); 1155 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1156 1157 if (!rc) 1158 rc = fwcmd->hdr.u0.rsp.status; 1159 if (rc) 1160 device_printf(sc->dev, 1161 "%s failed - cmd status: %d addi status: %d\n", 1162 __FUNCTION__, rc, 1163 fwcmd->hdr.u0.rsp.additional_status); 1164 return rc; 1165 } 1166 1167 /** 1168 * @brief Function to update the muticast filter with 1169 * values in dma_mem 1170 * @param sc software handle to the device 1171 * @param dma_mem pointer to dma memory region 1172 * @returns 0 on success, EIO on failure 1173 */ 1174 int 1175 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem) 1176 { 1177 struct oce_mbx mbx; 1178 struct oce_mq_sge *sgl; 1179 struct mbx_set_common_iface_multicast *req = NULL; 1180 int rc = 0; 1181 1182 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast); 1183 mbx_common_req_hdr_init(&req->hdr, 0, 0, 1184 MBX_SUBSYSTEM_COMMON, 1185 OPCODE_COMMON_SET_IFACE_MULTICAST, 1186 MBX_TIMEOUT_SEC, 1187 sizeof(struct mbx_set_common_iface_multicast), 1188 OCE_MBX_VER_V0); 1189 1190 bzero(&mbx, sizeof(struct oce_mbx)); 1191 1192 mbx.u0.s.embedded = 0; /*Non embeded*/ 1193 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast); 1194 mbx.u0.s.sge_count = 1; 1195 sgl = &mbx.payload.u0.u1.sgl[0]; 1196 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr)); 1197 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF); 1198 sgl->length = htole32(mbx.payload_length); 1199 1200 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1201 1202 rc = oce_mbox_post(sc, &mbx, NULL); 1203 if (!rc) 1204 rc = req->hdr.u0.rsp.status; 1205 if (rc) 1206 device_printf(sc->dev, 1207 "%s failed - cmd status: %d addi status: %d\n", 1208 __FUNCTION__, rc, 1209 req->hdr.u0.rsp.additional_status); 1210 return rc; 1211 } 1212 1213 /** 1214 * @brief Function to send passthrough Ioctls 1215 * @param sc software handle to the device 1216 * @param dma_mem pointer to dma memory region 1217 * @param req_size size of dma_mem 1218 * @returns 0 on success, EIO on failure 1219 */ 1220 int 1221 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size) 1222 { 1223 struct oce_mbx mbx; 1224 struct oce_mq_sge *sgl; 1225 int rc = 0; 1226 1227 bzero(&mbx, sizeof(struct oce_mbx)); 1228 1229 mbx.u0.s.embedded = 0; /*Non embeded*/ 1230 mbx.payload_length = req_size; 1231 mbx.u0.s.sge_count = 1; 1232 sgl = &mbx.payload.u0.u1.sgl[0]; 1233 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr)); 1234 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF); 1235 sgl->length = htole32(req_size); 1236 1237 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1238 1239 rc = oce_mbox_post(sc, &mbx, NULL); 1240 return rc; 1241 } 1242 1243 int 1244 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1245 uint32_t if_id, uint32_t *pmac_id) 1246 { 1247 struct oce_mbx mbx; 1248 struct mbx_add_common_iface_mac *fwcmd; 1249 int rc = 0; 1250 1251 bzero(&mbx, sizeof(struct oce_mbx)); 1252 1253 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload; 1254 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1255 MBX_SUBSYSTEM_COMMON, 1256 OPCODE_COMMON_ADD_IFACE_MAC, 1257 MBX_TIMEOUT_SEC, 1258 sizeof(struct mbx_add_common_iface_mac), 1259 OCE_MBX_VER_V0); 1260 1261 fwcmd->params.req.if_id = (uint16_t) if_id; 1262 bcopy(mac_addr, fwcmd->params.req.mac_address, 6); 1263 1264 mbx.u0.s.embedded = 1; 1265 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac); 1266 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1267 rc = oce_mbox_post(sc, &mbx, NULL); 1268 if (!rc) 1269 rc = fwcmd->hdr.u0.rsp.status; 1270 if (rc) { 1271 device_printf(sc->dev, 1272 "%s failed - cmd status: %d addi status: %d\n", 1273 __FUNCTION__, rc, 1274 fwcmd->hdr.u0.rsp.additional_status); 1275 goto error; 1276 } 1277 *pmac_id = fwcmd->params.rsp.pmac_id; 1278 error: 1279 return rc; 1280 } 1281 1282 int 1283 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id) 1284 { 1285 struct oce_mbx mbx; 1286 struct mbx_del_common_iface_mac *fwcmd; 1287 int rc = 0; 1288 1289 bzero(&mbx, sizeof(struct oce_mbx)); 1290 1291 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload; 1292 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1293 MBX_SUBSYSTEM_COMMON, 1294 OPCODE_COMMON_DEL_IFACE_MAC, 1295 MBX_TIMEOUT_SEC, 1296 sizeof(struct mbx_del_common_iface_mac), 1297 OCE_MBX_VER_V0); 1298 1299 fwcmd->params.req.if_id = (uint16_t)if_id; 1300 fwcmd->params.req.pmac_id = pmac_id; 1301 1302 mbx.u0.s.embedded = 1; 1303 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac); 1304 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1305 1306 rc = oce_mbox_post(sc, &mbx, NULL); 1307 if (!rc) 1308 rc = fwcmd->hdr.u0.rsp.status; 1309 if (rc) 1310 device_printf(sc->dev, 1311 "%s failed - cmd status: %d addi status: %d\n", 1312 __FUNCTION__, rc, 1313 fwcmd->hdr.u0.rsp.additional_status); 1314 return rc; 1315 } 1316 1317 int 1318 oce_mbox_check_native_mode(POCE_SOFTC sc) 1319 { 1320 struct oce_mbx mbx; 1321 struct mbx_common_set_function_cap *fwcmd; 1322 int rc = 0; 1323 1324 bzero(&mbx, sizeof(struct oce_mbx)); 1325 1326 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload; 1327 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1328 MBX_SUBSYSTEM_COMMON, 1329 OPCODE_COMMON_SET_FUNCTIONAL_CAPS, 1330 MBX_TIMEOUT_SEC, 1331 sizeof(struct mbx_common_set_function_cap), 1332 OCE_MBX_VER_V0); 1333 1334 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS | 1335 CAP_BE3_NATIVE_ERX_API; 1336 1337 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API; 1338 1339 mbx.u0.s.embedded = 1; 1340 mbx.payload_length = sizeof(struct mbx_common_set_function_cap); 1341 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1342 1343 rc = oce_mbox_post(sc, &mbx, NULL); 1344 if (!rc) 1345 rc = fwcmd->hdr.u0.rsp.status; 1346 if (rc) { 1347 device_printf(sc->dev, 1348 "%s failed - cmd status: %d addi status: %d\n", 1349 __FUNCTION__, rc, 1350 fwcmd->hdr.u0.rsp.additional_status); 1351 goto error; 1352 } 1353 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags) 1354 & CAP_BE3_NATIVE_ERX_API; 1355 1356 error: 1357 return 0; 1358 } 1359 1360 int 1361 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1362 uint8_t loopback_type, uint8_t enable) 1363 { 1364 struct oce_mbx mbx; 1365 struct mbx_lowlevel_set_loopback_mode *fwcmd; 1366 int rc = 0; 1367 1368 bzero(&mbx, sizeof(struct oce_mbx)); 1369 1370 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload; 1371 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1372 MBX_SUBSYSTEM_LOWLEVEL, 1373 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, 1374 MBX_TIMEOUT_SEC, 1375 sizeof(struct mbx_lowlevel_set_loopback_mode), 1376 OCE_MBX_VER_V0); 1377 1378 fwcmd->params.req.src_port = port_num; 1379 fwcmd->params.req.dest_port = port_num; 1380 fwcmd->params.req.loopback_type = loopback_type; 1381 fwcmd->params.req.loopback_state = enable; 1382 1383 mbx.u0.s.embedded = 1; 1384 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode); 1385 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1386 1387 rc = oce_mbox_post(sc, &mbx, NULL); 1388 if (!rc) 1389 rc = fwcmd->hdr.u0.rsp.status; 1390 if (rc) 1391 device_printf(sc->dev, 1392 "%s failed - cmd status: %d addi status: %d\n", 1393 __FUNCTION__, rc, 1394 fwcmd->hdr.u0.rsp.additional_status); 1395 1396 return rc; 1397 1398 } 1399 1400 int 1401 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1402 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1403 uint64_t pattern) 1404 { 1405 1406 struct oce_mbx mbx; 1407 struct mbx_lowlevel_test_loopback_mode *fwcmd; 1408 int rc = 0; 1409 1410 bzero(&mbx, sizeof(struct oce_mbx)); 1411 1412 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload; 1413 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1414 MBX_SUBSYSTEM_LOWLEVEL, 1415 OPCODE_LOWLEVEL_TEST_LOOPBACK, 1416 MBX_TIMEOUT_SEC, 1417 sizeof(struct mbx_lowlevel_test_loopback_mode), 1418 OCE_MBX_VER_V0); 1419 1420 fwcmd->params.req.pattern = pattern; 1421 fwcmd->params.req.src_port = port_num; 1422 fwcmd->params.req.dest_port = port_num; 1423 fwcmd->params.req.pkt_size = pkt_size; 1424 fwcmd->params.req.num_pkts = num_pkts; 1425 fwcmd->params.req.loopback_type = loopback_type; 1426 1427 mbx.u0.s.embedded = 1; 1428 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode); 1429 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1430 1431 rc = oce_mbox_post(sc, &mbx, NULL); 1432 if (!rc) 1433 rc = fwcmd->hdr.u0.rsp.status; 1434 if (rc) 1435 device_printf(sc->dev, 1436 "%s failed - cmd status: %d addi status: %d\n", 1437 __FUNCTION__, rc, 1438 fwcmd->hdr.u0.rsp.additional_status); 1439 1440 return rc; 1441 } 1442 1443 int 1444 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1445 POCE_DMA_MEM pdma_mem, uint32_t num_bytes) 1446 { 1447 1448 struct oce_mbx mbx; 1449 struct oce_mq_sge *sgl = NULL; 1450 struct mbx_common_read_write_flashrom *fwcmd = NULL; 1451 int rc = 0, payload_len = 0; 1452 1453 bzero(&mbx, sizeof(struct oce_mbx)); 1454 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom); 1455 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024; 1456 1457 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1458 MBX_SUBSYSTEM_COMMON, 1459 OPCODE_COMMON_WRITE_FLASHROM, 1460 LONG_TIMEOUT, 1461 payload_len, 1462 OCE_MBX_VER_V0); 1463 1464 fwcmd->flash_op_type = LE_32(optype); 1465 fwcmd->flash_op_code = LE_32(opcode); 1466 fwcmd->data_buffer_size = LE_32(num_bytes); 1467 1468 mbx.u0.s.embedded = 0; /*Non embeded*/ 1469 mbx.payload_length = payload_len; 1470 mbx.u0.s.sge_count = 1; 1471 1472 sgl = &mbx.payload.u0.u1.sgl[0]; 1473 sgl->pa_hi = upper_32_bits(pdma_mem->paddr); 1474 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF; 1475 sgl->length = payload_len; 1476 1477 /* post the command */ 1478 rc = oce_mbox_post(sc, &mbx, NULL); 1479 if (!rc) 1480 rc = fwcmd->hdr.u0.rsp.status; 1481 if (rc) 1482 device_printf(sc->dev, 1483 "%s failed - cmd status: %d addi status: %d\n", 1484 __FUNCTION__, rc, 1485 fwcmd->hdr.u0.rsp.additional_status); 1486 1487 return rc; 1488 1489 } 1490 1491 int 1492 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1493 uint32_t offset, uint32_t optype) 1494 { 1495 1496 int rc = 0, payload_len = 0; 1497 struct oce_mbx mbx; 1498 struct mbx_common_read_write_flashrom *fwcmd; 1499 1500 bzero(&mbx, sizeof(struct oce_mbx)); 1501 1502 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload; 1503 1504 /* Firmware requires extra 4 bytes with this ioctl. Since there 1505 is enough room in the mbx payload it should be good enough 1506 Reference: Bug 14853 1507 */ 1508 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4; 1509 1510 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1511 MBX_SUBSYSTEM_COMMON, 1512 OPCODE_COMMON_READ_FLASHROM, 1513 MBX_TIMEOUT_SEC, 1514 payload_len, 1515 OCE_MBX_VER_V0); 1516 1517 fwcmd->flash_op_type = optype; 1518 fwcmd->flash_op_code = FLASHROM_OPER_REPORT; 1519 fwcmd->data_offset = offset; 1520 fwcmd->data_buffer_size = 0x4; 1521 1522 mbx.u0.s.embedded = 1; 1523 mbx.payload_length = payload_len; 1524 1525 /* post the command */ 1526 rc = oce_mbox_post(sc, &mbx, NULL); 1527 if (!rc) 1528 rc = fwcmd->hdr.u0.rsp.status; 1529 if (rc) { 1530 device_printf(sc->dev, 1531 "%s failed - cmd status: %d addi status: %d\n", 1532 __FUNCTION__, rc, 1533 fwcmd->hdr.u0.rsp.additional_status); 1534 goto error; 1535 } 1536 bcopy(fwcmd->data_buffer, flash_crc, 4); 1537 error: 1538 return rc; 1539 } 1540 1541 int 1542 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info) 1543 { 1544 1545 struct oce_mbx mbx; 1546 struct mbx_common_phy_info *fwcmd; 1547 int rc = 0; 1548 1549 bzero(&mbx, sizeof(struct oce_mbx)); 1550 1551 fwcmd = (struct mbx_common_phy_info *)&mbx.payload; 1552 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1553 MBX_SUBSYSTEM_COMMON, 1554 OPCODE_COMMON_GET_PHY_CONFIG, 1555 MBX_TIMEOUT_SEC, 1556 sizeof(struct mbx_common_phy_info), 1557 OCE_MBX_VER_V0); 1558 1559 mbx.u0.s.embedded = 1; 1560 mbx.payload_length = sizeof(struct mbx_common_phy_info); 1561 1562 /* now post the command */ 1563 rc = oce_mbox_post(sc, &mbx, NULL); 1564 if (!rc) 1565 rc = fwcmd->hdr.u0.rsp.status; 1566 if (rc) { 1567 device_printf(sc->dev, 1568 "%s failed - cmd status: %d addi status: %d\n", 1569 __FUNCTION__, rc, 1570 fwcmd->hdr.u0.rsp.additional_status); 1571 goto error; 1572 } 1573 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type); 1574 phy_info->interface_type = 1575 HOST_16(fwcmd->params.rsp.phy_info.interface_type); 1576 phy_info->auto_speeds_supported = 1577 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported); 1578 phy_info->fixed_speeds_supported = 1579 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported); 1580 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params); 1581 error: 1582 return rc; 1583 1584 } 1585 1586 int 1587 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1588 uint32_t data_offset, POCE_DMA_MEM pdma_mem, 1589 uint32_t *written_data, uint32_t *additional_status) 1590 { 1591 1592 struct oce_mbx mbx; 1593 struct mbx_lancer_common_write_object *fwcmd = NULL; 1594 int rc = 0, payload_len = 0; 1595 1596 bzero(&mbx, sizeof(struct oce_mbx)); 1597 payload_len = sizeof(struct mbx_lancer_common_write_object); 1598 1599 mbx.u0.s.embedded = 1;/* Embedded */ 1600 mbx.payload_length = payload_len; 1601 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload; 1602 1603 /* initialize the ioctl header */ 1604 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0, 1605 MBX_SUBSYSTEM_COMMON, 1606 OPCODE_COMMON_WRITE_OBJECT, 1607 LONG_TIMEOUT, 1608 payload_len, 1609 OCE_MBX_VER_V0); 1610 1611 fwcmd->params.req.write_length = data_size; 1612 if (data_size == 0) 1613 fwcmd->params.req.eof = 1; 1614 else 1615 fwcmd->params.req.eof = 0; 1616 1617 strcpy(fwcmd->params.req.object_name, "/prg"); 1618 fwcmd->params.req.descriptor_count = 1; 1619 fwcmd->params.req.write_offset = data_offset; 1620 fwcmd->params.req.buffer_length = data_size; 1621 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF; 1622 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr); 1623 1624 /* post the command */ 1625 rc = oce_mbox_post(sc, &mbx, NULL); 1626 if (!rc) 1627 rc = fwcmd->params.rsp.status; 1628 if (rc) { 1629 device_printf(sc->dev, 1630 "%s failed - cmd status: %d addi status: %d\n", 1631 __FUNCTION__, rc, 1632 fwcmd->params.rsp.additional_status); 1633 goto error; 1634 } 1635 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length); 1636 *additional_status = fwcmd->params.rsp.additional_status; 1637 error: 1638 return rc; 1639 1640 } 1641 1642 int 1643 oce_mbox_create_rq(struct oce_rq *rq) 1644 { 1645 1646 struct oce_mbx mbx; 1647 struct mbx_create_nic_rq *fwcmd; 1648 POCE_SOFTC sc = rq->parent; 1649 int rc, num_pages = 0; 1650 1651 if (rq->qstate == QCREATED) 1652 return 0; 1653 1654 bzero(&mbx, sizeof(struct oce_mbx)); 1655 1656 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload; 1657 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1658 MBX_SUBSYSTEM_NIC, 1659 NIC_CREATE_RQ, MBX_TIMEOUT_SEC, 1660 sizeof(struct mbx_create_nic_rq), 1661 OCE_MBX_VER_V0); 1662 1663 /* oce_page_list will also prepare pages */ 1664 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 1665 1666 if (IS_XE201(sc)) { 1667 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 1668 fwcmd->params.req.page_size = 1; 1669 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1; 1670 } else 1671 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size); 1672 fwcmd->params.req.num_pages = num_pages; 1673 fwcmd->params.req.cq_id = rq->cq->cq_id; 1674 fwcmd->params.req.if_id = sc->if_id; 1675 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 1676 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue; 1677 1678 mbx.u0.s.embedded = 1; 1679 mbx.payload_length = sizeof(struct mbx_create_nic_rq); 1680 1681 rc = oce_mbox_post(sc, &mbx, NULL); 1682 if (!rc) 1683 rc = fwcmd->hdr.u0.rsp.status; 1684 if (rc) { 1685 device_printf(sc->dev, 1686 "%s failed - cmd status: %d addi status: %d\n", 1687 __FUNCTION__, rc, 1688 fwcmd->hdr.u0.rsp.additional_status); 1689 goto error; 1690 } 1691 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 1692 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 1693 error: 1694 return rc; 1695 1696 } 1697 1698 int 1699 oce_mbox_create_wq(struct oce_wq *wq) 1700 { 1701 struct oce_mbx mbx; 1702 struct mbx_create_nic_wq *fwcmd; 1703 POCE_SOFTC sc = wq->parent; 1704 int rc = 0, version, num_pages; 1705 1706 bzero(&mbx, sizeof(struct oce_mbx)); 1707 1708 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload; 1709 if (IS_XE201(sc)) 1710 version = OCE_MBX_VER_V1; 1711 else if(IS_BE(sc)) 1712 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2) 1713 : (version = OCE_MBX_VER_V0); 1714 else 1715 version = OCE_MBX_VER_V2; 1716 1717 if (version > OCE_MBX_VER_V0) 1718 fwcmd->params.req.if_id = sc->if_id; 1719 1720 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1721 MBX_SUBSYSTEM_NIC, 1722 NIC_CREATE_WQ, MBX_TIMEOUT_SEC, 1723 sizeof(struct mbx_create_nic_wq), 1724 version); 1725 1726 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]); 1727 1728 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type; 1729 fwcmd->params.req.num_pages = num_pages; 1730 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1; 1731 fwcmd->params.req.cq_id = wq->cq->cq_id; 1732 fwcmd->params.req.ulp_num = 1; 1733 1734 mbx.u0.s.embedded = 1; 1735 mbx.payload_length = sizeof(struct mbx_create_nic_wq); 1736 1737 rc = oce_mbox_post(sc, &mbx, NULL); 1738 if (!rc) 1739 rc = fwcmd->hdr.u0.rsp.status; 1740 if (rc) { 1741 device_printf(sc->dev, 1742 "%s failed - cmd status: %d addi status: %d\n", 1743 __FUNCTION__, rc, 1744 fwcmd->hdr.u0.rsp.additional_status); 1745 goto error; 1746 } 1747 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id); 1748 if (version == OCE_MBX_VER_V2) 1749 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset); 1750 else 1751 wq->db_offset = PD_TXULP_DB; 1752 error: 1753 return rc; 1754 1755 } 1756 1757 int 1758 oce_mbox_create_eq(struct oce_eq *eq) 1759 { 1760 struct oce_mbx mbx; 1761 struct mbx_create_common_eq *fwcmd; 1762 POCE_SOFTC sc = eq->parent; 1763 int rc = 0; 1764 uint32_t num_pages; 1765 1766 bzero(&mbx, sizeof(struct oce_mbx)); 1767 1768 fwcmd = (struct mbx_create_common_eq *)&mbx.payload; 1769 1770 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1771 MBX_SUBSYSTEM_COMMON, 1772 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC, 1773 sizeof(struct mbx_create_common_eq), 1774 OCE_MBX_VER_V0); 1775 1776 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]); 1777 fwcmd->params.req.ctx.num_pages = num_pages; 1778 fwcmd->params.req.ctx.valid = 1; 1779 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1; 1780 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256); 1781 fwcmd->params.req.ctx.armed = 0; 1782 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd; 1783 1784 mbx.u0.s.embedded = 1; 1785 mbx.payload_length = sizeof(struct mbx_create_common_eq); 1786 1787 rc = oce_mbox_post(sc, &mbx, NULL); 1788 if (!rc) 1789 rc = fwcmd->hdr.u0.rsp.status; 1790 if (rc) { 1791 device_printf(sc->dev, 1792 "%s failed - cmd status: %d addi status: %d\n", 1793 __FUNCTION__, rc, 1794 fwcmd->hdr.u0.rsp.additional_status); 1795 goto error; 1796 } 1797 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id); 1798 error: 1799 return rc; 1800 } 1801 1802 int 1803 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable) 1804 { 1805 struct oce_mbx mbx; 1806 struct mbx_create_common_cq *fwcmd; 1807 POCE_SOFTC sc = cq->parent; 1808 uint8_t version; 1809 oce_cq_ctx_t *ctx; 1810 uint32_t num_pages, page_size; 1811 int rc = 0; 1812 1813 bzero(&mbx, sizeof(struct oce_mbx)); 1814 1815 fwcmd = (struct mbx_create_common_cq *)&mbx.payload; 1816 1817 if (IS_XE201(sc)) 1818 version = OCE_MBX_VER_V2; 1819 else 1820 version = OCE_MBX_VER_V0; 1821 1822 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1823 MBX_SUBSYSTEM_COMMON, 1824 OPCODE_COMMON_CREATE_CQ, 1825 MBX_TIMEOUT_SEC, 1826 sizeof(struct mbx_create_common_cq), 1827 version); 1828 1829 ctx = &fwcmd->params.req.cq_ctx; 1830 1831 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]); 1832 page_size = 1; /* 1 for 4K */ 1833 1834 if (version == OCE_MBX_VER_V2) { 1835 ctx->v2.num_pages = LE_16(num_pages); 1836 ctx->v2.page_size = page_size; 1837 ctx->v2.eventable = is_eventable; 1838 ctx->v2.valid = 1; 1839 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1840 ctx->v2.nodelay = cq->cq_cfg.nodelay; 1841 ctx->v2.coalesce_wm = ncoalesce; 1842 ctx->v2.armed = 0; 1843 ctx->v2.eq_id = cq->eq->eq_id; 1844 if (ctx->v2.count == 3) { 1845 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1) 1846 ctx->v2.cqe_count = (4*1024)-1; 1847 else 1848 ctx->v2.cqe_count = cq->cq_cfg.q_len; 1849 } 1850 } else { 1851 ctx->v0.num_pages = LE_16(num_pages); 1852 ctx->v0.eventable = is_eventable; 1853 ctx->v0.valid = 1; 1854 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1855 ctx->v0.nodelay = cq->cq_cfg.nodelay; 1856 ctx->v0.coalesce_wm = ncoalesce; 1857 ctx->v0.armed = 0; 1858 ctx->v0.eq_id = cq->eq->eq_id; 1859 } 1860 1861 mbx.u0.s.embedded = 1; 1862 mbx.payload_length = sizeof(struct mbx_create_common_cq); 1863 1864 rc = oce_mbox_post(sc, &mbx, NULL); 1865 if (!rc) 1866 rc = fwcmd->hdr.u0.rsp.status; 1867 if (rc) { 1868 device_printf(sc->dev, 1869 "%s failed - cmd status: %d addi status: %d\n", 1870 __FUNCTION__, rc, 1871 fwcmd->hdr.u0.rsp.additional_status); 1872 goto error; 1873 } 1874 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id); 1875 error: 1876 return rc; 1877 1878 } 1879 1880 int 1881 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num) 1882 { 1883 int rc = 0; 1884 struct oce_mbx mbx; 1885 struct mbx_read_common_transrecv_data *fwcmd; 1886 struct oce_mq_sge *sgl; 1887 OCE_DMA_MEM dma; 1888 1889 /* Allocate DMA mem*/ 1890 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data), 1891 &dma, 0)) 1892 return ENOMEM; 1893 1894 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data); 1895 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data)); 1896 1897 bzero(&mbx, sizeof(struct oce_mbx)); 1898 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1899 MBX_SUBSYSTEM_COMMON, 1900 OPCODE_COMMON_READ_TRANSRECEIVER_DATA, 1901 MBX_TIMEOUT_SEC, 1902 sizeof(struct mbx_read_common_transrecv_data), 1903 OCE_MBX_VER_V0); 1904 1905 /* fill rest of mbx */ 1906 mbx.u0.s.embedded = 0; 1907 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data); 1908 mbx.u0.s.sge_count = 1; 1909 sgl = &mbx.payload.u0.u1.sgl[0]; 1910 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 1911 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 1912 sgl->length = htole32(mbx.payload_length); 1913 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1914 1915 fwcmd->params.req.port = LE_32(sc->port_id); 1916 fwcmd->params.req.page_num = LE_32(page_num); 1917 1918 /* command post */ 1919 rc = oce_mbox_post(sc, &mbx, NULL); 1920 if (!rc) 1921 rc = fwcmd->hdr.u0.rsp.status; 1922 if (rc) { 1923 device_printf(sc->dev, 1924 "%s failed - cmd status: %d addi status: %d\n", 1925 __FUNCTION__, rc, 1926 fwcmd->hdr.u0.rsp.additional_status); 1927 goto error; 1928 } 1929 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0) 1930 { 1931 bcopy((char *)fwcmd->params.rsp.page_data, 1932 &sfp_vpd_dump_buffer[0], 1933 TRANSCEIVER_A0_SIZE); 1934 } 1935 1936 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2) 1937 { 1938 bcopy((char *)fwcmd->params.rsp.page_data, 1939 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE], 1940 TRANSCEIVER_A2_SIZE); 1941 } 1942 error: 1943 oce_dma_free(sc, &dma); 1944 return rc; 1945 } 1946 1947 void 1948 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1949 int num) 1950 { 1951 struct oce_mbx mbx; 1952 struct mbx_modify_common_eq_delay *fwcmd; 1953 int rc = 0; 1954 int i = 0; 1955 1956 bzero(&mbx, sizeof(struct oce_mbx)); 1957 1958 /* Initialize MODIFY_EQ_DELAY ioctl header */ 1959 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload; 1960 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1961 MBX_SUBSYSTEM_COMMON, 1962 OPCODE_COMMON_MODIFY_EQ_DELAY, 1963 MBX_TIMEOUT_SEC, 1964 sizeof(struct mbx_modify_common_eq_delay), 1965 OCE_MBX_VER_V0); 1966 /* fill rest of mbx */ 1967 mbx.u0.s.embedded = 1; 1968 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay); 1969 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1970 1971 fwcmd->params.req.num_eq = num; 1972 for (i = 0; i < num; i++) { 1973 fwcmd->params.req.delay[i].eq_id = 1974 htole32(set_eqd[i].eq_id); 1975 fwcmd->params.req.delay[i].phase = 0; 1976 fwcmd->params.req.delay[i].dm = 1977 htole32(set_eqd[i].delay_multiplier); 1978 } 1979 1980 /* command post */ 1981 rc = oce_mbox_post(sc, &mbx, NULL); 1982 1983 if (!rc) 1984 rc = fwcmd->hdr.u0.rsp.status; 1985 if (rc) 1986 device_printf(sc->dev, 1987 "%s failed - cmd status: %d addi status: %d\n", 1988 __FUNCTION__, rc, 1989 fwcmd->hdr.u0.rsp.additional_status); 1990 } 1991 1992 int 1993 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss) 1994 { 1995 struct oce_mbx mbx; 1996 struct mbx_common_get_profile_config *fwcmd; 1997 int rc = 0; 1998 int version = 0; 1999 struct oce_mq_sge *sgl; 2000 OCE_DMA_MEM dma; 2001 uint32_t desc_count = 0; 2002 struct oce_nic_resc_desc *nic_desc = NULL; 2003 int i; 2004 boolean_t nic_desc_valid = FALSE; 2005 2006 if (IS_BE2(sc)) 2007 return -1; 2008 2009 /* Allocate DMA mem*/ 2010 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config), 2011 &dma, 0)) 2012 return ENOMEM; 2013 2014 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2015 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config); 2016 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config)); 2017 2018 if (!IS_XE201(sc)) 2019 version = OCE_MBX_VER_V1; 2020 else 2021 version = OCE_MBX_VER_V0; 2022 2023 bzero(&mbx, sizeof(struct oce_mbx)); 2024 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2025 MBX_SUBSYSTEM_COMMON, 2026 OPCODE_COMMON_GET_PROFILE_CONFIG, 2027 MBX_TIMEOUT_SEC, 2028 sizeof(struct mbx_common_get_profile_config), 2029 version); 2030 /* fill rest of mbx */ 2031 mbx.u0.s.embedded = 0; 2032 mbx.payload_length = sizeof(struct mbx_common_get_profile_config); 2033 mbx.u0.s.sge_count = 1; 2034 sgl = &mbx.payload.u0.u1.sgl[0]; 2035 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2036 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2037 sgl->length = htole32(mbx.payload_length); 2038 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2039 2040 fwcmd->params.req.type = ACTIVE_PROFILE; 2041 2042 /* command post */ 2043 rc = oce_mbox_post(sc, &mbx, NULL); 2044 if (!rc) 2045 rc = fwcmd->hdr.u0.rsp.status; 2046 if (rc) { 2047 device_printf(sc->dev, 2048 "%s failed - cmd status: %d addi status: %d\n", 2049 __FUNCTION__, rc, 2050 fwcmd->hdr.u0.rsp.additional_status); 2051 goto error; 2052 } 2053 2054 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2055 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2056 for (i = 0; i < desc_count; i++) { 2057 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2058 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2059 nic_desc_valid = TRUE; 2060 break; 2061 } 2062 nic_desc = (struct oce_nic_resc_desc *) \ 2063 ((char *)nic_desc + nic_desc->desc_len); 2064 } 2065 if (!nic_desc_valid) { 2066 rc = -1; 2067 goto error; 2068 } 2069 else { 2070 sc->max_vlans = HOST_16(nic_desc->vlan_count); 2071 sc->nwqs = HOST_16(nic_desc->txq_count); 2072 if (sc->nwqs) 2073 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2074 else 2075 sc->nwqs = OCE_MAX_WQ; 2076 2077 sc->nrssqs = HOST_16(nic_desc->rssq_count); 2078 if (sc->nrssqs) 2079 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2080 else 2081 sc->nrssqs = max_rss; 2082 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2083 } 2084 error: 2085 oce_dma_free(sc, &dma); 2086 return rc; 2087 2088 } 2089 2090 int 2091 oce_get_func_config(POCE_SOFTC sc) 2092 { 2093 struct oce_mbx mbx; 2094 struct mbx_common_get_func_config *fwcmd; 2095 int rc = 0; 2096 int version = 0; 2097 struct oce_mq_sge *sgl; 2098 OCE_DMA_MEM dma; 2099 uint32_t desc_count = 0; 2100 struct oce_nic_resc_desc *nic_desc = NULL; 2101 int i; 2102 boolean_t nic_desc_valid = FALSE; 2103 uint32_t max_rss = 0; 2104 2105 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native)) 2106 max_rss = OCE_LEGACY_MODE_RSS; 2107 else 2108 max_rss = OCE_MAX_RSS; 2109 2110 /* Allocate DMA mem*/ 2111 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config), 2112 &dma, 0)) 2113 return ENOMEM; 2114 2115 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2116 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config); 2117 bzero(fwcmd, sizeof(struct mbx_common_get_func_config)); 2118 2119 if (IS_SH(sc)) 2120 version = OCE_MBX_VER_V1; 2121 else 2122 version = OCE_MBX_VER_V0; 2123 2124 bzero(&mbx, sizeof(struct oce_mbx)); 2125 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2126 MBX_SUBSYSTEM_COMMON, 2127 OPCODE_COMMON_GET_FUNCTION_CONFIG, 2128 MBX_TIMEOUT_SEC, 2129 sizeof(struct mbx_common_get_func_config), 2130 version); 2131 /* fill rest of mbx */ 2132 mbx.u0.s.embedded = 0; 2133 mbx.payload_length = sizeof(struct mbx_common_get_func_config); 2134 mbx.u0.s.sge_count = 1; 2135 sgl = &mbx.payload.u0.u1.sgl[0]; 2136 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2137 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2138 sgl->length = htole32(mbx.payload_length); 2139 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2140 2141 /* command post */ 2142 rc = oce_mbox_post(sc, &mbx, NULL); 2143 if (!rc) 2144 rc = fwcmd->hdr.u0.rsp.status; 2145 if (rc) { 2146 device_printf(sc->dev, 2147 "%s failed - cmd status: %d addi status: %d\n", 2148 __FUNCTION__, rc, 2149 fwcmd->hdr.u0.rsp.additional_status); 2150 goto error; 2151 } 2152 2153 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2154 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2155 for (i = 0; i < desc_count; i++) { 2156 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2157 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2158 nic_desc_valid = TRUE; 2159 break; 2160 } 2161 nic_desc = (struct oce_nic_resc_desc *) \ 2162 ((char *)nic_desc + nic_desc->desc_len); 2163 } 2164 if (!nic_desc_valid) { 2165 rc = -1; 2166 goto error; 2167 } 2168 else { 2169 sc->max_vlans = nic_desc->vlan_count; 2170 sc->nwqs = HOST_32(nic_desc->txq_count); 2171 if (sc->nwqs) 2172 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2173 else 2174 sc->nwqs = OCE_MAX_WQ; 2175 2176 sc->nrssqs = HOST_32(nic_desc->rssq_count); 2177 if (sc->nrssqs) 2178 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2179 else 2180 sc->nrssqs = max_rss; 2181 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2182 } 2183 error: 2184 oce_dma_free(sc, &dma); 2185 return rc; 2186 2187 } 2188 2189 /* hw lro functions */ 2190 2191 int 2192 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags) 2193 { 2194 struct oce_mbx mbx; 2195 struct mbx_nic_query_lro_capabilities *fwcmd; 2196 int rc = 0; 2197 2198 bzero(&mbx, sizeof(struct oce_mbx)); 2199 2200 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload; 2201 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2202 MBX_SUBSYSTEM_NIC, 2203 0x20,MBX_TIMEOUT_SEC, 2204 sizeof(struct mbx_nic_query_lro_capabilities), 2205 OCE_MBX_VER_V0); 2206 2207 mbx.u0.s.embedded = 1; 2208 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities); 2209 2210 rc = oce_mbox_post(sc, &mbx, NULL); 2211 if (!rc) 2212 rc = fwcmd->hdr.u0.rsp.status; 2213 if (rc) { 2214 device_printf(sc->dev, 2215 "%s failed - cmd status: %d addi status: %d\n", 2216 __FUNCTION__, rc, 2217 fwcmd->hdr.u0.rsp.additional_status); 2218 2219 return rc; 2220 } 2221 if(lro_flags) 2222 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags); 2223 2224 if(lro_rq_cnt) 2225 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt); 2226 2227 return rc; 2228 } 2229 2230 int 2231 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable) 2232 { 2233 struct oce_mbx mbx; 2234 struct mbx_nic_set_iface_lro_config *fwcmd; 2235 int rc = 0; 2236 2237 bzero(&mbx, sizeof(struct oce_mbx)); 2238 2239 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload; 2240 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2241 MBX_SUBSYSTEM_NIC, 2242 0x26,MBX_TIMEOUT_SEC, 2243 sizeof(struct mbx_nic_set_iface_lro_config), 2244 OCE_MBX_VER_V0); 2245 2246 mbx.u0.s.embedded = 1; 2247 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config); 2248 2249 fwcmd->params.req.iface_id = sc->if_id; 2250 fwcmd->params.req.lro_flags = 0; 2251 2252 if(enable) { 2253 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE; 2254 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6; 2255 2256 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */ 2257 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */ 2258 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */ 2259 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */ 2260 } 2261 2262 rc = oce_mbox_post(sc, &mbx, NULL); 2263 if (!rc) 2264 rc = fwcmd->hdr.u0.rsp.status; 2265 if (rc) { 2266 device_printf(sc->dev, 2267 "%s failed - cmd status: %d addi status: %d\n", 2268 __FUNCTION__, rc, 2269 fwcmd->hdr.u0.rsp.additional_status); 2270 2271 return rc; 2272 } 2273 return rc; 2274 } 2275 2276 int 2277 oce_mbox_create_rq_v2(struct oce_rq *rq) 2278 { 2279 struct oce_mbx mbx; 2280 struct mbx_create_nic_rq_v2 *fwcmd; 2281 POCE_SOFTC sc = rq->parent; 2282 int rc = 0, num_pages = 0; 2283 2284 if (rq->qstate == QCREATED) 2285 return 0; 2286 2287 bzero(&mbx, sizeof(struct oce_mbx)); 2288 2289 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload; 2290 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2291 MBX_SUBSYSTEM_NIC, 2292 0x08, MBX_TIMEOUT_SEC, 2293 sizeof(struct mbx_create_nic_rq_v2), 2294 OCE_MBX_VER_V2); 2295 2296 /* oce_page_list will also prepare pages */ 2297 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 2298 2299 fwcmd->params.req.cq_id = rq->cq->cq_id; 2300 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 2301 fwcmd->params.req.num_pages = num_pages; 2302 2303 fwcmd->params.req.if_id = sc->if_id; 2304 2305 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 2306 fwcmd->params.req.page_size = 1; 2307 if(rq->cfg.is_rss_queue) { 2308 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO); 2309 }else { 2310 device_printf(sc->dev, 2311 "non rss lro queue should not be created \n"); 2312 goto error; 2313 } 2314 mbx.u0.s.embedded = 1; 2315 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2); 2316 2317 rc = oce_mbox_post(sc, &mbx, NULL); 2318 if (!rc) 2319 rc = fwcmd->hdr.u0.rsp.status; 2320 if (rc) { 2321 device_printf(sc->dev, 2322 "%s failed - cmd status: %d addi status: %d\n", 2323 __FUNCTION__, rc, 2324 fwcmd->hdr.u0.rsp.additional_status); 2325 goto error; 2326 } 2327 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 2328 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 2329 2330 error: 2331 return rc; 2332 } 2333